TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 HDMI HIDER • • • • FEATURES • • • • • • • • Supports 2.25 Gbps Signaling Rate for 480i/p, 720i/p, and 1080i/p Resolution to 12-Bit Color Depth Compatible with HDMI 1.3a Integrated Receiver Termination 8-dB Equalizer Compensates Losses from 5-m or Longer HDMI Cables Selectable Output De-Emphasis Supports 1-m HDMI Transmission I2C™ Repeater Isolates Bus Capacitance at Both Ends High Impedance Outputs When Disabled TMDS Inputs HBM ESD Protection Exceeds 6 kV 3.3-V Supply Operation 40-Pin QFN Package (RHA) ROHS Compatible and 260°C Reflow Rated Accepts AC Couple DisplayPort Dual-Mode Signals and Translates Them into a HDMI1.3a Compatable TMDS Signal APPLICATIONS • • • • • • • Digital TV DVD Player Set-Top-Box Audio Video Receiver Digital Projector DVI or HDMI cable DisplayPort Level Translator DESCRIPTION The TMDS141 HDMI hider is designed to accommodate a 1-m HDMI cable between a HDMI connector and a receiver. The internal cable causes signal distortion to high-speed TMDS signals, as well as increasing capacitance to the DDC channel. Each TMDS141 contains four TMDS repeaters to transmit digital content with signaling rates of up to 2.25-Gbps, and an I2C repeater to link extended display identification data (EDID) reading and high-bandwidth digital content protection (HDCP) key exchange under I2C standard mode operations. The device includes four TMDS compliant differential receivers with 50-Ω termination resistors and 3.3-V termination voltage integrated at each receiver input pin. External terminations are not required. A built-in frequency response equalization circuit, 8 dB at 825 MHz, compensates inter-symbol interference (ISI) losses from a 5-m or longer input cable link. The device also includes four TMDS compliant differential drivers. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. A selectable de-emphasis circuit is available via the PRE input to drive long PCB traces or cables. When PRE is high, the 3.5-dB high frequency gain offsets the losses due to the FR4 trace. PRE can be left open or kept low when the de-emphasis function is not desired. TYPICAL APPLICATION Digital TV Interface Unit Audiovisual Processing Unit HDMI Rx TMDS 141 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED With standard TMDS terminations at the outputs, all TMDS outputs are forced high-impedance when OE is set high. The I2C repeater isolates the buses without accumulating the capacitance of both sides. It allows DDC capacitance to be controlled under the desired load. The I2C outputs are high-impedance when device supply voltage is less than 1.5 V or I2CEN is low. The OVS pin, output voltage select, provides the flexibility of adjusting the output voltage level of the TSCL and TSDA side to optimize noise margins while interfacing to different HDMI receivers. The device is characterized for operation from 0°C to 70°C. FUNCTIONAL BLOCK DIAGRAM VSADJ OE PRE V CC RINT RX2 TX2 RX2 TMDS Receiver w/EQ TMDS Driver TMDS Receiver w/EQ TMDS Driver TMDS Receiver w/EQ TMDS Driver TMDS Receiver w/EQ TMDS Driver TX2 V CC RINT RX1 TX1 RX1 TX1 V CC RINT RX0 TX0 RX0 TX0 V CC RINT RXC RXC TXC RSCL TSCL RSDA TSDA I2CEN OVS 2 TXC Submit Documentation Feedback TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 22 21 VCC TSDA TSCL GND 23 25 24 27 26 RX1 VCC 28 VSADJ VCC RX0 RX0 GND RX1 30 31 29 GND RXC RXC RSCL RSDA VCC GND OVS RHA PACKAGE (TOP VIEW) GND TXC TXC 20 14 38 13 39 12 40 11 TX1 VCC PRE GND TX2 Tx2 6 5 3 4 9 15 37 VCC TX0 TX0 GND TX1 10 36 8 16 7 17 35 1 18 34 2 33 RX2 GND VCC I2CEN OE 19 Rx2 32 TERMINAL FUNCTIONS TERMINAL NAME RX2, RX1, RX0, RXC NO. 1, 38, 35, 32 I/O DESCRIPTION I TMDS Negative inputs RX2, RX1, RX0, RXC 2, 39, 36, 33 I TMDS Positive inputs TX2, TX1, TX0, TXC 10, 13, 16, 19 O TMDS Negative outputs TX2, TX1, TX0, TXC 9, 12, 15, 18 O TMDS Positive outputs RSCL 29 I/O DDC Bus clock line to source RSDA 28 I/O DDC Bus data line to source TSCL 22 I/O DDC Bus clock line to sink TSDA 23 I/O DDC Bus data line to sink VSADJ 30 I TMDS Compliant voltage swing control I2CEN 5 I I2C Repeater enable Low: High-Z High: Active OVS 25 I TSCL/TSDA Output voltage select OE 6 I TMDS Output enable Low: Active High: High-Z PRE 7 I TMDS Output de-emphasis adjustment Low: 0 dB High: 3.5 dB VCC 4, 11, 17, 24, 27, 34, 40 Power supply GND 3, 8, 14, 20, 21, 26, 31, 37 Ground Submit Documentation Feedback 3 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS TMDS Input Stage VCC VCC Y 25W Z 25W 50W Control Input Stage TMDS Output Stage 50W A B PRE OE I2CEN 400W 10mA 2 2 T-Side I C Input/Output Stage R-Side I C Input/Output Stage RSCL RSDA 400W VCC VCC VCC TSCL TSDA Control Input Stage VCC VCC 400W OVS 400W VOL ORDERING INFORMATION (1) (1) 4 PART NUMBER PART MARKING PACKAGE TMDS141RHAR TMDS141 40-PIN QFN Tape/Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Submit Documentation Feedback TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2) VCC –0.5 V to 4 V RX, RX Voltage range 2.0 V to 4 V TX, TX, PRE, VSADJ, OE, I2CEN, OVS, HPDn –0.5V to 4 V RSCL, RSDA, TSCL, TSDA –0.5 V to 6 V Electrostatic discharge ±6 kV RX, RX Human body model (3) ±4 kV All pins Charged-device model (4) (all pins) ±1500 V (5) ± 200 V Machine model (all pins) Continuous power dissipation (1) (2) (3) (4) (5) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS (1) (2) (3) (1) DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING PACKAGE PCB JEDEC STANDARD TA ≤ 25°C 40-QFN RHA Low-K (2) 839.7 mW 8.39 mW/°C 461.8 mW 40-QFN RHA High-K (3) 3030.3 mW 30.3 mW/°C 1666.6mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-3 In accordance with the High-K thermal metric definitions of EIA/JESD51-7 THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJB Junction-to-board thermal resistance 30.9 6 °C/W RθJC Junction- to-case thermal resistance 32.4 2 °C/W PD Device power dissipation VIH = VCC, VIL = VCC - 0.5 V, RT = 50 Ω, VCC = AVCC = 3.3V, Rvsadj = 4.64 kΩ PRE = Low 344 370 PRE = High 381 407 VIH = VCC, VIL = VCC - 0.6 V, RT = 50 Ω, VCC = 3.6 V, AVCC = 3.3V, Rvsadj = 4.6 kΩ PRE = Low 484 PRE = High 526 mW mW RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 UNIT V TA Operating free-air temperature 0 70 °C VCC–400 VCC+10 mV TMDS DIFFERENTIAL PINS (RX/ RXC) VIC Input common mode voltage VID Receiver peak-to-peak differential input voltage 150 1560 mVp-p RVSADJ Resistor for TMDS compliant voltage swing range 4.6 4.64 4.68 kΩ AVCC TMDS Output termination voltage, see Figure 1 3 3.3 3.6 V RT Termination resistance, see Figure 1 45 50 Signaling rate 0 Submit Documentation Feedback 55 2.25 Ω Gbps 5 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT CONTROL PINS (PRE, OE, I2CEN) VIH LVTTL High-level input voltage 2 VCC V VIL LVTTL Low-level input voltage GND 0.8 V CONTROL PINS (OVS) VIH LVTTL High-level input voltage 3 3.6 V VIL LVTTL Low-level input voltage -0.5 0.5 V I2C PINS (TSCL, TSDA) VIH High-level input voltage 0.7VCC 5.5 V VIL Low-level input voltage -0.5 0.3VCC V VICL Low-level input voltage contention (1) -0.5 0.4 V I2C PINS (RSCL, RSDA) VIH High-level input voltage 2.1 5.5 V VIL Low-level input voltage -0.5 1.5 V (1) VIL specification is for the first low level seen by the SCL/SDA lines. VICL is for the second and subsequent low levels seen by the TSCL/TSDA lines. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ICC Supply current VIH = VCC, VIL = VCC – 0.4 V, RT = 50 Ω, AVCC = 3.3 V, RVSADJ = 4.64 kΩ, 1.65-Gbps HDMI data pattern, 165-MHz Pixel clock, PRE = Low PD Power dissipation VIH = VCC, VIL = VCC – 0.4 V, RT = 50 Ω, AVCC = 3.3 V, RVSADJ = 4.64 kΩ, 1.65-Gbps HDMI data pattern, 165-MHz Pixel clock, PRE = Low MIN TYP (1) MAX UNIT 108 130 (2) mA 497 (2) mW TMDS DIFFERENTIAL PINS (TX, TXC) VOH Single-ended high-level output voltage AVCC–10 AVCC+10 mV VOL Single-ended low-level output voltage AVCC–600 AVCC–400 mV Vswing Single-ended output swing voltage 400 600 mV VOD(O) Overshoot of output differential voltage VOD(U) Undershoot of output differential voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states I(O)OFF Single-ended standby output current VOD(pp) Peak-to-peak output differential voltage VODE(SS) Steady state output differential voltage with de-emphasis I(OS) Short circuit output current See Figure 4 VI(open) Single-ended input voltage under high impedance input or open input II = 10 µA RINT Input termination resistance VIN = 2.9 V See Figure 2, AVCC = 3.3 V, RT = 50 Ω 15% 2× Vswing 25% 2× Vswing 0 V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V, RT = 50 Ω See Figure 3, PRE = High, AVCC = 3.3 V, RT = 50 Ω 5 mV –10 10 µA 800 1200 600 820 -12 12 mA VCC–10 VCC+10 mV 45 50 mVp-p 55 Ω CONTROL PINS (PRE, OE, I2CEN, OVS) |IIH| High-level digital input current VIH = 2 V or VCC -10 10 µA |IIL| Low-level digital input current VIL = GND or 0.8 V -10 10 µA VI = 5.5 V -50 50 VI = VCC -10 10 VO = 3.6 V -10 10 I2C |Ilkg| Input leakage current |IOH| High-level output current (1) (2) 6 PINS (TSCL, TSDA) All typical values are at 25°C and with a 3.3-V supply. The maximum rating is characterized under 3.6 V VCC and 600 mV VID. Submit Documentation Feedback µA µA TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER |IIL| Low-level input current TEST CONDITIONS Low-level output voltage IOL = 400 µA or 4 mA TYP (1) 40 0.47 0.6 OVS = GND (3) 0.6 0.75 OVS = VCC (3) 0.75 0.95 OVS = NC (3) VOL-VILC Low-level input voltage below output low-level voltage level Ensured by design OVS = Input/output capacitance UNIT µA V 70 GND (3) 220 OVS = VCC (3) CIO MAX -40 OVS = NC (3) VOL MIN VIL = GND mV 370 VI = 5.0 V or 0 V, Freq = 100 kHz 25 VI = 3.0 V or 0 V, Freq = 100 kHz 10 pF I2C PINS (RSCL, RSDA) VI = 5.5 V -50 50 VI = VCC -10 10 High-level output current VO = 3.6 V -10 10 µA Low-level input current VIL = GND -10 10 µA Low-level output voltage IOL = 4 mA 0.2 V VI = 5.0 V or 0 V, Freq = 100 kHz 25 VI = 3.0 V or 0 V, Freq = 100 kHz 10 |Ilkg| Input leakage current |IOH| |IIL| VOL CI (3) Input capacitance µA pF The patent of the OVS pin is filed. SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT TMDS DIFFERENTIAL PINS (TX/TXC) tPLH Propagation delay time, low-to-high-level output 100 500 ps tPHL Propagation delay time, high-to-low-level output 100 500 ps tr Differential output signal rise time (20% - 80%) 75 240 ps tf Differential output signal fall time (20% - 80%) 75 240 ps See Figure 2, AVCC = 3.3 V, RT = 50 Ω tPLH|) (2) tsk(p) Pulse skew (|tPHL– 50 ps tsk(D) Intra-pair differential skew, see Figure 5 35 ps tsk(o) Inter-pair channel-to-channel output skew (3) 80 ps tsk(pp) Part-to-part skew 200 ps ten Enable time 10 ns tdis Disable time 10 ns tjit(pp) Peak-to-peak output jitter from TXC, residual jitter (5) tjit(pp) Peak-to-peak output jitter from TX0 - TX2, residual jitter (5) tjit(pp) Peak-to-peak output jitter from TXC, residual jitter (5) tjit(pp) Peak-to-peak output jitter from TX0 - TX2, residual jitter (5) (1) (2) (3) (4) (5) (4) See Figure 6 See Figure 7, RXC = 165-MHz clock, RX = 1.65-Gbps HDMI pattern, Input: 5m 28AWG HDMI cable, Output: 1m 28AWG HDMI cable, PRE = high 14 30 ps 30 88 ps See Figure 7, RXC = 225-MHz clock, RX = 2.25-Gbps HDMI pattern, Input: 5m 28AWG HDMI cable, Output: 1m 28AWG HDMI cable, PRE = high 25 42 88 ps All typical values are at 25°C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs are tied together. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, or between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits. Jitter specifications are ensured by design and characterization and measured in BER-12 Submit Documentation Feedback 7 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 SWITCHING CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 459 ns 120 ns 351 ns 120 ns I2C PINS (RSCL, RSDA, TSCL, TSDA) 8 tPLH Propagation delay time, low-to-high-level output TSCL/TSDA to RSCL/RSDA 204 tPHL Propagation delay time, high-to-low-level output TSCL/TSDA to RSCL/RSDA 35 tPLH Propagation delay time, low-to-high-level output RSCL/RSDA to TSCL/TSDA 194 tPHL Propagation delay time, high-to-low-level output RSCL/RSDA to TSCL/TSDA tr TSCL/TSDA Output signal rise time 500 800 ns tf TSCL/TSDA Output signal fall time 30 72 ns tr RSCL/RSDA Output signal rise time 796 999 ns tf RSCL/RSDA Output signal fall time 20 72 ns tset Enable to start condition thold Enable after stop condition See Figure 8, OVS = NC See Figure 9 Submit Documentation Feedback 35 100 ns 100 ns TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION AVcc RT RT ZO = RT TMDS Driver TMDS Receiver ZO = RT Figure 1. Typical Termination for TMDS Output Driver Vcc RINT RINT RT TX RX TMDS Receiver VIC VRX TMDS Driver CL 0.5 pF AVcc RT VTX TX RX VTX VRX VIC = | VRX − VRX| Vswing = | VTX − VTX| VRX DC Coupled Vcc AC Coupled Vcc+0.2 V VRX Vcc−0.4 V Vcc−0.2 V VIC 0.4 V VIC VID(pp) 0V −0.4 V t PHL t PLH 100% 80% Vswing VOD(O) 0V Differential VOD(pp) 20% 0% tf VOC tr VOD(U) nVOC(SS) NOTE: PRE = low. All input pulses are supplied by a generator having the following characteristics: tr or tf < 100 ps, 100 MHz from Agilent 81250. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement equipment provides a bandwidth of 20 GHz minimum. Figure 2. TMDS Timing Test Circuit and Definitions Submit Documentation Feedback 9 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) 1 to N bit 1 bit VODE(SS) VOD(pp) 80% 20% t PRE Figure 3. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions 50 W IOS TMDS Driver 50 W + _ 0 V or 3.6 V Figure 4. Short Circuit Output Current Test Circuit VTX 50% VTX tsk(D) Figure 5. Definition of Intra-Pair Differential Skew VCC 1.5 V OE 0V TX VOD = 75 mV TX VOD = -75 mV VOD = 400 mV 0V Hi-Z tdis VOD = -400 mV ten Figure 6. TMDS Enable and Disable Timing Definitions 10 Submit Documentation Feedback TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) AVcc RT Data + Coax Video Data Patterm Generator Coax 800mVpp or 1200mVpp Differential SMA SMA RX +EQ SMA 28AWG HDMI Cable SMA Jitter Test Instrument AVcc RT RT SMA RX +EQ Coax Transmission media HDMI cable or FR4 PCB trace TMDS141 SMA Coax Clk- OUT SMA Coax Clk+ RT Coax Coax OUT SMA Coax Jitter Test Instrument XTP1 XTP2 XTP3 XTP4 10-12 A. All jitters are measured in BER of B. The residual jitter reflects the total jitter measured at XTP4, subtract the total jitter at XTP1 Figure 7. Jitter Test Circuit Vcc VCC 3.3V + 10% RSCL/RSDA Input Vcc/2 RL=4.7kW PULSE GENERATOR 0.1V D.U.T. RT tPHL C L=100pF VIN tPLH 80% VOUT TSCL/TSDA Output 80% 20% 1.5V 20% tf 3.3V + 10% tr VOL Vcc VCC 5V + 10% TSCL/TSDA Input 1.5V RL=1.67kW PULSE GENERATOR 0.1V D.U.T. RT tPHL C L=400pF VIN 80% VOUT RSCL/RSDA Output 80% 20% 20% tf tr 5V + 10% Vcc/2 VOL Vcc TSCL/TSDA Input 0.5V tPLH 5V + 10% RSCL/RSDA Output Vcc/2 Figure 8. I2C Timing Test Circuit and Definition Submit Documentation Feedback 11 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) START STOP V DD SCL 0V V DD SDA 1.5V 0V V DD 1.5V I2CEN 0V t SET t HOLD Figure 9. I2C Setup and Hold Definition 12 Submit Documentation Feedback TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 120 120 110 110 100 100 90 ICC - Supply Current - mA ICC - Supply Current - mA SUPPLY CURRENT vs FREQUENCY OE = Low, PRE = High 80 70 OE = Low, PRE = Low 60 50 OE = High, PRE = Low 40 30 20 10 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, VID(PP) = 1200 mVp-p 80 70 60 50 40 30 VCC = AVCC = 3.3 V, RT = 50 W, 20 RVSADJ = 4.64 kW, VID(PP) = 1200 mVp-p, Rx0 - Rx2 HDMI Data Pattern, 2.25 Gbps RxC, 225 MHz 10 0 0 75 165 185 205 f - Frequency - MHz 1 225 2 3 4 5 6 TA - Free- Air Temperature - °C Figure 10. Figure 11. RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE (DC Coupled Input: 5m 28AWG, Output: 1m 28AWG) RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE (DC Coupled Input: 3m 30AWG, Output: 1m 28AWG) 20 20 16 14 PRE = Low, 1200 mVPP 12 10 8 PRE = High, 800 mVPP 6 PRE = High, 1200 mVPP 4 2 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, OE = Low, HDMI Data Pattern 0 750 1450 1650 1850 2250 Residual Peak-peak Jitter - % of Tbit 18 PRE = Low, 800 mVPP 18 Residual Peak-peak Jitter - % of Tbit OE = Low, PRE = High 90 16 PRE = Low, 1200 mVPP 14 12 PRE = Low, 800 mVPP 10 8 PRE = High, 1200 mVPP 6 PRE = High, 800 mVPP 4 2 0 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, OE = Low, HDMI Data Pattern 750 Data Rate - Mbps 1450 1650 1850 2250 Data Rate - Mbps Figure 12. Figure 13. Submit Documentation Feedback 13 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) RESIDUAL PEAK-TO-PEAK JITTER vs DATA RATE (AC Coupled Input: 3m 30AWG, Output: 1m 28AWG) RESIDUAL PEAK-TO-PEAK JITTER vs 8-MIL FR4 TRACE OUTPUT (DC Coupled Input: 5m 28AWG) 20 15 16 PRE = Low, 800 mVPP 14 12 PRE = Low, 1200 mVPP 10 8 PRE = High, 1200 mVPP 6 4 PRE = High, 800 mVPP 14 Residual Peak-peak jitter - % of Tbit Residual Peak-peak Jitter - % of Tbit VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW, 18 TA = 25°C, OE = Low, HDMI Data Pattern 10 2 1450 1650 1850 9 8 7 XTP1 VID = 800 mVPP 6 XTP1 VID = 1200 mVPP 5 4 3 2 1 0 0 750 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW,TA = 25°C, PRE = High, 13 OE = Low, 1.65 Gbps HDMI Pattern, 12 165-Mhz Pixel Clock, VID(PP) at XTP1, 11 Source Jitter < 0.3 UI, See Figure 7 2250 5 Data Rate - Mbps 7 11 15 8-mil FR4 Trace Length - inch Figure 14. Figure 15. RESIDUAL PEAK-TO-PEAK JITTER vs PEAK-TO-PEAK DIFFERENTIAL INPUT VOLTAGE (at XTP2) Residual Peak-peak Jitter - % of Tbit 8 7.5 7 6.5 VCC = AVCC = 3.3 V, RT = 50 W, RVSADJ = 4.64 kW, TA = 25°C, OE = Low, 28AWG HDMI Cable, 1.65 Gbps HDMI Data Pattern, 165 Mhz Pixel Clock, VID(PP) at XTP1, Source Jitter < 0.3 UI, See Figure 7 Output = 0m, PRE = Low 6 5.5 5 Output = 1m, PRE = High 4.5 4 300 500 700 900 1100 1300 1500 1700 Peak-to-Peak Differential Input Voltage - mVp-p Figure 16. 14 Submit Documentation Feedback 18 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 APPLICATION INFORMATION Supply Voltage All VCC pins can be tied to a single 3.3-V power source. A 0.01-µF capacitor is connected from each VCC pin directly to ground to filter supply noise. TMDS Inputs Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each input channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDS input pins must be limited per the absolute maximum ratings. An unused input should not be connected to ground as this would result in excessive current flow damaging the device. TMDS input pins do not incorporate failsafe circuits. An unused input channel can be externally biased to prevent output oscillation. The complementary input pin is recommended to be grounded through a 1-kΩ resistor and the other pin left open. TMDS Outputs A 1% precision resister, 4.64-kΩ, connected from VSADJ to ground is recommended to allow the differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current sink capability, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor. AVCC VCC TMDS141 ZO = RT TMDS Driver RT RT ZO = RT TMDS Receiver GND Figure 17. TMDS Driver and Termination Circuit Referring to Figure 17, if both VCC (TMDS141 supply) and AVCC (sink termination supply) are both powered, the TMDS output signals is high impedance when OEB = high. Both supplies being active is the normal operating condition. Again refer to Figure 17, if VCC is on and AVCC is off, the TMDS outputs source a typical 5-mA current through each termination resistor to ground. A total of 10-mW of power is consumed by the terminations independent of the OEB logical selection. When AVCC is powered on, normal operation (OEB controls output impedance) is resumed. When the power source of the device is off and the power source to termination is on, the IO(off), output leakage current, specification ensures the leakage current is limited 10-µA or less. The PRE pin provides 3dB de-emphasis, allowing output signal pre-conditioning to offset interconnect losses from the TMDS141 outputs to a TMDS receiver. PRE is recommended to be set low while connecting to a receiver throw short PCB route. I2C Function Description The RSCL/RSDA and TSCL/TSDA pins are 5-V tolerant when the device is powered off and high impedance under low supply voltage, 1.5 V or below. If the device is powered up and the I2C circuits are enabled, and I2CEN = high, the driver T (see Figure 18) is turned on or off depending up on the corresponding R side voltage level. When the R side is pulled low below 1.5 V, the corresponding T side driver turns on and pulls the T side down to a low level output voltage, VOL. The value of VOL depends on the input to the OVS pin. When OVS is left floating Submit Documentation Feedback 15 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) or not connected, VOL is typically 0.5 V. When OVS is connected to GND, VOL is typically 0.65 V. When OVS is connected to VCC, VOL is typically 0.8 V. VOL is always higher than the driver R input threshold, VIL, which is typically 0.4 V, preventing lockup of the repeater loop. The VOL value can be selected to improve or optimize noise margins between VOL and the VIL of the repeater itself or the VIL of some external device connected on the T side. When the R side is pulled up, above 1.5 V, the T side driver turns off and the T side pin is high impedance. OVS T RSCL RSDA TSCL TSDA I2CEN R Figure 18. I2C Drivers in TMDS141 When the T side is pulled below 0.4 V by an external I2C driver, both drivers R and T are turned on. Driver R pulls the R side to near 0 V, and driver T is on, but is overridden by the external I2C driver. If driver T is already on, due to a low on the R side, driver R just turns on. When the T side is released by the external I2C driver, driver T is still on, so the T side is only able to rise to the VOL of driver T. Driver R turns off, since VOL is above its 0.4-V VIL threshold, releasing the R side. If no external I2C driver is keeping the R side low, the R side rises, and driver T turns off once the R side rises above 1.5 V, see Figure 19. Vcc TSCL/TSDA 0.5V tPLH 5V + 10% RSCL/RSDA Vcc/2 Figure 19. Waveform of Turning Driver T Off It is important that any external I2C driver on the T side is able to pull the bus below 0.4 V to ensure full operation. If the T side cannot be pulled below 0.4 V, driver R may not recognize and transmit the low value to the R side. I2C Enable The I2CEN pin is active high with an internal pull-up to VCC. It can be used to isolate a badly behaved slave during power up. It should never change state during an I2C operation because disabling during a bus operation may hang the bus and enabling part way through a bus cycle could confuse the I2C parts being enabled. I2C Behavior The typical application of the TMDS141 is as a repeater in a TV connecting the HDMI input connector and an internal HDMI Rx through flat cables. The I2C repeater is 5-V tolerant, and no additional circuitry is required to translate between 3.3-V to 5-V bus voltages. In the following example, the system master is running on an R-side I2C-bus while the slave is connected to a T-side bus. Both buses run at 100 kHz supporting standard-mode I2C operation. Master devices can be placed on either bus. 16 Submit Documentation Feedback TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) VRdd V Tdd Driver T RRup RTup Master Slave CSOURCE CI CO Cslave Driver R Cmedium CCABLE Figure 20. Typical Application Figure 21 illustrates the waveforms seen on the R-side I2C-bus when the master writes to the slave through the I2C repeater circuit of the TMDS141. This looks like a normal I2C transmission, and the turn on and turn off of the acknowledge signals are slightly delayed. 9th Clock Pulse - Acknowledge From Slave RSCL RSDA Figure 21. Bus R Waveform Figure 22 illustrates the waveforms seen on the T-side I2C-bus under the same operation in Figure 21. On the T-side of the I2C repeater, the clock and data lines would have a positive offset from ground equal to the VOL of the driver T. After the 8th clock pulse, the data line is pulled to the VOL of the slave device which is very close to ground in this example. At the end of the acknowledge, the slave device releases and the bus level rises back to the VOL set by the driver until the R-side rises above VCC/2, after which it continues to high. It is important to note that any arbitration or clock stretching events require that the low level on the T-side bus at the input of the TMDS141 I2C repeater is below 0.4 V to be recognized by the device and then transmitted to the R-side I2C bus. 9th Clock Pulse - Acknowledge From Slave TSCL TSDA VOL Of Driver T V OL Of Slave Figure 22. Bus T Waveform The I2C circuitry inside the TMDS141 allows multiple stage operation as shown in Figure 23. I2C-Bus slave devices can be connected to any of the bus segments. The number of devices that can be connected in series is limited by repeater delay/time of flight considerations for the maximum bus speed requirements. Submit Documentation Feedback 17 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) Source Sink Repeater 3.3V 5V 5V 5V Rup 5V 3.3V Rup SOURCE SOURCE Rup 1 3.3V Rup Rup 2 Rup SINK SINK SDA RSDA TSDA RSDA TSDA RSDA TSDA SDA SCL RSCL TSCL RSCL TSCL RSCL TSCL SCL BUS MASTER C1 TMDS141 C2 C3 C2 C2 C2 C3 TMDS141 EN EN TMDS141 C1 BUS SLAVE EN Figure 23. Typical Series Application I2C Pull-up Resistors The pull-up resistor value is determined by two requirements: 1. The maximum sink current of the I2C buffer: The maximum sink current is 3 mA or slightly higher for an I2C driver supporting standard-mode I2C operation. R up(min) + VDDńlsink (1) 2. The maximum transition time on the bus: The maximum transition time, T, of an I2C bus is set by an RC time constant, where R is the pull-up resistor value, and C is the total load capacitance. The parameter, k, can be calculated from equation 3 by solving for t, the times at which certain voltage thresholds are reached. Different input threshold combinations introduce different values of t. Table 1 summarizes the possible values of k under different threshold combinations. T + k RC (2) V(t) + V (1 * e *tńRC) DD (3) Table 1. Value k Upon Different Input Threshold Voltages Vth-\Vth+ 0.7VDD 0.65VDD 0.6VDD 0.55VDD 0.5VDD 0.45VDD 0.4VDD 0.35VDD 0.3VDD 0.1VDD 1.0986 0.9445 0.8109 0.6931 0.5878 0.4925 0.4055 0.3254 0.2513 0.15VDD 1.0415 0.8873 0.7538 0.6360 0.5306 0.4353 0.3483 0.2683 0.1942 0.2VDD 0.9808 0.8267 0.6931 0.5754 0.4700 0.3747 0.2877 0.2076 0.1335 0.25VDD 0.9163 0.7621 0.6286 0.5108 0.4055 0.3102 0.2231 0.1431 0.0690 0.3VDD 0.8473 0.6931 0.5596 0.4418 0.3365 0.2412 0.1542 0.0741 - From equation 1, Rup(min) = 5.5V/3mA = 1.83 kΩ to operate the bus under a 5-V pull-up voltage and provide less than 3 mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is allowed, Rup(min) can be as low as 1.375 kΩ. Given a 5-V I2C device with input low and high threshold voltages at 0.3 Vdd and 0.7 Vdd, the valued of k is 0.8473 from Table 1. Taking into account the 1.83-kΩ pull-up resistor, the maximum total load capacitance is C(total-5V) = 645 pF. Ccable(max) should be restricted to be less than 545 pF if Csource and Ci can be as heavy as 50 pF. Here the Ci is treated as Csink, the load capacitance of a sink device. Fixing the maximum transition time from Table 1, T = 1 µs, and using the k values from Table 1, the recommended maximum total resistance of the pull-up resistors on an I2C bus can be calculated for different system setups. To support the maximum load capacitance specified in the HDMI spec, Ccable(max) = 700pF/Csource = 50pF/Ci = 50pF, R(max) can be calculated as shown in Table 2. 18 Submit Documentation Feedback TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 Table 2. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads Vth-\Vth+ 0.7VDD 0.65VDD 0.6VDD 0.55VDD 0.5VDD 0.45VDD 0.4VDD 0.35VDD 0.3VDD UNIT 0.1VDD 1.14 1.32 1.54 1.80 2.13 2.54 3.08 3.84 4.97 kΩ 0.15VDD 1.20 1.41 1.66 1.97 2.36 2.87 3.59 4.66 6.44 kΩ 0.2VDD 1.27 1.51 1.80 2.17 2.66 3.34 4.35 6.02 9.36 kΩ 0.25VDD 1.36 1.64 1.99 2.45 3.08 4.03 5.60 8.74 18.12 kΩ 0.3VDD 1.48 1.80 2.23 2.83 3.72 5.18 8.11 16.87 - kΩ Or, limiting the maximum load capacitance of each cable to be 400 pF to accommodate with I2C spec version 2.1. Ccable(max) = 400pF/Csource=50pF/Ci = 50pF, the maximum values of R(max) are calculated as shown in Table 3. Table 3. Pull-Up Resistor Upon Different Threshold Voltages and 500-pF Loads Vth-\Vth+ 0.7VDD 0.65VDD 0.6VDD 0.55VDD 0.5VDD 0.45VDD 0.4VDD 0.35VDD 0.3VDD UNIT 0.1VDD 1.82 2.12 2.47 2.89 3.40 4.06 4.93 6.15 7.96 kΩ 0.15VDD 1.92 2.25 2.65 3.14 3.77 4.59 5.74 7.46 10.30 kΩ 0.2VDD 2.04 2.42 2.89 3.48 4.26 5.34 6.95 9.63 14.98 kΩ 0.25VDD 2.18 2.62 3.18 3.92 4.93 6.45 8.96 13.98 28.99 kΩ 0.3VDD 2.36 2.89 3.57 4.53 5.94 8.29 12.97 26.99 - kΩ Obviously, to accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support a maximum 800-pF load capacitance for a standard-mode I2C bus. When the input low and high level threshold voltages, Vth- and Vth+, are 0.7 V and 1.9 V, which is 0.15 VDD and 0.4 VDD approximately with VDD = 5 V, from Table 2, the maximum pull-up resistor is 3.59 kΩ. The allowable pull-up resistor is in the range of 1.83 kΩ and 3.59 kΩ. Thermal Dissipation On a high-K board – It is always recommended to solder the PowerPAD™ onto the thermal land. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board the TMDS141 can operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias. On a low-K board – In order for the device to operate across the temperature range on a low-K board, a 1-oz Cu trace connecting the GND pins to the thermal land must be used. A simulation shows RθJA = 100.84°C/W allowing 545 mW power dissipation at 70°C ambient temperature. A general PCB design guide for PowerPAD packages is provided in the document SLMA002 - PowerPAD Thermally Enhanced Package. Submit Documentation Feedback 19 TMDS141 www.ti.com SLLS737C – JUNE 2006 – REVISED JUNE 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from A Revision (August 2006) to B Revision ............................................................................................... Page • • • • • • • • • • • • • Changed Features ................................................................................................................................................................ 1 Changed Signaling rate from 1.65 Gbps to 2.25 Gbps ........................................................................................................ 5 Added PRE = Low to supply current test conditions ............................................................................................................ 6 Added PRE = Low to power dissipation test conditions ....................................................................................................... 6 Deleted TTL high- and low-level output voltages ................................................................................................................. 7 Changed Peak-to-peak output jitter from TX0 - TX2, residual jitter from 90 to 88 ps .......................................................... 7 Added Peak-to-peak output jitter from TXC, residual jitter ................................................................................................... 7 Added Peak-to-peak output jitter from TX0 - TX2, residual jitter.......................................................................................... 7 Changed Figure 10 ............................................................................................................................................................ 13 Changed Figure 11 ............................................................................................................................................................ 13 Changed Figure 12 ............................................................................................................................................................ 13 Changed Figure 13 ............................................................................................................................................................ 13 Changed Figure 14 ............................................................................................................................................................ 14 Changes from B Revision (April 2007) to C Revision ................................................................................................... Page • • • 20 Added Feature - Accepts AC Couple DisplayPort Dual-Mode Signals and Translates Them into a HDMI1.3a Compatable TMDS Signal .................................................................................................................................................... 1 Added Application - DisplayPort Level Translator ............................................................................................................... 1 Changed SWITCHING CHARACTERISTICS - tsk(D) max from 60 to 35 ps ......................................................................... 7 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 1-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TMDS141RHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMDS141RHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device TMDS141RHAR 21-May-2007 Package Pins RHA 40 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) MLA 330 16 6.3 6.3 1.5 12 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TMDS141RHAR RHA 40 MLA 346.0 346.0 33.0 Pack Materials-Page 2 W Pin1 (mm) Quadrant 16 Q2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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