ICs for Consumer Electronics SRC-Scan Rate Converter SDA 9255 Data Sheet 1998-02-01 Edition 1998-02-01 This edition was realized using the software system FrameMaker Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 8.2.98. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. ICs for Consumer Electronics Scan Rate Converter SDA 9255 Data Sheet 1998-02-01 SDA 9255 Revision History: Current Version: 1998-02-01 Previous Version: 1997-07-01 Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) Definition of N.C. pins Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA = 25°C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright Siemens AG 1997. All rights reserved. Terms of delivery and right to change design reserved. SDA 9255 Table of Contents Page 1 1.1 1.2 1.3 1.4 1.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Input Timing and Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Delay of Vertical Input Synchronization Signal . . . . . . . . . . . . . . . . . . . . . . 11 Number of Active Lines of an Input Field . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Number of Not Active Lines of an Input Field . . . . . . . . . . . . . . . . . . . . . . . . 12 Not Active Pixels of Input Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Timing and Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Number of Not Active Lines of Output Field . . . . . . . . . . . . . . . . . . . . . . . . . 14 Number of Not Active Pixels of Output Field . . . . . . . . . . . . . . . . . . . . . . . . 15 VOUT, HOUT and HREF Signal Length . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Synchronization Raster and Interlaced Output Signal . . . . . . . . . . . 16 Motion Adaptive Temporal Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . 17 Digital Vertical Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 3.1 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Characteristics (Assuming Recommended Operating Conditions) . . . . 34 4 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Timing of the SDA 9255 (HSINP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . Output Timing of the SDA 9255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Vertical Synchronization Signal (VSINP = 0) . . . . . . . . . . . . . . . . . Example for Not Active Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Not Active Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Not Active Output Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing for HOUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing for VOUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing for HREF Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Group 3 5 5 5 6 7 8 36 36 37 37 38 38 39 39 40 40 1998-02-01 SDA 9255 Table of Contents Page 5.10 5.11 5.12 5.13 Example for INTERLACED Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Timing START/STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Timing DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Semiconductor Group 4 41 41 42 42 1998-02-01 SRC-Scan Rate Converter SDA 9255 CMOS 1 Overview 1.1 Features • • • • • • • • • • • • • 100/120 Hz interlaced scan conversion Data format 4:1:1 On chip field memory Digital vertical zooming P-MQFP-64-1 Digital vertical panning Motion adaptive temporal noise reduction, field based Still field Color difference input data representation 2’s complement or unsigned Color difference output data representation 2’s complement or unsigned Sync Generation for backend IC I2C-Bus control (400 kHz) P-MQFP-64 package 5 V ± 5 % supply voltage 1.2 General Description The SDA 9255 is a new component of the Siemens MEGAVISION® IC set. The SDA 9255 comprises some of the functionalities of the MEGAVISION® IC’s SDA 9220 (Memory Sync Controller) and SDA 9254 (Triple TV-SAM plus Noise Reduction) and can therefore be used as a low cost digital featurebox. Type Ordering Code Package SDA 9255 Q67101-H5190 P-MQFP-64-1 Semiconductor Group 5 1998-02-01 SDA 9255 TESTI1 TESTI2 TESTI3 UVIN4 UVIN5 UVIN6 UVIN7 VDD YIN0 VSS YIN1 YIN2 YIN3 YIN4 YIN5 Pin Configuration YIN6 1.3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 YIN7 49 32 TESTI0 TEST 50 31 RESET LL2CLK 51 30 SYNCEN TESTO7 52 29 TESTO6 TESTO8 53 28 TESTO5 TESTO9 VSS 54 27 55 26 TESTO4 VSS VDD 56 25 VDD VSS 57 24 VSS LL2CLK 58 23 HIN INTERLACED 59 22 VIN HOUT 60 21 SDA VOUT 61 20 SCL HREF 62 19 TESTIN YOUT7 63 18 TESTEN YOUT6 64 17 TESTO3 UEP10014 TESTO2 YOUT0 VSS TESTO1 YOUT1 9 10 11 12 13 14 15 16 TESTO0 YOUT2 8 UVOUT4 7 UVOUT5 6 UVOUT6 5 UVOUT7 4 VDD 3 YOUT3 2 YOUT5 VSS 1 YOUT4 SDA 9255 Figure 1 Semiconductor Group 6 1998-02-01 SDA 9255 1.4 Pin Description Pin No. Type Description 2,8,24,26,41,55, VSS 57 S Supply voltage (VSS = 0 V) 9,25,40,56 VDD S Supply voltage (VDD = 5 V) 42,...,49 YIN0 ... 7 I/TTL Data input Y (see data format) 36,...,39 UVIN4 ... 7 I/TTL Data input UV (see data format) 30 SYNCEN I/TTL Synchronization enable input 31 RESET I/TTL System reset. The RESET input is low active. In order to ensure correct operation a "Power On Reset" must be performed. The RESET pulse must have a minimum duration of two clock periods of the system clock (LL2CLK). 23 HIN I/TTL H-Sync input 22 VIN I/TTL V-Sync input 21 SDA I/O 20 SCL I 19 TESTIN I/TTL 18 TESTEN I/TTL 13,...,10 UVOUT4 ... 7 O/TTL 7,...,3,1,64,63 YOUT0 ... 7 O/TTL 62 HREF O/TTL 61 VOUT O/TTL 60 HOUT O/TTL 59 INTERLACED O/TTL 58,51 LL2CLK I/TTL 50 TEST I/TTL 27,28,29, 52,53,54 TESTO 4...9 O I2C-Bus data line I2C-Bus clock line Test input, connect to VSS for normal operation Test enable input, connect to VSS for normal operation Data output UV (see data format) Data output Y (see data format) Horizontal active video output V-Sync output H-Sync output Interlace signal for AC coupled vertical deflection System clock Test input, connect to VSS for normal operation Do not connect, Pins have to be left open 14,15,16,17 TESTO 0...3 O Not used output stages, do not connect to any other driver, VSS or VDD ; Pins can be left open 32,33,34,35 TESTI 0...3 I Input stages (internal pull-down); Pins can be left open S: supply, Name I: input, Semiconductor Group O: output, TTL: digital (TTL) 7 1998-02-01 SDA 9255 1.5 Block Diagram VDD VSS SDA SCL Ι 2 C-Bus Interface Memory Controller Form UVOUT Field Memory Upconversion Vertical Zooming Panning YOUT INTERLACED UVIN Reform Noise Reduction HOUT Sync Signal Generator YIN VOUT HREF VIN SYNCEN UEB10013 HIN Figure 2 Semiconductor Group 8 1998-02-01 SDA 9255 2 System Description The device generates at its output an opportune sequence of 100/120 Hz fields (ααββ) [50/60 Hz frames (αβ)] derived by processing the field A or B which is stored in one internal field memory. The fields can be noise reduced and vertically zoomed. Additionally the device generates a vertical sync pulse, a horizontal sync pulse and a horizontal reference signal (horizontal active video output) in phase with the output data. Furthermore an interlace signal for AC coupled vertical deflection is available. 2.1 Input Data Formats The SDA 9255 accepts at the input side the following input format (relations of Y : (B-Y) : (R-Y) : 4 : 1 : 1). The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned) or two's complement code (TWOIN, TWOOUT, subaddress 00H, see description of I2C Bus). Data Pin SDA 9255 YIN7 Y07 Y17 Y27 Y37 YIN6 Y06 Y16 Y26 Y36 YIN5 Y05 Y15 Y25 Y35 YIN4 Y04 Y14 Y24 Y34 YIN3 Y03 Y13 Y23 Y33 YIN2 Y02 Y12 Y22 Y32 YIN1 Y01 Y11 Y21 Y31 YIN0 Y00 Y10 Y20 Y30 UVIN7 U07 U05 U03 U01 UVIN6 U06 U04 U02 U00 UVIN5 V07 V05 V03 V01 UVIN4 V06 V04 V02 V00 XAB: X: signal component, A: sample number, B: bit number The amplitude resolution for each input signal component is 8 Bit, the maximum clock frequency is 27 MHz. Semiconductor Group 9 1998-02-01 SDA 9255 2.2 Output Data Formats Data Pin YOUT7 Y07 Y17 Y27 Y37 YOUT6 Y06 Y16 Y26 Y36 YOUT5 Y05 Y15 Y25 Y35 YOUT4 Y04 Y14 Y24 Y34 YOUT3 Y03 Y13 Y23 Y33 YOUT2 Y02 Y12 Y22 Y32 YOUT1 Y01 Y11 Y21 Y31 YOUT0 Y00 Y10 Y20 Y30 UVOUT7 U07 U05 U03 U01 UVOUT6 U06 U04 U02 U00 UVOUT5 V07 V05 V03 V01 UVOUT4 V06 V04 V02 V00 XAB: X: signal component, 2.3 Input Timing and Parameter A: sample number, B: bit number The SDA 9255 has five input signals: HIN Pin 23 Horizontal synchronization signal - low or high active VIN Pin 22 Vertical synchronization signal - low or high active SYNCEN Pin 30 Enable signal for HIN and VIN signal, low active YIN0 ... 7 Pin 42, 43, 44, 45, 46, 47 ,48, 49 Luminance input UVIN4 ... 7 Pin 36, 37, 38, 39 Chrominance input The SDA 9255 includes a V-Sync delay block.This is implemented to make sure that the field identification is working correctly. This is briefly described below. The phase relation of the incoming horizontal synchronization signal (HIN) and the incoming data for HSINP = 0 and VSINP = 0 is shown in figure 7 (see chapter 5.1, Input Timing of the SDA 9255 (HSINP = 0)). The SDA 9255 needs the synchronization enable input (SYNCEN) which is used to gate HIN and VIN. This is implemented for frontends which are working with 13.5 MHz and a large output delay time for H-Sync and Semiconductor Group 10 1998-02-01 SDA 9255 V-Sync (e.g. Intermetall VPC3200A, output delay: 35 ns). For this application the half system clock (13.5 MHz) from the frontend should be provided at this pin. In case the frontend is working at 27.0 MHz with sync signals whose delay time are smaller than 25 ns, this input can be set to low level (SYNCEN = VSS) (e.g. Siemens SDA 9257, SDA 9206, output delay: 25 ns). Thus the falling edge of HIN signal is detected when the SYNCEN input is low. The incoming HIN (and VIN) is sampled with the system clock (LL2CLK = 27.0 MHz). The register value HSDLY and MCNAPIP (subaddress 0BH and 0CH, see description of I2C Bus) have to be adjusted in the way that the distance from the falling edge of the HIN to the first active pixel is correct. The half, quarter and eighth system clock is also shown in this diagram. They are generated inside the SDA 9255. The half system clock (LL_CLK = 13.5 MHz) is used to sample the incoming YUV data and run some blocks inside the SDA 9255. The quarter system clock (LH_CLK = 6.75 MHz) is used to run some blocks inside the SDA 9255. The eighth system clock (LQ_CLK = 3.375 MHz) is used to synchronize the 4:1:1 input data stream. The setting of the register HSDLY and MCNAPIP is explained in chapter 1. The SDA 9255 has a fixed number of active pixels per input line. It is fixed to 720 luminance pixels and 180 chrominance pixels. 2.3.1 Delay of Vertical Input Synchronization Signal In order to have always the same raster of the vertical and horizontal synchronization signal inside the SDA 9255 it is possible to shift the V-Sync signal. The subaddress 09H of the SDA 9255 (VSDLY, see description of I2C Bus) controls the shift of the V-Sync. The user has to know the input sync raster and then the user can adjust the VSDLY register value in the way that the field identify circuit inside the SDA 9255 can work properly. The adjustment of the V-Sync can be done in steps of 32 clock periods (LL2CLK). Thus the delay is also dependent on the system clock frequency. The formula to calculate the delay is shown below. DELAY (VIN to VS_int) = (VSDLY * 32 + 7 ... 11) * TLL2CLK where: VIN: VS_int: TLL2CLK : Incoming V-Sync at pin 22; VSDLY: is the register value Internal V-Sync System clock period (e.g 1/27.0 MHz = 37.04 ns) The initial delay (7 ... 11 system clocks) is caused by flip-flops at the input. This delay is not a fixed number, because a quarter of the system clock (LH_CLK) is used to set the delay. The phase of the LH_CLK is dependent on the RESET and the SYNCEN (see figure 7). An example shows figure 9 (see chapter 5.3, Internal Vertical Synchronization Signal (VSINP = 0)). In this example the falling edge of the VIN signal of field A is at 35 µs and the falling edge of the VS_int signal is at 16 µs (both signals are related to the falling Semiconductor Group 11 1998-02-01 SDA 9255 edge of the previous HS_int, compare chapter 1). Thus the sampling points of the field identify circuit (marked in the diagram with „a“ and „b“) have uniform distances to the falling edge of the VS_int. The falling edge of the VIN signal of field B is at 3 µs and the falling edge of the VS_int signal is at 48 µs (related to the falling edge of the previous HIN). Here the sampling points have also uniform distances to the falling edge of the VS_int signal. The user should adjust this value carefully. Dependent on the input mode of the frontend circuit the integration time of the V-Sync can change. For non-standard signals, for instance, a shorter integration time may be chosen. The internal V-Sync (VS_int) must have the falling edge at line 2 for field A. All the other settings (NALIP ...) are dependent on this internal V-Sync. The default setting of the VSDLY is 3AH. This corresponds to a delay of about 69 µs (58 (= 3AH) * 32 * 37 ns), which suits for the clock sync generator SDA 9257 and SDA 9206. 2.3.2 Number of Active Lines of an Input Field The subaddress 0AH (AL, see description of I2C Bus) is used to adjust the number of active lines per input and output field. It is independent of the MODE10050 in subaddress 00H. The register value AL has to be chosen in the following way: Number of lines per field – 2 288 – 2- = 143 AL = -------------------------------------------------------------------------- ; e.g. ----------------- 2 2 2.3.3 Number of Not Active Lines of an Input Field Due to the fact that the SDA 9255 stores only the active field in the field memory, it requires the information of the start of the active field and the active line. A not-activeline counter (NALIP, subaddress 0BH, see description of I2C Bus) starts counting the incoming H-Syncs when it detects a falling edge of the VS_int signal. If VS_int is adjusted as recommended in the explanation of subaddress 09H then the calculation of the NALIP value can be done in the following way: NALIP = first active line of field A – 5 (e.g. 23 – 5 = 18) In figure 10 (see chapter 5.4, Example for Not Active Input Register) an example for NALIP = 18 is shown. As you can see for field A 21 H-Syncs are counted and for field B 22 H-Syncs are counted. If NALIP is set to '0' line 5 is the first active line of field A and line 318 the first active line of field B (318 – 5 = 313). The difference between first active line of field B and field A should be: δ = (No.lines per frame DIV 2) + 1; e.g. δ = 625 DIV 2 + 1 = 313 Semiconductor Group 12 1998-02-01 SDA 9255 2.3.4 Not Active Pixels of Input Field In the SDA 9255 an H-Sync delay circuit is implemented. The output of this block is the HS_int. The distance of the incoming H-Sync (HIN, falling edge for HSINP = 0) and the active data is adjustable by the HSDLY register value and the MCNAPIP register value (subaddress 0BH and 0CH, see description of I2C Bus). With the HSDLY register the delay of the external (HIN) to the internal H-Sync (HS_int) is adjustable. DELAY (HIN to HS_int) = (HSDLY * 64 + 4) * TLL2CLK This internal H-Sync (HS_int) is fed to the memory control unit. The MCNAPIP (memory controller not active pixel at input) is used to adjust the distance to the active line in steps of one system clock period. So the MCNAPIP is used to set the phase of the internal generated clocks LL_CLK, LH_CLK and LQ_CLK. DELAY (HS_int to active data) = (MCNAPIP + 61) * TLL2CLK The total distance of the falling edge of the incoming H-Sync (HIN, falling edge for HSINP = 0) to the active data of the line is: DELAY (HIN to active data) = (HSDLY * 64 + MCNAPIP + 65) * TLL2CLK In the formula above you can see that the first active pixel occurs 65 system clocks after the falling edge of the HIN signal, if HSDLY and MCNAPIP are set to zero. In the figure 7 (see chapter 5.1, Input Timing of the SDA 9255 (HSINP = 0)) the input timing of the SDA 9255 is shown. The luminance and chrominance data are coming with half the system clock speed (e.g. 13.5 MHz). The SDA 9255 accepts the YIN data every second edge of the LL2CLK clock; in the SDA 9255 the luminance and chrominance data are sampled with the rising edge of the internal LL_CLK, which is half the system clock (e.g. 13.5 MHz). At the position of the first active pixel the phase of the half system clock (LL_CLK = 13.5 MHz), the quarter system clock (LH_CLK = 6.75 MHz) and the eighth system clock (LH_CLK = 3.375 MHz) is always as shown in the diagram. The LL_CLK is used for sampling the incoming data. The LQ_CLK is used to synchronize the 4:1:1 data stream. Semiconductor Group 13 1998-02-01 SDA 9255 2.4 Output Timing and Parameter The SDA 9255 has six output signals: HOUT Pin 60 Horizontal synchronization signal - high active VOUT Pin 61 Vertical synchronization signal - high active HREF Pin 62 Horizontal active video output INTERLACED Pin 59 Interlace signal YOUT0 ... 7 Pin 7, 6, 5, 4, 3, 1, 64, 63 Luminance output UVOUT4 ... 7 Pin 13, 12, 11, 10 Chrominance output There are different modes of output synchronization raster possible. The data output signal of the SDA 9255 (YOUT, UVOUT and HREF) are fed to the digital-to-analog converter. The timing of the output signals is given in figure 8 (see chapter 5.2, Output Timing of the SDA 9255). 2.4.1 Number of Not Active Lines of Output Field The register values NALOP and NAPOP are used to set the position of the active output field on the screen. To do this the register value to align the not active lines (NALOP, subaddress 0DH, see description of I2C Bus) and the register value to align the not active pixels (NAPOP, subaddress 0EH, see description of I2C Bus) for the output signal are available. To change the vertical position of the picture on the screen the NALOP register can be utilized. The NALOP register (not active lines for output) is used to adjust the number of not active output lines in steps of two lines in case of 100/120 Hz interlaced and in steps of four lines in case of 50/60 Hz proscan. To calculate the first active output line the following formula can be used: for MODE10050 = 0 ==> 100/120 Hz interlaced: FAOPL = NALOP * 2 + 3 for MODE10050 = 1 ==> 50/60 Hz proscan: FAOPL = NALOP * 4 + 5 where FAOPL: NAL_OP: The first active output line Register value The maximum value for the first active line is 65 for 100/120 Hz and 129 for 50/60 Hz. In figure 11 (see chapter 5.5, Example for Not Active Output Register) an example for the setting of the NALOP register is shown. The synchronization output (HOUT, Semiconductor Group 14 1998-02-01 SDA 9255 VOUT, HREF) signals are high active. In the example the register value is 10 and the mode is '0' (100/120 Hz/interlaced). FAOPL = NALOP * 2 + 3 = 10 * 2 + 3 = 23 So line 23 is the first active output line. For proper operation the number of not active lines at output side plus the number of active lines have to be smaller than the total number of lines. The following formula should be true. NALOP * 2 + AL * 2 + 3 ≤ (No. of lines per frame) DIV 2 (e.g. 312) where AL: NALOP: Register value Register value 2.4.2 Number of Not Active Pixels of Output Field To change the horizontal position of the picture on the screen the NAPOP register value can be utilized. The not active pixels for output register ( NAPOP ) is used to adjust the number of not active output pixels of a line. The register value is multiplied by '4' and has an initial value of 9 ... 12 (HSODLY = 0), depending on the MCNAPIP setting (subaddress 0BH and 0CH, see description of I2C Bus). FAOPP = NAPOP * 4 + 9 ... 12 – HSODLY = 0 FAOPP = NAPOP * 4 + (- 163) ... (- 160) ; HSODLY = 1 is equal to : FAOPP = NAPOP * 4 + 9 ... 12 – 172 * HSODLY where FAOPP: NAPOP: HSODLY: The first active output pixel after rising edge of HOUT Register value Register value The time from the rising edge of the HOUT signal to the first active output pixel can be calculated in the following way: tNAPOP = ( NAPOP * 4 + 9 ... 12 ) * tLL2CLK ; HSODLY = 0 tNAPOP = (NAPOP * 4 + (- 163) ... (-160)) * tLL2CLK ; HSODLY = 1 where tNAPOP : Time from rising edge of HOUT to first active output pixel tLL2CLK : System clock period (e.g. 1/27 MHz) figure 12 (see chapter 5.6, Example for Not Active Output Pixels) shows the effect of the register NAPOP. Semiconductor Group 15 1998-02-01 SDA 9255 2.4.3 VOUT, HOUT and HREF Signal Length The length of the output synchronization signals (HOUT, VOUT) is fixed. The HOUT signal is active high with a length of 32 system clocks (27.0 MHz) which corresponds to a length of 1.185 µs. The VOUT signal is also active high with a length of 2 output lines. So in case of PAL B/G the active high period of the VOUT lasts for 64 µs (see figure 13, Timing for HOUT Signal and figure 14, Timing for VOUT Signal). The HOUT signal of the SDA 9255 can be delayed by a fixed value of 172 system clocks (27.0 MHz) by setting the HSODLY bit of subaddress 0FH to ’1’(see description of I2C Bus). The number of active pixels per line is constant 720 pixels. The HREF output signal (pin 62) indicates the active part of the output lines. The length is also constant (720 system clocks). During the vertical and horizontal blanking period this signal is low. The timing is shown in figure 15 (see chapter 5.9, Timing for HREF Signal). The chrominance output format is like the output format as described in chapter 1. 2.4.4 Output Synchronization Raster and Interlaced Output Signal The output synchronization and data raster in 100/120 Hz mode can be set by the MODESYNC register value (subaddress 01H, see description of I2C Bus). In case of MODE10050 = 1 (50/60 Hz pro-scan mode) this register value has no effect. The interlaced signal INTERLACED (pin 59) is a control signal which may be used to control an AC coupled vertical deflection unit. If the MODESYNC register value (subaddress 01H, see description of I2C Bus) is set to AABB mode, where field 2 and 3 have to be shifted down (MODESYNC = 10). For this the interlaced register INTL (subaddress 0DH and 0EH, see description of I2C Bus) must be set to 0110. In figure 16 (see chapter 5.10, Example for INTERLACED Signal) an example for the INTL register value is shown. Bit zero defines the output for the first field (field A); bit one defines the output for the second field (field A); bit two defines the output of the third field (field B); bit three defines the output of the fourth field (field B). So if the bit is set to zero then the output is low and if the bit is set to one then the output is high. For DC coupled vertical deflection the INTERLACED signal is not required. Semiconductor Group 16 1998-02-01 SDA 9255 2.5 Motion Adaptive Temporal Noise Reduction Field Memory YIN/UVIN - + + + * k-factor LUT Address MDFORNR UEB10015 NRKF0 NRKF1 NRKF2 NRKF3 Figure 3 Block Diagram of Noise Reduction The diagram above shows a block diagram of the motion adaptive noise reduction. The noise reduction in the luminance path has the same structure as the noise reduction in the chrominance path. Subaddresses 02H and 03H (NRKF0, NRKF1, NRKF2, NRKF3, see description of I2C Bus) are used to align the filter coefficients of the noise reduction IIR filter. Four different k-factors NRKF0 ... 3 can be modified which are fed to the multiplier of the IIR filter. Depending on the output of the motion detection for noise reduction (MDFORNR) the corresponding k-factor NRKF0 ... 3 is used for the IIR filter (see the table below). Semiconductor Group 17 1998-02-01 SDA 9255 Table 1 MDFORNR and Corresponding k-Factor MDFORNR k-Factor Mode 0 NRKF0 Still 1 NRKF1 Quasi still 2 NRKF2 Quasi motion 3 NRKF3 Motion For NRKF0 ... 3 values between 0 and 7 can be chosen. The following table shows the theoretical amount of noise reduction dependent on the applied k-factor. Table 2 Filter Coefficients Dependent on the k-Factor k-Factor Amount of NR 0 0 dB 1 1.1 dB 2 2.2 dB 3 3.4 dB 4 4.8 dB 5 6.4 dB 6 8.5 dB 7 11.8 dB The subaddresses 04H, 05H and 06H (MDNRTH0, MDNRTH1, MDNRTH2, see description of I2C Bus) are used to align the motion detection for noise reduction (MDFORNR). The sensitivity of the motion detection is influenced by changing the threshold levels of the motion values. A rough block diagram of the motion detection for noise reduction is shown below. Semiconductor Group 18 1998-02-01 SDA 9255 Noise Reduction Field Memory DYIN MDNRTH0 MDNRTH1 MDNRTH2 + Low Pass Filter 1 ABS LIMITER THRESHOLD 0 MDFORNR MUX MUX FNR 0 NRHF 1 SNR UEB10016 YIN Figure 4 Block Diagram of Motion Detection for Noise Reduction The input signals for the motion detection for noise reduction are the just incoming luminance signal (YIN) and the already noise reduced luminance signal on one field delay (DYIN). Both signals are fed to a subtractor, followed by a low pass filter. This filter can be bypassed by setting the NRHF bit (see description subaddress 08H, Bit 0) to ’0’. The absolute value is calculated and given to a limiter block. The output signal is fed to the threshold block, where the value is quantized by using the 3 threshold values MDNRTH0, MDNRTH1 and MDNRTH2. The quantization characteristic of the threshold block is shown by the following table and diagram. Table 3 Quantization Table of MDFORNR Input Value Output Mode 0 ... (TH0 – 1) 0 Still TH0 ... (TH1 – 1) 1 Quasi still TH1 ... (TH2 – 1) 2 Quasi motion TH2 ... 31 3 Motion Semiconductor Group 19 1998-02-01 SDA 9255 3 2 1 0 ~ ~ MDNRTH0 MDNRTH1 MDNRTH2 31 UEB10017 0 Figure 5 Quantization Characteristic of MDFORNR The following table shows an example for noise reduction settings. These five settings could be implemented and the customer can choose, which he prefers. For example, to have a subjective impression of medium noise reduction of the picture, you have to set the k-factors: NRKF0 = 4, NRKF1 = 3, NRKF2 = 2, NRKF3 = 0 and MDNRTH0 = 4, MDNRTH1 = 8 and MDNRTH2 = 12. Table 4 Example for Noise Reduction Settings Amount of Noise Reduction Parameter No Slightly Medium Strong Heavy NRKF0 0 3 4 7 7 NRKF1 0 2 3 4 5 NRKF2 0 1 2 2 3 NRKF3 0 0 0 0 1 MDNRTH0 don’t care 2 4 4 4 MDNRTH1 don’t care 6 8 10 10 MDNRTH2 don’t care 10 12 14 16 Semiconductor Group 20 1998-02-01 SDA 9255 2.6 Digital Vertical Zooming and Panning The user can choose 17 different zoom factors and 37 pan factors. Every zoom factor can be used without considering other register values, but on the other hand the pan factor is very much dependent on the zoom factor. So be careful in choosing the pan factor. In the following table the zoom factor (subaddress 0FH, see description of I2C Bus) and the corresponding visual zoom of the input field is shown. In the third column the required number of input lines is shown, when the number of displayed output lines is 288. The fourth column shows the allowed value PAN value (subaddress 10H, see description of I2C Bus) and the last column the PAN register value for vertical centre position. Table 5 Table of Zoom Factors and Panning Factors Zoom Visual Zoom NoIPL (NoOPL = 288) Panning Range Centre Panning PAN PAN 16 1 288 0 0 15 1.03 279 0 ... 2 1 14 1.06 270 0 ... 4 2 13 1.10 261 0 ... 6 3 12 1.14 252 0 ... 9 4 11 1.18 243 0 ... 11 5 10 1.23 234 0 ... 13 6 9 1.28 225 0 ... 15 7 8 1.33 216 0 ... 18 8 7 1.39 207 0 ... 20 10 6 1.45 198 0 ... 22 11 5 1.52 189 0 ... 24 12 4 1.6 180 0 ... 27 13 3 1.68 171 0 ... 29 14 2 1.77 162 0 ... 31 15 1 1.88 153 0 ... 33 17 0 2.0 144 0 ... 36 18 Dependent on the zoom factor the SDA 9255 requires a certain number of input lines of a field. Semiconductor Group 21 1998-02-01 SDA 9255 ZOOM × 2 + 32 NoIPL = NoOPL × ----------------------------------------64 where NoIPL: NoOPL: ZOOM: Number of required input lines Number of generated output lines (AL * 2) + 2 Register value (0 ... 16) In the third column of the table above the required number of input lines is shown, if the generated number of output lines is 288 (AL = 143). In the last row you can see that for the visual zoom factor of 2 half the number of input lines is necessary, which is of course obvious. As mentioned before, only zoom factors between '0' and '16' are allowed. If factors bigger than 16 are chosen, they are set to '16'. Panning is possible in steps of 4 input lines. So the first active input line which is used to generate the first active output line can be calculated in the following way: FAIPL = PAN * 4 + 1 where FAIPL: First active input line to generate the first active output line PAN: Register value With PAN = 0 the first active input line is line 1, as expected. In case of PAN = 1 the first active input line is line 5, etc. So the allowed register value for pan can be calculated from the last column of the table above. In this example with 288 active lines and, for instance, zoom factor of '15', the maximum pan factor is '2'. Pan = '3' is permitted which can be seen by this calculation: 3 * 4 + 279 = 291. The required number of input lines plus the panning lines is larger than the actual number of input lines (288). A formula to calculate the maximum pan factor is shown below. NoOPL – NoIPL PAN ≤ int --------------------------------------------- 4 After some rearranging of the formula we get this simple formula to calculate the maximum register value of the pan factor. NoOPL 16 – ZOOM PAN ≤ int --------------------- × ------------------------------- 8 16 where NoIPL: NoOPL: Number of required input lines Number of generated output lines (AL * 2) + 2 Semiconductor Group 22 1998-02-01 SDA 9255 ZOOM: PAN: Register value (0 ... 16) Register value (0 ... 63) In the fourth column of table 5 the panning range is shown for NoOPL = 288. If the pan factor is larger than specified in the previous equation, the last input line is used for interpolation of the remaining lines. On the screen the last line is repeated. I2C Bus 2.7 2.7.1 I2C-Bus Slave Address Write Address: BCH Read Address: BDH 1 0 1 1 1 1 0 2.7.2 I2C-Bus Format The SDA 9255 I2C-Bus interface acts as a slave receiver and a slave transmitter and provides three different access modes (write, read, continuous read). All modes run with a subaddress auto increment. The interface supports the normal 100 kHz transmission speed as well as the high speed 400 kHz transmission. Write: S 1 0 1 1 1 1 0 0 A S: A: P: NA: Subaddress A Data Byte A ***** A P Start condition Acknowledge Stop condition Not Acknowledge Read: S 1 0 1 1 1 1 0 0 A Subaddress A S 1 0 1 1 1 1 0 1 A Data Byte A Data Byte ***** NA P Continuous Read: S 1 0 1 1 1 1 0 1 A Data Byte A ***** Data Byte NA P The transmitted data are internally stored in registers. The master has to write a don’t care byte to the subaddress FFH (store command) to make the register values available for the SDA 9255. To have a defined time step, where the data will be available, the data are made valid with the incoming V-Sync or with the next SYNC_ST pulse, which is an internal signal and indicates the start of a new output cycle of either four fields in 100/ 120 Hz interlaced mode or two frames in 50/60 Hz proscan mode. The subaddresses, where the data are made valid with the V-Sync (every 20 ms) are indicated in the overview of the subaddresses with „V“, where the data are made valid with the Semiconductor Group 23 1998-02-01 SDA 9255 SYNC_ST (every 40 ms) are indicated with „S“. The Ι2C-Bus status bits of the SDA 9255 (sub19H, Bit 7; sub1EH, Bit 7) reflect the state of the register values. If these bits are read as ’0’ then the store command was sent, but the data aren’t made available yet. If these bits are ’1’ then the data were made valid and a new write or read cycle can start. The I2C-Bus status bits have to be checked before writing or reading new data, otherwise data can be lost by overwriting. After switching on the IC, all bits of the SDA 9255 are set to defined states. In particular: Subaddress Default Value R/W Take Over Subaddress Default Value R/W Take Over 00H 6FH R/W S 0CH A2H R/W V 01H 56H R/W S 0DH 50H R/W S 02H 68H R/W V 0EH 2CH R/W S 03H 23H R/W V 0FH 81H R/W S 04H 10H R/W V 10H 00H R/W S 05H 30H R/W V 11H ... 18H not used R/W 06H 50H R/W V 19H 07H not used R/W 08H 61H R/W V 1EH 09H 74H R/W V 1FH ... FEH 0AH 8FH R/W V FFH 0BH 94H R/W V R/W: Take over: 1AH ... 1DH R not used R/W R not used R/W W R-Read Register, W-Write Register, R/W-Read and Write Register, V-take over with V-Sync, S-take over with SYNC_ST Semiconductor Group 24 1998-02-01 SDA 9255 2.7.3 I2C-Bus Commands Data Byte Subadd. (Hex.) D7 D6 D5 D4 D3 D2 D1 D0 TVMODE1 TVMODE0 00H MODE10050 1 1 FREEZE TWOIN TWOOUT 01H 0 1 0 1 0 MODESYNC1 MODESYNC0 0 02H NRKF02 NRKF01 NRKF00 NRKF12 NRKF11 NRKF10 x x 03H NRKF22 NRKF21 NRKF20 NRKF32 NRKF31 NRKF30 HSINP VSINP 04H MDNRTH04 MDNRTH03 MDNRTH02 MDNRTH01 MDNRTH00 x x x 05H MDNRTH14 MDNRTH13 MDNRTH12 MDNRTH11 MDNRTH10 x x x 06H MDNRTH24 MDNRTH23 MDNRTH22 MDNRTH21 MDNRTH20 x x x 08H SNR FNR1 FNR0 x x x x NRHF 09H VSDLY6 VSDLY5 VSDLY4 VSDLY3 VSDLY2 VSDLY1 VSDLY0 x 0AH AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 0BH NALIP4 NALIP3 NALIP2 NALIP1 NALIP0 MCNAPIP6 MCNAPIP5 MCNAPIP4 0CH MCNAPIP3 MCNAPIP2 MCNAPIP1 MCNAPIP0 HSDLY3 HSDLY2 HSDLY1 HSDLY0 0DH NALOP4 NALOP3 NALOP2 NALOP1 NALOP0 INTL3 INTL2 INTL1 0EH NAPOP6 NAPOP5 NAPOP4 NAPOP3 NAPOP2 NAPOP1 NAPOP0 INTL0 0FH ZOOM4 ZOOM3 ZOOM2 ZOOM1 ZOOM0 x x HSODLY 10H PAN5 PAN4 PAN3 PAN2 PAN1 PAN0 x x 19H VSTATUS x x x x x x x 1EH SSTATUS x x x x x x x FFH x x x x x x x x x = don’t care Semiconductor Group 25 1998-02-01 SDA 9255 2.7.4 Detailed Description Subaddress 00H Bit Name Function D7 MODE10050 Output mode switch: 0: 100/120 Hz (default value) 1: 50/60 Hz D6 1: Should be set to 1 D5 1: Should be set to 1 D4 FREEZE Still picture: 0: Off (default value) 1: On D3 TWOIN Chrominance input format: 0: Unsigned input (0 ... 255) 1: 2’s complement input (-128 ... 127) (default value) Inside the SDA 9255 the data are always processed as unsigned data D2 TWOOUT Chrominance output format: 0: Unsigned output (0 ... 255) 1: 2’s complement output (-128 ... 127) (default value) D1 ... D0 TVMODE Semiconductor Group Television system: 00: NTSC (1716) 01: Automatic PAL (n * 32) 10: Automatic NTSC (n * 32 + 20) 11: PAL (1728) (default value) The SDA 9255 is designed for a line-locked system. Therefore the number of system clock periods between two H-Sync (HIN) must be constant. In PAL (1728) mode the number of system clocks (~27.0 MHz) per input line is assumed to be constant 1728. In case of NTSC (1716) mode the number of system clock periods is assumed to be constant 1716. In automatic mode (01 and 10) the number of system clock periods (~27.0 MHz) per incoming line is measured and used to calculate the outgoing line length. In automatic PAL mode the number of system clock periods between two H-Syncs must be n * 32 (n = 1, 2, ..., 54, ...). In automatic NTSC mode the number of system clock periods between two H-Syncs must be n * 32 + 20 (n = 1, 2, ..., 53, ...). 26 1998-02-01 SDA 9255 Subaddress 01H Bit Name Function D7 ... D3 Should be set to 01010 D2 ... D1 MODESYNC Output synchronization mode: 00: Reserved 01: AABB mode for AC coupled vertical deflection, no data shift 10: AABB mode for AC coupled vertical deflection, field 2 and 3 shift down 11: AABB mode for DC coupled vertical deflection (default value) D0 0: Should be set to 0 Subaddress 02H Bit Name Function D7 ... D5 NRKF0 Noise Reduction k-factor KF 0: 011: (default value) D4 ... D2 NRKF1 Noise Reduction k-factor KF 1: 010: (default value) D1 ... D0 xx Semiconductor Group 27 1998-02-01 SDA 9255 Subaddress 03H Bit Name Function D7 ... D5 NRKF2 Noise Reduction k-factor KF 2: 001: (default value) D4 ... D2 NRKF3 Noise Reduction k-factor KF 3: 000: (default value) D1 HSINP H-Sync input polarity: 0: Low active 1: High active (default value) D0 VSINP V-Sync input polarity: 0: Low active 1: High active (default value) Subaddress 04H Bit Name Function D7 ... D3 MDNRTH0 Noise Reduction threshold 0: 00010: (default value) D2 ... D0 xxx Subaddress 05H Bit Name Function D7 ... D3 MDNRTH1 Noise Reduction threshold 1: 00110: (default value) D2 ... D0 xxx Subaddress 06H Bit Name Function D7 ... D3 MDNRTH2 Noise Reduction threshold 2: 01010: (default value) D2 ... D0 xxx Semiconductor Group 28 1998-02-01 SDA 9255 Subaddress 08H Bit Name Function D7 SNR Switch for fixed value for motion detection for noise reduction 0: Off (default value) 1: On D6 ... D5 FNR Fixed value for motion detection for noise reduction 11: (default value) D4 ... D1 xxxx D0 NRHF Switch for low pass filter for motion detection for noise reduction 0: Off 1: On (default value) Subaddress 09H Bit Name Function D7 ... D1 VSDLY V-Sync input delay (default value 3AH) D0 x Subaddress 0AH Bit Name D7 ... D0 AL Function (Number of active input lines per field – 2) / 2 (default value 8FH) Subaddress 0BH Bit Name D7 ... D3 NALIP Function Number of not active lines of input data (default value 12H) D2 ... D0 MCNAPIP6 ... 4 Number of system clocks from internal HS_int to active input data, Bit 6 to 4 (default value 4H) Semiconductor Group 29 1998-02-01 SDA 9255 Subaddress 0CH Bit Name Function D7 ... D4 MCNAPIP3 ... 0 Number of system clocks from internal HS_int to active input data, bit 3 to 0 (default value AH) D3 ... D0 HSDLY H-Sync input delay (default value 2H) Subaddress 0DH Bit Name Function D7 ... D3 NALOP Number of active lines at output (default value AH) D2 ... D0 INTL3 ... 1 Interlace output for field Bit 3 to 1 (default value 0H) Subaddress 0EH Bit Name Function D7 ... D1 NAPOP Number of not active pixels at output (default value 16H) D0 Interlace output for field bit 0 (default value 0H) INTL0 Subaddress 0FH Bit Name Function D7 ... D3 ZOOM Zooming factor (default value 10H) D2 ... D1 xx D0 HSODLY Delay of H-Sync output (default value 1H) Subaddress 10H Bit Name Function D7 ... D2 PAN Panning of the output picture (default value 0H) D1 ... D0 xx Semiconductor Group 30 1998-02-01 SDA 9255 Subaddress 19H Bit Name Function D7 VSTATUS Status bit for subaddresses, which will be made valid by VSync D6 ... D0 xxxxxxx Subaddress 1EH Bit Name Function D7 SSTATUS Status bit for subaddresses, which will be made valid by SYNC_ST D6 ... D0 xxxxxxx Subaddress FFH Bit Name D7 ... D0 Semiconductor Group Function Store command for all subaddresses, xxxxxxxx 31 1998-02-01 SDA 9255 3 Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. 0 70 °C -65 125 °C Junction temperature 125 °C Soldering temperature 260 °C Soldering time 10 s V Operating temperature TA Storage temperature Input voltage -0.3 Output voltage -0.3 VDD + 0.3 VDD + 0.3 -0.3 6 V 1.2 W Supply voltages VDD Total power dissipation Remark V ESD protection -2 2 kV MIL STD 883C method 3015.6, 100 pF, 1500 Ω Latch-up protection -100 100 mA All inputs/outputs All voltages listed are referenced to ground (0 V, VSS) except where noted. Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. Semiconductor Group 32 1998-02-01 SDA 9255 3.1 Recommended Operating Conditions Parameter Symbol VDD Ambient temperature TA Supply voltages Limit Values Unit min. nom. max. 4.75 5 5.25 V 0 25 70 °C Remark All TTL Inputs H-input voltage L-input voltage VIH VIL 2.0 VDD V 0 0.8 V VQH VQL 2.4 All TTL Outputs H-output voltage L-output voltage 0.4 V IQH = -2.0 mA IQL = 3.0 mA 0.5 V at IQL = max MHz see figure 19 V INPUT/OUTPUT: SDA L-output voltage VQL Clock TTL Input LL2CLK Clock frequency 1/T Low time tWL tWH tTLH tTHL High time Rise time Fall time 27 12 ns 12 ns 5 ns 5 ns I2C Bus (All values are referred to min (VIH) and max (VIL)), fSCL = 400 KHz VIH L-input voltage VIL SCL clock frequency fSCL Inactive time before tBUF H-input voltage 3 VDD V see figure 17 0 1.5 V see figure 18 0 400 kHz 1.3 µs start of transmission Set-up time start condition tSU; STA 0.6 µs Hold time start condition tHD; STA 0.6 µs SCL low time tLOW tHIGH tSU; DAT tHD; DAT 1.3 µs 0.6 µs 100 ns 0 µs SCL high time Set-up time DATA Hold time DATA Semiconductor Group 33 1998-02-01 SDA 9255 3.1 Recommended Operating Conditions (cont’d) Parameter Symbol Limit Values min. SDA/SCL rise times SDA/SCL fall times Set-up time stop condition Output valid from clock tR tF tSU; STO nom. 3.2 Remark max. 300 ns 300 ns µs 0.6 tAA Input filter spike tSP suppression (SDA and SCL pins) L-output current Unit IQL 900 ns 50 ns 3 mA Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Limit Values min. Average supply current Unit Remark 200 mA All VDD pins, typ. 170 mA 10 pF 10 µA max. ICC All Digital Inputs (Including I/O Inputs) CI Input leakage current II(L) Input capacitance -10 TTL Inputs: YIN, UVIN (Referred to LL2CLK) Set-up time Input hold time tSU tIH 0 ns 25 ns TTL Inputs: HIN, VIN, SYNCEN (Referred to LL2CLK) Set-up time Input hold time tSU tIH 7 ns 6 ns TTL Outputs: YOUT, UVOUT, HOUT, VOUT, HREF, INTERLACED (Referred to LL2CLK) Hold time Delay time Semiconductor Group tQH tQD 6 ns 25 ns 34 CL = 30 pF 1998-02-01 SDA 9255 4 Application Information 27.0 MHz CLK CLK YI 12 YUV UI VI 3ADC CSG SDA 9206 12 YUV 13.5 MHz HIN, VIN Scan Rate Converted HREF SDA 9255 YOUT Display Processor UOUT SDA 9280 27.0 MHz VOUT CVBS/ SYNC UES10018 HOUT, VOUT Figure 6 Semiconductor Group 35 1998-02-01 SDA 9255 5 Waveforms 5.1 Input Timing of the SDA 9255 (HSINP = 0) t IH ~ ~ ~ ~ LL2CLK HSIN t SU HS_int (HS_DLY x 64 + 4) x t LL2CLK LLCLK LH_CLK (MC_NAP_OP + 61) x t LL2CLK LQ_CLK t IH D/YIN XXXX Y0 t SU Y1 Y2 Y3 Y4 D/UVIN XXXX C0 C1 C2 C3 C4 UET10019 (HS_DLY x 64 + MC_NAP_IP + 65) x t LL2CLK Figure 7 Semiconductor Group 36 1998-02-01 SDA 9255 5.2 Output Timing of the SDA 9255 ~ ~ ~ ~ LL2CLK HOUT (NAPOP x 4 + 9...12 HSODLY x 172) x t LL2CLK HREF Black Y1 Y2 Y3 C0 C1 C2 C3 Y716 Y717 Y718 Y719 Default Value C716 C717 C718 C719 Default Value ~ ~ Y0 ~ ~ Default Value 16 Default Value 0 (128) Uncoloured ~ ~ UVOUT UET10020 ~ ~ YOUT Figure 8 5.3 Internal Vertical Synchronization Signal (VSINP = 0) Line 625 Line 1 Field A Line 2 Line 3 HS_int VIN DELAY(VIN to VS_int) VS_int a b Line 313 Line 314 a b Sample Points of Field Ident Field B a Line 316 Line 315 HS_int VIN VS_int a b a b a UET10021 DELAY(VIN to VS_int) Figure 9 Semiconductor Group 37 1998-02-01 SDA 9255 5.4 Example for Not Active Input Register VS_int Line 625 Line 2 Line 3 Line 313 Line 314 Line 315 Line 22 Line 23* ) Line 24 Line 25 Line 335 Line 336* ) Line 337 Line 338 ~ ~ Line 1 HN VS_int Line 312 ~ ~ UET10022 HN * ) : First active line of a field Figure 10 5.5 Example for Not Active Output Register Line 1 Line 2 Line 3 Line 21 Line 22 Line 23 Line 24 ~ ~ HREF ~ ~ HOUT ~ ~ VOUT First Active Output Line Black ~ ~ UET10023 Default Value 16 ~ ~ YOUT 38 1998-02-01 UVOUT Default Value 0 (2’s Complement) or 128 (Unsigned) Uncoloured Figure 11 Semiconductor Group SDA 9255 5.6 Example for Not Active Output Pixels ~ ~ LL2CLK HOUT (NAPOP x 4 + 9...12 - HSODLY x 172) x t LL2CLK t QH HREF YOUT UVOUT Default Value 16 Default Value 0 (128) Black Uncoloured Y0 Y1 Y2 Y3 Y4 Y5 C0 C1 C2 C3 C4 C5 UET10024 t QD Figure 12 5.7 Timing for HOUT Signal ~ ~ ~ ~ LL2CLK HOUT UET10025 32 x t LL2CLK Figure 13 Semiconductor Group 39 1998-02-01 SDA 9255 5.8 Timing for VOUT Signal HOUT t HOUT VOUT UET10026 2 x t HOUT Figure 14 5.9 Timing for HREF Signal ~ ~ LL2CLK HREF ~ ~ Y0 Y1 Y2 Y3 Y4 UVOUT 0 (128) C0 C1 C2 C3 C4 Y713 Y714 Y715 Y716 Y717 Y718 Y719 16 C713 C714 C715 C716 C717 C718 C719 0 (128) ~ ~ 16 ~ ~ YOUT ~ ~ UET10027 720 x t LL2CLK Figure 15 Semiconductor Group 40 1998-02-01 SDA 9255 5.10 Example for INTERLACED Signal VOUT YUVOUT FIELD A INTL0 FIELD A FIELD B INTL1 FIELD B INTL2 INTL3 FIELD A INTL0 UET10028 INTERLACED Figure 16 5.11 I2C-Bus Timing START/STOP ~ ~ VHYS SCL t HD:STA t SU:STO t SU:STA ~ ~ SDA ~ ~ STOP UET10029 START Figure 17 Semiconductor Group 41 1998-02-01 SDA 9255 I2C-Bus Timing DATA 5.12 tF t LOW t HIGH t LOW tR SCL t SU:STA t HD:DAT t SU:STO t HD:STA t SU:DAT SDA IN t SP t AA t AA t BUF UET10030 SDA OUT Figure 18 5.13 Timing Diagram Clock T t WH t WL V IH LL2CLK t TLH V IL UET10031 t THL Figure 19 Semiconductor Group 42 1998-02-01 SDA 9255 6 Package Outlines +0.15 7˚ max H 0.88 ±0.15 0.8 0.3 0.15 +0.08 -0.02 2.45 max 2 +0.1 -0.05 0.25 min P-MQFP-64-1 (Plastic Metric Quad Flat Package) 12 0.2 0.1 C M A-B D C 64x 17.2 14 0.2 A-B D 64x 1) 0.2 A-B D H 4x D B 14 1) 17.2 A 1) 0.6 x 45˚ Does not include plastic or metal protrusions of 0.25 max. per side GPM05250 64 1 Index Marking Figure 20 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group Dimensions in mm 43 1998-02-01