a Quad, 12-Bit DAC Voltage Output with Readback DAC8412/DAC8413 FUNCTIONAL BLOCK DIAGRAM FEATURES +5 V to ⴞ15 V Operation Unipolar or Bipolar Operation True Voltage Output Double-Buffered Inputs Reset to Min (DAC8413) or Center Scale (DAC8412) Fast Bus Access Time Readback VLOGIC DATA I/O 12 VDD I/O PORT DGND A0 A1 APPLICATIONS Automatic Test Equipment Digitally Controlled Calibration Servo Controls Process Control Equipment R/W CONTROL LOGIC CS VREFH INPUT REG A OUTPUT REG A DAC A VOUTA INPUT REG B OUTPUT REG B DAC B VOUTB INPUT REG C OUTPUT REG C DAC C VOUTC INPUT REG D OUTPUT REG D DAC D VOUTD RESET LDAC VREFL GENERAL DESCRIPTION The DAC8412 and DAC8413 are quad, 12-bit voltage output DACs with readback capability. Built using a complementary BiCMOS process, these monolithic DACs offer the user very high package density. Output voltage swing is set by the two reference inputs VREFH and VREFL. By setting the VREFL input to 0 V and VREFH to a positive voltage, the DAC will provide a unipolar positive output range. A similar configuration with VREFH at 0 V and VREFL at a negative voltage will provide a unipolar negative output range. Bipolar outputs are configured by connecting both VREFH and VREFL to nonzero voltages. This method of setting output voltage range has advantages over other bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. VSS Digital controls allow the user to load or read back data from any DAC, load any DAC and transfer data to all DACs at one time. An active low RESET loads all DAC output registers to midscale for the DAC8412 and zero scale for the DAC8413. The DAC8412/DAC8413 are available in 28-lead plastic DIP, PLCC and LCC packages. They can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 V to ±15 V, and references from +2.5 V to ± 10 V. Power dissipation is less than 330 mW with ± 15 V supplies and only 60 mW with a +5 V supply. For MIL-STD-883 applications, contact your local ADI sales office for the DAC8412/DAC8413/883 data sheet which specifies operation over the –55°C to +125°C temperature range. All 883 parts are also available on Standard Military Drawings 5962-91 76401MXA through 76404M3A. 0.500 +125ⴗC LINEARITY ERROR – LSB 0.375 +25ⴗC 0.250 0.125 0 –55ⴗC –0.125 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = –55ⴗC, +25ⴗC, +125ⴗC –0.250 –0.375 –0.500 0 512 1024 1536 2046 2548 2560 DIGITAL INPUT CODE – Decimal 3072 4096 Figure 1. INL vs. Code Over Temperature REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 DAC8412/DAC8413–SPECIFICATIONS (@ V = +15.0 V, V = –15.0 V, V DD SS LOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V, ELECTRICAL CHARACTERISTICS –40ⴗC ≤ T ≤ +85ⴗC unless otherwise noted. See Note 1 for supply variations.) A Parameter Symbol Conditions Integral Nonlinearity Error INL INL DNL VZSE VFSE TCVZSE TCVFSE E Grade F Grade Monotonic Over Temperature RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ Adjacent DAC Matching Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Reference Low Input Current Large Signal Bandwidth Min Typ Max Units 0.25 ± 0.5 ±1 LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB –1 ±2 ±2 15 20 ±1 IREFH IREFL BW VREFL + 2.5 –10 –2.75 +1.5 0 +2 –3 dB, VREFH = 0 V to +10 V p-p 160 VDD – 2.5 VREFH – 2.5 +2.75 +2.75 V V mA mA kHz AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate Analog Crosstalk IOUT tS SR RL = 2 kΩ, CL = 100 pF –5 to 0.01%, 10 V Step, RL = 1 kΩ 10% to 90% +5 mA µs V/µs dB LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Output High Voltage Logic Output Low Voltage Logic Input Current Input Capacitance Digital Feedthrough3 VINH VINL VOH VOL IIN CIN TA = +25°C TA = +25°C IOH = +0.4 mA IOL = –1.6 mA Note 2 Note 2 2.4 0.8 2.4 0.4 1 8 5 VREFH = +2.5 V, VREFL = 0 V LOGIC TIMING CHARACTERISTICS 3 Chip Select Write Pulsewidth Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulsewidth Reset Pulsewidth Chip Select Read Pulsewidth Read Data Hold Read Data Setup Data to Hi Z Chip Select to Data tWCS tWS tWH tAS tAH tLS tLH tWDS tWDH tLDW tRESET tRCS tRDH tRDS tDZ tCSD SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation PSS IDD ISS PDISS 10 2.2 72 V V V V µA pF nV-s Note 4 tWCS = 80 ns tWCS = 80 ns tWCS = 80 ns tWCS = 80 ns tRCS = 130 ns tRCS = 130 ns CL = 10 pF CL = 100 pF 80 0 0 0 0 70 30 20 0 170 140 130 0 0 200 160 14.25 V ≤ VDD ≤ 15.75 V VREFH = +2.5 V –10 8.5 –6.5 150 12 330 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ppm/V mA mA mW NOTES 1 All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with nominal supplies. 2 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 3 All parameters are guaranteed by design. 4 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. –2– REV. D DAC8412/DAC8413 ELECTRICAL CHARACTERISTICS (@ VDD = VLOGIC = +5.0 V ⴞ 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = –5.0 V ⴞ 5%, VREFL = –2.5 V, –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted. See Note 1 for supply variations.) Parameter Symbol Conditions Integral Nonlinearity Error INL INL INL INL DNL VZSE VFSE VZSE VFSE TCVZSE TCVFSE E Grade F Grade VSS = 0.0 V; E Grade2 VSS = 0.0 V; F Grade2 Monotonic Over Temperature VSS = –5.0 V VSS = –5.0 V VSS = 0.0 V VSS = 0.0 V Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Error Full-Scale Error Min-Scale Tempco Full-Scale Tempco Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Output High Voltage Logic Output Low Voltage Logic Input Current Input Capacitance LOGIC TIMING CHARACTERISTICS 4 Chip Select Write Pulsewidth Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulsewidth Reset Pulsewidth Chip Select Read Pulsewidth Read Data Hold Read Data Setup Data to Hi Z Chip Select to Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation Min Typ Max Units 1/2 ±1 ±2 ±2 ±4 LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB –1 ±4 ±4 ±8 ±8 100 100 ±1 Adjacent DAC Matching IREFH BW Note 3 VSS = 0.0 V VSS = –5.0 V Code 000H –3 dB, VREFH = 0 V to 2.5 V p-p VREFL + 2.5 0 –2.5 –1.0 IOUT tS SR RL = 2 kΩ, CL = 100 pF to 0.01%, 2.5 V Step, RL = 1 kΩ 10% to 90% –1.25 VINH VINL VOH VOL IIN CIN TA = +25°C TA = +25°C IOH = +0.4 mA IOL = –1.6 mA 2.4 VDD – 2.5 VREFH – 2.5 VREFH – 2.5 +1.0 V V V mA kHz +1.25 mA µs V/µs 450 7 2.2 0.8 2.4 0.45 1 8 Note 5 tWCS tWS tWH tAS tAH tLS tLH tWDS tWDH tLDW tRESET tRCS tRDH tRDS tDZ tCSD PSS IDD ISS PDISS tWCS = 150 ns tWCS = 150 ns tWCS = 150 ns tWCS = 150 ns tRCS = 170 ns tRCS = 170 ns CL = 10 pF CL = 100 pF 150 0 0 0 0 70 50 20 0 180 150 170 20 0 200 320 100 7 VSS = –5.0 V VSS = 0 V VSS = –5 V 12 –10 60 110 NOTES 1 All supplies can be varied ± 5%, and operation is guaranteed. Device is tested with V DD = +4.75 V. 2 For single supply operation only (V REFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002 H). 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 All parameters are guaranteed by design. 5 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. REV. D V V V V µA pF –3– ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ppm/V mA mA mW mW DAC8412/DAC8413 t RCS 80ns CS CS t RDH t RDS t AS R/W t AH A0/A1 tAS HI-Z DATA VALID ADDRESS ONE ADDRESS t DZ DATA OUT tWH tWS R/W HI -Z ADDRESS TWO ADDRESS THREE ADDRESS FOUR tLS tLH t CSD LDAC Figure 2. Data Output (Read Timing) tLDW tWDS t WCS DATA1 VALID DATA IN CS t WS t WH t AS t AH DATA2 VALID DATA3 VALID tWDH DATA4 VALID Figure 5. Double Buffer Mode R/W VDD VREFH VREFL A0/A1 + C1 t LDW t LH t LS D1 C2 VREFH VREFL N/C VOUTB VOUTC N/C N/C VOUTA VOUTD N/C C2 VSS t RESET DGND RESET Figure 3. Data WRITE (Input and Output Registers) Timing 80ns R6 CS R1 tWH tWS R3 R3 R5 R4 R4 VDD RESET CS LDAC A0 DB0 A1 DB1 R/W DB2 DB11 DB3 DB10 DB4 DB9 DB5 DB8 DB6 DB7 C2 * ONCE PER PORT DGND tAS ADDRESS ONE D1 ADDRESS TWO ADDRESS THREE VDD = +15V, VSS = –15V, VREFH = +10V, VREFL = 0V R1 = 10⍀, R2 = 100⍀, R3 = 5k⍀, R4 = 10k⍀, R5 = 100k⍀, R6 = 47⍀ FOR LCC, R6 = 100⍀ FOR DIP C1 = 4.7F (ONCE PER PORT), C2 = 0.01F (EACH DEVICE) D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT) tLH LDAC tWDS DATA1 VALID Figure 6. Burn-In Diagram tWDH DATA2 VALID DATA3 VALID + C1 VSS ADDRESS FOUR tLS DATA IN R3 VLOGIC R/W ADDRESS R1 D1 C2 t WDH DATA IN R2 R2 C1 + D1 LDAC t WDS + C1 DATA4 VALID Figure 4. Single Buffer Mode –4– REV. D DAC8412/DAC8413 ABSOLUTE MAXIMUM RATINGS Thermal Resistance (TA = +25°C unless otherwise noted) JA* JC Units Package Type VSS to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V VSS to VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7.0 V VSS to VREFL . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +VSS–2.0 V VREFH to VDD . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V VREFH to VREFL . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, VSS–VDD Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . ± 15 mA Digital Input Voltage to DGND . . . . . –0.3 V, VLOGIC +0.3 V Digital Output Voltage to DGND . . . . . . . . . . –0.3 V, +7.0 V Operating Temperature Range ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . –40°C to +85°C AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C 28-Lead Plastic DIP (P) 48 28-Lead Hermetic Leadless Chip Carrier (TC) 70 28-Lead Plastic Leaded Chip Carrier (PC) 63 22 °C/W 28 °C/W 25 °C/W *θJA is specified for worst-case mounting conditions, i. e., θJA is specified for device in socket. ORDERING INFORMATION 1, 2 INL (LSB) ±1 ± 1.5 0.5 ±1 ±1 ± 1.5 ± 0.5 ±1 Military3 Temperature –55ⴗC to +125ⴗC Extended Industrial3 Temperature –40ⴗC to +85ⴗC Package Description Package Option DAC8412FPC PLCC LCC Plastic DIP Plastic DIP PLCC LCC Plastic DIP Plastic DIP P-28A E-28A N-28 N-28 P-28A E-28A N-28 N-28 DAC8412BTC/883 DAC8412EP DAC8412FP DAC8413FPC DAC8413BTC/883 DAC8413EP DAC8413FP NOTES 1 Die Size 0.225 × 0.165 inches, 37,125 sq. mils (5.715 × 4.191 mm, 23.95 sq. mm). Substrate should be connected to V DD; Transistor Count = 2595. 2 Burn-in is available on extended industrial temperature range parts in cerdip. 3 A complete /883 data sheet is available. For availability and burn-in information, contact your local sales office. CAUTION 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 3. Remove power before inserting or removing units from their sockets. 4. Analog outputs are protected from short circuit to ground or either supply. REV. D –5– WARNING! ESD SENSITIVE DEVICE DAC8412/DAC8413 PIN FUNCTION DESCRIPTIONS LDAC 7 24 VLOGIC 23 CS TOP VIEW (NOT TO SCALE) DB0 (LSB) 8 22 A0 21 A1 DB1 9 20 R/W DB2 10 19 DB11 (MSB) DB3 11 18 DB10 DB4 12 17 DB9 DB5 13 16 DB8 DB6 14 15 DB7 VREFH VREFL VOUTD VOUTB VOUTC VOUTA PLCC 4 3 2 1 28 27 26 DGND 5 25 VDD RESET 6 24 VLOGIC LDAC 7 DB0 (LSB) 8 DB1 9 23 CS DAC8412PC DAC8413PC 22 A0 21 A1 DB2 10 20 R/W TOP VIEW (NOT TO SCALE) DB3 11 19 DB11 (MSB) DB9 DB10 VOUTC VOUTD DB8 DB7 12 13 14 15 16 17 18 VREFL LCC VREFH 4 3 2 1 28 27 26 DGND 5 25 VDD RESET 6 24 VLOGIC LDAC 7 DB0 (LSB) 8 DB1 9 23 CS DAC8412TC DAC8413TC 22 A0 21 A1 TOP VIEW (NOT TO SCALE) DB2 10 20 R/W 19 DB11 (MSB) DB3 11 –6– DB10 DB9 12 13 14 15 16 17 18 DB8 VDD VOUTD VOUTC VREFL RESET 6 DB7 25 26 27 28 25 VDD DAC8412 DAC8413 DGND 5 DB6 A1 A0 CS VLOGIC 26 VOUTD VSS 4 VOUTB 21 22 23 24 27 VOUTC VOUTA 3 DB6 LDAC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 R/W 28 VREFL VSS 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VREFH 1 VOUTB 2 DB5 High-Side DAC Reference Input DAC B Output DAC A Output Lower-Rail Power Supply Digital Ground Reset Input and Output Registers to all 0s, Enabled at Active Low Load Data to DAC, Enabled at Active Low Data Bit 0, LSB Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11, MSB Active Low to Write Data to DAC. Active High to Readback Previous Data at Data Bit Pins with VLOGIC Connected to +5 V Address Bit 1 Address Bit 0 Chip Select, Enabled at Active Low Voltage Supply for Readback Function. Can be Open Circuit If Not Used Upper-Rail Power Supply DAC D Output DAC C Output Low-Side DAC Reference Input DB4 VREFH VOUTB VOUTA VSS DGND RESET VSS 1 2 3 4 5 6 Plastic DIP VOUTA Description DB5 Name DB4 Pin PIN CONFIGURATIONS REV. D +1 0 VDD = +15V VSS = –15V VREFL = –10.0V TA = +25ⴗC –1 6 7 8 9 10 VREFH – Volts 11 VDD = +5V VSS = 0V VREFL = 0V TA = +25ⴗC +2 MAXIMUM LINEARITY ERROR – LSB MAXIMUM LINEARITY ERROR – LSB MAXIMUM LINEARITY ERROR – LSB Typical Performance Characteristics– DAC8412/DAC8413 +1 0 –1 –2 1 12 Figure 7. DNL vs. VREFH 2 VREFH – Volts 6 VDD = +5V VSS = 0V VREFL = 0V TA = +25ⴗC 2 VREFH – Volts X+3 –0.2 X –0.4 0 0 DAC A DAC D DAC B –0.4 DAC C –0.6 –75 0 75 TEMPERATURE – ⴗC Figure 13. Full-Scale Error vs. Temperature REV. D X –0.1 X–3 –0.3 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V –0.5 –0.7 1000 200 400 600 800 T = HOURS OF OPERATION AT +125ⴗC 150 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V 0.1 DAC A DAC C –0.1 DAC D DAC B –0.3 –0.5 –75 0 75 TEMPERATURE – ⴗC 150 Figure 14. Zero-Scale Error vs. Temperature –7– 0 200 400 600 800 1000 T = HOURS OF OPERATION AT +125ⴗC Figure 12. Zero-Scale Error vs. Time Accelerated by Burn-In 0.3 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V ZERO-SCALE ERROR – LSB FULL-SCALE ERROR – LSB 0 Figure 11. Full-Scale Error vs. Time Accelerated by Burn-In 0.2 –0.2 X+3 0.1 X–3 Figure 10. INL vs. VREFH 12 0.3 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V 0.2 –0.6 3 8 10 VREFH – Volts Figure 9. INL vs. VREFH ZERO-SCALE ERROR – LSB FULL-SCALE ERROR – LSB MAXIMUM LINEARITY ERROR – LSB 0 VDD = +15V VSS = –15V VREFL = 0V TA = +25ⴗC 0.1 Figure 8. DNL vs. VREFH +1 1 0.2 3 0.4 –1 0.3 0.500 0.26125 0.375 0.18750 0.250 LINEARITY ERROR – LSB 0.37500 0.08375 0 –0.09375 –0.18750 VREFH = +10V VREFL = 0V TA = +25ⴗC –0.23125 –0.37500 0 0 –0.125 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = –55ⴗC, +25ⴗC, +125ⴗC –0.250 –0.375 1024 1536 2048 2560 3072 DIGITAL INPUT CODE – Decimal 512 0.125 3584 –0.500 4096 0 512 Figure 15. Channel-to-Channel Matching (VSUPPLY = ± 15 V) 2.0 VDD = +5.0V VSS = 0V VREFH = +2.5V TA = +25ⴗC 0.75 0.50 1024 1536 2048 2560 3072 DIGITAL INPUT CODE – Decimal 3584 4096 3583 4095 Figure 18. INL vs. Code 1.00 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 1.5 IVREFH – mA 0.25 0 –0.25 1.0 0.5 –0.50 0 –0.75 –1.00 –0.5 0 1024 1536 2048 2560 3072 DIGITAL INPUT CODE – Decimal 512 3584 0 4096 Figure 16. Channel-to-Channel Matching (VSUPPLY = +5 V/GND) 511 1023 1535 2047 2559 3071 DIGITAL INPUT CODE – Decimal Figure 19. IVREFH vs. Code 13 VDD = +15V VSS = –15V VREFL = –10V 10 IDD – mA LINEARITY ERROR – LSB LINEARITY ERROR – LSB DAC8412/DAC8413 7 4 –7 –3 1 5 VREFH – Volts 9 13 Figure 17. IDD vs. VREFH All DACs High –8– REV. D DAC8412/DAC8413 32.5mV 15.5mV +5V INPUT 0 0 INPUT –5V 5mV/DIV 1 LSB ERROR BAND 10V VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 1V/ DIV EA 2mV/DIV V 5 DIV 5 V DIV TRIG'D VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC –17.5mV –1.96s 2s/DIV 18.04s Figure 20. Settling Time (Positive) TRIG'D TRIG'D –4.5mV –1.96s 2s/DIV 0V –580ns 18.04s 0.6 TRIG'D INL – LSB FULL SCALE VOLTAGE – V VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 0.8 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 0.4 0.2 1s/DIV –0.2 0.01 9.42s Figure 23. Negative Slew Rate 0.10 1.00 10.0 LOAD RESISTANCE – K⍀ Figure 24. DAC 8412 INL vs. Load Resistance VDD = +15V VSS = –15V VREFH = 0 ⴞ100mV VREFL = –10V DATA BITS = +5V 200mV p-p –30 –50 0 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 26. Small Signal Response REV. D VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 6 4 0.10 1.00 10.0 LOAD RESISTANCE – K⍀ 100 Figure 25. DAC 8412 Output Swing vs. Load Resistance 100 POWER SUPPLY REJECTION – dB POWER SUPPLY CURRENT – mA GAIN – dB –10 8 0 0.01 100 10 0 10 2 0.0 0V –580ns 9.42s 12 1.0 1V/ DIV EA 1s/DIV Figure 22. Positive Slew Rate Figure 21. Settling Time (Negative) 10V VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC IDD 6 VDD = +15V VSS = –15V 2 –2 ISS –6 –10 –75 0 75 TEMPERATURE – ⴗC 150 Figure 27. Power Supply Current vs. Temperature –9– +PSRR 80 –PSRR 60 40 20 0 10 +PSRR: VDD = +15Vⴞ1Vp VSS = –15V –PSRR: VDD = +15V VSS = –15Vⴞ1V VREFH = 10V ALL DATA 0 100 1k 10k 100k FREQUENCY – Hz 1M Figure 28. PSRR vs. Frequency DAC8412/DAC8413 0 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 1.00 30 20 IOUT – mA NOISE DENSITY – V 10.0 0.10 0.01 10 VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC DATA = 000H +ISC CH1 MEAN 66.19V VDD = +15V VSS = –15V VREFH = +10V VREFL = –10V TA = +25ⴗC 1 0 –10 –ISC –20 –30 20uV/DIV 0.001 1 10 100 1000 NOISE FREQUENCY – Hz 10000 0 –25 –20 –15 –10 –5 0 5 VOUT – Volts Figure 29. DAC8412 Noise Frequency vs. Noise Density 10 15 20 Figure 30. IOUT vs. VOUT 20 IOUT – mA 10 5 A CH1 12.9mV Figure 31. Broadband Noise 10s 25 15 M 200s 25 VDD = +15V VSS = 0V VREFH = +10V VREFL = 0V TA = +25ⴗC DATA = 800H +ISC 4s 1V GLITCH AT DAC OUTPUT 0 2 –5 –10 –15 1 –ISC –25 –6 DEGLITCHER OUTPUT 1V –20 –4 –2 0 2 VOUT – Volts 4 CH2 6 Figure 32. IOUT vs. VOUT 1.86V Figure 33. Glitch and Deglitched Results OPERATION Introduction The DAC8412 and DAC8413 are quad, voltage output, 12-bit parallel input DACs featuring a 12-bit data bus with readback capability. The only differences between the DAC8412 and DAC8413 are the reset functions. The DAC8412 resets to midscale (code 800H) and the DAC8413 resets to minimum scale (code 000H). precision instrumentation control, a deglitcher circuit can be implemented with a standard sample-and-hold circuit. (See Figure 34.) When CS is enabled by synchronizing the hold period to be longer than the glitch tradition, the output voltage can be smoothed with minimum disturbance. A quad sampleand-hold amplifier, SMP04, has been used to illustrate the deglitching result. (See Figure 33.) The ability to operate from a single +5 V supply is a unique feature of these DACs. Operation of the DAC8412 and DAC8413 can be viewed by dividing the system into three separate functional groups: the digital I/O and logic, the digital to analog converters and the output amplifiers. DACOUT DACOUT' S/H DACOUT DACs Each DAC is a voltage switched, high impedance (R = 50 kΩ), R-2R ladder configuration. Each 2R resistor is driven by a pair of switches that connect the resistor to either VREFH or VREFL. CS S/H H S H S Glitch Worst-case glitch occurs at the transition between half-scale digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111 1111 1111. It can be measured at about 2 V µs. (See Figure 33.) For demanding applications such as waveform generation or –10– DACOUT' Figure 34. Deglitcher Circuit REV. D DAC8412/DAC8413 Reference Inputs All four DACs share common reference high (VREFH) and reference low (VREFL) inputs. The voltages applied to these reference inputs set the output high and low voltage limits of all four of the DACs. Each reference input has voltage restrictions with respect to the other reference and to the power supplies. The VREFL can be set at any voltage between VSS and VREFH – 2.5 V, and VREFH can be set to any value between +VDD – 2.5 V and VREFL + 2.5 V. Note that because of these restrictions the DAC8412 references cannot be inverted (i.e., VREFL cannot be greater than VREFH). It is important to note that the DAC8412’s VREFH input both sinks and sources current. Also the input current of both VREFH and VREFL are code dependent. Many references have limited current sinking capability and must be buffered with an amplifier to drive VREFH. The VREFL has no such special requirements. It is recommended that the reference inputs be bypassed with 0.2 µF capacitors when operating with ± 10 V references. This limits the reference bandwidth. Digital I/O See Table I for digital control logic truth table. Digital I/O consists of a 12-bit bidirectional data bus, two registers select inputs, A0 and A1, a R/W input, a RESET input, a Chip Select (CS), and a Load DAC (LDAC) input. Control of the DACs and bus direction is determined by these inputs as shown in Table I. Digital data bits are labeled with the MSB defined as data bit “11” and the LSB as data bit “0.” All digital pins are TTL/ CMOS compatible. See Figure 35 for a simplified I/O logic diagram. The register select inputs A0 and A1 select individual DAC registers “A” (binary code 00) through “D” (binary code 11). Decoding of the registers is enabled by the CS input. When CS is high no decoding takes place, and neither the writing nor the reading of the input registers is enabled. The loading of the second bank of registers is controlled by the asynchronous LDAC input. By taking LDAC low while CS is enabled, all output registers can be updated simultaneously. Note that the tLDW required pulsewidth for updating all DACs is a minimum of 170 ns. The R/W input, when enabled by CS, controls the writing to and reading from the input register. Coding Both the DAC8412 and DAC8413 use binary coding. The output voltage can be calculated by: VOUT = VREFL + (VREF H _ VREFL ) × N 4096 where N is the digital code in decimal. RESET The RESET function can be used either at power-up or at any time during the DAC’s operation. The RESET function is independent of CS. This pin is active LOW and sets the DAC output registers to either center code for the DAC8412, or zero code for the DAC8413. The reset to center code is most useful when the DAC is configured for bipolar references and an output of zero volts after reset is desired. Supplies Supplies required are VSS, VDD and VLOGIC. The VSS supply can be set between –15 V and 0 V. VDD is the positive supply; its operating range is between +5 V and +15 V. VLOGIC is the digital output supply voltage for the readback function. It is normally connected to +5 V. This pin is a logic reference input only. It does not supply current to the device. If you are not using the readback function, VLOGIC can be left opencircuit. While VLOGIC does not supply current to the DAC8412, it does supply currents to the digital outputs when readback is used. Amplifiers Unlike many voltage output DACs, the DAC8412 features buffered voltage outputs. Each output is capable of both sourcing and sinking 5 mA at ± 10 volts, eliminating the need for external amplifiers when driving 500 pF or smaller capacitive load in most applications. These amplifiers are short-circuit protected. Table I. DAC8412/DAC8413 Logic Table A1 A0 R/W CS RS LDAC INPUT REG L L H H L L H H L L H H X X X X L H L H L H L H L H L H X X X X L L L L L L L L H H H H X X X X L L L L L L L L L L L L H H X H H H H H H H H H H H H H H H L g L L L L H H H H H H H H L H X X WRITE WRITE Transparent WRITE WRITE Transparent WRITE WRITE Transparent WRITE WRITE Transparent WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT WRITE HOLD WRITE INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT READ HOLD READ INPUT HOLD Update all output registers HOLD HOLD HOLD *All registers reset to mid/zero-scale *All registers latched to mid/zero-scale OUTPUT REG MODE DAC A B C D A B C D A B C D All All All All *DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care. Input and Output registers are transparent when asserted. REV. D –11– DAC8412/DAC8413 VDD VREFH RDDACA CS WRDB0 DAC A WRDB1 WRDACA RDDACB A0 VSS VOUTA WRDB2 WRDB3 DAC B WRDB4 OUTPUT WRDB5 REGISTER WRDACB INPUT REGISTER WRDB6 RDDACC WRDB7 A1 WRDACC R/W VOUTB DAC C VOUTC WRDB8 WRDB9 RDDACD WRDB10 DAC D WRDB11 VOUTD WRDACD DB11..DB0 VLOGIC VREFL LDAC RESET READOUTBAR READBACKDATAIN_DB11 READBACKDATAIN_DB10 READBACK DATAOUT_DB11 READOUT DGND Figure 35. Simplified I/O Logic Diagram Careful attention to grounding is important to accurate operation of the DAC8412. This is not because the DAC8412 is more sensitive than other 12-bit DACs, but because with four outputs and two references there is greater potential for ground loops. Since the DAC8412 has no analog ground, the ground must be specified with respect to the reference. +15V 39k⍀ +15V 6.2⍀ Output voltage ranges can be configured as either unipolar or bipolar, and within these choices a wide variety of options exists. The unipolar configuration can be either positive or negative voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical. GAIN 100k⍀ 0.2F DAC8412 OR DAC8413 AD688 FOR ⴞ10V AD588 FOR ⴞ 5V 0.1F //10F 6.2⍀ VREFL 0.2F VSS 1F +15V +15V –15V ⴞ5 OR ⴞ10V OPERATION + INPUT OP-400 OP400 OUTPUT VREFH 0.2F REF10 VREFH BALANCE 100k⍀ Reference Configurations VDD TRIM 10k⍀ DAC8412 OR DAC8413 VREFL +10V OPERATION Figure 37. Symmetrical Bipolar Operation VDD VSS –15V Figure 36. Unipolar +10 V Operation 0.1F //10F Figure 37 (Symmetrical Bipolar Operation) shows the DAC8412 configured for ± 10 V operation. Note: See the AD688 data sheet for a full explanation of reference operation. Adjustments may not be required for many applications since the AD688 is a very high accuracy reference. However if additional adjustments are required, adjust the DAC8412 full scale first. Begin by loading the digital full-scale code (FFFH), and then adjust the Gain Adjust potentiometer to attain a DAC output voltage of 9.9976 V. Then, adjust the Balance Adjust to set the center scale output voltage to 0.000 V. –12– REV. D DAC8412/DAC8413 The 0.2 µF bypass capacitors shown at the reference inputs in Figure 37 should be used whenever ± 10 V references are used. Applications with single references or references to ± 5 V may not require the 0.2 µF bypassing. The 6.2 Ω resistor in series with the output of the reference amplifier is to keep the amplifier from oscillating with the capacitive load. We have found that this is large enough to stabilize this circuit. Larger resistor values are acceptable, provided that the drop across the resistor doesn’t exceed a VBE. Assuming a minimum VBE of 0.6 V and a maximum current of 2.75 mA, then the resistor should be under 200 Ω for the loading of a single DAC8412. Figure 38 shows the DAC8412 configured for –10 V to 0 V operation. A REF08 with a –10 V output is connected directly to VREFL for the reference voltage. Single +5 V Supply Operation For operation with a +5 V supply, the reference voltage should be set between 1.0 V and +2.5 V for optimum linearity. Figure 39 shows a REF43 used to supply a +2.5 V reference voltage. The headroom of the reference and DAC are both sufficient to support a +5 V supply with ± 5% tolerance. VDD and VLOGIC should be connected to the same supply. Separate bypassing to each pin should also be used. Using two separate references is not recommended. Having two references could cause different drifts with time and temperature; whereas with a single reference, most drifts will track. +5V 10F Unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. This is preferable to using a reference and dividing down to the required value. For a 10 V full-scale output, the circuit can be configured as shown in Figure 38. In this configuration the full-scale value is set first by adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V. 0.01F INPUT VREFH OUTPUT REF43 0.2F TRIM 10k⍀ GND VDD DAC8412 OR DAC8413 0.1F //10F VREFL 10k⍀ VSS VREFH TRIM REF08 GND OUTPUT DAC8412 OR DAC8413 0.2F 0.01F ZERO TO +2.5V OPERATION SINGLE +5V SUPPLY VDD 0.1F //10F Figure 39. +5 V Single Supply Operation VREFL VSS 10F ZERO TO –10V OPERATION –15V Figure 38. Unipolar –10 V Operation REV. D –13– DAC8412/DAC8413 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.458 (11.63) 0.442 (11.23) SQ 0.095 (2.41) 0.075 (1.90) 0.300 (7.62) BSC 0.150 (3.51) BSC 0.015 (0.38) MIN 4 26 28 25 5 0.028 (0.71) 0.022 (0.56) 1 0.458 (11.63) MAX SQ TOP VIEW 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) C1544a–2–3/00 (rev. D) 28-Position Leadless Chip Carrier (TC Suffix) BOTTOM VIEW 0.050 (1.27) BSC 19 11 0.055 (1.40) 0.045 (1.14) 0.200 (5.08) BSC 18 12 45ⴗ TYP 28-Lead PLCC (P-28A) (PC Suffix) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 5 PIN 1 IDENTIFIER 26 25 11 12 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 0.020 (0.50) R 0.025 (0.63) 0.015 (0.38) 0.032 (0.81) 0.026 (0.66) 19 18 0.430 (10.92) 0.390 (9.91) 0.040 (1.01) 0.025 (0.64) 0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32) 0.110 (2.79) 0.085 (2.16) 28-Lead Epoxy DIP (N-28) (P Suffix) 1.565 (39.70) 1.380 (35.10) 28 15 0.580 (14.73) 0.485 (12.32) 14 0.060 (1.52) 0.015 (0.38) 0.250 (6.35) MAX 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 SEATING (1.77) PLANE MAX –14– PRINTED IN U.S.A. 1 PIN 1 0.625 (15.87) 0.600 (15.24) 0.195 (4.95) 0.125 (3.18) 0.015 (0.381) 0.008 (0.204) REV. D