ETC PI74FCT162501CTV

PI74FCT16501/162501/162H501T
PI74FCT16501T
18-BIT
REGISTERED
TRANSCEIVERS
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PI74FCT162501T
PI74FCT162H501T
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Fast CMOS 18-Bit
Registered Transceivers
Product Features
Product Description
Common Features:
• PI74FCT16501T, PI74FCT162501T, and PI74FCT162H501T
are high-speed,
low power devices with high current drive.
• VCC = 5V ±10%
• Hysteresis on all inputs
• Packages available
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
PI74FCT16501T Features
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162501T Features
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
at VCC = 5V, TA = 25°C
PI74FCT162H501T Features
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
Pericom Semiconductor’s PI74FCT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16501T, PI74FCT162501T, and PI74FCT162H501T are
18-bit registered bus transceivers designed with D-type latches and
flip-flops to allow data flow in transparent, latched, and clocked
modes. The Output Enable (OEAB and OEBA, Latch Enable (LEAB
and LEBA) and Clock (CLKAB and CLKBA) inputs control the data
flow in each direction. When LEAB is HIGH, the device operates in
transparent mode for A-to-B data flow. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic level. The
A bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CLKAB, if LEAB is LOW. OEAB performs the output
enable function on the B port. Data flow from B port to A port is similar
using OEBA, LEBA and CLKBA. These high-speed, low power
devices offer a flow-through organization for ease of board layout.
The PI74FCT16501T output buffers are designed with a Power-Off
disable allowing "live insertion" of boards when used as backplane
drivers.
The PI74FCT162501T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H501T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
C
D
D
B1
A1
C
C
D
D
TO 17 OTHER CHANNELS
1
PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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Product Pin Description
Pin Name
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
GND
VCC
Note:
Truth Table(1,4)
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
Ground
Power
OEAB
L
H
H
H
H
H
H
Product Pin Configuration
LEAB
A0
GND
A1
A2
VCC
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
VCC
A15
A16
GND
A17
OEBA
LEBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
56-PIN
14
V56 43
15
A56 42
16
41
17
40
18
39
19
38
GND
20
21
37
B13
B14
22
23
24
25
26
36
35
34
33
32
31
27
28
30
29
CLKBA
Ax
X
L
H
L
H
X
X
Outputs
Bx
Z
L
H
L
H
B(2)
B(3)
Notes:
1. A-to-B data flow is shown. B-to-A data flow is similar but
uses OEBA, LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW
before LEAB went LOW.
4. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
1. For the PI74FCT162H501T, these pins have “Bus
Hold.” All other pins are standard, outputs, or I/Os.
OEAB
Inputs
LEAB
CLKAB
X
X
H
X
H
X
L
↑
L
↑
L
L
L
H
CLKAB
B0
GND
B1
B2
VCC
B3
B4
B5
GND
B6
B7
B8
B9
B10
B11
GND
B12
VCC
B15
B16
GND
B17
GND
2
PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................................... –65°C to +150°C
Ambient Temperature with Power Applied ....................................–40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... –0.5V to +7.0V
DC Input Voltage ............................................................................ –0.5V to +7.0V
DC Output Current ..................................................................................... 120 mA
Power Dissipation ..........................................................................................1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description
VIH
VIL
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IBHH
IBHL
IOZH(5)
IOZL(5)
VIK
IOS
IO
VH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input HIGH Current
Input HIGH Current
Input HIGH Current
Input LOW Current
Input LOW Current
Input LOW Current
Input LOW Current
Bus Hold
Sustain Current
High-Impedance
Output Current
(3-STATE OUTPUTS)
Clamp Diode Voltage
Short Circuit Current
Output Drive Current
Input Hysteresis
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Standard Input, VCC = Max.
Standard I/O, VCC = Max.
Bus Hold Input(4), VCC = Max.
Bus Hold I/O(4), VCC = Max.
Standard Input, VCC = Min.
Standard I/O, VCC = Min.
Bus Hold Input(4), VCC = Min.
Bus Hold I/O(4), VCC = Min.
Bus Hold Input(4), VCC = Min.
VCC = Max.
VCC = Max.
VCC = Min., IIN = –18 mA
VCC = Max.(3), VOUT = GND
VCC = Max.(3), VOUT = 2.5V
Min.
Typ(2)
2.0
VIN = VCC
VIN = VCC
VIN = VCC
VIN = VCC
VIN = GND
VIN = GND
VIN = GND
VIN = GND
VIN = 2.0V
VIN = 0.8V
VOUT = 2.7V
VOUT = 0.5V
–50
+50
–80
–50
–0.7
–140
100
Max.
Units
0.8
1
1
±100
±100
–1
–1
±100
±100
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
1
–1
µA
µA
–1.2
–200
–180
V
mA
mA
mV
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
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PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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PI74FCT16501T Output Drive Characteristics (Over the Operating Range)
Parameters Description
Test Conditions(1)
VOH
Output HIGH Voltage
VCC = Min., VIN = VIH or VIL
VOL
IOFF
Output LOW Voltage
Power Down Disable
VCC = Min., VIN = VIH or VIL
VCC = 0V, VIN or VOUT ≤4.5V
IOH = –3.0 mA
IOH = –15.0 mA
IOH = –32.0 mA
IOL = 64 mA
Min.
Typ(2)
2.5
2.4
2.0
3.5
3.5
3.0
0.2
—
0.55
±100
V
µA
Min.
Typ(2)
Max.
Units
2.4
3.3
0.3
115
–115
0.55
150
–150
V
V
mA
mA
—
Max.
Units
V
PI74FCT162501T/162H501T Output Drive Characteristics (Over the Operating Range)
Parameters Description
VOH
VOL
IODL
IODH
Output HIGH Voltage
Output LOW Voltage
Output LOW Current
Output HIGH Current
Test Conditions(1)
VCC = Min., VIN = VIH or VIL
IOH = –24.0 mA
VCC = Min., VIN = VIH or VIL
IOL = 24 mA
VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3)
VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3)
60
–60
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
CIN
COUT
Description
Test Conditions
Typ
Max.
Units
Input Capacitance
Output Capacitance
VIN = 0V
VOUT = 0V
4.5
5.5
6
8
pF
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
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PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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Power Supply Characteristics
Test Conditions(1)
Parameters Description
Min.
Typ(2)
Max.
Units
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
0.1
500
µA
∆ICC
Supply Current per
Input @ TTL HIGH
VCC = Max.
VIN = 3.4V(3)
0.5
1.5
mA
ICCD
Supply Current per
Input per MHz(4)
VCC = Max., Outputs Open
OEAB = OEBA = VCC or GND
One Bit Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
75
120
µA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fCP = 10 MHZ (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
One Bit Toggling
fI = 5 MHZ
50% Duty Cycle
VIN = VCC
VIN = GND
0.8
1.7(5)
mA
VIN = 3.4V
VIN = GND
1.3
4.2(5)
VIN = VCC
VIN = GND
3.8
6.5(5)
VIN = 3.4V
VIN = GND
8.5
20.8(5)
VCC = Max., Output Open
fCP = 10 MHZ (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
Eighteen Bits Toggling
fI = 2.5 MHZ
50% Duty Cycle
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
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PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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PI74FCT16501T Switching Characteristics over Operating Range
Parameters
Description
Conditions
(1)
16501AT
16501CT
16501DT
16501ET
Com.
Com.
Com.
Com.
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tMAX
CLKAB or CLKBA frequency
CL = 50 pF
—
150
—
150
—
150
—
150
MHz
t PLH
t PHL
Propagation Delay
AX to BX or AX to BX
RL = 500Ω
1.5
5.1
1.5
4.6
1.5
4.1
1.5
3.8
ns
t PLH
t PHL
Propagation Delay
LEBA to AX, LEAB to BX
1.5
5.6
1.5
5.3
1.5
4.6
1.5
4.2
ns
t PLH
t PHL
Propagation Delay
CLKBA to AX, CLKAB to BX
1.5
5.6
1.5
5.3
1.5
4.6
1.5
4.2
ns
t PZH
t PZL
Output Enable Time
OEBA to AX, OEAB to BX
1.5
6.0
1.5
5.6
1.5
5.2
1.5
4.8
ns
t PHZ
t PLZ
Output Disable Time(3)
OEBA to AX, OEAB to BX
1.5
5.6
1.5
5.2
1.5
5.2
1.5
5.2
ns
tSU
Setup Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
3.0
—
3.0
—
3.0
—
2.4
—
ns
tH
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
0
—
0
—
0
—
0
—
ns
tSU
Setup Time
HIGHorLOW
Ax to LEAB,
Bx to LEBA
Clock HIGH
3.0
—
3.0
—
3.0
—
2.0
—
ns
Clock LOW
1.5
—
1.5
—
1.5
—
1.5
—
ns
tH
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
1.5
—
1.5
—
1.5
—
0.5
—
ns
tW
LEAB or LEBA Pulse Width
HIGH(3)
3.0
—
3.0
—
3.0
—
3.0
—
ns
tW
CLKAB or CLKBA Pulse Width
HIGH or LOW(3)
3.0
—
3.0
—
3.0
—
3.0
—
ns
tSK(O)
Output Skew(4)
—
0.5
—
0.5
—
0.5
—
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
6
PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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PI74FCT162501T Switching Characteristics over Operating Range
Parameters
Description
162501AT
162501CT
162501DT
162501ET
Com.
Com.
Com.
Com.
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Unit
(1)
tMAX
CLKAB or CLKBA frequency
CL = 50 pF
—
150
—
150
—
150
—
150
MHz
tPLH
tPHL
Propagation Delay
AX to BX or AX to BX
RL = 500Ω
1.5
5.1
1.5
4.6
1.5
4.1
1.5
3.8
ns
tPLH
tPHL
Propagation Delay
LEBA to AX, LEAB to BX
1.5
5.6
1.5
5.3
1.5
4.6
1.5
4.2
ns
tPLH
tPHL
Propagation Delay
CLKBA to AX, CLKAB to BX
1.5
5.6
1.5
5.3
1.5
4.6
1.5
4.2
ns
tPZH
tPZL
Output Enable Time
OEBA to AX, OEAB to BX
1.5
6.0
1.5
5.6
1.5
5.2
1.5
4.8
ns
tPHZ
tPLZ
Output Disable Time(3)
OEBA to AX, OEAB to BX
1.5
5.6
1.5
5.2
1.5
5.2
1.5
5.2
ns
tSU
Setup Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
3.0
—
3.0
—
3.0
—
2.4
—
ns
tH
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
0
—
0
—
0
—
0
—
ns
tSU
Setup Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
Clock HIGH
3.0
—
3.0
—
3.0
—
2.0
—
ns
Clock LOW
1.5
—
1.5
—
1.5
—
1.5
—
ns
tH
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
1.5
—
1.5
—
1.5
—
0.5
—
ns
tW
LEAB or LEBA Pulse Width
HIGH(3)
3.0
—
3.0
—
3.0
—
3.0
—
ns
tW
CLKAB or CLKBA Pulse Width
HIGH or LOW(3)
3.0
—
3.0
—
3.0
—
3.0
—
ns
tSK(O)
Output Skew(4)
—
0.5
—
0.5
—
0.5
—
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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PS2035A 03/11/96
PI74FCT16501/162501/162H501T
18-BIT
REGISTERED
TRANSCEIVERS
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PI74FCT162H501T Switching Characteristics over Operating Range (Advance Information)
Parameters
Description
162H501AT
162H501CT
162H501DT
162H501ET
Com.
Com.
Com.
Com.
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Unit
(1)
tMAX
CLKAB or CLKBA frequency
CL = 50 pF
—
150
—
150
—
150
—
150
MHz
tPLH
tPHL
Propagation Delay
AX to BX or AX to BX
RL = 500Ω
1.5
5.1
1.5
4.6
1.5
4.1
1.5
3.8
ns
tPLH
tPHL
Propagation Delay
LEBA to AX, LEAB to BX
1.5
5.6
1.5
5.3
1.5
4.6
1.5
4.2
ns
tPLH
tPHL
Propagation Delay
CLKBA to AX, CLKAB to BX
1.5
5.6
1.5
5.3
1.5
4.6
1.5
4.2
ns
tPZH
tPZL
Output Enable Time
OEBA to AX, OEAB to BX
1.5
6.0
1.5
5.6
1.5
5.2
1.5
4.8
ns
tPHZ
tPLZ
Output Disable Time(3)
OEBA to AX, OEAB to BX
1.5
5.6
1.5
5.2
1.5
5.2
1.5
5.2
ns
tSU
Setup Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
3.0
—
3.0
—
3.0
—
2.4
—
ns
tH
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
0
—
0
—
0
—
0
—
ns
tSU
Setup Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
Clock HIGH
3.0
—
3.0
—
3.0
—
2.0
—
ns
Clock LOW
1.5
—
1.5
—
1.5
—
1.5
—
ns
tH
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
1.5
—
1.5
—
1.5
—
0.5
—
ns
tW
LEAB or LEBA Pulse Width
HIGH(3)
3.0
—
3.0
—
3.0
—
3.0
—
ns
tW
CLKAB or CLKBA Pulse Width
HIGH or LOW(3)
3.0
—
3.0
—
3.0
—
3.0
—
ns
tSK(O)
Output Skew(4)
—
0.5
—
0.5
—
0.5
—
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
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PS2035A 03/11/96