PERICOM PI74FCT162823T

PI74FCT16823T/162823/162H823T
PI74FCT16823T
18-BIT REGISTERS
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PI74FCT162823T
PI74FCT162H823T
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
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Fast CMOS
18-Bit Registers
Product Features:
Product Description:
Common Features:
• PI74FCT16823T and PI74FCT162823T are high-speed, low
power devices with high current drive.
• VCC = 5V ±10%
• Hysteresis on all inputs
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide palstic SSOP (V)
PI74FCT16823T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162823T Features:
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
at VCC = 5V, TA = 25°C
PI74FCT162H823T Features:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
Pericom Semiconductor’s PI74FCT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16823T, PI74FCT162823T and PI74FCT162H823
are 18-bit wide registers with clock enable (xCLKEN) and clear
(xCLR) controls that make these devices especially suitable for
parity bus interfacing in high-performance systems. The devices
can be operated as two 9-bit registers or one 18-bit register using the
control inputs. Signal pins are arranged in a flow-through
organization for ease of layout and hysteresis is designed into all
inputs to improve noise margin.
The PI74FCT16823T output buffers are designed with a PowerOff disable function allowing “live insertion” of boards when the
devices are used as backplane drives.
The PI74FCT162823T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H823T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1OE
2OE
1CLR
2CLR
1CLK
2CLK
1CLKEN
2CLKEN
R
R
C
D
C
1 Q1
D
1D 1
2Q1
2D1
To 8 other channels
To 8 other channels
1
PS2040A 03/11/96
PI74FCT16823T/162823/162H823T
18-BIT REGISTERS
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Product Pin Configuration
Product Pin Description
1CLR
1
56
1CLK
1OE
2
55
1CLKEN
1Q1
GND
3
4
54
53
1D1
GND
1Q2
5
52
1D2
1Q3
6
51
1D3
VCC
7
50
VCC
1Q4
8
49
1D4
1Q5
9
48
1D5
1Q6
10
11
47
46
1D6
GND
GND
1D7
1Q9
12 56-PIN 45
V56 44
13
A56
14
43
2Q1
15
42
2D1
2Q2
16
41
2D2
2Q3
GND
17
18
40
39
2D3
GND
2Q4
19
38
2D4
2Q5
20
37
2D5
2Q6
21
36
VCC
22
35
2D6
VCC
2Q7
23
34
2D7
2Q8
24
33
2D8
GND
25
2Q9
26
32
31
GND
2D9
2OE
27
30
2CLKEN
2CLR
28
29
2CLK
1Q7
1Q8
Pin Name
Description
xDx
Data Inputs(1)
xCLK
Clock Inputs
xCLKEN
Clock Enable Inputs (Active LOW)
xCLR
Asynchronous Clear Inputs (Active LOW)
xOE
Output Enable Inputs (Active LOW)
xQx
3-State Outputs
Note: 1. For the PI74FCT162H823T, these pins have “Bus
Hold.” All other pins are standard, outputs, or I/Os.
PI74FCT16823 Truth Table(1)
1D8
Inputs
1D9
Function xOE
High-Z
H
Clear
L
Hold
L
Load
H
H
L
L
1.
2.
2
xCLR xCLKEN xCLK
X
X
X
L
X
X
H
H
X
H
L
↑
H
L
↑
H
L
↑
H
L
↑
Outputs
xDx
X
X
X
L
H
L
H
xQx
Z
L
Q(2)
Z
Z
L
H
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH Transition
Output level before indicated steady-state
input conditions were established.
PS2040A 03/11/96
PI74FCT16823T/162823/162H823T
18-BIT REGISTERS
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................................... –65°C to +150°C
Ambient Temperature with Power Applied .................................... –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... –0.5V to +7.0V
DC Input Voltage ............................................................................ –0.5V to +7.0V
DC Output Current ..................................................................................... 120 mA
Power Dissipation ..........................................................................................1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description
VIH
VIL
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IBHH
IBHL
IOZH(5)
IOZL(5)
VIK
IOS
IO
VH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input HIGH Current
Input HIGH Current
Input HIGH Current
Input LOW Current
Input LOW Current
Input LOW Current
Input LOW Current
Bus Hold
Sustain Current
High-Impedance
Output Current
(3-STATE OUTPUTS)
Clamp Diode Voltage
Short Circuit Current
Output Drive Current
Input Hysteresis
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Standard Input, VCC = Max.
Standard I/O, VCC = Max.
Bus Hold Input(4), VCC = Max.
Bus Hold I/O(4), VCC = Max.
Standard Input, VCC = Min.
Standard I/O, VCC = Min.
Bus Hold Input(4), VCC = Min.
Bus Hold I/O(4), VCC = Min.
Bus Hold Input(4), VCC = Min.
VCC = Max.
VCC = Max.
VCC = Min., IIN = –18 mA
VCC = Max.(3), VOUT = GND
VCC = Max.(3), VOUT = 2.5V
Min.
Typ(2)
Max.
Units
0.8
1
1
±100
±100
–1
–1
±100
±100
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
1
–1
µA
µA
–1.2
–200
–180
V
mA
mA
mV
2.0
VIN = VCC
VIN = VCC
VIN = VCC
VIN = VCC
VIN = GND
VIN = GND
VIN = GND
VIN = GND
VIN = 2.0V
VIN = 0.8V
VOUT = 2.7V
VOUT = 0.5V
–50
+50
–80
–50
–0.7
–140
100
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
3
PS2040A 03/11/96
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18-BIT REGISTERS
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PI74FCT16823T Output Drive Characteristics (Over the Operating Range)
Test Conditions(1)
Parameters Description
VOH
Output HIGH Voltage
VCC = Min., VIN = VIH or VIL
VOL
IOFF
Output LOW Voltage
Power Down Disable
VCC = Min., VIN = VIH or VIL
VCC = 0V, VIN or VOUT ≤ 4.5V
IOH = –3.0 mA
IOH = –15.0 mA
IOH = –32.0 mA
IOL = 64 mA
Min.
Typ(2)
2.5
2.4
2.0
3.5
3.5
3.0
0.2
—
0.55
±100
V
µA
Min.
Typ(2)
Max.
Units
2.4
3.3
0.3
115
–115
0.55
150
–150
V
V
mA
mA
—
Max.
Units
V
PI74FCT162823T/162H823T Output Drive Characteristics (Over the Operating Range)
Test Conditions(1)
Parameters Description
VOH
VOL
IODL
IODH
Output HIGH Voltage
Output LOW Voltage
Output LOW Current
Output HIGH Current
VCC = Min., VIN = VIH or VIL
IOH = –24.0 mA
VCC = Min., VIN = VIH or VIL
IOL = 24 mA
VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3)
VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3)
60
–60
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
CIN
COUT
Description
Test Conditions
Typ
Max.
Units
Input Capacitance
Output Capacitance
VIN = 0V
VOUT = 0V
4.5
5.5
6
8
pF
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
4
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18-BIT REGISTERS
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Power Supply Characteristics
Test Conditions(1)
Parameters Description
Min.
Typ(2)
Max.
Units
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND
or VCC
0.1
500
µA
∆ICC
Supply Current per
Input @ TTL HIGH
VCC = Max.
VIN = 3.4V(3)
0.5
1.5
mA
ICCD
Supply Current per
Input per MHz(4)
VCC = Max.,
Outputs Open
XOE = xCLKEN = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
75
120
µA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fCP = 10 MHZ
50% Duty Cycle
XOE = xCLKEN = GND
fI = 5 MHZ
One Bit Toggling
VCC = Max.,
Outputs Open
fCP = 10 MHZ
50% Duty Cycle
XOE = xCLKEN = GND
Eighteen Bits Toggling
fI = 2.5 MHZ
50% Duty Cycle
VIN = VCC
VIN = GND
0.8
2.7
mA
VIN = 3.4V
VIN = GND
1.3
3.2
VIN = VCC
VIN = GND
4.2
7.1(5)
VIN = 3.4V
VIN = GND
9.2
22.1(5)
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V).
DH = Duty Cycle for TTL Inputs High.
NT = Number of TTL Inputs at DH.
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL).
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at f .
All currents are in milliamps and all frequencies are in megahertz.
5
PS2040A 03/11/96
PI74FCT16823T/162823/162H823T
18-BIT REGISTERS
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PI74FCT16823T Switching Characteristics over Operating Range
Parameters
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tSU
tH
tW
tW
tREM
tSK(O)
(1)
16823AT
16823BT
16823CT
16823DT
16823ET
Com.
Com.
Com.
Com.
Com.
Description
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
CL = 50 pF
RL = 500Ω
CL = 300 pF(3)
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 300 pF(3)
RL = 500Ω
CL = 5 pF(3)
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 50 pF
RL = 500Ω
1.5
10.0
1.5
7.5
1.5
6.0
1.5
5.0
1.5
4.4
ns
1.5
20.0
1.5
15.0
1.5
12.5
1.5
8.5
1.5
8.0
ns
1.5
14.0
1.5
9.0
1.5
8.0
1.5
5.0
1.5
4.4
ns
1.5
12.0
1.5
8.0
1.5
7.0
1.5
4.8
1.5
4.4
ns
1.5
23.0
1.5
15.0
1.5
12.5
1.5
10.0
1.5
9.0
ns
1.5
7.0
1.5
6.5
1.5
6.2
1.5
5.0
1.5
4.0
ns
1.5
8.0
1.5
7.5
1.5
6.5
1.5
5.0
1.5
4.0
ns
4.0
—
3.0
—
3.0
—
3.0
—
1.5
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
0
—
ns
4.0
—
3.0
—
3.0
—
3.0
—
2.5
—
ns
2.0
—
0
—
0
—
0
—
0
—
ns
7.0
—
6.0
—
6.0
—
6.0
—
3.0
—
ns
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
3.0
3.0
—
—
ns
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
XCLK to XQX
Propagation Delay
XCLR to XQX
Output Enable Time
XOE to XQX
Output Disable Time(3)
XOE to XQX
Setup Time HIGH or
LOW, XDX to XCLK
Hold Time HIGH or
LOW, XDX to XCLK
Setup Time HIGH or
LOW, XCLKEN to XCLK
Hold Time HIGH or
LOW, XCLKEN to XCLK
xCLK Pulse Width
HIGH or LOW(3)
xCLR Pulse Width LOW(3)
Recovery Time(3)
XCLR to XCLK
Output Skew (4)
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
6
PS2040A 03/11/96
PI74FCT16823T/162823/162H823T
18-BIT REGISTERS
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT162823T Switching Characteristics over Operating Range
Parameters
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tSU
tH
tW
tW
tREM
tSK(O)
(1)
162823AT
162823BT
162823CT
162823DT
162823ET
Com.
Com.
Com.
Com.
Com.
Description
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
CL = 50 pF
RL = 500Ω
CL = 300 pF(3)
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 300 pF(3)
RL = 500Ω
CL = 5 pF(3)
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 50 pF
RL = 500Ω
1.5
10.0
1.5
7.5
1.5
6.0
1.5
5.0
1.5
4.4
ns
1.5
20.0
1.5
15.0
1.5
12.5
1.5
8.5
1.5
8.0
ns
1.5
14.0
1.5
9.0
1.5
8.0
1.5
5.0
1.5
4.4
ns
1.5
12.0
1.5
8.0
1.5
7.0
1.5
4.8
1.5
4.4
ns
1.5
23.0
1.5
15.0
1.5
12.5
1.5
10.0
1.5
9.0
ns
1.5
7.0
1.5
6.5
1.5
6.2
1.5
5.0
1.5
4.0
ns
1.5
8.0
1.5
7.5
1.5
6.5
1.5
5.0
1.5
4.0
ns
4.0
—
3.0
—
3.0
—
3.0
—
1.5
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
0
—
ns
4.0
—
3.0
—
3.0
—
3.0
—
2.5
—
ns
2.0
—
0
—
0
—
0
—
0
—
ns
7.0
—
6.0
—
6.0
—
6.0
—
3.0
—
ns
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
3.0
3.0
—
—
ns
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
XCLK to XQX
Propagation Delay
XCLR to XQX
Output Enable Time
XOE to XQX
Output Disable Time(3)
XOE to XQX
Setup Time HIGH or
LOW, XDX to XCLK
Hold Time HIGH or
LOW, XDX to XCLK
Setup Time HIGH or
LOW, XCLKEN to XCLK
Hold Time HIGH or
LOW, XCLKEN to XCLK
xCLK Pulse Width
HIGH or LOW(3)
xCLR Pulse Width LOW(3)
Recovery Time(3)
XCLR to XCLK
Output Skew (4)
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
7
PS2040A 03/11/96
PI74FCT16823T/162823/162H823T
18-BIT REGISTERS
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT162H823T Switching Characteristics over Operating Range
Parameters
t PLH
t PHL
t PHL
t PZH
t PZL
t PHZ
t PLZ
tSU
tH
tSU
tH
tW
tW
tREM
tSK(O)
(1)
162H823AT
162H823BT
1628H23CT
162H823DT
162H823ET
Com.
Com.
Com.
Com.
Com.
Description
Conditions
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Propagation Delay
XCLK to XQX
CL = 50 pF
RL = 500Ω
CL = 300 pF(3)
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 300 pF(3)
RL = 500Ω
CL = 5 pF(3)
RL = 500Ω
CL = 50 pF
RL = 500Ω
CL = 50 pF
RL = 500Ω
1.5
10.0
1.5
7.5
1.5
6.0
1.5
5.0
1.5
4.4
ns
1.5
20.0
1.5
15.0
1.5
12.5
1.5
8.5
1.5
8.0
ns
1.5
14.0
1.5
9.0
1.5
8.0
1.5
5.0
1.5
4.4
ns
1.5
12.0
1.5
8.0
1.5
7.0
1.5
4.8
1.5
4.4
ns
1.5
23.0
1.5
15.0
1.5
12.5
1.5
10.0
1.5
9.0
ns
1.5
7.0
1.5
6.5
1.5
6.2
1.5
5.0
1.5
4.0
ns
1.5
8.0
1.5
7.5
1.5
6.5
1.5
5.0
1.5
4.0
ns
4.0
—
3.0
—
3.0
—
3.0
—
1.5
—
ns
2.0
—
1.5
—
1.5
—
1.5
—
0
—
ns
4.0
—
3.0
—
3.0
—
3.0
—
2.5
—
ns
2.0
—
0
—
0
—
0
—
0
—
ns
7.0
—
6.0
—
6.0
—
6.0
—
3.0
—
ns
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
6.0
6.0
—
—
3.0
3.0
—
—
ns
ns
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
Propagation Delay
XCLR to XQX
Output Enable Time
XOE to XQX
Output Disable Time(3)
XOE to XQX
Setup Time HIGH or
LOW, XDX to XCLK
Hold Time HIGH or
LOW, XDX to XCLK
Setup Time HIGH or
LOW, XCLKEN to XCLK
Hold Time HIGH or
LOW, XCLKEN to XCLK
xCLK Pulse Width
HIGH or LOW(3)
xCLR Pulse Width LOW(3)
Recovery Time(3)
XCLR to XCLK
Output Skew (4)
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
8
PS2040A 03/11/96