AD AD5273BRJ10

64-Position OTP Digital Potentiometer
AD5273
FEATURES
64 Positions
OTP (One-Time-Programmable)1 Set-and-Forget
Resistance Setting
1 k⍀, 10 k⍀, 50 k⍀, 100 k⍀ End-to-End Terminal Resistance
Compact Standard SOT23-8 Package
Ultralow Power: IDD = 5 ␮A Max
Fast Settling Time: tS = 5 ␮s Typ in Power-Up
I2C Compatible Digital Interface
Computer Software2 Replaces ␮C in Factory Programming
Applications
Wide Temperature Range: –40ⴗC to +105ⴗC
5 V Programming Voltage
Low Operating Voltage, 2.7 V to 5.5 V
OTP Validation Check Function
APPLICATIONS
Systems Calibrations
Electronics Level Settings
Mechanical Trimmers® Replacement in New Designs
Automotive Electronics Adjustments
Transducer Circuits Adjustments
Programmable Filters up to 6 MHz BW3
GENERAL DESCRIPTION
The AD5273 is a 64-position, One-Time-Programmable (OTP)
digital potentiometer4 that employs fuse link technology to achieve
the permanent program setting. This device performs the same
electronic adjustment function as most mechanical trimmers and
variable resistors. It allows unlimited adjustments before permanently setting the resistance values. The AD5273 is programmed
using a 2-wire, I2C compatible digital control. During the write
mode, a fuse blow command is executed after the final value
is determined, therefore freezing the wiper position at a given
setting (analogous to placing epoxy on a mechanical trimmer).
When this permanent setting is achieved, the value will not change
regardless of the supply variations or environmental stresses under
normal operating conditions. To verify the success of permanent
programming, Analog Devices patterned the OTP validation such
that the fuse status can be discerned from two validation bits in
the read mode.
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
A0
A
I2C INTERFACE
AND
CONTROL LOGIC
B
AD5273
WIPER
REGISTER
VDD
GND
W
FUSE
LINK
In addition, for applications that program AD5273 at the factory,
Analog Devices offers device programming software2 running in
Windows® NT, 2000, and XP operating systems. This software
application effectively replaces any external I2C controllers, which
in turn enhances users’ systems time-to-market.
AD5273 is available in 1 k⍀, 10 k⍀, 50 k⍀, and 100 k⍀ in
compact SOT23 8-lead standard package and operates from
–40°C to +105°C.
Besides its unique OTP feature, the AD5273 lends itself well to
general digital potentiometer applications due to its effective
resolution, array resistance options, small footprint, and low cost.
An AD5273 evaluation kit and software are available. The kit includes
the connector and cable that can be converted for further factory
programming applications.
For applications that require dynamic adjustment of resistance
settings with nonvolatile EEMEM, users should refer to AD523x
and AD525x families of nonvolatile memory digital potentiometers.
NOTES
1
One-Time-Programmable—Unlimited adjustments before permanent setting.
2
ADI cannot guarantee the software to be 100% compatible in all systems due to
the wide variations in computer configurations.
3
Applies to 1 k⍀ parts only.
4
The terms digital potentiometer, VR, and RDAC are used interchangeably.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002. All rights reserved.
AD5273–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 1 k, 10 k, 50 k, 100 k VERSIONS
(VDD = 2.7 V to 5.5 V, VA < VDD, VB = 0 V, –40°C < TA < +105°C, unless otherwise noted.)
Parameter
DC CHARACTERISTICS
RHEOSTAT MODE
Resolution
Resistor Differential NL2
(10 k⍀, 50 k⍀, 100 k⍀)
(1 k⍀)
Resistor Nonlinearity2
(10 k⍀, 50 k⍀, 100 k⍀)
(1 k⍀)
Nominal Resistance Tolerance3
(10 k⍀, 50 k⍀, 100 k⍀)
Nominal Resistance (1 k⍀)
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider
Temperature Coefficient
Full-Scale Error
Zero-Scale Error
(10 k⍀, 50 k⍀, 100 k⍀)
(1 k⍀)
RESISTOR TERMINALS
Voltage Range5
Capacitance6 A, B
Symbol
Conditions
Min
Typ1
N
R-DNL
Max
Unit
6
Bits
LSB
LSB
LSB
LSB
LSB
RWB, VA = NC
RWB, VA = NC
–0.5
–1
+0.05
+0.25
+0.5
+1
RWB, VA = NC
RWB, VA = NC
TA = 25°C
–0.5
–5
+0.10
+2
+0.5
+5
R-INL
⌬RAB
RAB
RAB/⌬T
RW
–30
0.8
Capacitance6 W
CW
Common Mode Leakage
ICM
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High (SDO)
Output Logic Low (SDO)
Input Logic Current
Input Capacitance6
VIH
VIL
VIH
VIL
VIH
VIL
IIL
CIL
POWER SUPPLIES
Power Supply Range
OTP Power Supply7
Supply Current
OTP Supply Current8
Power Dissipation9
Power Supply Sensitivity
VDD
VDD_OTP
IDD
IDD_OTP
PDISS
PSSR
LSB
LSB
–1
–6
0
0
0
0
1
5
ppm/°C
LSB
LSB
LSB
LSB
0
VDD
V
25
pF
55
pF
nA
–0.5
–0.5
Code = 20H
Code = 3FH
Code = 00H
Code = 00H
VA,B,W
CA,B
+0.5
+0.5
VAB = VDD, Wiper = No Connect
IW = VDD/R, VDD = 3 V or 5 V
DNL
INL
⌬VW/⌬T
VWFSE
VWZSE
100
%
k⍀
ppm/°C
⍀
1.2
300
60
+0.1
+30
1.6
10
f = 5 MHz, Measured to GND,
Code = 20H
f = 1 MHz, Measured to GND,
Code = 20H
VA = VB = VW
1
2.4
0.8
VLOGIC = 3 V
VLOGIC = 3 V
2.1
0.6
4.9
VIN = 0 V or 5 V
TA = 25°C
VIH = 5 V or VIL = 0 V
TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
0.01
5
2.7
5
0.1
5.5
6
5
100
0.2
–0.015
–2–
0.4
1
0.3
+0.015
V
V
V
V
V
V
µA
pF
V
V
µA
mA
mW
%/%
REV. 0
AD5273
Parameter
Symbol
Conditions
Total Harmonic Distortion
BW_1 k
BW_10 k
BW_50 k
BW_100 k
THDW
Adjustment Settling Time
tS1
OTP Settling Time12
tS_OTP
Power-Up Settling Time –
Post Fuses Blown
R AB = 1 k, Code = 20H
R AB = 10 k, Code = 20H
R AB = 50 k, Code = 20H
R AB = 100 k, Code = 20H
VA = 1 V rms, R AB = 1 k,
V B = 0 V, f = 1 kHz
VA = 5 V ± 1 LSB Error Band, V B = 0,
Measured at V W
VA = 5 V ± 1 LSB Error Band, V B = 0,
Measured at V W
tS2
Resistor Noise Voltage
eN_WB
Min
Typ
Max
Unit
6, 10, 11
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
VA = 5 V ± 1 LSB Error Band, VB = 0,
Measured at VW
RAB = 1 k, f = 1 kHz, Code = 20H
RAB = 20 kk, f = 1 kHz, Code = 20H
RAB = 50 kk, f = 1 kHz, Code = 20H
RAB = 100 kk, f = 1 kHz, Code = 20H
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 11, 13)
SCL Clock Frequency
fSCL
tBUF Bus Free Time between
STOP and START
t1
tHD;STA Hold Time
(repeated START)
t2
After this period, the first clock
pulse is generated.
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU;STA Setup Time for START
Condition
t5
tHD;DAT Data Hold Time
t6
tSU;DAT Data Setup Time
t7
tF Fall Time of Both SDA and
SCL Signals
t8
tR Rise Time of Both SDA and
SCL Signals
t9
tSU;STO Setup Time for STOP
Condition
t10
6000
600
110
60
kHz
kHz
kHz
kHz
0.014
%
5
µs
400
ms
5
3
13
20
28
µs
nV/√Hz
nV/√Hz
nV/√Hz
√
√Hz
nV/√Hz
√
√Hz
400
kHz
1.3
µs
0.6
1.3
0.6
µs
µs
µs
0.6
0.1
0.6
50
0.9
µs
µs
µs
0.3
µs
0.3
µs
µs
NOTES
1
Typicals represent average readings at 25°C, VDD = 5 V, VSS = 0 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, Wiper (VW) = No Connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Different from operating power supply, power supply for OTP is used one time only.
8
Different from operating current, supply current for OTP lasts approximately 400 ms for one time needed only.
9
PDISS is calculated from (IDD  VDD). CMOS logic level inputs result in minimum power dissipation.
10
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
11
All dynamic characteristics use VDD = 5 V.
12
Different from settling time after fuses are blown. The OTP settling time occurs once only.
13
See Figure 1 for location of measured values.
Specifications subject to change without notice.
REV. 0
–3–
AD5273
ABSOLUTE MAXIMUM RATINGS1
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . . .300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
Thermal Resistance3 ␪JA, SOT-23 . . . . . . . . . . . . . . . . 230°C/W
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +6.5 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . GND, VDD
A–B, A–W, B–W
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Digital Input and Output Voltage to GND . . . . . . . . . . 0 V, VDD
Operating Temperature Range . . . . . . . . . . . . –40°C to +105°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . . .150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating; functional operation of the device at
these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied voltage
across any two of the A, B, and W terminals at a given resistance.
3
Package Power Dissipation = (TJ MAX – TA)/␪JA
ORDERING GUIDE
Model
Resistance
RAB (k)
Package
Code
Package
Description
Full Container
Quantities
Brand
AD5273BRJ1-REEL7
AD5273BRJ10-REEL7
AD5273BRJ50-REEL7
AD5273BRJ100-REEL7
AD5273BRJ1-R2
AD5273BRJ10-R2
AD5273BRJ50-R2
AD5273BRJ100-R2
AD5273EVAL
1
10
50
100
1
10
50
100
*
RJ
RJ
RJ
RJ
RJ
RJ
RJ
RJ
NA
SOT23-8
SOT23-8
SOT23-8
SOT23-8
SOT23-8
SOT23-8
SOT23-8
SOT23-8
NA
3000
3000
3000
3000
250
250
250
250
*
DYA
DYB
DYC
DYD
DYA
DYB
DYC
DYD
NA
*Users should order samples additionally as the evaluation kit comes with a socket but does not include the parts.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD5273 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
–4–
REV. 0
AD5273
W 1
VDD 2
8
AD5273
A
7
B
TOP VIEW
GND 3 (Not to Scale) 6 A0
SCL 4
5
SDA
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
W
Wiper Terminal W
2
VDD
Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V.
For OTP programming, VDD needs to be a minimum of 5 V.
3
GND
Common Ground
4
SCL
Serial Clock Input. Requires Pull-Up Resistor.
5
SDA
Serial Data Input/Output. Requires Pull-Up Resistor.
6
A0
I2C Device Address Bit
7
B
Resistor Terminal B
8
A
Resistor Terminal A
REV. 0
–5–
AD5273–Typical Performance Characteristics
0.10
0.5
RAB = 10k
POTENTIOMETER MODE DNL – LSB
RHEOSTAT MODE INL – LSB
RAB = 10k
TA = 25C
0.3
VDD = 3V
0.1
–0.1
VDD = 5V
–0.3
–0.5
0
8
16
24
32
40
CODE – Decimal
48
56
0.06
TA = +85C
–0.02
TA = +25C
–0.06
TPC 1. RINL vs. Code vs. Supply Voltages
0
8
16
24
32
40
CODE – Decimal
48
POTENTIOMETER MODE INL – LSB
0.15
VDD = 5V
0.05
–0.05
VDD = 3V
–0.15
–0.25
0
8
16
24
32
40
CODE – Decimal
48
56
RAB = 10k
TA = 25C
0.06
3V
0.02
5V
–0.02
–0.06
–0.10
64
TPC 2. RDNL vs. Code vs. Supply Voltages
0
8
16
24
32
40
CODE – Decimal
48
56
64
TPC 5. INL vs. Code vs. Supply Voltages
0.10
0.10
RAB = 10k
TA = 25C
POTENTIOMETER MODE DNL – LSB
RAB = 10k
POTENTIOMETER MODE INL – LSB
64
0.10
RAB = 10k
TA = 25C
0.06
TA = +85C
TA = +125C
0.02
–0.02
TA = +25C
–0.06
–0.10
56
TPC 4. DNL vs. Code vs. Temperature
0.25
RHEOSTAT MODE DNL – LSB
TA = +125C
0.02
–0.10
64
TA = –40C
TA = –40C
0.06
3V
0.02
5V
–0.02
–0.06
–0.10
0
8
16
24
32
40
CODE – Decimal
48
56
64
0
TPC 3. INL vs. Code vs. Temperature
8
16
24
32
40
CODE – Decimal
48
56
64
TPC 6. DNL vs. Code vs. Supply Voltages
–6–
REV. 0
AD5273
1.0
TA = 25C
RAB = 10k
CODE = 20H
0.020
RAB = 10k
0.9
0.8
0.7
0.015
ZSE – LSB
POTENTIOMETER MODE LINEARITY – LSB
0.025
0.010
0.6
0.5
VDD = 3V
0.4
VDD = 5V
0.3
0.005
0.2
0.1
0
0
1
2
3
4
SUPPLY VOLTAGE – V
5
0
–40
6
–20
TPC 7. INL Oversupply Voltage
VDD = 5.5V
RAB = 10k
0.3
0.14
SUPPLY CURRENT – A
RHEOSTAT MODE LINEARITY – LSB
100
80
0.16
TA = 25C
RAB = 10k
CODE = 20H
0.2
0.1
0
0.12
0.10
0.08
0.06
0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE – V
5.0
0.04
–55
6.0
TPC 8. RINL Oversupply Voltage
–15
–35
5
25
45
65
TEMPERATURE – C
85
105
115
TPC 11. Supply Current vs. Temperature
0
10
RAB = 10k
–0.1
1
–0.2
SUPPLY CURRENT – mA
VDD = 5V
–0.3
FSE – LSB
20
40
60
TEMPERATURE – C
TPC 10. Zero-Scale Error
0.4
–0.1
0
–0.4
VDD = 3V
–0.5
–0.6
–0.7
VDD = 5V
TA = 25C
RAB = 10k
ALL DIGITAL
PINS TIED
TOGETHER
0.1
VDD = 2.7V
0.01
0.001
–0.8
–0.9
–1.0
–40
0.0001
–20
0
20
40
60
TEMPERATURE – C
80
100
0
TPC 9. Full-Scale Error
REV. 0
1
2
3
4
INPUT LOGIC VOLTAGE – V
5
6
TPC 12. Supply Current vs. Digital Input Voltage
–7–
AD5273
VDD = 5.5V
TA = 25C
400
0
–6
1k
200
10k
100
0
–12
08H
–18
–24
04H
02H
–30
01H
–36
50k
–100
–42
100k
–200
–300
3FH
20H
10H
300
MAGNITUDE – dB
RHEOSTAT MODE TEMPCO – ppm/C
500
–48
0
8
16
24
32
40
CODE – Decimal
48
–54
100
64
56
TPC 13. Rheostat Mode Tempco ⌬RWB/⌬T vs. Code
00H
1k
10k
FREQUENCY – Hz
100k
1M
TPC 16. Gain vs. Frequency vs. Code, RAB = 10 k⍀
VDD = 5.5V
0
30
1k
20
–6
10k
10
0
–10
10k
–20
10H
–12
08H
–18
–24
04H
02H
–30
–36
10k
01H
–42
–30
–48
–40
–54
100
8
0
16
24
32
40
CODE – Decimal
48
56
64
TPC 14. Potentiometer Mode Tempco ⌬VWB/⌬T vs. Code
3FH
0
20H
–6
–6
MAGNITUDE – dB
08H
–18
04H
–24
–30
–36
02H
01H
100k
1M
3FH
08H
–24
02H
–48
–48
10k
100k
FREQUENCY – Hz
1M
–54
100
10M
TPC 15. Gain vs. Frequency vs. Code, RAB = 1 k⍀
04H
–30
–36
00H
10H
–18
–42
1k
10k
FREQUENCY – Hz
–12
–42
–54
100
1k
20H
10H
–12
00H
TPC 17. Gain vs. Frequency vs. Code, RAB = 50 k⍀
0
MAGNITUDE – dB
3FH
20H
MAGNITUDE – dB
POTENTIOMETER MODE TEMPCO – ppm/C
40
01H
00H
1k
10k
FREQUENCY – Hz
100k
1M
TPC 18. Gain vs. Frequency vs. Code, RAB = 100 k⍀
–8–
REV. 0
AD5273
12
1k
10k
6
0
MAGNITUDE – dB
fCLK = 100kHz
VDD = 5.5V
VA = 5.5V
VB = GND
–6
50k
–12
–18
VW = 10mV/DIV
100k
–24
–30
–36
SCL = 5V/DIV
10mV
–42
–48
100
1k
10k
100k
FREQUENCY – Hz
1M
5V
500ns
10M
TPC 22. Digital Feedthrough vs. Time
TPC 19. –3 dB Bandwidth
0.3
VDD = 5.5V
VA = 5.5V
VB = GND
0.2
1k
MAGNITUDE – dB
0.1
DATA 00 H
3FH
fCLK = 400kHz
0
VW = 5V/DIV
–0.1
10k
100k
–0.2
–0.3
SCL = 5V/DIV
50k
–0.4
–0.5
–0.6
5V
–0.7
10
100
1k
10k
100k
FREQUENCY – Hz
1M
5V
5s
10M
TPC 23. Large Settling Time
TPC 20. Normalized Gain Flatness vs. Frequency
POWER SUPPLY REJECTION RATIO – –dB
80
TA = 25C
CODE = 20H
VA = 2.5V, VB = 0V
VDD = 5.5V
VA = 5.5V
VB = GND
fCLK = 100kHz
1FH
DATA 20H
60
VDD = 5V DC 1.0V p-p AC
40
VDD = 3V DC 0.6V p-p AC
VW = 50mV/DIV
20
SCL = 5V/DIV
50mV
0
100
1k
10k
FREQUENCY – Hz
100k
200ns
1M
TPC 24. Midscale Glitch Energy
TPC 21. PSRR vs. Frequency
REV. 0
5V
–9–
AD5273
10
VA = VB = OPEN
TA = 25C
THEORETICAL IWB_MAX – mA
OTP PROGRAMMED AT MS
VDD = 5.5V
VA = 5.5V
RAB = 10k
VW = 1V/DIV
VDD = 5V/DIV
1V
5V
RAB = 1k
RAB = 10k
1.0
RAB = 50k
0.1
RAB = 100k
5s
0.01
0
24
32
40
CODE – Decimal
16
8
48
56
64
TPC 26. IWB_MAX vs. Code
TPC 25. Power-Up Settling Time, after Fuses Blown
t6
t9
t8
SCL
t4
t2
t5
t10
t7
t3
t9
t8
SDA
t1
P
P
S
Figure 1. Interface Timing Diagram
Table I. SDA Write Mode Bit Format
S
0
1
0
1
1
0
A0
0
A
T
X
X
SLAVE ADDRESS BYTE
X
X
X
X
X
A
X
X
D5
INSTRUCTION BYTE
D4
D3
D2
D1
D0
A
P
DATA BYTE
Table II. SDA Read Mode Bit Format
S
0
1
0
1
1
0
A0
1
A
E1
SLAVE ADDRESS BYTE
E0
D5
D4
D3
D2
D1
D0
A
P
DATA BYTE
SDA BITS DEFINITIONS AND DESCRIPTIONS
S = Start Condition
D5, D4, D3, D2, D1, D0 = Data Bits
P = Stop Condition
E1, E0 = OTP Validation Bits
A = Acknowledge
0, 0 = Ready to Program
X = Don’t Care
0, 1 = Test Fuse not Blown Successfully. (Check Setup.)
T = OTP Programming Bit. Logic 1 programs wiper position
permanently.
1, 0 = Fatal Error. Retry.
1, 1 = Programmed Successfully. No Further Adjustments
Possible.
–10–
REV. 0
AD5273
THEORY OF OPERATION
DETERMINING THE VARIABLE RESISTANCE AND
VOLTAGE*
Rheostat Operation
The AD5273 is a One-Time-Programmable (OTP), Set-andForget, 6-bit digital potentiometer. It is comprised of six data
fuses, which control the address decoder for programming the
RDAC, one user mode test fuse for checking setup error, and one
programming lock fuse for disabling any further programming
once the data fuses are programmed correctly.
The nominal resistance of the RDAC between terminals A and B
is available in 1 k⍀, 10 k⍀, 50 k⍀, and 100 k⍀. The final two or
three digits of the part number determine the nominal resistance
value, e.g., 1 k⍀ = 1, 10 k⍀ = 10; 50 k⍀ = 50; 100 k⍀ = 100. The
nominal resistance (RAB) of the RDAC has 64 contact points
accessed by the wiper terminal, plus the B terminal contact. The
6-bit data in the RDAC latch is decoded to select one of the 64
possible settings. Assuming that a 10 k⍀ part is used, the wiper’s
first connection starts at the B terminal for data 00H. Since there
is a 60 ⍀ wiper contact resistance, such connection yields a
minimum of 60 ⍀ resistance between terminals W and B. The
second connection is the first tap point and corresponds to 219 ⍀
(RWB = RAB/63 + RW = 159 + 60) for data 01H. The third connection is the next tap point representing 378 ⍀ (159 ⫻ 2 + 60)
for data 02H, and so on. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
10060 ⍀ [RAB + RW]. Figure 3 shows a simplified diagram of the
equivalent RDAC circuit. The general equation determining the
digitally programmed output resistance between W and B is:
D
RWB (D) =
¥ RAB + RW
63
(1)
where:
One-Time-Programming (OTP)
AD5273 has an internal power-on preset that places the wiper
in the midscale during power-on. After the wiper is adjusted to
the desired position, the wiper setting can be permanently programmed by setting the T bit, MSB of the Instruction Byte, to 1
along with the proper coding. Refer to Table I.
The one-time program control circuit has two validation bits, E1
and E0, that can be read back in the Read mode for checking the
programming status. Table III shows the validation status.
Table III. Validation Status
E1 E0 Status
0
0
1
1
0
1
0
1
Ready for Programming
Test Fuse Not Blown Successfully (For Setup Checking)
Fatal Error. Some fuses are not blown. Retry.
Successful. No further programming is possible.
The detailed programming sequence is explained further below.
When the OTP T bit is set, the internal clock is enabled. The
program will attempt to blow a test fuse. The operation stops if
this fuse is not blown successfully. The validation bits, E1 and E0,
show 01 and the users should check the setup. If the test fuse is
blown successfully, the data fuses will be programmed next. The
six data fuses will be programmed in six clock cycles. The output
of the fuses is compared with the code stored in the DAC register. If they do not match, E1 E0 = 10 is issued as a fatal error and
the operation stops. Users may retry with the same code. If the
output and the stored code match, the programming lock fuse
will be blown so that no further programming is possible. In the
meantime, E1 E0 will issue 11 indicating the lock fuse is blown
successfully. All the fuse latches are enabled at power on from this
point on. Figure 2 shows a detailed functional block diagram.
D is the decimal equivalent of the binary code loaded in the 6-bit
RDAC register.
RAB is the nominal end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of the
internal switch.
Again, if RAB = 10 k⍀ and terminal A is opened, the following
output resistance values RWB will be set for the following RDAC
latch codes.
D(DEC)
R WB (⍀)
Output State
63
32
1
0
10060
5139
219
60
Full-Scale (RAB + RW)
Midscale
1 LSB
Zero-Scale (Wiper contact resistance)
*Applies to Potentiometer Mode only
A
SCL
SDA
I2C
INTERFACE
DAC
REG.
DECODER
MUX
W
B
COMPARATOR
FUSES
EN
FUSE
REG.
ONE TIME
PROGRAM/TEST
CONTROL BLOCK
Figure 2. Detailed Functional Block Diagram
REV. 0
–11–
AD5273
Note that in the zero-scale condition a finite wiper resistance of
60 ⍀ is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of no
more than 20 mA. Otherwise, degradation or possible destruction
of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, terminal B can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value. The
general equation for this operation is:
63 – D
RWA (D) =
¥ RAB + RW
63
(2)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as:
R (D )
VW (D) = WB
VA
RAB
(4)
Operation of the digital potentiometer in the divider mode results
in a more accurate operation overtemperature. Unlike the rheostat
mode, the output voltage is dependent mainly on the ratio of the
internal resistors RWA and RWB and not the absolute values, therefore, the temperature drift reduces to 10 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figures 4a and 4b. This
applies to digital input pins SDA and SCL.
For RAB = 10 k⍀ and terminal B is opened, the following output
resistance RWA will be set for the following RDAC latch codes.
D (DEC)
R WA ()
Output State
63
32
1
0
60
4980
9901
10060
Full-Scale
Midscale
1 LSB
Zero-Scale
340
LOGIC
Figure 4a. ESD Protection of Digital Pins
A,B,W
The typical distribution of the nominal resistance RAB from channel
to channel matches within ±1%. Device-to-device matching is
process lot dependent and is possible to have ±30% variation.
Figure 4b. ESD Protection of Resistor Terminals
A
D5
D4
D3
D2
D1
D0
TERMINAL VOLTAGE OPERATING RANGE
The VDD of AD5273 defines the boundary conditions for proper
3-terminal digital potentiometer operation. Supply signals present
on terminals A, B, and W that exceed VDD will be clamped by the
internal forward-biased diodes. See Figure 5.
RS
RS
VDD
W
A
W
B
GND
RDAC
LATCH
AND
DECODER
RS
Figure 5. Maximum Terminal Voltages Set by VDD
B
POWER-UP SEQUENCE
Since there are ESD protection diodes that limit the voltage compliance at terminals A, B, and W (Figure 5), it is important to power
VDD first before applying any voltage to terminals A, B, and W.
Otherwise, the diode will be forward-biased such that VDD will
be powered unintentionally and may affect the rest of the users’
circuits. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and VA/B/W. The order of powering VA,
VB, VW, and digital inputs is not important as long as they are
powered after VDD.
Figure 3. Equivalent RDAC Circuit
Voltage Output Operation
Similar to the D/A converter, the digital potentiometer easily
generates a voltage divider at wiper-to-B and wiper-to-A to be
proportional to the input voltage at A–B. Unlike the polarity of
VDD, which must be positive, voltage across A–B, W–A, and W–B
can be at either polarity as long as the voltage across them is < IVDDI.
If ignoring the effect of the wiper resistance for approximation,
connecting terminal A to 5 V and terminal B to ground produces
an output voltage at the wiper-to-B starting at 0 V up to 5 V. Each
LSB of voltage is equal to the voltage applied across terminal A–B,
divided by the 63 position of the potentiometer divider as:
D
VW (D) =
VA
63
(3)
POWER SUPPLY CONSIDERATIONS
AD5273 employs fuse link technology, which requires an adequate
current density to blow the internal fuses to achieve a given setting.
As a result, the power supply, either an on-board linear regulator
or rack-mount power supply, must be rated at 5 V with less than
±5% tolerance. The supply should be able to handle 100 mA of
transient current, and lasts about 400 ms, during the one-time
programming. A low ESR 1 µF to 10 µF tantalum or electrolytic
–12–
REV. 0
AD5273
bypass capacitor should be applied at VDD to minimize the transient
disturbances during the programming as shown in Figure 6a. Once
the programming is completed, the supply voltage can be reduced
to 2.7 V with supply current of less than 1 µA.
5V 5%
100mA
SCL
10F
SDA
Figure 6a. OTP Power Supply Requirement
5V 5%
(REMOVED AFTER OTP PROGRAMMING)
100mA
3V
C
10F
There are two ways of controlling the AD5273. Users can either
program the device with computer software or with external I2C
controllers.
Software Programming
AD5273
VDD
C
CONTROLLING THE AD5273
Due to the advantage of the one-time-programmable feature, most
systems using the AD5273 will program the devices in the factories before shipping to the end users. As a result, ADI offers device
programming software that can be implemented in the factory on
computers running Windows NT, 2000, and XP platforms. The
software can be downloaded from the AD5273 product folder at
www.analog.com and is an executable file that does not require
any programming languages or user programming skills. Figure 7
shows the software interface.
AD5273
Write
VDD
The AD5273 starts at midscale after power up prior to any OTP
programming. To increment or decrement the resistance, the user
may simply move the scrollbar on the left. Once the desired setting is found, the user may press the Program Permanent button
to lock the setting permanently. To write any specific values, the
user should use the bit pattern control in the upper screen and
press the Run button. The format of writing data to the device
is shown in Table I. Once the desired setting is found, the user
may turn the T bit to 1 and press the Run button to program the
setting permanently.
SCL
SDA
Figure 6b. External Power Supply Applied for Programming
For users who have an on-board 3 V supply for portable applications, a separate 5 V supply must be applied one time in the
factories for programming and a low VF Schoktty Diode should
be designed with the AD5273 to isolate the supply voltages.
Once the programming is done, the 5 V supply can be removed
with VDD maintained at 2.7 V for minimum operation. Figure 6b
shows one such implementation.
Read
To read the validation bits and data out from the device, the user
may simply press the Read button. The user may also set the bit
pattern in the upper screen and press the Run button. The format
of reading data out from the device is shown in Table II.
Figure 7. Computer Software
REV. 0
–13–
AD5273
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
Address byte, which consists of the 6 MSBs as slave address
defined as 010110. The next bit is AD0; it is an I2C device
address bit. Depending on the states of their AD0 bits, two
AD5273s can be addressed on the same bus. (See Figure 12.)
The last LSB is the R/W bit, which determines whether data
will be read from or written to the slave device.
VDD
R4
10k
R3
100
R5
10k
SCL
R2
100 READ
SDA
100
R1 WRITE
Figure 8. Parallel Port Connection. Pin 2 = SDA_write,
Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND
In both Read and Write operations, the program generates the
I2C digital signals through the parallel port LPT1 pins 2, 3, 15,
and 25 for SDA_write, SCL, SDA_read, and DGND, respectively,
to control the device. See Figure 8.
To apply the device programming software in the factories, users
may lay out the AD5273 SCL and SDA pads on the PCB such
that the programming signals can be communicated to and from
the parallel port. Figure 9 shows a recommended AD5273 PCB
layout that pogo pins can be inserted for factory programming.
100 ⍀ resistors should also be put in series to the SCL and SDA
pins to prevent damaging the PC parallel port. Pull-up resistors
on SCL and SDA are also required.
W
VDD
DGND
SCL
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register.
A
B
A0
SDA
Figure 9. Recommended AD5273 PCB Layout. The SCL
and SDA pads allow pogo pins to be inserted so that
signals can be communicated through the parallel port
for programming. Refer to Figure 8.
For users who do not use the software solution, the AD5273 can
be controlled via an I2C compatible serial bus and is connected
to this bus as a slave device. Referring to Figures 10a, 10b, and
11, the 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when SDA goes from high to low while
SCL is high, Figure 10a. The following byte is the Slave
2. A Write operation contains one more Instruction byte than the
Read operation. The Instruction byte in the Write mode follows the Slave Address byte. The MSB of the Instruction byte
labeled T is the One Time Programming bit. After acknowledging the Instruction byte, the last byte in the Write mode
is the Data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
Acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL. See Figure 10a.
3. In the Read mode, the Data byte follows immediately after the
acknowledgment of the Slave Address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (slight difference with the Write mode, there are eight data bits followed
by a No Acknowledge bit). Similarly, the transitions on the SDA
line must occur during the low period of SCL and remain
stable during the high period of SCL as shown in Figure 11.
4. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined
as a low-to-high transition on the SDA line while SCL is high.
In the Write mode, the master will pull the SDA line high
during the tenth clock pulse to establish a STOP condition,
Figures 10a and 10b. In the Read mode, the master will issue
a No Acknowledge for the ninth clock pulse, i.e., the SDA
line remains high. The master will then bring the SDA line
low before the tenth clock pulse which goes high to establish a
STOP condition. See Figure 11.
A repeated Write function gives the user flexibility to update the
RDAC output a number of times, except after permanent programming, after addressing and instructing the part only once.
During the Write cycle, each data byte will update the RDAC
output. For example, after the RDAC has acknowledged its Slave
Address and Instruction bytes, the RDAC output will update after
these two bytes. If another byte is written to the RDAC while it is
still addressed to a specific slave device with the same instruction,
this byte will update the output of the selected slave device. If different instructions are needed, the Write mode has to be started
with a new Slave Address, Instruction, and Data bytes again.
Similarly, a repeated Read function of the RDAC is also allowed.
–14–
REV. 0
AD5273
I2C Controller Programming
Write Bit Pattern Illustrations
0
8
8
0
8
0
SCL
0
SDA
1
0
1
0
1
0
AD0 R/W
X
X
X
X
X
X
X
ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
X
X
D4
D5
D3
D2
D1
D0
ACK. BY
AD5273
ACK. BY
AD5273
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
STOP BY
MASTER
Figure 10a. Writing to the RDAC Register
0
8
8
0
8
0
SCL
SDA
0
1
0
1
0
1
AD0 R/W
1
X
X
X
X
X
X
X
ACK. BY
AD5273
START BY
MASTER
X
X
D4
D5
D3
D2
D1
ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE
D0
ACK. BY
AD5273
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
STOP BY
MASTER
Figure 10b. Activating One Time Programming
Read Bit Pattern Illustration
0
8
8
0
SCL
SDA
0
1
0
1
1
0
E1
AD0 R/W
E0
D5
D4
D3
D2
D1
D0
ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
NO ACK. BY
MASTER
FRAME 2
DATA BYTE FROM SELECTED
RDAC REGISTER
STOP BY
MASTER
Figure 11. Reading Data From the RDAC Register
5V
CONTROLLING TWO DEVICES ON ONE BUS
U3
Figure 12 shows two AD5273 devices on the same serial bus.
Each has a different slave address since the state of each AD0
pin is different. This allows each device to operate independently.
The master device output bus line drivers are open-drain pull
downs in a fully I2C compatible interface.
1
VIN
AD5273
VOUT
3
5V
A W
B
U2
VO
AD8601
GND
2
5V
Rp
U1
ADR03
Rp
Figure 13. Programmable Voltage Reference
SDA
MASTER
SCL
SDA SCL
AD0
AD5273
5V
SDA SCL
AD0
Programmable Voltage Source with Boosted Output
For applications that require high current adjustment such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered. See Figure 14.
U3 2N7002
AD5273
VOUT
VIN
U1
Figure 12. Two AD5273 Devices on One Bus
AD5273
A
APPLICATIONS
Programmable Voltage Reference
For Voltage Divider mode operation, as shown in Figure 13, it is
common to buffer the output of the digital potentiometer unless
the load is much larger than RWB. Not only does the buffer serve
the purpose of impedance conversion, it also allows a heavier
load to be driven.
REV. 0
B
+V
W
U2
CC
SIGNAL
RBIAS
IL
AD8601
LD
–V
Figure 14. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-Ch
–15–
AD5273
FET N1. N1 power handling must be adequate to dissipate
(VIN –VOUT) ⫻ IL power. This circuit can source a maximum of
100 mA with a 5 V supply. For precision applications, a voltage
reference such as ADR421, ADR03, or ADR370 can be applied
at the A terminal of the digital potentiometer.
the input is a step function. Similarly, it is also likely to ring when
switching between two gain values because this is equivalent to a
step change at the input. To reduce the effect of C1, users should
also configure B or A rather than W terminal at the inverting node.
Depending on the op amp GBP, reducing the feedback resistor may
extend the zero’s frequency far enough to overcome the problem.
A better approach is to include a compensation capacitor C2 to
cancel the effect caused by C1. Optimum compensation occurs
when R1 ⫻ C1 = R2 ⫻ C2. This is not an option because of the
variation of R2. As a result, one may use the relationship above
and scale C2 as if R2 is at its maximum value. Doing so may
overcompensate by slowing down the settling time when R2 is
set at low values. As a result, C2 should be found empirically for
a given application. In general, C2 in the range of a few pF to no
more than a few tenths of a pF is adequate for the compensation.
Programmable Current Source
A programmable current source can be implemented with the
circuit shown in Figure 15. The load current is simply the voltage
across terminals B-to-W of the AD5273 divided by RS. Notice
at zero-scale, the A terminal of the AD5273 will be at –2.048 V,
which makes the wiper voltage clamped at ground potential.
Dependent on the load, Equation 5 is therefore valid only at certain codes. For example, when the compliance voltage VL equals
half of the VREF, the current can be programmed from midscale
to full-scale of the AD5273.
There is also a W terminal capacitance connected to the output
(not shown); its effect on stability is less significant so that the
compensation may not be necessary unless the op amp is driving
a large capacitive load.
+5V
2
U1
VIN
VOUT
3
SLEEP
0 TO (2.048 + VL)
6
GND
B
U3
AD5273
REF191
C1
Programmable Low-Pass Filter
In A/D conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. To minimize various
system redesigns, users may use two 1 k⍀ AD5273s to construct a
generic second-order Sallen Key low-pass filter. Since the AD5273
is a single supply device, the input must be dc offset when an ac
signal is applied to avoid clipping at ground. This is illustrated in
Figure 17. The design equations are:
W
1F
A
4
RS
102
+5V
U2
V+
OP1177
VL
V–
–2.048 + VL
RL
IL
100
–5V
VO
=
VI
Figure 15. Programmable Current Source
IL =
(VREF ¥ D ) / 64
32 £ D £ 63
RS
Gain Control Compensation
As seen in Figure 16, the digital potentiometers are commonly
used in gain controls or sensor transimpedance amplifier signal
conditioning applications.
C2
4.7pF
B R2 A
R1
47k
(7)
1
1
Q =
+
R1C1 R2C2
(8)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, R1 and R2 can
be adjusted to the same setting to achieve the desirable bandwidth.
100k W
U1
C1
(6)
1
R1R2C1C2
wO =
(5)
2
wO
w
2
S 2 + O S + wO
Q
C1
VO
+2.5V
C
VI
VI
A
R1
R2
B
W
A
B
W C2
V+
C
AD8601
VO
V–
ADJUSTED TO
SAME SETTINGS
Figure 16. Typical Noninverting Gain Amplifier
In both applications, one of the digital potentiometer terminals is
connected to the op amp inverting node with finite terminal capacitance C1. It introduces a zero for the 1 ␤o term with 20 dB/dec
whereas a typical op amp GBP has –20 dB/dec characteristics. A
large R2 and finite C1 can cause this zero’s frequency to fall well
below the crossover frequency. Thus the rate of closure becomes
40 dB/dec and the system has 0° phase margin at the crossover
frequency. The output may ring or in the worst case oscillate when
U1
–2.5V
Figure 17. Sallen Key Low-Pass Filter
Level Shift for Different Voltages Operation
When users need to interface a 2.5 V controller with the AD5273,
a proper voltage level shift must be employed so that the digital
potentiometer can be read from or written to the controller;
Figure 18 shows one of the implementations. M1 and M2 should
be low threshold N-Ch Power MOSFETs such as FDV301N.
–16–
REV. 0
AD5273
Resolution Enhancement
VDD2 = 5V
VDD1 = 2.5V
Rp
Rp
Rp
Borrowed from ADI’s patented RDAC segmentation technique,
users can configure three AD5273s to double the resolution. (See
Figure 21.) First, U3 must be paralleled with a discrete resistor
RP that is chosen to be equal to a step resistance (RP = RAB/64). We
may see that adjusting U1 and U2 together forms the coarse 6-bit
adjustment and adjusting U3 alone forms the finer 6-bit adjustment. As a result, the effective resolution becomes 12-bit.
Rp
G
D
S
SDA1
SDA2
D
S
M1
SCL1
G
SCL2
M2
A1
2.7V–5.5V
2.5V
CONTROLLER
W1
AD5273
U1
A3
B1
Figure 18. Level Shift for Different Voltage Operation
RP
A2
Resistance Scaling
VW (D) =
U2
B2
COARSE
ADJUSTMENT
RDAC CIRCUIT SIMULATION MODEL
(9)
VDD
R3
A
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentiometers.
Configured as a potentiometer divider, the –3 dB bandwidth of
the AD5273 (1 k⍀ resistor) measures 6 MHz at half scale. TPCs
15–18 provide the large signal BODE plot characteristics of the
four available resistor versions 1 k⍀, 10 k⍀, 50 k⍀, and 100 k⍀.
Figure 22 shows a parasitic simulation model. The code following
Figure 22 provides a macro model net list for the 1 k⍀ device:
R1
R2
B
FINE
ADJUSTMENT
Figure 21. Double the Resolution in Rheostat Mode Operation
(RAB / /R2)
R 3 + RAB
B3
W2
The AD5273 offers 1 k⍀, 10 k⍀, 50 k⍀, and 100 k⍀ nominal
resistances. For users who need to optimize the resolution with
an arbitrary full-range resistance, the following techniques can
be the solutions. Applicable only to the voltage divider mode, by
paralleling a discrete resistor as shown in Figure 19, a proportionately lower voltage appears at terminal A–B. This translates
into a finer degree of precision because the step size at terminal
W will be smaller. The voltage can be found as:
D
¥
¥ VDD
/ /R2 256
W3
U3
A
W
1k
B
CW
CA
25pF
CB
25pF
55pF
W
Figure 19. Lowering the Nominal Resistance
Figure 22. Circuit Simulation Model for RDAC = 1 k⍀
Figure 19 shows that the digital potentiometer changes steps linearly. On the other hand, log taper adjustment is usually preferred in
applications like volume control. Figure 20 shows another way of
resistance scaling. In this circuit, the smaller the R2 with respect
to RAB, the more the pseudo log taper characteristic it behaves.
The wiper voltage is simply:
VW (D) =
RWB (D) / /R2
RWA (D) + RWB (D) / /R2
VO
R1
B
.PARAM D = 63, RDAC = 1E3
*
.SUBCKT DPOT (A,W,B)
*
¥ VI
VI
A
Macro Model Net List for RDAC
W
R2
(10)
CA
A
0
25E-12
RWA
A
W
{(1-D/63)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/63*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
Figure 20. Resistor Scaling with Log Adjustment
Characteristics
REV. 0
–17–
AD5273
EVALUATION BOARD
JP5
VCC
JP3
VDD
V+
VDD
C4
0.1F
ADR03
C6
0.1F
CP3
VREF
–IN1
C5
0.1F
CP1
2
3
4
+IN1
VDD
R1
10k
8
7
6
5
4
3
2
1
U3A CP6
B
VDD
U1
1
A
2 W
V
B
3 DD
GND AD0
4
SCL SDA
C2
0.1F
SCL
8
7
6
5
U2
1
A
2 W
B
3 VDD
GND AD0
4
SCL SDA
C3
0.1F
AD5170
8
7
6
5
OUT1
1
JP7
W VIN
R2
10k
CP4
8
JP8
A
C1
10F
C7
10F
CP2
JP1
J1
–IN1
U4
5
1
2 TEMP TRIM
3 GND
4
VIN
VOUT
CP7 OUT1
V–
CP5
JP2
JP4
AGND
C8
0.1F
AD5171/AD5273
SDA
C9
10F
JP6
–IN2
7
+IN2
VEE
6
OUT2
5
U3B
Figure 23. Evaluation Board Schematic
CP2
VDD
VREF
VREF
JP1
A
B
2
W
A
VO U2
B
JP7
W
JP2
3
JP3
4
U3A
V+ 1
V–
11
OUT1
AD822
JP4
Figure 24. One of the Possible Configurations:
Programmable Voltage Reference
Figure 25. Evaluation Board
–18–
REV. 0
AD5273
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE*
Part
Number
Number
of VRs per
Package
Terminal Interface
Voltage
Data
Range (V) Control
Nominal
Resistance
(k)
Resolution
Power Supply
(No. of Wiper Current
Packages
Positions)
(IDD) (A)
AD5201
1
±3, 5.5
3-wire
10, 50
33
40
MSOP-10
Full AC Specs, Dual
Supply, Power-On-Reset,
Low Cost
AD5220
1
5.5
UP/DOWN
10, 50, 100
128
40
PDIP, SOIC-8,
MSOP-8
No Rollover,
Power-On-Reset
AD7376
1
±15, 28
3-wire
10, 50, 100,
1000
128
100
PDIP-14,
SOIC-16,
TSSOP-14
Single 28 V or Dual
±15 V Supply Operation
AD5200
1
±3, 5.5
3-wire
10, 50
256
40
MSOP-10
Full AC Specs, Dual
Supply, Power-On-Reset
AD8400
1
5.5
3-wire
1, 10, 50, 100 256
5
SOIC-8
Full AC Specs
AD5260
1
±5, 15
3-wire
20, 50, 200
256
60
TSSOP-14
5 V to 15 V or ±5 V
Operation, TC < 50 ppm/°C
AD5280
1
±5, 15
2-wire
20, 50, 200
256
60
TSSOP-14
5 V to 15 V or ±5 V
Operation, TC < 50 ppm/°C
AD5241
1
±3, 5.5
2-wire
10, 100, 1000 256
50
SOIC-14,
TSSOP-14
I2C Compatible,
TC < 50 ppm/°C
AD5231
1
±2.75, 5.5
3-wire
10, 50, 100
1024
20
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD5222
2
±3, 5.5
UP/DOWN
10, 50, 100,
1000
128
80
SOIC-14,
TSSOP-14
No Rollover, Stereo,
Power-On-Reset,
TC < 50 ppm/°C
AD8402
2
5.5
3-wire
1, 10, 50, 100 256
5
PDIP, SOIC-14, Full AC Specs, nA
TSSOP-14
Shutdown Current
AD5207
2
±3, 5.5
3-wire
10, 50, 100
256
40
TSSOP-14
Full AC Specs, Dual
Supply, Power-On-Reset,
SDO
AD5232
2
±2.75, 5.5
3-wire
10, 50, 100
256
20
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD5235
2
±2.75, 5.5
3-wire
25, 250
1024
20
TSSOP-16
Nonvolatile Memory,
Direct Program,
TC < 50 ppm/°C
AD5242
2
±3, 5.5
2-wire
10, 100, 1000 256
50
SOIC-16,
TSSOP-16
I2C Compatible,
TC < 50 ppm/°C
AD5262
2
±5, 15
3-wire
20, 50, 200
256
60
TSSOP-16
5 V to 15 V or ±5 V
Operation, TC < 50 ppm/°C
AD5282
2
±5, 15
3-wire
20, 50, 200
256
60
TSSOP-16
5 V to 15 V or ±5 V
Operation, TC < 50 ppm/°C
AD5203
4
5.5
3-wire
10, 100
64
5
PDIP, SOIC-24, Full AC Specs, nA
TSSOP-24
Shutdown Current
AD5233
4
±2.75, 5.5
3-wire
10, 50, 100
64
20
TSSOP-24
AD5204
4
±3, 5.5
3-wire
10, 50, 100
256
60
PDIP, SOIC-24, Full AC Specs, Dual
TSSOP-24
Supply, Power-On-Reset
AD8403
4
5.5
3-wire
1, 10, 50, 100 256
5
PDIP, SOIC-24, Full AC Specs, nA
TSSOP-24
Shutdown Current
AD5206
6
±3, 5.5
3-wire
10, 50, 100
60
PDIP, SOIC-24, Full AC Specs, Dual
TSSOP-24
Supply, Power-On-Reset
256
*For the most current information on digital potentiometers, check the website at: www.analog.com/digitalpotentiometers
REV. 0
–19–
Comments
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD5273
OUTLINE DIMENSIONS
8-Lead Plastic Surface-Mount Package [SOT-23]
(RT-8)
C03224–0–11/02(0)
Dimensions shown in millimeters
2.90 BSC
8
7
6
5
1
2
3
4
2.80 BSC
1.60 BSC
PIN 1
0.65 BSC
1.30
1.15
0.90
1.95
BSC
1.45 MAX
0.38
0.22
SEATING
PLANE
10
0
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178BA
PRINTED IN U.S.A.
0.15 MAX
0.22
0.08
–20–
REV. 0