ETC XRT73L03IVS

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XRT73L03
ADVANCED CONFIDENTIAL
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
MAY 2000
REV. A1.0.7
GENERAL DESCRIPTION
APPLICATIONS
The XRT73L03, 3-Channel, E3/DS3/STS-1 Line Interface Unit consists of three independent line transmitters and receivers integrated on a single chip, designed for E3, DS3 or SONET STS-1 applications.
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
Each channel within the XRT73L03 device can be
configured to support the E3 (34.368 Mbps), DS3
(44.736 Mbps) or the SONET STS-1 (51.84 Mbps)
rates. Each channel can be configured to operate in
a mode/data rate that is independent of the other
channels.
• Multiplexers
• ATM Switches
FEATURES
• Meets E3/DS3/STS-1 Jitter Tolerance Requirements
In the transmit direction, each channel within the
XRT73L03 will encode input data to either B3ZS or
HDB3 format and convert the data into the appropriate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
• Contains a 4-Wire Microprocessor Serial Interface
• Full Loop-back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
In the receive direction, the XRT73L03 can perform
Equalization on incoming signals, perform Clock Recovery, decode data from either B3ZS or HDB3 format, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and declare the occurrence of Line code Violations.
• Single +3.3V Power Supply
• Uses Minimum External components
• -40°C to +85°C Operating Temperature Range
• Available in a 120 pin TQFP package
• 5V tolerant I/O
XRT73L03 BLOCK DIAGRAM
E3_Ch(n)
RTIP(n)
RRing(n)
STS-1/DS3_Ch(n)
AGC/
Equalizer
Host/(HW)
RLOL(n)
Clock
Recovery
Slicer
Peak
Detector
REQEN(n)
RxOFF(n)
EXClk(n)
Data
Recovery
LOS Detecto r
LOSTHR(n)
RxClkINV
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
SClk
CS
LCV(n)
ENDECDIS
SDI
SDO
RNEG(n)
RLOS(n)
Serial
Processor
Interface
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TRing(n)
MTIP(n)
MRing(n)
TxClk(n)
TxLEV(n)
Device
Monitor
DMO(n)
TxOFF(n)
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in
"Harware" Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT73L03
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
TRANSMIT INTERFACE CHARACTERISTICS
RECEIVE INTERFACE CHARACTERISTICS
• Accepts either Single Rail or Dual Rail data from
Terminal Equipment, and generates a bipolar signal
from the line.
• Integrated Adaptive Receive Equalization
(Optional) and Timing Recovery.
• Integrated Pulse Shaping Circuit.
• Declares and Clears the LOS defect per ITU-T
G.775 requirements (E3 and DS3 applications).
• Built-in B3ZS/HDB3 Encoder (which can be disabled)
• Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 (for E3 Applications).
• Contains "Transmit Clock Duty Cycle Correction"
Circuit on-chip.
• Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE (for DS3 Applications).
• Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
• Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
• Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993.
• Built-in B3ZS/HDB3 Decoder (which can be disabled)
• Recovered Data can be muted while the LOS Condition is declared.
• Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253CORE.
• Outputs either Single Rail or Dual Rail data to the
Terminal Equipment.
• Transmitter can be turned off in order to support
"redundancy designs".
• Receiver can be powered down in order to conserve power in "redundancy designs
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REGR/(RxClkINV)
STS1/DS3_Ch2
AGND3
SR/(DR)
E3_CH2
NC
NC
LOSTHR2
LLB2
RLB2
RxAVDD2
RRing2
RTIP2
RxAGND2
REQEN2
RxAGND3
RTIP3
RRing3
RxAVDD3
RLB3
LLB3
LOSTHR3
REQEN1
RxAGND1
RTIP1
RRing1
RxAVDD1
RLB1
LLB1
LOSTHR1
ICT
STS1/DS3_Ch1
SDO/(E3_Ch1)
SDI/(RxOFF1)
SClk/(RxOFF2)
CS/(ENDECDIS)
PIN OUT OF THE XRT73L03 IN THE 14 X 20MM, 0.5MM PITCH TQFP
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120
XRT73L03
TNData2
TPData2
TxClk2
MRing2
MTIP2
TAOS2
TAOS3
TxLev2
TxLev3
TTIP2
TxAVDD2
TRing2
TxAGND2
TxAGND3
MRing3
MTIP3
TxAGND3
TRing3
TxAVDD3
TTIP3
DMO3
TxAVDD3
TNData3
TPData3
TxClk3
TxAGND1
TRing1
TxAVDD1
TTIP1
MTIP1
MRing1
TNData1
TPData1
TxClk1
TxLEV1
TAOS1
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3
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25
26
27
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30
31
32
33
34
35
36
EXDGND
EXDVDD
EXClk2
REQEN3
STS1/DS3_Ch3
E3_CH3
EXClk3
RxOFF3
RLOL2
LCV2
RLOS2
RxDGND2
RPOS2
RNEG2
RxClk2
LOSMUTEN
RxDVDD2
AGND2
TxOFF3
TxOFF2
TxOFF1
TxAGND2
TxAVDD2
DMO2
2
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RLOL3
LCV3
RLOS3
RLOL1
LCV1
RLOS1
RxDGND1
RPOS1
RNEG1
RxClk1
RxDVDD1
EXClk1
NC
NC
RxDGND3
RPOS3
RNEG3
RxClk3
HOST/(HW)
RxDVDD3
AGND1
TxAGND1
DMO1
TxAVDD1
áç
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
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AGND3
SR/(DR)
E3_CH2
NC
NC
LOSTHR2
LLB2
RLB2
RxAVDD2
RRing2
RTIP2
RxAGND2
REQEN2
RxAGND3
RTIP3
RRing3
RxAVDD3
RLB3
LLB3
LOSTHR3
REQEN1
RxAGND1
RTIP1
RRing1
RxAVDD1
RLB1
LLB1
LOSTHR1
ICT
STS1/DS3_Ch1
FIGURE 1. PIN OUT OF THE XRT72L03 IN THE 14 X14 MM, 0.4MM PITCH TQFP
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120
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36
35
34
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32
31
XRT73L03
SDO/(E3_Ch1)
SDI/(RxOFF1)
SClk/(RxOFF2)
CS/(ENDECDIS)
RLOL3
LCV3
RLOS3
RLOL1
LCV1
RLOS1
RxDGND1
RPOS1
RNEG1
RxClk1
RxDVDD1
EXClk1
NC
NC
RxDGND3
RPOS3
RNEG3
RxClk3
HOST/(HW)
RxDVDD3
AGND1
TxAGND1
DMO1
TxAVDD1
TAOS1
TxLEV1
MTIP2
TAOS2
TAOS3
TxLEV2
TxLEV3
TTIP2
TxDVDD2
TRing2
TxDGND2
TxAGND3
MRing3
MTIP3
TxDGND3
TRing3
TxDVDD3
TTIP3
DMO3
TxAVDD3
TNData3
TPData3
TxClk3
TxDGND1
TRing1
TxDVDD1
TTIP1
MTIP1
MRing1
TNData1
TPData1
TxClk1
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2
3
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5
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22
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25
26
27
28
29
30
STS1/DS3_Ch2
REGR/(RxClkINV)
EXDGND
EXDVDD
EXClk2
REQEN3
STS1/DS3_Ch3
E3_CH3
EXClk3
RxOFF3
RLOL2
LCV2
RLOS2
RxDGND2
RPOS2
RNEG2
RxClk2
LOSMUTEN
RxDVDD2
AGND2
TxOFF3
TxOFF2
TxOFF1
TxAGND2
TxAVDD2
DMO2
TNData2
TPData2
TxClk2
MRing2
ORDERING INFORMATION
PART #
PACKAGE
OPERATING TEMPERATURE RANGE
XRT73L03IV
120 Pin TQFP 14mm X 20mm
-40oC to +85oC
XRT73L03IVS
120 Pin TQFP 14mm X 14mm
-40oC to +85oC
3
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XRT73L03
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
áç
ADVANCED CONFIDENTIAL
REV. A1.0.7
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS .........................................................................................................................................
FEATURES ....................................................................................................................................................
XRT73L03 BLOCK DIAGRAM ........................................................................................................................
TRANSMIT INTERFACE CHARACTERISTICS ......................................................................................................
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................
PIN OUT OF THE XRT73L03 IN THE 14 X 20MM, 0.5MM PITCH TQFP ...............................................................
1
1
1
2
2
2
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS .......................................................................................................... 3
PIN DESCRIPTION ........................................................................................................... 3
ELECTRICAL CHARACTERISTICS ................................................................................ 16
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 21
SYSTEM DESCRIPTION .................................................................................................. 24
THE TRANSMIT SECTION (CHANNELS 1, 2 AND 3 ..........................................................................................
THE RECEIVE SECTION (CHANNELS 1, 2 AND 3) ..........................................................................................
THE MICROPROCESSOR SERIAL INTERFACE .................................................................................................
THE HARDWARE MODE ...............................................................................................................................
THE HOST MODE ........................................................................................................................................
1.0 Selecting the Data Rate ....................................................................................................................
24
24
24
24
24
25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................................... 25
2.0 The Transmit Section ....................................................................................................................... 27
COMMAND REGISTER, CR4-(N) ...................................................................................................... 27
2.1 THE TRANSMIT LOGIC BLOCK ............................................................................................................................ 27
COMMAND REGISTER CR1-(N) ....................................................................................................... 29
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................................... 29
2.3 THE HDB3/B3ZS ENCODER BLOCK .................................................................................................................. 29
COMMAND REGISTER, CR2-(N) ...................................................................................................... 31
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY ....................................................................................................... 31
COMMAND REGISTER, CR1-(N) ...................................................................................................... 32
COMMAND REGISTER, CR1-(N) ...................................................................................................... 33
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L03 DEVICE TO THE LINE ............................................... 33
TRANSFORMER VENDOR INFORMATION ........................................................................................... 34
3.0 The Receive Section ......................................................................................................................... 34
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L03 DEVICE TO THE LINE ................................................. 35
TRANSFORMER VENDOR INFORMATION ........................................................................................... 35
3.2 THE RECEIVE EQUALIZER BLOCK ...................................................................................................................... 36
COMMAND REGISTER CR-2 (N) ...................................................................................................... 38
3.3 CLOCK RECOVERY PLL .................................................................................................................................... 38
3.4 THE HDB3/B3ZS DECODER ............................................................................................................................. 38
COMMAND REGISTER CR2-(N) ....................................................................................................... 40
3.5 LOS DECLARATION/CLEARANCE ....................................................................................................................... 40
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
REGISTER CR0-(N)
REGISTER CR2-(N)
REGISTER CR0-(N)
REGISTER CR2-(N)
REGISTER CR3-(N)
.......................................................................................................
.......................................................................................................
.......................................................................................................
.......................................................................................................
.......................................................................................................
43
43
43
44
44
3.6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE "RECEIVING TERMINAL EQUIPMENT" ............ 44
COMMAND REGISTER CR3-(N) ....................................................................................................... 46
COMMAND REGISTER CR3-(N) ....................................................................................................... 46
3.7 SHUTTING OFF THE RECEIVE SECTION ............................................................................................................. 47
COMMAND REGISTER CR3-(N) ....................................................................................................... 48
4.0 Diagnostic Features of the XRT73L03 Device ............................................................................... 49
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
4.1 THE ANALOG LOCAL LOOP-BACK MODE ............................................................................................................ 49
COMMAND REGISTER CR4-(N) ...................................................................................................... 50
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ............................................................................................................ 50
4.3 THE REMOTE LOOP-BACK MODE ....................................................................................................................... 51
COMMAND REGISTER CR4-(N) ...................................................................................................... 51
4.4 TXOFF FEATURES ........................................................................................................................................... 52
COMMAND REGISTER CR4-(n) ...................................................................................................... 52
COMMAND REGISTER CR1-(N) ...................................................................................................... 52
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ....................................................................................................... 52
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .................................................................................................... 53
COMMAND REGISTER CR1-(N) ...................................................................................................... 53
5.0 The Microprocessor Serial Interface .............................................................................................. 54
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................................... 54
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
REGISTER CR0-(N) .......................................................................................................
REGISTER CR1-(N) ......................................................................................................
REGISTER CR2-(N) ......................................................................................................
REGISTER CR3-(N) ......................................................................................................
REGISTER CR4-(N) ......................................................................................................
56
56
57
58
59
5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................................... 59
ORDERING INFORMATION ............................................................................................. 62
62
63
REVISION HISTORY ..................................................................................................................................... 64
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XRT73L03
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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ADVANCED CONFIDENTIAL
REV. A1.0.7
LIST OF FIGURES
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
PIN OUT OF THE XRT72L03 IN THE 14 X14 MM, 0.4MM PITCH TQFP .................................................... 3
TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL) .. 21
TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE ..................................................... 22
TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE .................................................... 22
MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE ................................................................ 23
TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE .................................................... 23
FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L03 DEVICE .............................................................. 25
ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL RAIL FORMAT,
FROM THE "TRANSMITTING" TERMINAL EQUIPMENT TO THE "TRANSMIT SECTION" OF A CHANNEL WITHIN THE
XRT73L03 DEVICE .......................................................................................................................................... 28
FIGURE 9. ILLUSTRATION ON HOW THE XRT73L03 DEVICE SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT
PINS ................................................................................................................................................................. 28
FIGURE 10. ILLUSTRATION OF THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT
LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT ........................................... 29
FIGURE 11. AN EXAMPLE OF B3ZS ENCODING ................................................................................................. 30
FIGURE 12. AN EXAMPLE OF HDB3 ENCODING ................................................................................................ 30
FIGURE 13. THE "BELLCORE GR-499-CORE" TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS . 31
FIGURE 14. THE "BELLCORE GR-253-CORE" TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ............................................................................................................................................................... 32
FIGURE 15. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73L03 DEVICE TO
THE LINE .......................................................................................................................................................... 34
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L03 DEVICE TO
THE LINE (TRANSFORMER-COUPLING) ............................................................................................................... 35
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L03 DEVICE TO
THE LINE (CAPACITIVE-COUPLING) .................................................................................................................... 36
FIGURE 18. ILLUSTRATION OF THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER .................................... 37
FIGURE 19. AN EXAMPLE OF B3ZS DECODING ................................................................................................ 39
FIGURE 20. AN EXAMPLE OF HDB3 DECODING ................................................................................................ 39
FIGURE 21. ILLUSTRATION OF THE SIGNAL LEVELS THAT THE XRT73L03 DEVICE WILL DECLARE AND CLEAR LOS .
41
FIGURE 22. THE BEHAVIOR THE LOS OUTPUT INDICATOR, IN RESPONSE TO THE LOSS OF SIGNAL, AND THE RESTORATION OF SIGNAL ............................................................................................................................................ 42
FIGURE 23. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT,
FROM THE "RECEIVE SECTION" OF THE XRT73L03 DEVICE" TO THE RECEIVING TERMINAL EQUIPMENT ............. 45
FIGURE 24. ILLUSTRATION ON HOW THE XRT73L03 DEVICE OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
45
FIGURE 25. ILLUSTRATION OF THE BEHAVIOR OF THE RPOS, RNEG, AND RXCLK SIGNALS, WHEN RXCLK IS INVERTED .................................................................................................................................................................... 46
FIGURE 26. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A "SINGLE-RAIL FORMAT", FROM THE "RECEIVE SECTION OF THE XRT73L03 DEVICE" TO THE RECEIVING TERMINAL EQUIPMENT ..... 47
FIGURE 27. ILLUSTRATION OF THE BEHAVIOR OF THE RPOS AND RXCLK OUTPUT SIGNALS, WHILE THE XRT73L03
DEVICE IS TRANSMITTING "SINGLE-RAIL" DATA TO THE RECEIVING TERMINAL EQUIPMENT .................................. 47
FIGURE 28. ILLUSTRATION OF A CHANNEL (WITHIN THE XRT73L03 DEVICE) OPERATING IN THE ANALOG LOCAL
LOOP-BACK MODE ............................................................................................................................................ 49
FIGURE 29. ILLUSTRATION OF THE "DIGITAL LOCAL LOOP-BACK" PATH WITHIN A GIVEN CHANNEL (OF THE XRT73L03
DEVICE) ............................................................................................................................................................ 50
FIGURE 30. ILLUSTRATION OF THE "REMOTE LOOP-BACK" PATH, WITHIN A GIVEN CHANNEL (OF THE XRT73L03 DEVICE) ................................................................................................................................................................ 51
FIGURE 31. ILLUSTRATION OF THE XRT73L03 DEVICE EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES . 53
FIGURE 32. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE .............................................................. 60
FIGURE 33. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE .................................................. 61
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III
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
LIST OF TABLES
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L03 DEVICE IS OPERATING IN THE
"HARDWARE" MODE ........................................................................................................................................ 24
TABLE 2: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS ............................................. 26
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(N), (WITHIN THE XRT73L03 DEVICE), VIA THE "E3_CH(N)"
AND "STS-1/DS3_CH(N)" INPUT PINS (HARDWARE MODE) ............................................................................... 27
TABLE 4: SELECTING THE DATA RATE FOR CHANNEL“(N)” (WITHIN THE XRT73L03 DEVICE); VIA THE "STS-1/
DS3_CH(N)" AND THE "E3_CH(N)" BIT-FIELDS, WITHIN THE APPROPRIATE COMMAND REGISTER (HOST MODE) 27
TABLE 5: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................................ 42
TABLE 6: THE RELATIONSHIP BETWEEN THE “TXOFF” INPUT PIN, THE “TXOFF” BIT FIELD AND THE STATE OF THE
TRANSMITTER ................................................................................................................................................... 52
TABLE 7: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS ............................................. 55
TABLE 8: CONTENTS OF "LLB(N)" AND "RLB(N)" AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL(N)
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IV
XRT73L03
áç
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTIONS
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
1
117
TNData2
I
DESCRIPTION
Transmit Negative Data Input - Channel 2:
Refer to the description of pin 32 or 28, TnData1
2
118
TPData2
I
Transmit Positive Data Input - Channel 2:
Refer to the description of pin 33 or 29, TPData1
3
119
TxClk2
I
Transmit Clock Input for TPData and TNData - Channel 2:
Refer to the description of pin 34 or 31, TxClk1
4
120
MRing2
I
Monitor Ring Input - Channel 2:
Refer to the description of pin 31 or 27, MRing1
5
1
MTIP2
I
Monitor Tip Input - Channel 2:
Refer to the description of pin 30 or 26, MTIP1
6
2
Transmit All Ones Select - Channel 2:
TAOS2
Refer to description of pin 36 or 32, TAOS1
7
3
Transmit All Ones Select - Channel 3:
TAOS3
Refer to description of 36 or 32, TAOS1
8
4
TxLEV2
I
Transmit Line Build-Out Enable/Disable Select - Channel 2:
NOTE: Refer to the description of 35 or 31, TxLEV1
9
5
TxLEV3
I
Transmit Line Build-Out Enable/Disable Select - Channel 3:
Refer to the description of 35 or 31, TxLEV1
10
6
TTIP2
O
Transmit TTIP Output - Channel 2:
Refer to the description of pin 29 or 25, TTIP1
11
7
TxAVDD2
****
12
8
TRing2
O
Transmitter Analog 3.3V+ 5% VDD - Transmitter 2
Transmit Ring Output - Channel 2:
Refer to the description of pin 27 or 23, TRing1
13
9
TxAGND2
****
Transmitter Analog GND - Transmitter 2
14
10
TxAGND3
****
Transmitter Analog GND - Channel 3
15
11
MRing3
I
Monitor Ring Input - Channel 3:
Refer to the description of pin 31 or 27, MRing1
16
12
MTIP3
I
Monitor Tip Input - Channel 3:
Refer to the description of pin 30 or 26, MTIP1
17
13
TxAGND3
****
18
14
TRing3
O
Transmitter Analog GND - Transmitter 3
Transmit Ring Output - Channel 3:
Refer to the description of pin 27 or 23, TRing1
19
15
TxAVDD3
****
Transmitter Analog 3.3V+ 5% VDD - Transmitter 3
3
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
20
16
TTIP3
O
DESCRIPTION
Transmit TTIP Output - Channel 3:
Refer to the description of pin 29 or 25, TTIP1
21
17
DMO3
O
Drive Monitor Output - Channel 3:
Refer to the description of pin 38 or 34, DMO1
22
18
TxAVDD3
****
23
19
TNData3
I
Transmitter Analog 3.3V+ 5% VDD - Transmitter 3
Transmit Negative Data Input - Channel 3:
Refer to the description of pin 32 or 28, TnData1
24
20
TPData3
I
Transmit Positive Data Input - Channel 3:
Refer to the description of pin 33 or 29, TPData1
25
21
TxClk3
I
Transmit Clock Input for TPData and TNData - Channel 3:
Refer to the description of pin 34 or 31, TxClk1
26
22
TxAGND1
****
27
23
TRing1
O
Transmitter Analog GND - Transmitter 1:
Transmit Ring Output - Channel 1:
The XRT73L03 device will use this pin, along with TTIP1, to
transmit a bipolar line signal, via a 1:1 transformer.
28
24
TxAVDD1
****
29
25
TTIP1
O
Transmitter Analog 3.3V+ 5% VDD - Transmitter 1:
Transmit TTIP Output - Channel 1:
The XRT73L03 device will use this pin, along with TRing1, to
transmit a bipolar line signal, via a 1:1 transformer.
30
26
MTIP1
I
Monitor Tip Input - Channel 1:
The bipolar line output signal, from TTIP1 can be connected to
this pin, via a 270-ohm resistor, in order to check for line driver
failure. This pin is internally pulled "high".
31
27
MRing1
I
Monitor Ring Input - Channel 1:
The bipolar line output signal, from TRing1 can be connected to
this pin, via a 270-ohm resistor, in order to check for line driver
failure. This pin is internally pulled "high".
32
28
TNData1
I
Transmit Negative Data Input - Channel 1:
The XRT73L03 device will sample this pin, on the falling edge of
TxClk1. If the device samples a "1" at this input pin, then it will
generate and transmit a "negative" polarity pulse to the line.
NOTES:
1. This input pin will be ignored and should be tied to GND,
if the Transmit Section is configured to accept "SingleRail" data from the Terminal Equipment.
2. If the XRT73L03 device is operating in the "Host" Mode,
then the user can (if desired) to configure the XRT73L03
to sample the TNData1 pin on either the rising or falling
edge of TxClk1.
4
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
33
29
TPData1
I
DESCRIPTION
Transmit Positive Data Input - Channel 1:
The XRT73L03 device will sample this pin, on the falling edge of
TxClk. If the device samples a "1" at this input pin, then it will
generate and transmit a "positive" polarity pulse to the line.
NOTES:
1. The data should be applied to this input pin if the "Transmit Section" is configured to accept Single-Rail data
from the Terminal Equipment.
2. If the XRT73L03 device is operating in the "Host" Mode,
then the user can (if desired) to configure the XRT73L03
to sample the TPData1 pin on either the rising or falling
edge of TxClk1.
34
30
TxClk1
I
Transmit Clock Input for TPData and TNData - Channel 1:
This input pin must be driven at 34.368 MHz (for E3 applications), 44.736 MHz (for DS3 applications), or 51.84 MHz (for
SONET STS-1 applications). The XRT73L03 device will use this
signal to sample the TPData1 and TNData1 input pins. By
default, the XRT73L03 will be configured to sample these two
pins on the falling edge of this signal.
If the XRT73L03 device is operating in the "Host" Mode, then the
device can be configured to sample the TPData1 and TNData1
input pins on either the rising or falling edge of TxClk1.
5
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
DESCRIPTION
35
31
TxLEV1
I
Transmit Line Build-Out Enable/Disable Select - Channel 1:
This input pin permits the user to enable or disable the Transmit
Line Build-Out circuit, within Channel 1 of the XRT73L03 device.
Setting this pin to "HIGH" disables the Line Build-Out circuit
within Channel 1. In this mode, Channel 1 will output unshaped
(e.g., square-wave) pulses onto the line via the TTIP1 and
TRing1 output pins.
Setting this pin to "LOW" enables the Line Build-Out circuit within
Channel 1. In this mode, Channel 1 will output shaped pulses
onto the line via the TTIP1 and TRing1 output pins.
In order to comply with the "Isolated DSX-3/STSX-1 Pulse Template Requirements (per Bellcore GR-499-CORE or Bellcore
GR-253-CORE), the user should:
1. Set this input pin to "1", if the cable length (between the
Cross-Connect and the transmit output of Channel 1) is greater
than 225 feet.
2. Set this input pin to "0", if the cable length (between the
Cross-Connect and the transmit output of Channel 1) is less than
225 feet.
This pin is active only if the following two conditions are true:
a. The XRT73L03 is configured to operate in either the DS3 or
SONET STS-1 Modes.
b. The XRT73L03 is configured to operate in the "Hardware"
Mode.
NOTE: The user should tie this pin to GND if the XRT73L03
device is going to be operating in the "Host" Mode
36
32
TAOS1
I
Transmit All Ones Select - Channel 1:
A "high" on this pin causes the Transmit Section, within Channel
1 to generate and transmit a continuous AMI "All 1s" pattern onto
the line. The frequency of this "1s" pattern is determined by
TxClk1.
NOTES:
1. This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode.
2. The user should tie this pin to GND, if the XRT73L03 is
going to be operating in the "Host" Mode.
37
33
TxAVDD1
****
38
34
DMO1
O
Transmitter Analog 3.3V+ 5% VDD - Transmitter 1
Drive Monitor Output - Channel 1:
If no transmitted AMI signal is present on MTIP1 and MRing1
input pins for 128±32 TxClk periods, then DMO1 will toggle and
remain "high" until the next AMI signal is detected.
39
35
TxAGND1
****
Transmitter Analog GND - Transmitter 1
40
36
AGND1
****
Analog GND (Substrate Connection) - Channel 1:
41
37
RxDVDD3
****
Receive Digital 3.3V+ 5% VDD (for Receiver 3):
6
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XRT73L03
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
42
38
Host/(HW)
I
DESCRIPTION
Host_Hardware Mode Select:
This input pin permits the user to enable or disable the Microprocessor Serial Interface (e.g., consisting of the SDI, SDO, SClk,
and CSB pins).
Setting this input pin "high" enables the Microprocessor Serial
Interface (or configures the XRT73L03 device to operate in the
"Host" Mode). In this mode, the user is expected to configure
the XRT73L03 device via the Microprocessor Serial Interface.
As a consequence, when the XRT73L03 is operating in the
"Host" Mode, then it will ignore the states of many of the discrete
input pins. Setting this input pin "low" disables the Microprocessor Serial Interface (e.g., configures the XRT73L03 device to
operate in the "Hardware" Mode). In this mode, many of the
external input control pins will be functional.
43
39
RxClk3
O
Receive Clock Output pin - Channel 3:
This output pin is the Recovered Clock signal from the incoming
line signal for Channel 3. The receive section of Channel 3 will
output data via the RPOS3 and RNEG3 output pins, on the rising
edge of this clock signal.
NOTE: The user can configure the Receive Section of Channel 3
to update the data on the RPOS3 and RNEG3 output pins on the
falling edge of RxClk3 by doing one of the following:
1. If the XRT73L03 is operating in the Hardware Mode
Pulling the "RxClkINV" pin (pin 62) to "high".
2. If the XRT73L03 is operating in the Host Mode
Writing a "1" into the "RxClkINV" bit-field within the Command
Register.
44
40
RNEG3
O
Receive Negative Data Output - Channel 3:
This output pin will pulse "high" whenever Channel 3, within the
XRT73L03 device has received a "Negative Polarity" pulse, in
the incoming line signal, at the RTIP3/RRing3 inputs.
NOTE: If the B3ZS/HDB3 Decoder (within Channel 3) is
"enabled" then the "zero suppression" patterns, in the incoming
line signal (such as: "00V", "000V", "B0V", "B00V") will not be
reflected at this output.
45
41
RPOS3
O
Receive Positive Data Output - Channel 3:
This output pin will pulse "high" whenever Channel 3, within the
XRT73L03 device has received a "Positive Polarity" pulse, in the
incoming line signal, at the RTIP3/RRing3 inputs.
NOTE: If the B3ZS/HDB3 Decoder (within Channel 3) is
"enabled" then the "zero suppression" patterns, in the incoming
line signal (such as: "00V", "000V", "B0V", "B00V") will not be
reflected at this output.
****
Receive Digital GND - Channel 3:
46
42
RxDGND3
47
43
NC
No Connection
48
44
NC
No Connection
7
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
49
45
EXClk1
I
DESCRIPTION
External Reference Clock Input - Channel 1:
The user is expected to apply a 34.368 MHz clock signal (for E3
applications), a 44.736 MHz clock signal (for DS3 applications),
or a 51.84 MHz clock signal (for SONET STS-1 applications).
The Clock Recovery PLL (within Channel 1) will use this signal
as a "Reference Signal" for Declaring and Clearing the "Receive
Loss of Lock" Alarm.
NOTES:
1. It is permissible to use the same clock, which is also
driving the "TxClk" input pin.
2. It is permissible to operate the three Channels at different data rates.
50
46
RxDVDD1
****
51
47
RxClk1
O
Receive Digital 3.3V+ 5% VDD (for Receiver 1):
Receive Clock Output - Channel 1:
See description of pin 43 or 39, RxClk3
52
48
RNEG1
O
Receive Negative Data Output - Channel 1:
Refer to the description of pin 44 or 40, RNEG3
53
49
RPOS1
O
Receive Positive Data Output - Channel 1:
Refer to the description of pin 45 or 41, RPOS3
54
50
RxDGND1
****
55
51
RLOS1
O
Receive Digital GND - Channel 1:
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "high" if Channel 1, within the XRT73L03
has detected a "Loss of Signal" Condition in the incoming line
signal.
The exact criteria that the XRT73L03 device uses to declare an
"LOS Condition" depends upon whether the device is operating
in the E3 or STS-1/DS3 Mode.
56
52
LCV1
O
Line Code Violation Indicator - Channel 1:
Whenever the Receive Section of Channel 1 detects a Line
Code Violation, then it will pulse this output pin "high". This output pin will remain "low" at all other times.
NOTE: The XRT73L03 device will output an NRZ pulse via this
output pin. Hence, the user is advised to sample this output pin
via the RxClk1 clock output signal.
57
53
RLOL1
O
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "high" if Channel 1, within the XRT73L03
device has detected a "Loss of Lock" Condition. Channel 1 will
declare an LOL (Loss of Lock) Condition if the recovered clock
frequency deviates from the Reference Clock frequency (available at the EXClk(n) input pin) by more than 0.5%.
58
54
RLOS3
O
Receive Loss of Signal Output Indicator - Channel 3:
Refer to the description of pin 55 or 51, RLOS1
59
55
LCV3
O
Line Code Violation Indicator - Channel 3:
Refer to the description of pin 56 or52, LCV1
8
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XRT73L03
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
60
56
RLOL3
O
DESCRIPTION
Receive Loss of Lock Output Indicator - Channel 3:
Refer to the description of pin 57 or53, RLOL1
61
57
CS/(ENDECDIS)
I
Microprocessor Serial Interface - Chip Select Input/EncoderDecoder Disable Input:
The exact functionality of this pin depends upon whether the
XRT73L03 device is operating in the Host or Hardware Mode.
Host Mode Operation - Chip Select Input (for the Microprocessor Serial Interface):
The Local Microprocessor must assert this pin (e.g., set it to "0")
in order to enable communication with the XRT73L03, via the
Microprocessor Serial Interface.
NOTE: This pin is internally pulled "high".
Hardware Mode - B3ZS/HDB3 Encoder & Decoder Disable:
Setting this input pin "high" disables the "B3ZS/HDB3 Encoder &
Decoder" blocks (within the XRT73L03 device) and configures
the XRT73L03 device to transmit and receive the line signal in an
AMI format. Conversely, setting this input pin "low" enables the
"B3ZS/HDB3 Encoder & Decoder" blocks and configures the
XRT73L03 device to transmit and receive the line signal in the
B3ZS format, (for STS-1/DS3 operation) or in the HDB3 format,
(for E3 operation).
NOTE: If the XRT73L03 device is operating in the "Hardware"
Mode, then this pin setting configures the "B3ZS/HDB3" Encoder
and Decoder Blocks for all Channels.
62
58
SClk/
(RxOFF2)
I
Microprocessor Serial Interface Clock Signal/"Channel 2
Receiver Shut OFF" Input:
The exact role of this particular pin depends upon whether the
XRT73L03 device is operating in the "Host" Mode or in the
"Hardware" Mode.
Host Mode - Microprocessor Serial Interface Clock Signal:
This signal will be used to sample the data, on the SDI pin, on
the rising edge of this signal. Additionally, during "Read" operations, the Microprocessor Serial Interface will update the SDO
output on the falling edge of this signal.
Hardware Mode - Channel 2 Receiver Shut OFF input pin:
Setting this input pin "high" shuts off the Channel 2 receiver.
Conversely, setting this input pin "low" enables the Receive Section for full operation.
9
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
63
59
SIGNAL NAME
TYPE
SDI/
(RxOFF1)
I
DESCRIPTION
Serial Data Input for the Microprocessor Serial Interface/
Channel 1 - Receiver Shut OFF Input pin:
The exact function of this input depends upon whether the
XRT73L03 device is operating in the "Host" Mode or in the
"Hardware" Mode.
Host Mode - Serial Data Input for the Microprocessor Serial
Interface:
Whenever the user wishes to read or write data into the Command Registers, over the Microprocessor Serial Interface; the
user is expected to apply the "Read/Write" bit, the Address Values (of the Command Registers) and Data Value to be written
(during "Write" Operations) to this pin.
This input will be sampled on the rising edge of the SClk pin (pin
18).
Hardware Mode - Channel 1 Receiver Shut OFF Input pin:
Setting this input pin "high" shuts off the Channel 1 receiver.
Conversely, setting this input pin "low" enables the Receive Section for full operation.
64
60
SDO/
(E3_Ch1)
I/O
Serial Data Output from the Microprocessor Serial Interface/
E3_Mode Select - Channel 1:
The exact functionality of this pin depends upon whether the
XRT73L03 device is operating in the "Host" Mode or in the
"Hardware" Mode.
Host Mode Operation - Serial Data Output for the Microprocessor Serial Interface:
This pin will serially output the contents of the specified Command Register, during "Read" Operations. The data, on this pin,
will be updated on the falling edge of the SClk input signal. This
pin will be tri-stated upon completion of data transfer.
Hardware Mode Operation - E3 Mode Select - Channel 1:
This input pin permits the user to configure Channel 1 (within the
XRT73L03 device) to operate in the E3 or STS/DS3 Modes. Setting this input pin to "HIGH" configures Channel 1 to operate in
the "E3" Mode. Setting this input pin to "LOW" configures Channel 1 to operate in either the DS3 or STS-1 Modes (depending
upon the state of the "STS-1/DS3_Ch1 input pin (pin 31).
NOTE: This pin is internally pulled “low” when XRT73L03 is in
the Harware Mode.
65
61
STS1/
DS3_Ch1
I
STS-1/DS3 Select Input - Channel 1:
High for STS-1 and low for Ds3 Operation.
3. The XRT73L03 will ignore this pin if the "E3_Ch1" pin
(pin 28) is set to "1".
4. This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode.
5. The user should tie this pin to GND, if the XRT73L03 is
going to be operating in the "Host" Mode.
10
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
66
62
ICT
I
DESCRIPTION
In-Circuit Test Input:
Setting this pin "low" causes all digital and analog outputs to go
into a high-impedance state to allow for in-circuit testing. Hence,
the user should set this pin "high" for normal operation.
NOTE: This pin is internally pulled "high".
67
63
LOSTHR1
I
Loss of Signal Threshold Control - Channel 1 :
The voltage forced on this pin controls the input loss of signal
threshold for Channel 1. Forcing the LOSTHR1 pin to GND or
VDD provides two settings. This pin must be set to the desired
level upon power up and should not be changed during operation.
NOTE: This pin is only applicable during DS3 or STS-1 operations.
68
64
LLB1
I
Local Loop-back - Channel 1:
This input pin, along with "RLB1" dictates which loop-back mode
Channel 1 (within the XRT73L03 device) will be operating in.
A "high" on this pin (with "RLB1" being set to "low") configures
Channel 1, within the XRT73L03 device to operate in the "Analog Local Loop-back" Mode.
A "high" on this pin (with "RLB1" also being set to "high") configures Channel 1, within the XRT73L03 device to operate in the
"Digital Local Loop-back" Mode.
NOTE: This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode, and the user should connect this pin to GND.
69
65
RLB1
I
Remote Loop-back - Channel 1:
This input pin, along with "LLB1" dictates which loop-back mode
"Channel 1 (within the XRT73L03 device) will be operating in.
A "high" on this pin (with "LLB1" being set to "low") configures
Channel 1, within the XRT73L03 device to operate in the
Remote Loop-back Mode.
A "high" on this pin (with "LLB1" also being set to "high") configures Channel 1, within the XRT73L03 device to operate in the
"Digital Local Loop-back" Mode.
NOTE: This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode, and the user should connect this pin to GND.
70
66
RxAVDD1
****
71
67
RRing1
I
Receive Analog 3.3V+ 5% VDD - Channel 1
Receive Ring Input - Channel 1:
This input pin, along with RTIP1 is used to receive the bipolar
line signal from the "Remote DS3/E3 Terminal".
72
68
RTIP1
I
Receive TIP Input - Channel 1:
This input pin, along with RRing1 is used to receive the bipolar
line signal from the "Remote DS3/E3/STS-1 Terminal".
73
69
RxAGND1
****
Receive Analog GND - Channel 1
11
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
74
70
REQEN1
I
DESCRIPTION
Receive Equalization Enable Input - Channel 1:
Setting this input pin "high" enables in the Internal Receive
Equalizer, within Channel 1. Setting this pin "low" disables the
Internal Receive Equalizer. The guidelines for enabling and disabling the Receive Equalizer are described in Section 3.2.
NOTE: This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode, and the user should connect this pin to GND.
75
71
LOSTHR3
I
Loss of Signal Threshold Control - Channel 3:
Refer to the description of pin 67 or 63, LOSTHR1
76
72
LLB3
I
Local Loop-back - Channel 3:
Refer to the description of pin 68 or 64, LLB1
77
73
RLB3
I
Remote Loop-back - Channel 3:
Refer to the description of pin 69 or 65, RLB1
78
74
RxAVDD3
****
79
75
RRing3
I
Receive Analog 3.3V+ 5% VDD - Channel 3
Receive Ring Input - Channel 3:
Refer to the description of pin 71 or 67, RRing 1
80
76
RTIP3
I
Receive TIP Input - Channel 3:
Refer to the description of pin 72 or 68, RTIP 1
81
77
RxAGND3
****
82
78
REQEN2
I
Receive Analog GND - Channel 3
Receive Equalization Enable Input - Channel 2:
Refer to the description of pin 74 or 70, REQEN1
83
79
RxAGND2
****
84
80
RTIP2
I
Receive Analog GND - Channel 2
Receive TIP Input - Channel 2:
Refer to the description of pin 72 or 68, RTIP 1
85
81
RRing2
I
Receive Ring Input - Channel 2:
Refer to the description of pin 71 or 67, RRing 1
86
82
RxAVDD2
****
87
83
RLB2
I
Receive Analog 3.3V+ 5% VDD - Channel 2
Remote Loop-back - Channel 2:
Refer to the description of pin 69 or 65, RLB1
88
84
LLB2
I
Local Loop-back - Channel 2:
Refer to the description of pin 68 or 64, LLB1
89
85
LOSTHR2
I
Loss of Signal Threshold Control - Channel 2 :
Refer to the description of pin 67 or 63, LOSTHR1
90
86
NC
No Connection
91
87
NC
No Connection
12
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XRT73L03
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
92
88
E3_Ch2
I
DESCRIPTION
E3 Select Input - Channel 2:
A "high" on this pin configures Channel 2 of the XRT73L03
device to operate in the E3 Mode.
A "low" on this pin configures Channel 2 of the XRT73L03 to
check the state of the STS-1/DS3_Ch2 input pin
NOTE: This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode, and the user should connect this pin to GND.
93
89
SR/(DR)
I
Receive Output Single-Rail/Dual-Rail Select:
Setting this pin "HIGH" configures the Receive Sections of all
Channels, to output data (in a Single-Rail Mode) to the Terminal
Equipment.
Setting this pin "LOW" configures the Receive Section of all
Channels, to output data (in a Dual-Rail Mode) to the Terminal
Equipment.
94
90
AGND3
****
95
91
STS1/
DS3_Ch2
I
REGR/
(RxClkINV)
I
96
92
Analog Ground (Substrate Connection) - Channel 3
STS-1/DS3 Select Input - Channel 2:
Refer to the description of pin 65 or 61, STS1/DS3_Ch1
Register Reset Input pin (Invert RxClk(n) Output Select):
The function of this pin depends upon whether the XRT73L03
device is operating in the "Host" Mode or in the "Hardware"
Mode.
NOTE: This pin is internally pulled "high".
Host-Mode - Register Reset Input pin:
Setting this input pin "low" causes the XRT73L03 device to reset
the contents of the Command Registers to their default settings.
Additionally, it resets the XRT73L03 device to its "default" operating configuration.
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "high" configures the Receive Section of all
Channels (within the XRT73L03 device) to invert their "RxClk(n)"
clock output signals.
Specifically, setting this pin "low" configures Channel (n) to output the recovered data (via the RPOS(n) and RNEG(n) output
pins) on the "rising" edge of RxClk(n).
Conversely, setting this input pin "high" configures Channel (n) to
output the recovered data (via the RPOS(n) and RNEG(n) output
pins) on the "falling" edge of RxClk(n).
97
93
EXDGND
****
External Reference Clock GND
98
94
EXDVDD
****
External Reference Clock Power Supply
99
95
EXClk2
I
External Reference Clock Input - Channel 2:
Refer to the description of pin 49 or 45, EXCLK1
13
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
100
96
REQEN3
I
DESCRIPTION
Receive Equalization Enable Input - Channel 3:
Refer to the description of pin 74 or 70, REQEN1
101
102
97
98
STS1/
DS3_Ch3
I
E3_CH3
I
STS-1/DS3 Select Input - Channel 3:
Refer to the description of pin 65 or 61, STS1/DS3_Ch1
E3 Select Input - Channel 3:
Refer to the description of pin 92 or 88, E3_Ch2
103
99
EXClk3
I
External Reference Clock Input - Channel 3:
Refer to the description of pin 49 or 45, EXCLK1
104
100
Channel 3 Receiver Shut OFF" Input:
RxOFF3
Hardware Mode - Channel 3 Receiver Shut OFF Input pin:
Setting this input pin "high" shuts off the Receive Section within
Channel 3. Conversely, setting this input pin "low" enables the
Receive Section for full operation.
105
101
RLOL2
O
Receive Loss of Lock Output Indicator - Channel 2:
Refer to the description of pin 57 or53, RLOL1
106
102
LCV2
O
Line Code Violation Indicator - Channel 2:
Refer to the description of pin 56 or52, LCV1
107
103
RLOS2
O
Receive Loss of Signal Output Indicator - Channel 2:
Refer to description of pin 55 or 51, RLOS1
108
104
RxDGND2
****
109
105
RPOS2
O
Receive Digital Ground - Channel 2
Receive Positive Pulse Output - Channel 2:
Refer to the description of pin 45 or 41, RPOS3
110
106
RNEG2
O
Receive Negative Pulse Output - Channel 2:
Refer to the description of pin 44 or 40, RNEG3
111
107
RxClk2
O
Receive Clock Output pin - Channel 2:
See description of pin 43 or 39, RxClk3
14
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
PIN DESCRIPTION
PIN #
14 X 20MM
PIN #
14X14MM
SIGNAL NAME
TYPE
112
108
LOSMUTEN
I
DESCRIPTION
MUTE-upon-LOS Enable Input (Hardware Mode):
This input pin permits the user to configure the XRT73L03
device (while it is operating in the "Hardware Mode") to MUTE
the recovered data (via the RPOS(n), RNEG(n) output pins),
whenever one of the Channels declares an LOS conditions.
Setting this input pin "high" will configure all Channels to automatically pull the RPOS(n) and RNEG(n) output pins to "GND",
whenever it is declaring an LOS condition (thereby MUTing the
data being output to the Terminal Equipment).
Setting this input pin "low" configures all Channels to NOT automatically MUTE the recovered data, whenever an LOS condition
is declared.
NOTES:
1. This input pin is ignored if the XRT73L03 is operating in
the "Host" Mode, and the user should connect this pin to
GND.
2. This pin is internally pulled "High".
113
109
RxDVDD2
****
Receive Digital 3.3V+ 5% VDD - Channel 2
114
110
AGND2
****
Analog Ground (Substrate Connection) - Channel 2
115
111
TxOFF3
I
Transmitter OFF Input - Channel 3:
Refer to the description of pin 117 or 113, TxOFF1
116
112
TxOFF2
I
Transmitter OFF Input - Channel 2:
Refer to the description of pin 117 or 113, TxOFF1
117
113
TxOFF1
I
Transmitter OFF Input - Channel 1:
Setting this input pin "high" configures the XRT73L03 device to
turn off the Transmit Section within Channel 1. In this mode, the
TTIP1 and TRing1 outputs will be tri-stated.
NOTES:
1. This input pin controls the TTIP1 and TRing1 outputs,
even when the XRT73L03 is operating in the "Host"
Mode.
2. For Host Mode Operation, the user should tie this pin to
GND, if the Transmitter is intended to be turned off via
the Microprocessor Serial Interface.
118
114
TxAGND2
****
Transmitter Analog GND - Transmitter 2
119
115
TxAVDD2
****
Transmitter Analog 3.3V+ 5% VDD - Transmitter 2
120
116
DMO2
O
Drive Monitor Output - Channel 2:
Refer to the description of pin 38 or 34, DMO1
15
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XRT73L03
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
DC Electrical Characteristics
DVDD
Digital DC Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog DC Supply Voltage
3.135
3.3
3.465
V
TBD
TBD
mA
0.8
V
2.0
VDD
V
ICC
Supply Current (Measured while Transmitting and Receiving all
"1s"
VIL
Input Low Voltage *
VIH
Input High Voltage *
VOL
Output Low Voltage, IOUT = -4.0mA *
0
0.4
V
VOH
Output High Voltage, IOUT = 4.0mA *
2.8
VDD
V
±10
µA
IL
Input Leakage Current *
NOTE: * Not applicable to pins with pull-down resistors.
ELECTRICAL CHARACTERISTICS (CONTIUED) (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
AC ELECTRICAL CHARACTERISTICS (SEE FIGURE 1)
TERMINAL SIDE TIMING PARAMETERS (SEE FIGURES 2 AND 3) -- {(n) =1,2 OR 3}
PARAMETER
MIN.
TYP.
MAX.
UNITS
TxClk(n) Clock Duty Cycle STS-1/DS3)
30
50
70
%
TxClk(n) Clock Duty Cycle (E3)
30
50
70
%
SYMBOL
TxClk(n) Frequency (SONET STS-1)
51.84
MHz
TxClk(n) Frequency (DS3)
44.736
MHz
TxClk(n) Frequency (E3)
34.368
MHz
tRTX
TxClk(n) Clock Rise Time (10% to 90%)
3
5
ns
tFTX
TxClk(n) Clock Fall Time (90% to 10%)
3
5
ns
tTSU
TPData(n)/TNData(n) to TxClk(n) Falling Set up time
3
1.5
ns
tTHO
TPData(n)/TNData(n) to TxClk(n) Falling Hold time
3
1.5
ns
tLCVO
RxClk(n) to rising edge of LCV1(n) output delay
2.5
ns
tTDY
TTIP(n)/TRing(n) to TxClk(n) Rising Propagation Delay time
8
ns
RxClk(n) Clock Duty Cycle
50
%
RxClk(n) Frequency (SONET STS-1)
51.84
MHz
RxClk(n) Frequency (DS3)
44.736
MHz
RxClk(n) Frequency (E3)
34.368
MHz
2.5
ns
tCO
0
RxClk(n) to RPOS(n)/RNEG(n) Delay Time
16
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
ELECTRICAL CHARACTERISTICS (CONTIUED) (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
AC ELECTRICAL CHARACTERISTICS (SEE FIGURE 1)
TERMINAL SIDE TIMING PARAMETERS (SEE FIGURES 2 AND 3) -- {(n) =1,2 OR 3}
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
tRRX
RxClk(n) Clock Rise Time (10% to 90%)
1.5
ns
tFRX
RxClk(n) Clock Fall Time (10% to 90%)
1.5
ns
CI
Input Capacitance
5
TBD
pF
CL
Load Capacitance
5
TBD
pF
2. All XRT73L03 digital outputs are also TTL 5V compliant. however these outputs will not drive to 5V
nor will they accept external 5V pullups.
NOTES:
1. All XRT73L03 digital inputs are designed to be TTL
5V compliant.
ELECTRICAL CHARACTERISTICS (CONTIUED), (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS E3 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 1)
PARAMETER
MIN.
TYP.
MAX
UNITS
Transmit Output Pulse Amplitude
(Measured at Secondary Output of Transformer, see Figure 1)
0.9
1.0
1.1
Vpk
Transmit Output Pulse Amplitude Ratio
0.95
1.00
1.05
Transmit Output Pulse Width
12.5
14.55
16.5
Transmit Output Pulse Width Ratio
0.95
1.00
1.05
0.02
0.05
SYMBOL
Transmit Output Jitter with jitter-free input @ TxClk(n)
ns
UIpp
Receive Line Characteristics (See Figure 3)
Receive Sensitivity (Length of cable)
1200
feet
Interference Margin
TBD
dB
Signal Level to Declare Loss of Signal
-35
dB
Signal Level to Clear Loss of Signal
-15
dB
Occurrence of LOS to LOS Declaration Time
10
255
UI
Termination of LOS to LOS Clearance Time
10
255
UI
Intrinsic Jitter (As Measured in the RxClk(n) signal)
TBD
UI
Jitter Transfer Function, -3dB Frequency
TBD
kHz
Jitter Transfer Function, Peak Gain
TBD
dB
Jitter Tolerance @ Jitter Frequency = 100Hz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 1kHz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 10kHz
TBD
UI
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
ELECTRICAL CHARACTERISTICS (CONTIUED), (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS E3 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 1)
SYMBOL
PARAMETER
MIN.
TBD
Jitter Tolerance @ Jitter Frequency = 800kHz
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TYP.
MAX
UNITS
UI
XRT73L03
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
ELECTRICAL CHARACTERISTICS (CONTIUED), (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS SONET STS-1 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 2)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
Transmit Output Pulse Amplitude
(Measured with TxLEV=0, see Figure 1)
0.68
0.75
0.85
Vpk
Transmit Output Pulse Amplitude
(Measured with TxLEV=1, see Figure 1)
0.93
0.98
1.08
Vpk
Transmit Output Pulse Width
8.6
9.65
10.6
ns
Transmit Output Pulse Amplitude Ratio
0.9
1.0
1.1
0.02
0.05
Transmit Output Jitter with jitter-free input @ TxClk(n)
UI
Receive Line Characteristics (See Figure 3)
1000
feet
Signal Level to Declare Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 1)
90
mV
Signal Level to Clear Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 1)
240
mV
Signal Level to Declare Loss of Signal
(LOSTHR(n) = 1, REQEN(n) = 1)
35
mV
Signal Level to Clear Loss of Signal (LOSTHR(n) = 1,
REQEN(n) = 1)
90
mV
Signal Level to Declare Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 0)
70
mV
Signal Level to Clear Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 0)
190
mV
Signal Level to Declare Loss of Signal (LOSTHR(n) = 1,
REQEN(n) = 0)
35
Signal Level to Clear Loss of Signal (LOSTHR(n) = 1,
REQEN(n) = 0)
65
mV
Intrinsic Jitter (As Measured at the RxClk(n) Output Pin)
TBD
UI
Jitter Transfer Function, -3dB Frequency
TBD
kHz
Jitter Transfer Function, Peak Gain
TBD
dB
Jitter Tolerance @ Jitter Frequency = 100Hz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 1kHz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 10kHz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 800kHz
TBD
UI
Receive Sensitivity (Length of Table)
19
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90
mV
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
ELECTRICAL CHARACTERISTICS (CONTIUED), (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS DS3 APPLICATION
Transmit Characteristics (see Figure 2)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
Transmit Output Pulse Amplitude
(Measured a 0 feet, TxLEV=0, see Figure 1)
0.68
0.75
0.85
Vpk
Transmit Output Pulse Amplitude
(Measured a 0 feet, TxLEV=1, see Figure 1)
0.9
1.0
1.1
Vpk
10.10
11.18
12.28
ns
0.9
1.0
1.1
0.02
0.05
Transmit Output Pulse Width
Transmit Output Pulse Amplitude Ratio
Transmit Output Jitter with jitter-free input @ TxClk(n)
UI
Receive Line Characteristics (See Figure 3)
Receive Sensitivity (Length of Table)
1000
feet
Receive Intrinsic Jitter (All One’s Pattern)
TBD
UI
Receive Intrinsic Jitter (Using PRBS 2^23-1 Pattern)
TBD
UI
Signal Level to Declare Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 1)
70
mV
Signal Level to Clear Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 1)
200
mV
Signal Level to Declare Loss of Signal
(LOSTHR(n) = 1, REQEN(n) = 1)
35
mV
Signal Level to Clear Loss of Signal (LOSTHR(n) = 1,
REQEN(n) = 1)
80
mV
Signal Level to Declare Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 0)
50
mV
130
mV
Signal Level to Declare Loss of Signal (LOSTHR(n) = 1,
REQEN(n) = 0)
25
mV
Signal Level to Clear Loss of Signal (LOSTHR(n) = 1,
REQEN(n) = 0)
55
mV
Intrinsic Jitter (As Measured at the RxClk(n) Output Pin)
TBD
UI
Jitter Transfer Function, -3dB Frequency
TBD
kHz
Jitter Transfer Function, Peak Gain
TBD
dB
Jitter Tolerance @ Jitter Frequency = 100Hz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 1kHz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 10kHz
TBD
UI
Jitter Tolerance @ Jitter Frequency = 800kHz
TBD
UI
Signal Level to Clear Loss of Signal (LOSTHR(n) = 0,
REQEN(n) = 0)
20
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
ELECTRICAL CHARACTERISTICS (CONTIUED), (TA = 250C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED)
MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 4)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
t21
CS Low to Rising Edge of SClk Setup Time
50
ns
t22
CS High to Rising Edge of SClk Hold Time
20
ns
t23
SDI to Rising Edge of SClk Setup Time
50
ns
t24
SDI to Rising Edge of SClk Hold Time
50
ns
t25
SClk "Low" Time
240
ns
t26
SClk "High" Time
240
ns
t27
SClk Period
500
ns
t28
CS Low to Rising Edge of SClk Hold Time
50
ns
t29
CS "Inactive" Time
250
ns
t30
Falling Edge of SClk to SDO Valid Time
200
ns
t31
Falling Edge of SClk to SDO Invalid Time
100
ns
t32
Falling Edge of SClk, or rising edge of CS to High Z
t33
Rise/Fall time of SDO Output
100
ns
40
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 650C to + 1500C
Operating Temperature
- 400C to + 850C
Supply Voltage Range
-0.5V to +3.465V
FIGURE 2. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL)
TTIP(n)
R1
31.6
W
Channel (n)
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TPData(n)
TNData(n)
TxClk(n)
R3
75W
1:1
TRing(n)
Only One Channel Shown
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R2
31.6
W
ns
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
FIGURE 3. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
tSU
tHO
TPDATA
TNDATA
TxCLK
FIGURE 4. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
tCO
RPOS
RNEG
RxCLK
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
FIGURE 5. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
A4
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
High Z
High Z
SDO
3. R/W = "0" for "Write" Operations
NOTES:
1. A5 is always "0".
4. A shaded pulse, denotes a “don’t care” value.
2. R/W = "1" for "Read" Operations
FIGURE 6. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SCLK
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SCLK
t31
t30
SDO
SDI
Hi-Z
D0
t33
D2
D1
Hi-Z
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t32
D7
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
SYSTEM DESCRIPTION
THE HARDWARE MODE
A functional block diagram of the XRT73L03 E3/DS3/
STS-1 Transceiver IC is presented in Figure 7. In
general, the XRT73L03 device contains three separte
channels with three distinct sections:
When the XRT73L03 device is operating in the "Hardware Mode", then the following is true.
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT73L03 device is configured via input
pin settings.
The XRT73L03 device can be configured to operate
in the "Hardware Mode" by tying the "Host/(HW)" input pin (pin 8) to GND.
• The Transmit Section - Channels 1,2 and 3
• The Receive Section - Channels 1,2 and 3
• The Microprocessor Serial Interface section
Each of these sections are briefly discussed below.
THE TRANSMIT SECTION (CHANNELS 1, 2 AND 3
Each of the pins associated with the Microprocessor
Serial Interface will take on their alternative role, as
defined in Table 1.
The Transmit Section, within each Channel, accepts
TTL/CMOS level signals from the "Terminal Equipment" in either a "Single-Rail" or "Dual Rail" format.
The Transmit Section will then take this data and do
the following.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL
INTERFACE PINS WHEN THE XRT73L03 DEVICE IS
OPERATING IN THE "HARDWARE" MODE
• Encode this data into the B3ZS format (if the DS3
or SONET STS-1 Modes have been selected) or
into the HDB3 format (if the E3 Mode has been
selected).
• Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
• Drive these pulses onto the line via the TTIP(n) and
TRing(n) output pins, across a 1:1 Transformer.
FUNCTION, WHILE IN
PIN #
PIN NAME
25
CS/(ENDECDIS)
ENDECDIS
26
SClk/(RxOFF2)
RxOFF2
27
SDI/(RxOFF1)
RxOFF1
28
SDO/(E3_Ch1)
E3_Ch1
62
REGR/(RxClkINV)
RxCKlkINV
HARDWARE MODE
NOTE: Note: The Transmit Section will drive a "1" (or a
"Mark") onto the line by driving either a positive or negative
polarity pulse across the 1:1 Transformer, within a given bit
period. The Transmit Section will drive a "0" (or a "Space")
onto the line by driving no pulse onto the line.
Additionally, when the XRT73L03 device is operating
in the "Hardware" Mode, all of the remaining input
pins become active.
THE RECEIVE SECTION (CHANNELS 1, 2 AND 3)
The XRT73L03 device can be configured to operate
in the "Host" Mode by tying the "Host/(HW)" input pin
(pin 8) to VDD.
THE HOST MODE
The Receive Section, within each Channel, receives
a bipolar signal from the line, via the RTIP and RRing
signals through via a "1:1 Transformer" or via a
"0.01µF Capacitor".
When the XRT73L03 device is operating in the "Host
Mode", then the following is true.
The recovered clock and data will be output to the
"Local Terminal Equipment", in the form of CMOS level signals, via the RPOS(n), RNEG(n) and RxClk(n)
output pins.
1. The Microprocessor Serial Interface block is
enabled. Writing the appropriate data into the
on-chip Command Registers makes many configuration selections.
THE MICROPROCESSOR SERIAL INTERFACE
2. All of the following input pins are disabled.
The XRT73L03 device can be configured to operate
in either the "Hardware" Mode or the "Host" Mode.
Each of these modes will be discussed below.
• Pins 1,90 & 89 - TxLEV(n)
The XRT73L03 contains three identical channels.
The Microprocessor Interface Inputs are common to
all channels. The descriptions that follow will refer to
Channel(n) where “(n)” will represent Channel1,
Channel2, or Channel3.
• Pin 35, 53 & 43 - RLB(n)
• Pins 2, 85 & 84 - TAOS(n)
• Pin 40, 48 & 66 - REQEN(n)
• Pin 34, 54 &42 - LLB(n)
• Pin 28, 56 & 68 - E3_Ch(n)
• Pin 61 - STS-1/DS3_Ch(n)
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
The user is advised to tie each of these pins to GND
to operate the XRT73L03 IC in the "Host" Mode.
system (designed for redundancy) to quickly switch
out a defective line card, and switch-in the back-up
line card.
In Host Mode Operation, the “TxOFF(n)” input pins
can still be used to turn on or turn off the “Transmit
Output Drivers” within Channels 1, 2 and 3, respectively. The intent behind this feature is to permit a
The remainder of this document presents a detailed
description of the features associated with the
XRT73L03 device.
FIGURE 7. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L03 DEVICE
E3_Ch(n)
RTIP(n)
RRing(n)
STS-1/DS3*_Ch(n)
Host/(HW*)
AGC/
Equalizer
RLOL(n) ExClk(n)
Clock
Recovery
Slicer
Peak
Detector
REQEN(n)
RxOFF(n)
Data
Recovery
LOS Detecto r
LOSTHR(n)
RClkINV
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
SClk
CS*
LCV(n)
ENDECDIS
SDI
SDO
RNEG(n)
RLOS(n)
Serial
Processor
Interface
LLB(n)
Loop MUX
RLB(n)
REGR*
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TRing(n)
TxLEV(n)
TxOFF(n)
TClk(n)
MTIP(n)
Device
Monitor
MRing(n)
DMO(n)
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in "Harwa re" Mode.
1.1 CONFIGURING CHANNEL(N)
1.0 SELECTING THE DATA RATE
Each channel within the XRT73L03 device can be
configured to support the E3 (34.368 Mbps), DS3
(44.736 Mbps) or the SONET STS-1 (51.84 Mbps)
rates. Further, each channel can be configured to operate in a mode/data rate that is independent of the
other channels.
For the following disscussion the reader should refer
to Table 2 to determine the approiate Address for
each command register of each channel in the
XRT73L03 device. The command register description will refer to CR(x)-(n), where (x) = 0 to 7 and (n)
refers to a particular channel of the XRT73L03.
The XRT73L03 device permits the user to select the
data rate (for each Channel) via one of two ways.
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
TABLE 2: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
D0
CHANNEL1
0x00
CR0-1
RO
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
0x01
CR1-1
R/W
TxOFF1
TAOS1
TxClkINV1
TxLEV1
1
0x02
CR2-1
R/W
Reserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
0x03
CR3-1
R/W
SR/(DR)_1
LOSMUT1
RxOFF1
RxClk1INV
Reserved
0x04
CR4-1
R/W
Reserved
STS-1/DS3_Ch1
E3_Ch1
LLB1
RLB1
0x05
CR5-1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x06
CR6-1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x07
CR7-1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
CHANNEL2
0x08
CR0-2
RO
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
0x09
CR1-2
R/W
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0x0A
CR2-2
R/W
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
0x0B
CR3-2
R/W
SR/(DR)_2
LOSMUT2
RxOFF2
RxClk2INV
Reserved
0x0C
CR4-2
R/W
Reserved
STS-1/DS3_Ch2
E3_Ch2
LLB2
RLB2
0x0D
CR5-2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x0E
CR6-2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x0F
CR7-2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
CHANNEL3
0x10
CR0-3
RO
RLOL3
RLOS3
ALOS3
DLOS3
DMO3
0x11
CR1-3
R/W
TxOFF3
TAOS3
TxClkINV3
TxLEV3
TxBIN3
0x12
CR2-3
R/W
Reserved
ENDECDIS3
ALOSDIS3
DLOSDIS3
REQEN3
0x13
CR3-3
R/W
SR/(DR)_3
LOSMUT3
RxOFF3
RxClk3INV
Reserved
0x14
CR4-3
R/W
Reserved
STS-1/DS3_Ch3
E3_Ch3
LLB3
RLB3
0x15
CR5-3
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x16
CR6-3
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x17
CR7-3
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Address:
Type:
The register addresses presented in the "hexadecimal" format.
The Command Registers are either "Read-Only"
(RO) type of registers, or are "Read/Write" (R/W) type
of registers.
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
The default value for each of the bit-fields, within these register will be "0".
"E3_Ch(n)", and the "STS-1/DS3_Ch(n)" input pins
(where n = 1,2 or 3) to the appropriate logic states,
as presented below in Table 3.
a. When operating in the "Hardware" Mode.
In order to configure individual Channels into the
appropriate mode, the user must set the
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL(N), (WITHIN THE XRT73L03 DEVICE), VIA THE "E3_CH(N)"
AND "STS-1/DS3_CH(N)" INPUT PINS (HARDWARE MODE)
STATE OF E3_CH(N) PIN
(PIN 28, 55, 68)
STATE OF STS-1/DS3_CH(N)
PIN
(PIN 31, 61, 67)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps)
1
X (Don't Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
STS-1 (51.84 Mbps)
0
1
B3ZS
DATA RATE
b. When operating in the "Host" Mode.
• HDB3/(B3ZS) Encoder
In order to configure a Channel into the appropriate
mode, the user must write the appropriate values into
the "STS-1/DS3_Ch(n)" and "E3_Ch(n)" bit-fields,
within Command Register CR4-(n), as illustrated below (please refer to Table 2 for the correct address for
each channel).
• Pulse Shaping Block
Each of these blocks will be discussed in some detail
below
In general, the purpose of the "Transmit Section",
within each Channel of the XRT73L03 device, is to
take TTL/CMOS level data, from the terminal equipment, and encode it into a format such that it can:
COMMAND REGISTER, CR4-(N)
D4
D3
D2
X
STS-1/(DS3)_(n))
x
x
D1
1. Be efficiently transmitted over coaxial cable; at
E3, DS3, or STS-1 data rates; and
D0
E3_Ch(n) LLB(n) RLB(n)
x
x
2. Be reliably received by the Remote Terminal
Equipment at the other end of the E3, DS3, or
STS-1 data link.
x
Table 4 relates the values of these two bit-fields to the
selected data rates.
3. Comply with the applicable pulse template
requirements.
TABLE 4: SELECTING THE DATA RATE FOR
CHANNEL“(N)” (WITHIN THE XRT73L03 DEVICE); VIA
THE "STS-1/DS3_CH(N)" AND THE "E3_CH(N)" BITFIELDS, WITHIN THE APPROPRIATE COMMAND REGISTER
(HOST MODE)
SELECTED DATA
RATE
STS-1/DS3_(N)
(D3)
E3_CH(N)
(D2)
E3
X (Don't Care)
1
DS3
0
0
STS-1
1
0
The circuitry that the Transmit Section, (within each
Channel of the XRT73L03 device) takes to accomplish this goal is discussed below.
2.1 THE TRANSMIT LOGIC BLOCK
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single Rail (e.g., a binary data
stream) TTL/CMOS level data and timing information
from the Terminal Equipment. The manner in which
the Transmit Logic Block accepts data in these formats are discussed below.
2.1.1 Accepting "Dual-Rail" Data from the Terminal Equipment
2.0 THE TRANSMIT SECTION
Whenever the XRT73L03 device accepts dual-rail data from the Terminal Equipment, it does so via the following input signals.
Figure 7 indicates that the Transmit Section, within
each Channel of the XRT73L03 device consists of the
following blocks:
• TPData(n)
• Transmit Logic Block
• TNData(n)
• The TxClk(n) Duty Cycle Adjust Block
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
• TxClk(n)
mat between the Terminal Equipment and the Transmit Section of the XRT73L03 device.
Figure 8 presents an illustration of the typical interface for the transmission of data in a "Dual-Rail" For-
FIGURE 8. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A
DUAL RAIL FORMAT, FROM THE "TRANSMITTING" TERMINAL EQUIPMENT TO THE "TRANSMIT
SECTION" OF A CHANNEL WITHIN THE XRT73L03 DEVICE
Terminal Equipment
(E3/DS3 or STS-1
Framer
TxPOS
TPData
TxNEG
TNData
TxLineClk
TxClk
Transmit
Logic
Block
Exar E3/DS3/STS-1 LIU
the data on the TPData and TNData input pins on the
falling edge of TxClk(n).
The manner that the LIU handles "Dual-Rail" data is
described below and is illustrated in Figure 9. The
Transmit Section (of a Channel) will typically sample
FIGURE 9. ILLUSTRATION ON HOW THE XRT73L03 DEVICE SAMPLES THE DATA ON THE TPDATA AND TNDATA
INPUT PINS
Data
1
1
0
TPData
TNData
TxClk
2.1.2 Accepting "Single-Rail" Data from the
Terminal Equipment
TxClk(n) is the clock signal that is of the selected data
rate frequency, which for E3 = 34.368 MHz, DS3 =
44.736 MHz and STS-1 = 51.84 MHz. If the Transmit
Section samples a "1" on the TPData input pin, then
the "Transmit Section" of the device will ultimately
generate a positive polarity pulse via the TTIP(n) and
TRing(n) output pins (across a 1:1 transformer).
Conversely, if the Transmit Section samples a "1" on
the TNData input pin, then the "Transmit Section" of
the device will ultimately generate a negative polarity
pulse via the TTIP(n) and TRing(n) output pins
(across a 1:1 transformer).
To transmit data in a "single-rail" data from the “Terminal Equipment”, configure the XRT73L03 in the “Host
Mode”.
To Configure Channel(n) to accept Single-Rail Data from the Terminal Equipment:
Write a "1" into the "TxBin(n)" (TRANSMIT BINary)
bit-field, within Command Register CR1-(n) shown
below. (Please refer to Table 2 for the Address of the
individual (n) channel.
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
NOTES:
1. In this mode, the Transmit Logic Block will ignore
the TNData input pin.
COMMAND REGISTER CR1-(N)
D4
D3
TxOFF(n) TAOS(n)
x
x
D2
TxClkINV(n)
D1
D0
2. If the user configures the Transmit Section (within a
given channel) to accept "Single-Rail" data from the
Terminal Equipment, then the user must enable the
"B3ZS/HDB3" Encoder.
TxLEV(n) TxBin(n)
x
x
1
Figure 10 Illustrates the behavior of the TPData and
TxClk(n) signals, when the Transmit Logic Block has
been configured to accept "single-rail" data from the
Terminal Equipment.
The Transmit Section (of each channel) will sample
this input pin on the "falling" edge of the TxClk(n)
clock signal, and will encode this data into the appropriate bipolar line signal across the TTIP(n) and
TRing(n) output pins.
FIGURE 10. ILLUSTRATION OF THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
TPData
TxClk
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
the number of consecutive zeros that can exist within
the line signal.
CUITRY
2.3.1
The on-chip "Pulse-Shaping" circuitry (within the
Transmit Section of each Channel in the XRT73L03
device) generates pulses of the appropriate shapes
and width to meet the applicable pulse template requirements. The widths of these "output" pulses are
defined by the width of the "half-period" pulses within
the TxClk(n) signal.
If the user has configured the XRT73L03 device to
operate in the DS3 or SONET STS-1 Modes, then the
"HDB3/B3ZS" Encoder blocks will operate in the
"B3ZS" Mode. When the Encoder is operating in this
mode, it will parse through and search the "Transmit
Binary Data Stream" (from the Transmit Logic Block)
for the occurrence of three (3) consecutive zeros
(e.g., "000"). If the "B3ZS Encoder" finds an occurrence of three consecutive zeros, then it will substitute these three "0s", with either a "00V" or a "B0V"
pattern.
However, if the widths of the pulses, within the TxClk(n) clock signal are allowed to vary significantly,
this could jeopardize the chip's ability to generate
Transmit Output pulses of the appropriate width, and
thereby not meeting the "Pulse Template" requirement specification. As consequence, the chip's ability to generate compliant pulses could depend upon
the duty cycle of the clock signal, applied to the TxClk(n) input pin.
Where:
"B" represents a "Bipolar" pulse that is compliant with
the "Alternating Polarity" requirements of the AMI (Alternate Mark Inversion) line code; and
The Transmit Clock Duty Cycle Adjust Circuitry accepts clock pulses, via the TxClk(n) input pin at duty
cycles ranging from 30% to 70%, and converts them
to a 50% duty cycle.
"V" represents a "bipolar Violation" (e.g., a "bipolar"
pulse that violates the "Alternating Polarity" requirements of the AMI line code).
The B3ZS Encoder will decide whether to substitute
with either the "00V" or the "B0V" pattern in order to
insure that an odd number of "bipolar" pulses exist
between any two consecutive "violation" pulses.
2.3 THE HDB3/B3ZS ENCODER BLOCK
The purpose of the "HDB3/B3ZS" Encoder Block is to
aid in the "Clock Recovery" process (at the Remote
Terminal Equipment) by ensuring an upper limit on
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XRT73L03
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
Figure 11 presents an illustration of the "B3ZS Encoder" at work, with two separate strings of three (or
more) consecutive zeros
FIGURE 11. AN EXAMPLE OF B3ZS ENCODING
Data 1
0
TPData
0
0
1
1
1
0
0
0
0 0
V
1
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
1
0
TNData
TxClk
Line
B
2.3.2
HDB3 Encoding
0 V
"000V" or a "B00V" pattern. The HDB3 Encoder will
decide whether to substitute with either the "000V" or
the "B00V" pattern in order to insure that an odd number of "bipolar" pulses exist between any two consecutive "violation" pulses.
If the user has configured the XRT73L03 device to
operate in the "E3 Mode", then the "HDB3/B3ZS" Encoder blocks will operate in the "HDB3" Mode. When
the Encoder is operating in this mode, it will parse
through and search the "Transmit Data Stream" (from
the Transmit Logic Block) for the occurrence of four
(4) consecutive zeros (e.g., "0000"). If the "HDB3 Encoder" finds an occurrence of four consecutive zeros,
then it will substitute these four "0s", with either a
Figure 12presents an illustration of the "HDB3 Encoder" at work, with two separate strings of four (or more)
consecutive zeros.
FIGURE 12. AN EXAMPLE OF HDB3 ENCODING
Data 1
0
TPData
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
TNData
TxClk
0 0
0
V
Line
B
2.3.3
Disabling the "HDB3/B3ZS" Encoder
0 0
V
The "HBD3/B3ZS Encoder" blocks (within all channels) are disabled by setting the "ENDECDIS (Encoder/Decoder Disable)" input pin (pin 25) to "0".
The XRT73L03 device permits the user to disable the
"HDB3/B3ZS" Encoder by two means.
NOTE: By executing this step, the user will globally disable
the "HDB3/B3ZS" Encoder and Decoder blocks within each
channel of the XRT73L03 device.
When the XRT73L03 Device is operating in the
"Hardware" Mode.
When the XRT73L03 Device is operating in the
"Host" Mode.
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
Configuring Channel(n)
The user can disable the "HDB3/B3ZS Encoder"
block within Channel(n) by setting the "ENDECDIS(n)" bit-field, within Command Register (CR2-(n)),
to "1" as illustrated below..
When the XRT73L03 device is operating in the "Host"
Mode, then the "HDB3/B3ZS" Encoders (within each
channel) can be individually enabled or disabled.
COMMAND REGISTER, CR2-(N)
D4
D3
D2
D1
D0
Reserved
ENDECDIS(n)
ALOSDIS(n)
DLOSDIS(n)
REQEN(n)
x
1
x
x
x
NOTE: This method can only be used if the XRT73L03
device is operating in the "Host" Mode.
device to transmit an output pulse which is compliant
to either of the following pulse template requirements
(when measured at the Digital Cross Connect System). Each of these Bellcore specifications further
state that the cable length (between the Transmit Output and the Digital Cross Connect system) can range
anywhere from 0 to 450 feet.
If the user employs either of these two methods to
disable the "HDB3/B3ZS" Encoder, then the LIU will
transmit the data as received via the TPData and
TNData input pins.
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY
The Isolated DSX-3 Pulse Template Requirement
(per Bellcore GR-499-CORE), is illustrated in Figure
13 and the Isolated STSX-1 Pulse Template Requirement (per Bellcore GR-253-CORE), is illustrated in
Figure 14.
The Transmit Pulse Shaper Circuitry consists of a
Transmit Line Build-Out circuit which can be enabled
or disabled, by setting the TxLEV(n) input pin (or "TxLEV(n)" bit-field) to "HIGH" or "LOW". The purpose
of the "Transmit Line Build-Out" circuit is to permit the
user to configure each channel within the XRT73L03
FIGURE 13. THE "BELLCORE GR-499-CORE" TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
D S 3 P u ls e T e m p la te
1.2
1
N o rm a l iz e d Am p l itu d e
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
2
3
4
1.
9
1.
8
0.
1.
7
0.
1
6
0.
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1
5
0.
T i m e , in U I
1.
4
0.
3
0.
2
0.
1
0
0.
0.
.2
.3
.4
.5
.6
.7
.8
.9
.1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-1
-0.2
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
.
FIGURE 14. THE "BELLCORE GR-253-CORE" TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1
APPLICATIONS
ST S-1 Pulse T em p late
1.2
1
Norm a lize d Am plitude
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
2
3
4
1.
1.
9
1
8
0.
1.
7
0.
1
6
0.
1.
5
4
0.
0.
3
0.
0.
2
0.
0
1
0.
.2
.3
.1
-0
-0
.4
-0
.5
-0
.7
.8
.6
-0
-0
-0
.9
-0
-0
-1
-0.2
Tim e , in UI
2.4.1
cuit
Enabling the Transmit Line Build-Out Cir-
The user enables the Transmit Line Build-Out circuit
(for each channel within the XRT73L03 device) by doing the following:
If the user enables the "Transmit Line Build-Out" Circuit, then the "Transmit Section" of the Channel (within the XRT73L03 device) will output shaped pulses
onto the line via the TTIP(n) and TRing(n) output
pins.
In the "Hardware" Mode
• Set the "TxLEV(n)" input pin to "LOW"
In the "Host" Mode
• Set the "TxLEV(n)" bit-field to "0", as illustrated
below.
COMMAND REGISTER, CR1-(N)
D4
D3
D2
D1
D0
TxOFF(n)
TAOS(n)
TxClkINV(n)
TxLEV(n)
TxBIN(n)
0
X
X
0
X
2.4.2
cuit
Disabling the Transmit Line Build-Out Cir-
(e.g., square-wave) pulses onto the line via the
TTIP(n) and TRing(n) output pins.
The user disables the Transmit Line Build-Out circuit
(within the XRT73L03 device) by doing the following:
If the user disables the "Transmit Line Build-Out" circuit, then the XRT73L03 device will output un-shaped
In the "Hardware" Mode.
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ADVANCED CONFIDENTIAL
REV. A1.0.7
• Set the "TxLEV(n)" input pin to "HIGH".
• Set the "TxLEV(n)" bit-field to "1" as illustrated
below.
In the "Host" Mode.
COMMAND REGISTER, CR1-(N)
D4
D3
D2
D1
D0
TxOFF(n)
TAOS(n)
TxClkINV(n)
TxLEV(n)
TxBin(n)
0
X
X
1
X
NOTE: In this case, the configured channel (within the
XRT73L03 device) will output un-shaped (e.g., squarewave) pulses onto the line via the TTIP(n) and TRing(n) output pins. The cable loss, that these pulses will experience
over long cable lengths (e.g., greater than 225 feet) will
cause these pulses to be "properly shaped" and comply
with the appropriate pulse template requirement.
2.4.3 Design Guideline for Setting the Transmit
Line Build-Out Circuit
The "TxLEV(n)" input pins or bit-fields should be set
based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect
system (where the pulse template measurements are
made).
2.4.4 The Transmit Line Build-Out Circuit and
E3 Applications
If the cable length (between the Transmitting Terminal and the DSX-3 or STSX-1) is less than 225
feet
The user is advised to enable the "Transmit Line
Build-Out circuit" by setting the "TxLEV(n)" input pin
or bit-field to "0".
The "ITU-T G.703 Pulse Template Requirements for
E3" states that the E3 transmit output pulse should be
measured at the Secondary Side of the Transmit Output Transformer, for "Pulse Template" compliance. In
other words, there is no "Digital Cross Connect System" pulse template requirement for E3. As a consequence, the "Transmit Line Build-Out" circuit, within a
given Channel (within the XRT73L03 device), is disabled whenever that channel has been configured to
operate in the E3 Mode.
NOTE: In this case, the configured channel (within the
XRT73L03 device) will output shaped (e.g., not squarewave) pulses onto the line via its TTIP(n) and TRing(n) output pins. The shape of this output pulse is such that it will
comply with the pulse template requirements even when
subjected to cable loss ranging from 0 to 225 feet.
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE
XRT73L03 DEVICE TO THE LINE
If the cable length (between the Transmitting Terminal and the DSX-3 or STSX-1) is greater than
225 feet.
The user is advised to disable the "Transmit Line
Build-Out circuit" by setting the "TxLEV(n)" input pin
or bit-field to "1".
The E3, DS3, and SONET STS-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 Ohm resistor.
As a consequence, the user is encouraged to interface the "Transmit Section" of the XRT73L03 device,
in the manner illustrated in Figure 15.
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
FIGURE 15. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73L03
DEVICE TO THE LINE
TTIP(n)
R1
31.6 Ω
Channel (n)
TxPOS(n)
TxNEG(n)
TxLineClk(n)
J1
BNC
TPData(n)
TNData(n)
TxClk(n)
1:1
R2
31.6 Ω
TRing(n)
Only One Channel Shown
The Surrey Research Park
Transmit Transformer Recommendations
PARAMETER
VALUE
Turns Ratio
1:1
Primary Inductance
4µH
Isolation Voltage
1500Vrms
Leakage Inductance
0.06µH
Guildford, Surrey GU2 5RE
United Kingdom
Tel: 44-1483-401700
FAX: 44-1483-401701
Asia
150 Kampong Ampat
#07-01/02
KA Centre
Singapore 368324
PART #
INSULATION
PACKAGE TYPE
PE-68629
3000V
Large Thru-Hole
PE-65966
1500V
Small Thru-Hole
PE-65967
1500V
Small, SMT
T3001
1500V
Small, SMT
Tel: 65-287-8998
FAX: 65-280-0080
3.0 THE RECEIVE SECTION
Figure 7 indicates that the Receive Section, within the
XRT73L03 device consists of the following blocks:
• AGC/Equalizer
TRANSFORMER VENDOR INFORMATION
• Peak Detector
Pulse
• Slicer
Corporate Office
• Clock Recovery PLL
12220 World Trade Drive
• Data Recovery
San Diego, CA 92128
• HDB3/B3ZS Decoder
Tel: (619)-674-8100
Each of these blocks will be discussed in some detail
below.
FAX: (619)-674-8262
In general, the purpose of the "Receive Section' within the XRT73L03 device is to take an incoming attenuated/distorted bipolar signal, from the line, and to
Europe
1 & 2 Huxley Road
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
encode it back into the TTL/CMOS format where it
can be received and processed by the Terminal
Equipment.
The design of the Receive Circuitry within the
XRT73L03 device permits the user to transformercouple or capacitive-couple the Receive Section to
the line. As mentioned earlier, the specification documents for E3, DS3, and STS-1 all specify 75 Ohm termination loads, when transmitting over coaxial cable. As a result, the user is recommended to interface the "Receive Section" of the XRT73L03 device to
the line in a manner as shown in Figure 16 and Figure
17.
The circuitry that the XRT73L03 device employs to
accomplish this goal is discussed below.
3.1 INTERFACING THE RECEIVE SECTIONS OF THE
XRT73L03 DEVICE TO THE LINE
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L03
DEVICE TO THE LINE (TRANSFORMER-COUPLING)
RTIP(n)
Channel (n)
RxPOS(n)
RxNEG(n)
RxClk(n)
R1
37.5Ω
RPOS(n)
RNEG(n)
RxClk(n)
T1
C1
0.01uf
R2
37.5Ω
RRing(n)
Only One Channel Shown
Corporate Office
Receive Transformer Recommendations
PARAMETER
VALUE
Turns Ratio
1:1
Primary Inductance
40µH
Isolation Voltage
1500Vrms
Leakage Inductance
0.6µH
12220 World Trade Drive
San Diego, CA 92128
Tel: (619)-674-8100
FAX: (619)-674-8262
Europe
1 & 2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
PART #
INSULATION
PACKAGE TYPE
PE-68629
3000V
Large Thru-Hole
FAX: 44-1483-401701
PE-65966
1500V
Small Thru-Hole
Asia
PE-65967
1500V
Small, SMT
T3001
1500V
Small, SMT
Tel: 44-1483-401700
150 Kampong Ampat
#07-01/02
KA Centre
TRANSFORMER VENDOR INFORMATION
Singapore 368324
Pulse
Tel: 65-287-8998
FAX: 65-280-0080
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J1
BNC
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
Figure 17 presents the recommended schematic for
capacitive-coupling each Receive Section of the
XRT73L03 device to the line.
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L03
LINE (CAPACITIVE-COUPLING)
DEVICE TO THE
J1
BNC
C1
0.01uf
RTIP(n)
R1
75Ω
Channel (n)
RxPOS(n)
RxNEG(n)
RxClk(n)
RPOS(n)
RNEG(n)
RxClk(n)
C2
0.01uf
RRing(n)
Only One Channel Shown
3.2 THE RECEIVE EQUALIZER BLOCK
Equalizer attempts to restore the shape of the line
signal so that the transmitted data and clock can be
recovered reliably.
The purpose of this block is to equalize the incoming
distorted signal, due to cable loss. The Receive
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ADVANCED CONFIDENTIAL
REV. A1.0.7
.
FIGURE 18. ILLUSTRATION OF THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
Digital Cross-Connect
System
Transmitting
Terminal
0 to 450 feet of
Cable
Pulses that are
compliant to the
Isolated DSX-3 or
STSX-1 Pulse Template
Requirement
DSX-3
or
STSX-1
0 to 450 feet of Cable
Receiving
Terminal
Design Considerations (for DS3 and STS-1 Applications)
b. That the length of cable between the Digital CrossConnect system and the Receive Terminal can range
between 0 and 450 feet.
When installing equipment into environments as depicted in Figure 18, we recommend that the user enable the Receive Equalizer, by setting the "REQDIS(n)" input pin (for Channel(n)) or the respective
bit-fields to "0". In fact, the only time that the user
should disable the Receive Equalizer is when an offchip equalizer in the Receive path, between the Digital Cross-Connect system and the RTIP/RRing input
pins, or in applications where the Receiver is monitoring the transmit output signal directly.
As a consequence, the overall cable length (between
the Transmitting Terminal and the Receiving Terminal)
can range between very short cable length (e.g., near
0 feet) up to 900 feet.
If, during System Installation, the overall cable length
is known, then (in order to optimize the performance
of the XRT73L03 device, in terms of receive jitter performance, etc.) the user should enable or disable the
Receive Equalizer, based upon the following recommendations.
Design Considerations (for E3 Applications or if
the Overall Cable Length is known)
As a guideline, the Receive Equalizer should be
"turned ON", if the Receive Section (of a given channel) is going to receive a line signal with an overall cable length of 300 feet or greater. Conversely, the Receive Equalizer should be "turned OFF" if the Receive
Section (of a given channel) is going to receive a line
signal over a cable length of less than 300 feet.
Figure 18 indicates the following.
a. That the length of cable between the Transmitting
Terminal and the Digital Cross-Connect system can
range between 0 and 450 feet.
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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ADVANCED CONFIDENTIAL
REV. A1.0.7
quency components within the line signal are subject to the same amount of attenuation). Flat loss is
handled by the AGC block.
NOTES:
1. If the user turns "ON" the Receive Equalizer block
(within a given Receive Section that is receiving a
line signal over short cable length), he/she runs the
risks of "over-equalizing" the received line signal
which could degrade performance by increasing
the amount of jitter that exists within the recovered
data and clock signals, or by creating bit-errors.
The user can disable the Receive Equalizer block by
doing either of the following.
2. The Receive Equalizer has been designed to
counter the "frequency-dependent" (e.g., cable
loss) that a line signal experiences as it travels from
the transmitting terminal to the receiving terminal.
However, Receive Equalizer was not designed to
counter "flat loss" (e.g., where all of the Fourier fre-
2. Writing a "0" to the "REQEN(n)" bit-field within
Command Register, CR2 (when operating the
XRT73L03 device in the "Host" Mode), as illustrated below.
Configuring Channel(n)
1. Setting the "REQEN(n)" input pin "low" (when
operating in the "Hardware" Mode); or
COMMAND REGISTER CR-2 (N)
D4
D3
D2
D1
D0
RESERVED
ENDECDIS(n)
ALOSDIS(n)
DLOSDIS(n)
REQEN(n)
X
X
X
X
0
3.3 CLOCK RECOVERY PLL
covery" PLL will be "locked" onto the line signal (via
the RTIP and RRing input pins).
The purpose of the Clock Recovery PLL is to track
the incoming "dual-rail" data stream and to derive and
generate a "recovered clock signal".
3.4 THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal, typically encodes
the line signal into some sort of "Zero Suppression"
Line Code (e.g., HDB3 for E3, and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process, of this data, within
the "Near-End" Receiving Terminal. However, once
the data has made it across the E3, DS3 or STS-1
Transport Medium, and has been "recovered" by the
Clock Recovery PLL, it is now necessary to restore
the original content of the data. Hence, the purpose
of the "HDB3/B3ZS Decoding" block is to restore the
data (transmitted over the E3, DS3 or STS-1 line) to
its original content prior to "Zero Suppression" Coding.
It is important to note that the "Clock Recovery PLL"
requires a "line rate" clock signal at the "ExClk" input
pin.
The "Clock Recovery PLL" operates in one of two
modes:
• The "Training" Mode.
• The "Data/Clock Recovery" Mode
Each of these modes will be briefly discussed below.
1. The Training Mode
If a given channel (within the XRT73L03 device) is not
receiving a line signal (via the "RTIP" and "RRing" input pins), or if the frequency difference between the
line signal and that applied via the ExClk input pin exceeds 0.5%, then the channel will be operating in the
"Training Mode". When the channel is operating in
the "Training Mode", it will do the following:
3.4.1
If the XRT73L03 device is configured to operate in the
DS3 or STS-1 Modes, then the "HDB3/B3ZS" Decoding Blocks will perform "B3ZS" Decoding. When the
Decoders are operating in this mode, each of the Decoders will parse through its respective incoming "Dual Rail" data and check for the occurrence of either a
"00V" or a "B0V" pattern. If the B3ZS Decoder detects this particular pattern, then it will substitute
these bits with a "000" pattern.
a. Declare a "Loss of Lock" indication, by toggling its
respective "RLOL(n)" output pin "high".
b. Output a clock signal (via the RxClk(n) output
pins) which is derived from the signal applied to
the "EXClk(n)" input pin.
2. The "Data/Clock Recovery" Mode
NOTE: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the"B3ZS Line Code" format;
or if the "B3ZS Decoder" detects a string of 3 (or more) consecutive "0s", in the incoming line signal, then the "B3ZS
Decoder" will flag this event as a "Line Code Violation" by
pulsing the "LCV" output pin "high".
If the frequency difference between the line signal
and that applied via the ExClk input pin is less than
0.5%, then the channel will be operating in the "Data/
Clock Recovery" mode. In this mode, the "Clock Re38
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3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
Figure 19 presents an illustration of the "B3ZS Decoder" at work, with two separate "Zero Suppression"
patterns, in the incoming "Dual Rail Data Stream".
FIGURE 19. AN EXAMPLE OF B3ZS DECODING
0 0
V
Line
B
0 V
RxClk
RPOS
RNEG
0
Data
0
3.4.2
1
0
0
1
1
0
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
1
1
HDB3 Decoding (E3 Applications)
particular pattern, then it will substitute these bits with
a "0000" pattern.
If the XRT73L03 is configured to operate in the "E3
Mode" then each of the "HDB3/B3ZS" Decoding
Blocks will perform "HDB3" Decoding. When the Decoders are operating in this mode, they will each
parse through the incoming "Dual Rail" data and
check for the occurrence of either a "000V" or a
"B00V" pattern. If the HDB3 Decoder detects this
Figure 20 presents an illustration of the "HDB3 Decoder" at work, with two separate "Zero Suppression"
patterns, in the incoming "Dual Rail Data Stream".
FIGURE 20. AN EXAMPLE OF HDB3 DECODING
0 0
0
V
Line Signal
B
0 0
V
RxCLK
RPOS
RNEG
Data
0
1
0
1
1
0
0
0
0
0
1
1
1
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the "HDB3
Line Code" format, or if the "HDB3 Decoder" detects a
string of 4 (or more) "0's" in the incoming line signal, then
the "HDB3 Decoder" will flag this event as a "Line Code
Violation" by pulsing the "LCV" output pin "high".
3.4.3
0
1
1
0
1
1
0
0
1
1
0
0
0
0
each Channel of the chip) by either of the following
means.
If the XRT73L03 Device is configured to operate in
the "Host" Mode
Configuring Channel(n)
Configuring the HDB3/B3ZS Decoder
The user can enable the "HDB3/B3ZS Decoder"
block within Channel(n) by writing a "0" into the
The XRT73L03 Device permits the user to enable or
disable the "HDB3/B3ZS Decoder" blocks (within
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XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
"ENDECDIS(n)" bit-field within Command Register
CR2-(n), as illustrated below.
COMMAND REGISTER CR2-(N)
D4
D3
D2
D1
D0
Rserved
ENDEC_DIS
ALOSDIS(n)
DLOSDIS(n)
REQEN(n)
X
0
X
X
1
If the XRT73L03 Device is configured to operate in
the "Hardware" Mode
Command Register 0 (or Command Register 8) to
"1".
The user can globally enable all "HDB3/B3ZS Decoder" blocks (within the XRT73L03 device) by pulling the
"ENDEC_DIS" input pin "low". Conversely, the user
can globally disable all "HDB3/B3ZS Decoder" blocks
(within the XRT73L03 device) and configure the device to transmit and receive in an AMI format by pulling the "ENDEC_DIS" input pin "high".
Conversely, if the channel (within the XRT73L03 device) determines that the incoming line signal has
been restored (e.g., there is sufficient amplitude and
pulses in the incoming line signal); then it will clear
the LOS condition by toggling its respective RLOS(n)
output pin "low" and setting its corresponding
"RLOS(n)" bit-field to "0".
3.5 LOS DECLARATION/CLEARANCE
1. The amplitude of the incoming line signal via the
RTIP and RRing inputs; and
In general, the LOS Declaration/Clearance scheme
that is employed within the XRT73L03 is based upon
ITU-T Recommendation G.775 for both E3 and DS3
applications. The LOS Declaration and Clearance
criteria that the XRT73L03 device uses for each of
these modes (e.g., E3 and DS3/STS-1) are presented below.
2. The number of pulses, detected (in the incoming
line signal) within a certain amount of time.
3.5.1 The LOS Declaration/Clearance Criteria
for E3 Applications
If a given channel (within the XRT73L03 device) determines that the incoming line signal is missing (either due to insufficient amplitude or a lack of pulses in
the incoming line signal), then it will declare a "Loss
of Signal" (LOS) condition. The channel (within the
XRT73L03 device) declares the LOS condition by
toggling its respective RLOS(n) output pin "high", and
by setting its corresponding "RLOS(n)" bit field, within
When the XRT73L03 device is operating in the "E3
Mode", a given channel will declare an LOS Condition
if its "receive line" signal amplitude drops to -35dB or
below. Further, the channel will clear the LOS Condition if its "receive line" signal amplitude rises back up
to -15dB or above. Figure 21 presents an illustration
that depicts the signal levels at which each channel
(within the XRT73L03 device) will declare and clear
LOS.
Each channel (within the XRT73L03 device) contains
circuitry that will monitor the following two parameters
associated with the incoming line signals.
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FIGURE 21. ILLUSTRATION OF THE SIGNAL LEVELS THAT THE XRT73L03 DEVICE WILL DECLARE AND CLEAR
LOS
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
Timing Requirements associated with Declaring
and Clearing the LOS Indicator
the actual time the LOS condition occurred. Further,
the channel will clear the LOS indicator within 10 to
255 UI after restoration of the incoming line signal.
Figure 22, illustrates the LOS Declaration and Clearance behavior, in response to first, the "Loss of Signal" event and then afterwards, the restoration of the
signal.
The XRT73L03 device was designed to meet the ITUT G.775 specification timing requirements for declaring and clearing the LOS indicator. In particular, a
channel (within the XRT73L03 device) will declare an
LOS, between 10 and 255 UI (or E3 bit-periods) after
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ADVANCED CONFIDENTIAL
REV. A1.0.7
FIGURE 22. THE BEHAVIOR THE LOS OUTPUT INDICATOR, IN RESPONSE TO THE LOSS OF SIGNAL, AND THE RESTOSIGNAL
RATION OF
Actual
O
of LOS Condition
Line Signal
is
R
d
RxIN
10 UI
255 UI
Time Range for
LOS
D l
i
10 UI
255 UI
RLOS Output Pin
0 UI
0 UI
G.775
Time Range
fLOS
C
G.775
3.5.2 The LOS Declaration/Clearance Criteria
for DS3 and STS-1 Applications
1. The Analog LOS (ALOS) Declaration/Clearance
Criteria
When the XRT73L03 device is operating in the DS3
or STS-1 Mode, then each channel (within the
XRT73L03 device) will declare and clear LOS based
upon the following two criteria.
A channel (within the XRT73L03 device) will declare
an "Analog LOS (ALOS(n)) Condition if the amplitude
of the incoming line signal drops below a specific amplitude as defined by the voltage at the LOSTHR input pin, and by whether the Receive Equalizer is enabled or not.
Analog LOS (ALOS) Declaration/Clearance Criteria
Table 5 presents the various voltage levels at the
LOSTHR input pin, the state of the Receive Equalizer,
and the corresponding ALOS (Analog LOS) threshold
amplitudes.
Digital LOS (DLOS) Declaration/Clearance Criteria
In the DS3 Mode, the LOS output (RLOS) is simply
the logical "OR" of the ALOS and DLOS states. The
Declaration/Clearance criteria for ALOS and DLOS
are discussed below.
TABLE 5: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION
REQEN SETTING
LOSTHR SETTING
SIGNAL LEVEL TO
DECLARE ALOS
SGNAL LEVEL TO CLEAR
ALOS
DS3
1
0
<55mV
>220mV
1
1
<22mV
>90mV
0
0
<35mV
>155mV
0
1
<17mV
>70mV
1
0
<75mV
>270mV
1
1
<25mV
>115mV
0
0
<55mV
>210mV
0
1
<20mV
>90mV
STS-1
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NOTE: There is approximately a 2dB hysteresis in the
received signal level that exists between declaring and
clearing ALOS(n), in order to prevent "chattering" in the
RLOS(n) output signal.
Declaring ALOS
A channel(n) (within the XRT73L03 device) will declare ALOS(n) whenever the amplitude of the receive
line signal falls below the "Signal Level to Declare
ALOS" levels specified in Table 5.
Monitoring the State of ALOS(n)
If the XRT73L03 device is operating in the "Host"
Mode, then the user can poll or monitor the state of
ALOS(n), within Channel(n) by reading in the contents of Command Register CR0. The bit-field of
Command Register 0 is presented below.
Clearing ALOS(n)
A channel(n) (within the XRT73L03 device) will clear
ALOS(n) whenever the amplitude of the receive line
signal increases above the "Signal Level to Clear
ALOS" levels specified in Table 5.
COMMAND REGISTER CR0-(N)
D4
D3
D2
D1
D0
RLOL(n)
RLOS(n)
ALOS(n)
DLOS(n)
DMO(n)
Read Only
Read Only
Read Only
Read Only
Read Only
For debugging purposes, it may be useful to be able
to disable the ALOS Detector, within the XRT73L03
device. If the XRT73L03 device is operating in the
"Host" Mode, then the user can disable the ALOS Detector, (within Channel(n)) by writing a "1" into the
"ALOSDIS(n)" bit-field, within Command Register
CR2; as depicted below.
If the "ALOS(n)" bit-field contains a "1", then the corresponding Channel(n) is currently declaring an
ALOS condition. Conversely, if the ALOS(n) bit-field
contains a "0", then the channel is not currently declaring an ALOS condition.
Disabling the ALOS Detector
COMMAND REGISTER CR2-(N)
D4
D3
D2
D1
D0
Reserved
ENDECDIS(n)
ALOSDIS(n)
DLOSDIS(n)
REQEN(n)
X
X
1
X
X
2. The Digital LOS (DLOS) Declaration/Clearance
Criteria
tents of Command Register CR0. The bit-field of
Command Register CR0 is presented below.
COMMAND REGISTER CR0-(N)
A given channel(n) (within the XRT73L03 device) will
declare a Digital LOS (DLOS(n)) condition if the
XRT73L03 device detects 160±32 or more consecutive "0s" in the incoming data.
The channel (within the XRT73L03 device) will clear
DLOS if it detects four consecutive sets of 32 bit-periods, each of which containing at least 10 "1s" (e.g.,
average pulse density of greater than 33%).
D4
D3
D2
D1
D0
RLOL(n)
RLOS(n)
ALOS(n)
DLOS(n)
DMO(n)
Read Only Read Only Read Only Read Only Read Only
If the “DLOS(n)” bit-field contains a “1”, then the corresponding channel(n) is currently declaring a DLOS
condition. Conversely, if the DLOS(n) bit-field contains a “0”, then the channel(n) is currently declaring
the DLOS condition.
Monitoring the State of DLOS
If the XRT73L03 device is operating in the "Host"
Mode, then the user can poll or monitor the state of
DLOS(n), within Channel(n) by reading in the con-
Disabling the DLOS Detector
For debugging purposes, it is useful to be able to disable the DLOS(n) detector, within the XRT73L03 device. If the XRT73L03 device is operating in the
“Host” Mode, the user can disable the DLOS Detector, (within Channel(n)) by writing a “1” into the
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REV. A1.0.7
“DLOSDIS(n)” bit-field, within Command Register
CR2, as depicted below.
COMMAND REGISTER CR2-(N)
D4
D3
D2
D1
D0
Reserved
ENDECDIS(n)
ALOSDIS(n)
DLOSDIS(n)
REQEN(n)
X
X
X
1
X
NOTE: Setting both the "ALOSDIS(n)" and "DLOSDIS(n)"
bit-fields to "1" will disable LOS Declaration by Channel(n).
This feature is available whenever XRT73L03 device
is operating in the Host Mode or Hardware Mode.
The approach for configuring the "MUTing upon LOS"
feature for both the Hardware and Host Modes are
presented below.
3.5.3 Muting the Recovered Data while the LOS
is being Declared
In some applications it is not desirable for a channel
(within the E3/DS3/STS-1 LIU) to recover data and
route it to the "Receiving Terminal", while the channel
is declaring an LOS condition. Consequently, the
XRT73L03 device includes an "LOS Muting" feature.
This feature (if enabled) will cause a given channel
(within the XRT73L03 device) to halt transmission of
the recovered data (to the Receiving Terminal) while
the LOS condition is "true". In this case, the RPOS(n)
and RNEG(n) output pins will be forced to "0". Once
the LOS condition has been cleared, then the channel(n) (within the XRT73L03 device) will resume normal transmission of the recovered data to the "Receiving Terminal."
Enabling and Disabling the "MUTing upon LOS"
feature if the XRT73L03 is operating in the Hardware Mode.
The "MUTing upon LOS" featureis enabled by pulling
the "LOSMUTEN" output pin (pin 78) "high". This enables the "MUTEing upon LOS" feature globally, for
all channels within the XRT73L03 device.
Enabling and Disabling the "MUTing upon LOS"
feature if the XRT73L03 is operating in the Host
Mode.
The "MUTing upon LOS" feature for each Channel
can be enabled by writing a "1" into the "LOSMUT(n)"
bit-field, within Command Register 3, as shown below.
COMMAND REGISTER CR3-(N)
D4
D3
D2
D1
D0
SR/(DR)_(n)
LOSMUT(n)
RxOFF(n)
RxClk(n)INV
Reserved
X
1x
x
x
x
NOTE: This step only enables the "MUTing upon LOS" feature within Channel(n).
3.6.1 Routing "Dual-Rail" Format Data to the
Receiving Terminal Equipment
3.6 ROUTING THE RECOVERED TIMING AND DATA
INFORMATION TO THE "RECEIVING TERMINAL
EQUIPMENT"
Whenever a channel (within the XRT73L03 device)
delivers dual-rail format to the Terminal Equipment, it
does so via the following signals.
Each channel, within the XRT73L03 device, ultimately
takes the Recovered Timing and Data information,
converts it into CMOS levels and routes it to the Receiving Terminal Equipment via the RPOS(n),
RNEG(n) and RxClk(n) output pins.
• RPOS(n)
• RNEG(n)
• RxClk(n)
Figure 23 presents an illustration of the typical interface for the transmission of data in a "Dual-Rail" Format from the Receive Section of a channel (within the
XRT73L03 device) to the "Receiving Terminal Equipment"
Each channel, within the XRT73L03 device can "deliver" the recovered data and clock information (to the
"Receiving Terminal") in either a "Single-Rail" or "Dual-Rail" format. Each of these methods are discussed
below.
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ADVANCED CONFIDENTIAL
REV. A1.0.7
.
FIGURE 23. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUALRAIL FORMAT, FROM THE "RECEIVE SECTION" OF THE XRT73L03 DEVICE" TO THE RECEIVING TERMINAL EQUIPMENT
Terminal Equipment
(E3/DS3 or STS-1
Framer
RxPOS
RPOS
RxNEG
RNEG
RxClk
RxClk
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
The manner that a given channel transmits "DualRail" data (to the Receiving Terminal Equipment) is
described below and is illustrated in Figure 24. Each
channel(n) (within the XRT73L03 device) will typically
update the data (on the RPOS(n) and RNEG(n) output pins) on the rising edge of RxClk(n).
FIGURE 24. ILLUSTRATION ON HOW THE XRT73L03 DEVICE OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT
PINS
RPOS
RNEG
RxClk
Each channel (within the XRT73L03 device) permits
the user to invert the RxClk(n) signals, with respect to
the "delivery" of the "RPOS(n)" and RNEG(n)" output
data to the "Receiving Terminal Equipment". This
feature may be useful for those customer whose "Receiving Terminal Equipment" logic design is such that
the RPOS(n) and RNEG(n) data must be sampled on
the rising edge of RxClk(n). Figure 25 illustrates the
behavior of the RPOS(n), RNEG(n), and RxClk(n)
signals, when the RxClk(n) signal has been inverted.
RxClk(n), is the Recovered Clock signal, from the incoming "Received" line signal. As a result, these
clock signals are typically 34.368 MHz for E3 applications; 44.736 MHz for DS3 applications, and 51.84
MHz for SONET STS-1 applications.
In general, if a given channel (within the XRT73L03
device) received a "positive-polarity" pulse in the incoming line signal (via the RTIP(n) and RRing(n) input pins), then the channel will pulse its corresponding RPOS(n) output pin "high". Conversely, if the
channel received a "negative-polarity" pulse in the incoming line signal (via the RTIP(n) and RRing(n) input pins), then the channel(n) will pulse its corresponding RNEG(n) output pin "high".
In the “Hardware Mode”
Setting the RxClkINV pin (pin 62) “high” will result in
all channels of the XRT73L03 to output the recovered
data on RPOS(n) and RNEG(n) on the “falling” edge
of RxClk(n). Setting this pin “low” will result in the re-
Inverting the RxClk(n) outputs
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covered data on RPOS(n) and RNEG(n) to ouput on
the “rising” edge of RxClk(n).
FIGURE 25. ILLUSTRATION OF THE BEHAVIOR OF THE RPOS, RNEG, AND RXCLK SIGNALS, WHEN RXCLK IS
INVERTED
RPOS
RNEG
RxClk
Inverting the RxClk(n) Signals via the Host Mode
To invert RxClk(n), associated with Channel(n), write
a "1" into the "RxClk(n)INV" bit-field within Command
Register CR-3.
In order to configure a channel(n) (within the
XRT73L03 device) to invert the RxClk(n) output signal; the user must be operating the XRT73L03 device
in the "Host" Mode.
COMMAND REGISTER CR3-(N)
D4
D3
D2
D1
D0
SR/(DR)_(n)
LOSMUT(n)
RxOFF(n)
RxClk(n)INV
Reserved
X
X
X
1
X
Inverting the RxClk(n) signals via the Hardware
Mode
in the XRT73L03 device), to the "Receiving Terminal
Equipment", do the following.
Setting the "RxClkINV" input pin (pin 62) "high" will invert all the RxClk(n) output signals.
If the XRT73L03 Device is operating in the "Host"
Mode
3.6.2 Routing Single-Rail Format (Binary Data
Stream) data to the Receive Terminal Equipment
To configure Channel(n) to output "Single-Rail" data
to the Terminal Equipment, write a "1" into the "SR/
(DR)_(n)" bit-field, within Command Register CR3(n); as depicted below.
To route "Single-Rail" format data (e.g., a binary data
stream), from the Receive Section of a channel (with-
COMMAND REGISTER CR3-(N)
D4
D3
D2
D1
D0
SR/(DR)_(n)
LOSMUT(n)
RxOFF(n)
RxClk(n)INV
Reserved
1
X
X
X
X
To configure the XRT73L03 device to output "SingleRail" data from the Receive Sections of all channels
by pulling the "SR/(DR)" pin (pin 57) to VDD.
The configured channel (within the XRT73L03 device) will output "Single-Rail" data to the "Receiving
Terminal Equipment" via its corresponding RPOS(n)
and RxClk(n) output pins, as illustrated below in Figure 26 and Figure 27.
NOTE: When the XRT73L03 device is operating in the
Hardware Mode, the setting of the "SR/(DR)" input pin
applies globally to all three channels.
If the XRT73L03 Device is operating in the Hardware Mode
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ADVANCED CONFIDENTIAL
REV. A1.0.7
.
FIGURE 26. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A "SINGLE-RAIL FORMAT", FROM THE "RECEIVE SECTION OF THE XRT73L03 DEVICE" TO THE RECEIVING
TERMINAL EQUIPMENT
Terminal Equipment
(E3/DS3 or STS-1
Framer
RxPOS
RPOS
RxNEG
RNEG
RxClk
RxClk
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
FIGURE 27. ILLUSTRATION OF THE BEHAVIOR OF THE RPOS AND RXCLK OUTPUT SIGNALS, WHILE THE
XRT73L03 DEVICE IS TRANSMITTING "SINGLE-RAIL" DATA TO THE RECEIVING TERMINAL EQUIPMENT
RPOS
RxClk
NOTE: The RNEG(n) output pin will be internally tied to
Ground, whenever this feature is implemented.
The user can implement the "RxOFF(n)" by the following means:
3.7 SHUTTING OFF THE RECEIVE SECTION
If the XRT73L03 Device is operating in the "Hardware" Mode
The XRT73L03 Device permits the user to shut off
the Receive Section of each channel. This feature
may come in handy in some "redundant system designs". Particularly, in those designs where the Receive Termination within the Secondary LIU Line
Card, has been "switched-out" and is not receiving
any traffic in parallel with the "Primary Line Card". In
this case, having the LIU (on the "Secondary Line
Card) consume the normal amount of current is a
dreadful waste of power. Hence, this feature can permit the user to power down the "Receive Section" of
the LIUs on the Secondary Line Card, which will reduce their power consumption by approximately 80%.
Configuring Channel(n)
The user can shut off the Receive Section of Channel(n) (where “n”= 1,2 or 3, within the XRT73L03 device) by pulling the "RxOFF(n)" input pin (pin 15,19 or
70 rsepectively) "high". Conversely, the user can turn
on the Receive Section of Channel(n) by pulling the
"RxOFF(n)" input pin to "low".
If the XRT73L03 Device is operating in the "Host"
Mode
The user can shut off the Receive Section of Channel(n) (within the XRT73L03 device) by writing a "1"
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into the "RxOFF(n)" bit-field (within Command Register CR3-(n)), as illustrated below.
COMMAND REGISTER CR3-(N)
D4
D3
D2
D1
D0
SR/(DR)_(n)
LOSMUT(n)
RxOFF(n)
RxClk(n)INV
Reserved
X
X
1
X
X
Conversely, the user can turn on the Receive Section
of Channel(n) by writing a "0" into the "RxOFF(n)" bitfield, within Command Register CR3-(n).
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4.0 DIAGNOSTIC FEATURES OF THE XRT73L03
DEVICE
"Transmitting Terminal Equipment" will transmit clock
and data into this channel via the TPData(n), TNData(n), and TxClk(n) input pins. This data will be processed through the "Transmit Clock Duty Cycle Adjust PLL" and the "HDB3/B3ZS Encoder". Finally,
this data will be output to the line via the TTIP(n) and
TRing(n) output pins. Additionally, this data (which is
being output via the TTIP(n) and TRing(n) output
pins) will also be looped back into the "Attenuator/Receive Equalizer Block". As a consequence, this data
will be processed through the entire "Receive Section" of the channel. After this "post-loop-back" data
has been processed through the "Receive Section" it
will be output, to the "Near-End Receiving Terminal
Equipment" via the RPOS(n), RNEG(n) and RxClk(n)
output pins.
The XRT73L03 device supports equipment diagnostic activities by supporting the following loop-back
modes within each channel (within the XRT73L03 device).
• Analog Local Loop-back.
• Digital Local Loop-back
• Remote Loop-back
The next two sections briefly discussed each of these
Loop-back schemes.
NOTE: In this data sheet we use the convention that Channel(n) refers to either channel 1, 2 or 3. Similarly, specific
input and output pins will use this convention to denote
which channel it is associated with.
Figure 28 illustrates the path that the data takes (within a given channel of the XRT73L03 device), when
the channel is configured to operate in the "Analog
Local Loop-back" Mode.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When a given channel (within the XRT73L03 device)
is configured to operate in the "Analog Local Loopback" Mode, the channel will ignore any signals that
are input to its RTIP(n) and RRing(n) input pins. The
FIGURE 28. ILLUSTRATION OF A CHANNEL (WITHIN THE XRT73L03 DEVICE) OPERATING IN THE ANALOG LOCAL
LOOP-BACK MODE
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
AGC/
Equalizer
REQEN(n)
Clock
Recovery
Slicer
Peak
Detector
Data
Recovery
LOS Detector
LOSTHR(n)
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
SClk
CS
LCV(n)
ENDECDIS
SDI
SDO
RNEG(n)
Serial
Processor
Interface
RLOS(n)
Analog Local
Loopback Path
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TRing(n)
TxLEV(n)
TxOFF(n)
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TxClk(n)
MTIP(n)
Device
Monitor
MRing(n)
DMO(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in
"Harware" Mode.
The user can configure a given channel, (within the
XRT73L03 device) to operate in the Analog Local
Loop-back Mode, by employing either one of the following two steps
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a. If the XRT73L03 device is operating in the
"Host" Mode
(pin 34, 54 or 42) "high" and the "RLB(n)" input pin
(pin 35, 53 or 43) "low".
NOTE: In this data sheet we use the convention that Channel(n) refers to either channel 1, 2 or 3. See Table 2 for a
description of Command Registers and Addresses for the
different channels.
4.2 THE DIGITAL LOCAL LOOP-BACK MODE.
When a given channel, within the XRT73L03 device is
configured to operate in the "Digital Local Loop-back"
Mode, the channel will ignore any signals that are input to the RTIP and RRing input pins. The "Transmitting Terminal Equipment" will transmit clock and data
into the XRT73L03 device via the "TPData", "TNData"
and "TxClk" input pins. This data will be processed
through the "Transmit Clock Duty Cycle Adjust" PLL
and the "HDB3/B3ZS Encoder" block. At this point,
this data will be looped back to the "HDB3/B3ZS Decoder" block. After this "post-loop back" data has
been processed through the "HDB3/B3ZS Decoder"
block, it will be output to the "Near-End" Receiving
Terminal Equipment" via the RPOS, RNEG and RxClk output pins.
To configure Channel (n) to operate in the "Analog
Local Loop-Back" Mode, write a "1" into the "LLB(n)"
bit-field and a "0" into the "RLB(n)" bit-field within
Command Register CR4, as illustrated below.
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X
STS-1/DS3_ Ch(n)
E3_ Ch(n)
LLB(n)
RLB(n)
X
X
X
1
0
b. If the XRT73L03 device is operating in the
"Hardware" Mode
Figure 29 illustrates the path that the data takes (within the XRT73L03 device), when the chip is configured
to operate in the "Digital Local Loop-back" Mode.
To configure Channel (n) to operate in the "Analog
Local Loop-back" Mode, set the "LLB(n)" input pin
FIGURE 29. ILLUSTRATION OF THE "DIGITAL LOCAL LOOP-BACK" PATH WITHIN A GIVEN CHANNEL (OF THE
XRT73L03 DEVICE)
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
AGC/
Equalizer
REQEN(n)
Peak
Detector
SDI
SClk
CS
Data
Recovery
LOS Detector
LOSTHR(n)
SDO
Clock
Recovery
Slicer
Serial
Processor
Interface
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
Digital Local
Loopback Path
RLOS(n)
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TRing(n)
TxLEV(n)
TxOFF(n)
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TxClk(n)
MTIP(n)
Device
Monitor
MRing(n)
DMO(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in
"Harware" Mode.
The user can configure a channel (within the
XRT73L03 device) to operate in the "Digital Local
Loop-back" Mode, by employing either one of the following two-steps:
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a. If the XRT73L03 device is operating in the
"Host" Mode
When a given channel (within the XRT73L03 device)
is configured to operate in the Remote Loop-back
Mode, the channel will ignore any signals that are input to the TPData and TNData input pins. The channel will receive the incoming line signal, via the RTIP
and RRing input pins. This data will be processed
through the entire Receive Section (within the channel) and will be output to the "Receive Terminal
Equipment" via the RPOS, RNEG and RxClk output
pins. Additionally, this data will also be internally
looped back into the "Pulse-Shaping" block within the
"Transmit Section". At this point, this data will be routed through the remainder of the "Transmit Section" of
the channel and will be transmitted out onto the line
via the TTIP(n) and TRing(n) output pins.
To configure Channel (n) to operate in the "Digital Local Loop-Back" Mode, write a "1" into both the "LLB"
and "RLB" bit-fields within Command Register CR4(n), as illustrated below.
COMMAND REGISTER CR4-(N)
D4
X
D3
D2
D1
D0
STS-1/DS3_Ch(n) E3_Ch(n) LLB(n)
X
X
RLB(n)
1
X
1
b. If the XRT73L03 device is operating in the
"Hardware" Mode.
To configure Channel (n) to operate in the "Digital Local Loop-back" Mode, pull both the "LLB" input pin
(pin 34, 54 or 42) and the "RLB" input pin (pin 35, 53
or 43) "high".
Figure 30 illustrates the path that the data takes (within the configured channel of the XRT73L03 device),
when the chip is configured to operate in the "Remote
Loop-back" Mode.
4.3 THE REMOTE LOOP-BACK MODE
FIGURE 30. ILLUSTRATION OF THE "REMOTE LOOP-BACK" PATH, WITHIN A GIVEN CHANNEL (OF THE XRT73L03
DEVICE)
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
AGC/
Equalizer
REQEN(n)
Clock
Recovery
Slicer
Peak
Detector
Data
Recovery
LOS Detector
LOSTHR(n)
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
SClk
CS
LCV(n)
ENDECDIS
SDI
SDO
RNEG(n)
Serial
Processor
Interface
RLOS(n)
Remote
Loopback Path
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TRing(n)
TxLEV(n)
TxOFF(n)
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TxClk(n)
MTIP(n)
Device
Monitor
MRing(n)
DMO(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in "Host" Mode and redefined in
"Harware" Mode.
The user can configure a channel (within the
XRT73L03 device) to operate in the "Remote Loop-
back" Mode, by employing either one of the following
two steps
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The user can shut off the Transmit Driver (within
Channel(n)) by toggling the "TxOFF(n)" input pin (pin
88, 87 or 86) "high". Conversely, the user can turn on
the "Transmit Driver" by toggling the "TxOFF(n)" input
pin "low".
a. If the XRT73L03 device is operating in the
"Host" Mode
To configure Channel (n) to operate in the "Remote
Loop-back" Mode, write a "1" into the "RLB" bit-field,
and a "0" into the "LLB" bit-field, within Command
Register CR4, as illustrated below.
When the XRT73L03 device is operating in the
"Host" Mode
COMMAND REGISTER CR4-(n)
D4
X
D3
D2
STS-1/DS3_Ch(n) E3_Ch(n)
X
X
D1
D0
LLB(n)
RLB(n)
0
1
X
Shutting off the Transmitter of Channel(n)
The user can turn off the Transmit Driver (within
Channel(n)) by setting the "TxOFF(n)" bit-field (within
Command Register CR1-(n)) to "1", as illustrated below.
b. If the XRT73L03 device is operating in the
"Hardware" Mode
COMMAND REGISTER CR1-(n)
D4
To configure Channel(n) to operate in the "Remote
Loop-back" Mode, pull both the "RLB" input pin (pin
35, 53 or 43) to "high", and the "LLB" input pin (pin
34, 54 or 42) to "low".
D3
TxOFF(n) TAOS(n)
1
4.4 TXOFF FEATURES
X
D2
TxClkINV(n)
X
D1
D0
TxLEV(n) TxBIN(n)
X
X
Conversely, writing a "0" into this bit-field enables the
"Transmit Driver within Channel(n).
The XRT73L03 device permits the user to shut off the
"Transmit Section of each Channel (within the
XRT73L03 device). When this feature is invoked the
Transmit Section (of the configured channel) will be
shut-off, and the Transmit Output signals (e.g.,
TTIP(n) and TRing(n)) will be tri-stated. This feature
can come in handy for system redundancy conditions
or during diagnostic testing. The user can activate
this feature by either of the following ways.
NOTE: In order to permit a system (designed for redundancy) to quickly shut-off a defective line card and turn-on
the “back-up” line card, the XRT73L03 device was designed
such that either Transmitter can quickly be turned-on or
turned-off by toggling the “TxOFF(n)” input pins. This
approach is much quicker then setting the “TxOFF(n)” bitfields via the Microprocessor Serial Interface.
Table 6 presents a “Truth Table” which relates the setting of the “TxOFF” external pin and bit-field (for a
channel) to the state of the Transmitter. Please note
that this table applies to all Channels of the
XRT73L03.
When the XRT73L03 device is operating in the
"Hardware" Mode
Shutting off the Transmitter of Channel(n)
TABLE 6: THE RELATIONSHIP BETWEEN THE “TXOFF” INPUT PIN, THE “TXOFF” BIT FIELD AND THE STATE OF THE
TRANSMITTER
STATE OF THE “TXOFF” STATE OF THE “TXOFF”
INPUT PIN
BIT FIELD
STATE OF THE TRANSMITTER
LOW
0
ON (Transmitter is Active)
LOW
1
OFF (Transmitter is Tri-Stated)
High
0
OFF (Transmitter is Tri-Stated)
HIGH
1
OFF (Transmitter is Tri-Stated)
To control the state of each transmitter, via the Microprocessor Serial interface connect the “TxOFF(n)” input pins to GND.
The Transmit Drive Monitor permits the user to monitor the line, in the Transmit Direction, for the occurrence of fault conditions such as a short circuit (on
the line), or a defective Transmit Drive in the
XRT73L03 device or even another LIU device.
4.5 THE TRANSMIT DRIVE MONITOR FEATURES
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(through a 270 Ohm resistor connected in series).
Such an approach is illustrated in Figure 31.
The user activates the Transmit Drive Monitor, within
Channel(n) by connecting the MTIP(n) pin (pin 117,
94 or 105) to the TTIP(n) line (through a 270 Ohm resistor connected in series); and by connecting the
MRing(n) pin (pin 116, 95 or 104) to the TRing(n) line
FIGURE 31. ILLUSTRATION OF THE XRT73L03 DEVICE EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES
J1
BNC
TTIP(n)
R1 = 31.6Ω
TRing(n)
TxPOS(n)
TxNEG(n)
TxLineClk(n)
R2 = 31.6Ω
TPData(n)
TNData(n)
TxClk(n)
1:1
MTIP(n)
R3 = 270Ω
MRing(n)
R4 = 270Ω
Channel (n)
Only One Channel Shown
When the Transmit Drive Monitor circuitry (within a
given line) is connected to the line, as illustrated in
31 , then it will monitor the line for transitions. As
long as the Transmit Drive Monitor circuitry detects
transitions on the line (via the MTIP(n) and MRing(n)
pins), then it will keep the DMO (Drive Monitor Output) signal "low". However, if the Transmit Drive Monitor circuit detects no transitions on the line for 128(32
TxClk periods, then the DMO (Drive Monitor Output)
signal will toggle "high".
The user can configure Channel(n) (within the
XRT73L03 device) to transmit an "All Ones" pattern
by toggling the "TAOS(n)" input pin (pin 2, 85 or 84)
"high". Conversely, the user can terminate the "All
Ones" pattern by toggling the "TAOS(n)" input pin
"low".
NOTE: The user does not have to use the Transmit Drive
Monitor circuit in order to operate the Transmit Section of
the XRT73L03 device. This is purely a diagnostic feature.
The user can configure Channel(n) (within the
XRT73L03 device) to transmit an "All Ones" pattern
by writing to Command Register CR1-(n) and setting
the "TAOS(n)" bit-field (bit D3) to "1", as illustrated below.
When the XRT73L03 device is operating in the
"Host" Mode.
Configuring a Channel
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE
The XRT73L03 device permits the user to command
either channel to transmit an "All Ones" pattern onto
the line by toggling a single input pin, or by setting a
single bit-field (within one of the Command Registers)
to "1". Please note that when this feature is activated,
the Transmit Section of the configured channel (within
the XRT73L03 device) will overwrite the "Terminal
Equipment" data with this "All Ones" pattern. The user can activate this feature by either of the following
ways.
COMMAND REGISTER CR1-(N)
D4
TxOFF(n) TAOS(n)
0
1
D2
TxClkINV(n)
X
D1
D0
TxLEV(n) TxBIN(n)
X
X
Conversely, the user can terminate the "All Ones" pattern by writing to Command Register, CR1-(n) and
setting the "TAOS(n)" bit-field (D3) to "0".
When the XRT73L03 device is operating in the
"Hardware" Mode.
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ADVANCED CONFIDENTIAL
REV. A1.0.7
5.0 THE MICROPROCESSOR SERIAL INTERFACE
1. The description of the Command Registers.
2. A description on how to use the Microprocessor
Serial Interface.
The XRT73L03 DS3/E3/STS-1 Line Interface Unit IC
permits the user to have access to the "on-chip"
Command Registers. Through these Command Registers, the user can configure the XRT73L03 device
into a wide-variety of modes. This section discusses
the following:
5.1 DESCRIPTION OF THE COMMAND REGISTERS
Table 2 lists the Command Registers, their Addresses, and their bit-formats.
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TABLE 7: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
D0
CHANNEL 1
0x00
CR0-1
RO
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
0x01
CR1-1
R/W
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
0x02
CR2-1
R/W
Reserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
0x03
CR3-1
R/W
SR/DR_1
LOSMUT1
RxOFF1
RxClk1INV
Reserved
0x04
CR4-1
R/W
Reserved
STS-1/DS3
Channel 1
E3_CH1
LLB1
RLB1
0x05
CR5-1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x06
CR6-1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x07
CR7-1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
CHANNEL 2
0x08
CR0-2
RO
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
0x09
CR1-2
R/W
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0x0A
CR2-2
R/W
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
0x0B
CR3-2
R/W
SR/DR_2
LOSMUT2
RxOFF2
RxClk2INV
Reserved
0x0C
CR4-2
R/W
Reserved
STS-1/DS3
Channel 2
E3_CH2
LLB2
RLB2
0x0D
CR5-2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x0E
CR6-2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x0F
CR7-2
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
CHANNEL 3
0x10
CR0-3
RO
RLOL3
RLOS3
ALOS3
DLOS3
DMO3
0x11
CR1-3
R/W
TxOFF3
TAOS3
TxClkINV3
TxLEV3
TxBIN3
0x12
CR2-3
R/W
Reserved
ENDECDIS3
ALOSDIS3
DLOSDIS3
REQEN3
0x13
CR3-3
R/W
SR/DR_3
LOSMUT3
RxOFF3
RxClk3INV
Reserved
0x14
CR4-3
R/W
Reserved
STS-1/DS3
Channel 3
E3_CH3
LLB3
RLB3
0x15
CR5-3
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x16
CR6-3
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x17
CR7-3
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
The "role/meaning" associated with each of these bit-
fields is presented below.
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Address
This "Read-Only" bit-field indicates whether or not the
"Analog LOS Detector", within Channel(n), is currently declaring an LOS condition.
The register addresses are presented in the "hexadecimal" format.
This bit-field will be set to "0" if the "Analog LOS Detector", within Channel(n), is NOT (currently) declaring an LOS condition. Conversely, this bit-field will be
set to "1" if the "Analog LOS Detector", within Channel(n), is currently declaring an LOS condition.
Type:
The Command Registers are either "Read-Only"
(RO) type of registers, or are "Read/Write" (R/W) type
of registers. Each channel of the XRT73L03 has
eight command registers CR0-(n) through CR7-(n)
where (n) = 1, 2 or 3. The associated addresses for
each channel are presented in Table 2.
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the "Analog LOS" or the "Digital LOS" detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes
NOTE: The default value for each of the bit-fields, within
these register will be "0".
Bit D1 - DLOS1 (Digital Loss of Signal Status Channel(n))
Description of Bit-Fields for each Command Register
5.1.1
This "Read-Only" bit-field indicates whether or not the
"Digital LOS Detector", within Channel(n), is currently
declaring an LOS condition.
Command Register - CR0-(n)
The bit-format and default values for Command Register CR0-(n) are listed below.
This bit-field will be set to "0" if the "Digital LOS Detector", within Channel(n), is NOT (currently) declaring an LOS condition. Conversely, this bit-field will be
set to "1" if the "Digital LOS Detector", within Channel(n), is currently declaring an LOS condition.
COMMAND REGISTER CR0-(N)
D4
D3
D2
D1
D0
RLOL
RLOS
ALOS
DLOS
DMO
1
1
1
1
1
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the "Analog LOS" or the "Digital LOS" detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes.
The function of each of these bit-fields are presented
below.
Bit D0 - DMO (Drive Monitor Output Status - Channel(n))
Bit D4 - RLOL1 (Receive Loss of Lock Status Channel(n))
This "Read-Only" bit-field reflects the status of the
DMO output pin.
This "Read-Only" bit-field reflects the "lock" status of
the "Clock Recovery Phase-Locked-Loop", within
Channel(n) of the XRT73L03 device.
5.1.2 Command Register CR1
The bit-format and default values for Command Register CR1-(n) are listed below.
This bit-field will be set to "0" if the "Clock Recovery
PLL" (within Channel(n)) is in "lock" with the incoming
line signal. Conversely, this bit-field will be set to "1" if
the "Clock Recovery PLL" (within Channel(n)) is "out
of lock" with the incoming line signal.
COMMAND REGISTER CR1-(N)
D4
D3
TxOFF(n) TAOS(n)
Bit D3 - RLOS1 (Receive Loss of Signal Status Channel(n))
0
This "Read-Only" bit-field indicates whether or not the
Receiver, within Channel(n) is currently declaring an
LOS (Loss of Signal) Condition.
0
D2
TxClkINV(n)
0
D1
D0
TxLEV(n) TxBIN(n)
0
0
The function of each of these bit-fields are presented
below.
Bit D4 - TxOFF(n) (Transmitter OFF - Channel(n))
This bit-field will be set to "0" if Channel(n) is not (currently) declaring the LOS Condition. Conversely, this
bit-field will be set to "1" if Channel(n) is declaring an
LOS Condition.
This "Read/Write" bit-field permits the user to turn off
the Transmitter (within Channel(n)).
Writing a "1" to this bit field will turn off the Transmitter
and tri-state the Transmit Output. Conversely, writing
a "0" to this bit-field will turn-on the Transmitter.
Bit D2 - ALOS1 (Analog Loss of Signal Status Channel(n))
Bit D3 - TAOS(n) (Transmit All OneS - Channel(n))
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This "Read/Write" bit-field permits the user to command the Transmitter (within Channel(n)) to generate
and transmit an "All Ones" pattern onto the line.
a. Set this bit-field to "1", if the cable length (between
the Cross-Connect and the transmit output of Channel(n)) is greater than 225 feet.
Writing a "1" to this bit-field commands the Transmitter to transmit an "All Ones" pattern onto the line.
Writing a "0" to this bit-field commands normal operation.
b. Set this bit-field to "0", if the cable length (between
the Cross-Connect and the transmit output of Channel(n)) is less than 225 feet.
Bit D2 - TxClkINV(n) (Transmit Clock Invert Channel(n))
This bit-field is active only if the XRT73L03 device is
configured to operate in the DS3 or SONET STS-1
Modes.
This "Read/Write" bit-field permits the user to configure the "Transmitter" (within the XRT73L03 device) to
sample the signal (at the TPData and TNData pins)
on the "rising edge" or "falling edge" of TxClk (the
Transmit Line Clock signal).
If the cable length is greater than 225 feet, then the
user should set this bit-field to "1" (in order to increase the amplitude of the Transmit Output Signal).
Conversely, if the cable length is less than 225 feet,
then the user should set this bit-field to "0".
Writing a "1" to this bit-field configures the Transmitter
to sample the TPData and TNData input pins, on the
"rising edge" of TxClk. Conversely, writing a "0" to
this bit-field configures the Transmitter to sample the
TPData and TNData input pins, on the "falling edge"
of TxClk.
NOTE: This option is only available when the XRT73L03 is
operating in the DS3 or STS-1 Mode.
Bit D0 - TxBIN(n) (Transmit Binary Data - Channel(n))
This "Read/Write" bit-field permits the user to configure the "Transmitter" (within Channel(n)) to accept an
(un-encoded) binary data stream (via the TPData input) and converts this data into the appropriate bipolar signal (to the line).
Bit D1 - TxLEV(n) (Transmit Line Build-Out Enable/Disable Select - Channel(n))
This "Read/Write" bit-field permits the user to enable
or disable the Transmit Line Build-Out circuit, within
Channel(n) of the XRT73L03 device.
Writing a "1" configures the "Transmitter" to accept a
binary data stream via the TPData input. (Note: The
TNData input will be ignored). This form of data acceptance is sometimes referred to as "Single-rail"
mode operation. The Transmitter will then encode
this data into the appropriate line code (e.g., B3ZS or
HDB3) prior to its transmission over the line.
Setting this bit-field "HIGH" disables the Line BuildOut circuit within Channel(n). In this mode, Channel(n) will output unshaped (e.g., square-wave) pulses onto the line via the TTIP(n) and TRing(n) output
pins.
Setting this bit-field "LOW" enables the Line Build-Out
circuit within Channel(n). In this mode, Channel(n)
will output shaped pulses onto the line via the TTIP(n)
and TRing(n) output pins.
Writing a "0" configures the "Transmitter" to accept
data in a "dual-rail" manner (e.g., via both the TPData
and TNData inputs).
In order to comply with the "Isolated DSX-3/STSX-1
Pulse Template Requiremnts (per Bellcore GR-499CORE or GR-253-CORE), the user should:
The bit-format and default values for Command Register CR2-(n) are listed below.
5.1.3
Command Register CR2-(n)
COMMAND REGISTER CR2-(N)
D4
D3
D2
D1
D0
Reserved
ENDECDIS
ALOSDIS
DLOSDIS
REQEN
X
0
0
0
0
The function of each of these bit-fields are presented
below.
This "Read/Write" bit-field permits the user to enable
or disable the B3ZS/HDB3 Encoder and Decoder
blocks, within Channel(n).
Bit D4 - Reserved
Writing a "1" to this bit-field disables the B3ZS/HDB3
Encoder and Decoder blocks. Writing a "0" to this bitfield enables the B3ZS/HDB3 Encoder and Decoder
blocks.
Bit D3 - ENDECDIS (B3ZS/HDB3 Encoder/Decoder-Disable - Channel(n))
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NOTE: This Encoder/Decoder will perform HDB3 Encoding/
Decoding if the XRT73L03 is operating in the "E3 Mode".
Otherwise, it will perform B3ZS Encoding/Decoding.
Writing a "1" to this bit-field configures Channel(n) to
output data (to the Terminal Equipment) in a binary
(single-rail) format via the RPOS(n) output pin,
RNEG(n) will be grounded. Conversely, a "0" to this
bit-field configures Channel(n) to output data (to the
Terminal Equipment) in a "Dual Rail" format via both
the RPOS(n) and RNEG(n) output pins.
Bit D2 - ALOSDIS (Analog LOS Disable - Channel(n))
This "Read/Write" bit-field permits the user to disable
the Analog LOS Detector, within Channel(n).
Bit D3 - LOSMUT(n) (Recovered Data MUTing,
during LOS Condition - Channel(n))
Writing a "0" to this bit-field enables the Analog LOS
Detector. Writing a "1" to this bit-field disables the
Analog LOS Detector.
This "Read/Write" bit-field permits the user to configure Channel(n) (within the XRT73L03 device) to not
output any recovered data (from the line), while it is
declaring an LOS condition.
NOTE: If the user disables the Analog LOS Detector, then
the RLOS input pin will only be asserted by the DLOS (Digital LOS Detector).
Writing a "0" to this bit-field configures the chip to output recovered data, even while the XRT73L03 is declaring an "LOS" condition. Writing a "1" to this bitfield configures the chip to NOT output the recovered
data, while an LOS condition is being declared.
Bit D1 - DLOSDIS (Digital LOS Disable - Channel(n))
This "Read/Write" bit-field permits the user to disable
the Digital LOS Detector within Channel(n).
Writing a "0" to this bit-field enables the Digital LOS
Detector. Writing a "1" to this bit-field disables the
Digital LOS Detector.
NOTE: (In this mode, RPOS(n) and RNEG(n) will be set to
"0", asynchronously.)
Bit D2 - RxOFF(n) (Receive Section - Shut OFF Select)
NOTE: If the user disables the Digital LOS Detector, then
the RLOS input pin will only be asserted by the ALOS (Analog LOS Detector).
This "Read/Write" bit-field permits the user to shut-off
the "Receive Section of Channel(n) (within the
XRT73L03 device). The purpose of this feature is to
permit the user to conserve power consumption when
this device is the back-up device in a "Redundancy
System".
Bit D0 - REQEN (Receive Equalization Enable Channel(n))
This "Read/Write" bit-field permits the user to either
enable or disable the internal Receive Equalizer, within Channel(n) of the XRT73L03 device.
Writing a "1" into this bit-field shuts off the Receive
Section of Channel(n). Conversely, writing a "0" into
this bit-field turns on the Receive Section of Channel(n).
Writing a "1" to this bit-field enables the "Internal
Equalizer". Conversely, writing a "0" to this bit-field
disables the "Internal Equalizer".
5.1.4 Command Register CR3-(n)
The bit-format and default values for Command Register CR3 are listed below.
Bit D1 - RxClk(n)INV (Invert RxClk(n))
This "Read/Write" bit-field permits the user to configure the "Receiver" (within Channel(n) of the
XRT73L03 device) to output the recovered data on either the "rising edge" or the "falling edge" of the
RxClk(n) clock signal.
COMMAND REGISTER CR3-(N)
D4
D3
D2
D1
D0
SR/DR_(n) LOSMUT(n) RxOFF(n) RxClk(n)INV Reserved
0
1
0
0
Writing a "0" to this bit-field configures the Receiver to
output the recovered data on the "rising edge" of the
RxClk(n) output signal. Writing a "1" to this bit-field
configures the Receiver to output the recovered data
on the "falling edge" of the RxClk(n) output signal.
0
The function of each of these bit-fields are presented
below.
Bit D4 - SR/DR* (Single-Rail/Dual-Rail Data Output
- Channel(n))
Bit D0 - Reserved
This "Read/Write" bit-field permits the user to configure Channel(n) (within the XRT73L03 device) to output the "received" data (from the Remote Terminal) in
a binary or "dual-rail" format.
Command Register CR4-(n)
This bit-field has no defined functionality
The bit-format and default values for Command Register CR4 are listed below.
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This "Read/Write" bit-field permits the user to configure Channel(n) (within the XRT73L03 device) to operate in the E3 Mode.
COMMAND REGISTER CR4-(N)
D4
D3
D2
D1
D0
Writing a "0" into this bit-field configures Channel(n)
to operate in either the DS3 or SONET STS-1 Mode
(as specified by the setting of the "DS3" bit-field within this Command Register). Writing a "1" into this bitfield configures Channel(n) to operate in the E3
Mode.
Reserved STS-1/DS3_ Ch(n) E3_Ch(n) LLB(n) RLB(n)
0
0
0
0
0
The function of each of these bit-fields are presented
below.
Bit D1 - LLB(n) (Local Loop-back - Channel(n))
Bit D4 - Reserved
This "Read/Write" bit-field, along with "RLB(n)" permits the user to configure Channel(n) (within the
XRT73L03 device) to operate in any one of a variety
of loop-back modes.
This bit-field has no defined functionality
Bit D3 - STS-1/(DS3_(n))* - Channel(n) - Mode Select
This "Read/Write" bit field permits the user to configure Channel(n), (within the XRT73L03 device) to operate in either the SONET STS-1 Mode or the DS3
Mode.
Table 8 relates the contents of "LLB(n)" and "RLB(n)"
and the corresponding loop-back mode for Channel(n).
Bit D0 - RLB(n) (Remote Loop-back - Channel(n))
Writing a "0" into this bit-field configures Channel(n)
to operate in the "DS3 Mode". Writing a "1" into this
bit-field configures Channel(n) to operate in the SONET STS-1 Mode.
This "Read/Write" bit-field, along with "LLB(n)" permits the user to configure Channel(n) (within the
XRT73L03 device) to operate in any one of a variety
of loop-back modes.
NOTE: This bit-field is ignored if the "E3_Ch(n)" bit-field
(e.g., "D2" within this Command Register) is set to "1".
Table 8 relates the contents of "LLB(n)" and "RLB(n)"
and the corresponding loop-back mode for Channel(n).
Bit D2 - E3 Mode Select - Channel(n)
TABLE 8: CONTENTS OF "LLB(N)" AND "RLB(N)" AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL(N)
LLB(n)
RLB(n)
LOOP-BACK MODE (FOR CHANNEL(n))
0
0
None
1
0
Analog Loop-Back Mode (See Section 4.1 for Details)
1
1
Digital Loop-Back Mode (See Section 4.2 for Details
0
1
Remote Loop-Back Mode (See Section 4.3 for Details
5.2 OPERATING THE MICROPROCESSOR SERIAL
INTERFACE .
The following instructions, for using the Microprocessor Serial Interface, are best understood by referring
to the diagram in Figure 32and timing diagram in
Figure 33.
The XRT73L03 Serial Interface is a simple four wire
interface that is compatible with many of the microcontrollers available in the market. This interface
consists of the following signals:
In order to use the Microprocessor Serial Interface
the user must first provide a clock signal to the SClk
input pin. Afterwards, the user will initiate a "Read" or
"Write" operation by asserting the "active-low" Chip
Select input pin CS. It is important to assert the CS
pin (e.g., toggle it "low") at least 50ns prior to the very
first rising edge of the clock signal.
• CS - Chip Select (Active Low)
• SClk - Serial Clock
• SDI - Serial Data Input
• SDO - Serial Data Output
Once the CS input pin has been asserted the type of
operation and the target register address must now
be specified by the user. The user provides this infor-
Using the Microprocessor Serial Interface
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this point the user can begin reading the data contents of the addressed Command Register (at Address [A4,A3, A2, A1, A0]) via the SDO output pin.
The Microprocessor Serial Interface will output this
five bit data word (D0 through D4) in ascending order
(with the LSB first), on the falling edges of the SClk
pin. As a consequence, the data (on the SDO output
pin) will be sufficiently stable for reading (by the Microprocessor), on the very next rising edge of the
SClk pin.
mation to the Microprocessor Serial Interface by writing eight serial bits of data into the SDI input. Note:
each of these bits will be "clocked" into the SDI input,
on the rising edge of SClk. These eight bits are identified and described below.
Bit 1 - "R/W" (Read/Write) Bit
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
"Read" or "Write" operation. A "1" in this bit specifies
a "Read" operation; whereas, a "0" in this bit specifies
a "Write" operation.
Write Operation
Once the last address bit (A3) has been clocked into
the SDI input, the "Write" operation will proceed
through an idle period, lasting three SClk periods.
Prior to the rising edge of SClk Cycle # 9 (see
Figure 32) the user must begin to apply the eight bit
data word, that he/she wishes to write to the Microprocessor Serial Interface, onto the SDI input pin.
The Microprocessor Serial Interface will latch the value on the SDI input pin, on the rising edge of SClk.
The user must apply this word (D0 through D7) serially, in ascending order with the LSB first.
Bits 2 through 5: The four (4) bit Address Values
(labeled A0, A1, A2 , A3 and A4)
The next four rising edges of the SClk signal will clock
in the 4-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register, within the XRT73L03 device that the user
will either be reading data from, or writing data to.
The user must supply the address bits to the SDI input pin, in ascending order with the LSB (least significant bit) first.
Simplified Interface Option
Bits 6 and 7:
The user can simplify the design of the circuitry connecting to the Microprocessor Serial Interface by tying both the SDO and SDI pins together, and reading
data from and/or writing data to this "combined" signal. This simplification is possible because only one
of these signals are active at any given time. The inactive signal will be tri-stated.
A5 must be set to "0", as shown in Figure 32.
Bit 8 - A6
The value of "A6" is a "don't care".
Once these first 8 bits have been written into the Microprocessor Serial Interface, the subsequent action
depends upon whether the current operation is a
"Read" or "Write" operation.
NOTES:
1. A5 is always "0"
Read Operation
2. R/W = "1" for "Read" Operations
Once the last address bit (A3) has been clocked into
the SDI input, the "Read" operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 32) the
serial data output signal (SDO) becomes active. At
3. R/W = "0" for "Write" Operations
4.
- Denotes a "don't care" value
FIGURE 32. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
A4
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
High Z
High Z
SDO
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FIGURE 33. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SClk
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SClk
t31
t30
SDO
SDI
Hi-Z
D0
t33
D1
Hi-Z
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t32
D2
D7
áç
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L03
ADVANCED CONFIDENTIAL
REV. A1.0.7
ORDERING INFORMATION
PART #
PACKAGE
OPERATING TEMPERATURE RANGE
XRT73L03IV
120 Pin TQFP 14mm X 20mm
-40oC to +85oC
XRT73L03IVS
120 Pin TQFP 14mm X 14mm
-40oC to +85oC
120 LEAD THIN QUAD FLAT PACK
(14 x 14 x 1.4 mm, TQFP)
Rev. 1.00
D
D1
90
61
91
60
D1
D
31
120
1
30
e
A2
B
C
A
α
Seating Plane
A1
L
SYMBOL
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
A
0.055
0.063
1.40
1.60
A1
0.002
0.006
0.05
0.15
A2
0.053
0.057
1.35
1.45
B
0.005
0.009
0.13
0.23
C
0.004
0.008
0.09
0.20
D
0.622
0.638
15.80
16.20
D1
0.547
0.555
13.90
14.10
e
L
0.0157BSC
0.018
0.030
0.40BSC
0.45
0o
7o
0o
α
Note: The control dimension is in millimeter.
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0.75
7o
XRT73L03
áç
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
120 LEAD THIN QUAD FLAT PACK
14mm X 20 mm, TQFP
Rev. 1.00
D
D1
96
61
97
60
E1
120
E
37
A2
1
36
B
e
A
α
C
A1
SYMBOL
A
A1
A2
B
C
D
D1
E
E1
e
L
α
INCHES
MILLIMETERS
MIN
MAX
0.055
0.063
0.002
0.006
0.053
0.057
0.007
0.011
0.004
0.008
0.858
0.874
0.783
0.791
0.622
0.638
0.547
0.555
0.020BSC
0.018
0.030
0o
MIN
1.40
0.05
1.35
0.17
0.09
21.80
19.90
15.80
13.90
7o
Note: The control dimension is the millimeter column
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MAX
1.60
0.15
1.45
0.27
0.20
22.20
20.10
16.20
14.10
0.50BSC
0.45
0.75
0o
7o
L
XRT73L03
áç
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADVANCED CONFIDENTIAL
REV. A1.0.7
REVISION HISTORY
Rev. 1.0.1 to Rev.1.0.2
Edits to describe one channel only, as applicable to all channels. Corrected pin names for consistancy.
Rev. 1.0.2 to Rev. 1.0.3
Pin names, numbers and rotation have been changed.
Rev. 1.0.3 to Rev. 1.0.4
Changed package to 14X20mm with 0.5mm pin spacing. Pin #’s/ pin names have been changed.
Rev. 1.0.4 to Rev. 1.0.5
Added 120 lead 14x14mm, 0.4mm pitch package into data sheet, pin names have changed from Rev.
1.0.3.
Rev. 1.0.5 to Rev. 1.0.6
Rotated pins on 14X14mm packaage (pin 1 became 31).
Rev. 1.0.6 to Rev. A1.0.7
Corrected references to similar pins in the pin list to correspond to the changes in pin out.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2000 EXAR Corporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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