ETC XRT7302IV

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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
AUGUST 2000
REV. 1.1.5
• Digital Cross Connect Systems
GENERAL DESCRIPTION
• CSU/DSU Equipment
The XRT7302 Dual Channel E3/DS3/STS-1 Transceiver IC consists of two fully integrated transmitter
and receiver line transceivers designed for E3, DS3
or SONET STS-1 applications.
• Routers
• Fiber Optic Terminals
• Multiplexers
Each channel within the XRT7302 can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate
that is independent of the other channel.
• ATM Switches
FEATURES
• Meets E3/DS3/STS-1 Jitter Tolerance Requirements
In the transmit direction, each channel within the
XRT7302 will encode input data to either B3ZS or
HDB3 format and convert the data into the appropriate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
• Contains a 4-Wire Microprocessor Serial Interface
In the receive direction, the XRT7302 can perform
Equalization on incoming signals, perform Clock Recovery, decode data from either B3ZS or HDB3 format, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and declare the occurrence of Line code Violations.
• Single +5V Power Supply
• Full Loop-back Capability
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Uses Minimum External components
• Operates over -40°C to +85°C Temperature Range
• Available in an 80 pin TQFP Thermal Enhanced
package with integral Heat Sink
APPLICATIONS
XRT7302 BLOCK DIAGRAM
E3_Ch(n)
RTIP(n)
RRing(n)
STS-1/DS3_Ch(n)
AGC/
Equalizer
REQEN(n)
Host/HW
RLOL(n) ExClk(n)
RxClkINV
Clock
Recovery
Slicer
Data
Recovery
Peak Detector
RxOFF(n)
LOS Detecto r
LOSTHR(n)
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
SDI
SDO
SClk
CS
RLOS(n)
Serial
Processor
Interface
LLB(n)
Loop MUX
RLB(n)
REGR
TTIP(n)
Pulse
Shaping
TRing(n)
MTIP(n)
MRing(n)
HDB3/
B3ZS
Encoder
TAOS(n)
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
Device
Monitor
Tx
Control
DMO(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Channel 1
Channel 2
Notes: 1. (n) = 1 or 2 for the respective channel.
2. Serial Processor Interface pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
TRANSMIT INTERFACE CHARACTERISTICS
RECEIVE INTERFACE CHARACTERISTICS
• Accepts either Single Rail or Dual Rail data from
Terminal Equipment, and generates a bipolar signal
• Integrated Adaptive Receive Equalization
(Optional) and Timing Recovery
• Integrated Pulse Shaping Circuit
• Declares and Clears the LOS alarm per ITU-T
G.775 requirements (E3 and DS3 applications)
• Built-in B3ZS/HDB3 Encoder (which can be disabled)
• Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 (for E3 Applications)
• Contains "Transmit Clock Duty Cycle Correction"
Circuit on-chip
• Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE (for DS3 Applications)
• Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
• Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
• Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
• Built-in B3ZS/HDB3 Decoder (which can be disabled)
• Recovered Data can be automatically muted while
the LOS Condition is declared
• Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253CORE
• Outputs either Single Rail or Dual Rail data to the
Terminal Equipment
• Transmitter can be turned off in order to support
"redundancy designs"
• Receiver can be powered down in order to conserve power in "redundancy designs"
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
TxOff1
TxClk1
TPDATA1
TNDATA1
MTIP1
MRing1
AVDD
TTIP1
TRing1
AGND
AGND
TRing2
TTIP2
AVDD
MRing2
MTIP2
TNDATA2
TPDATA2
TxClk2
TxOff2
PIN OUT OF THE XRT7302
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80 Lead TQFP
STS-1/DS3_Ch1
ICT
LOSTHR1
LLB1
RLB1
AVDD
RRing1
RTIP1
AGND
REQEN1
REQEN2
AGND
RTIP2
RRing2
AVDD
RLB2
LLB2
LOSTHR2
E3_Ch2
SR/DR
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22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TxLEV1
TAOS1
DVDD
DMO1
DGND
AGND
DVDD
Host/(HW)
RxClk1
RNEG1
RPOS1
DGND
RLOS1
LCV1
RLOL1
EXClk1
CS/(ENDECDIS)
SClk/(RxOff2)
SDI/(RxOff1)
SDO/(E3_Ch1)
2
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TxLEV2
TAOS2
DVDD
DMO2
DGND
AGND
DVDD
LOSMUTEN
RxClk2
RNEG2
RPOS2
DGND
RLOS2
LCV2
RLOL2
EXClk2
VDD
GND
REGR/(RxClkINV)
STS-1/DS3_Ch2
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
TABLE OF CONTENTS
General description ........................................................................................................... 1
APPLICATIONS .........................................................................................................................................
FEATURES ................................................................................................................................................
XRT7302 BLOCK DIAGRAM .....................................................................................................................
TRANSMIT INTERFACE CHARACTERISTICS ........................................................................................
RECEIVE INTERFACE CHARACTERISTICS ...........................................................................................
PIN OUT OF THE XRT7302 ......................................................................................................................
1
1
1
2
2
2
TABLE OF CONTENTS I
Pin descriptions ................................................................................................................. 3
ELECTRICAL CHARACTERISTICS ................................................................................. 18
ABSOLUTE MAXIMUM RATINGS ................................................................................................... 18
Figure 1.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel shown) ......
Figure 2.Timing Diagram of the Transmit Terminal Input Interface ................................................................
Figure 3.Timing Diagram of the Receive Terminal Output Interface ..............................................................
Figure 4.Microprocessor Serial Interface Data Structure ...............................................................................
Figure 5.Timing Diagram for the Microprocessor Serial Interface ..................................................................
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24
25
SYSTEM DESCRIPTION ................................................................................................... 26
THE TRANSMIT SECTION (CHANNELS 1 AND 2) ................................................................................ 26
THE RECEIVE SECTION (CHANNELS 1 AND 2) ................................................................................... 26
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 26
THE HARDWARE MODE ........................................................................................................................ 26
THE HOST MODE ................................................................................................................................... 26
Table 1:Role of Microprocessor Serial Interface pins when the XRT7302 is operating in the "Hardware" Mode.
26
Figure 6.Functional Block Diagram of the XRT7302 ...................................................................................... 27
1.0 SELECTING THE DATA RATE ......................................................................................................... 27
1.1 CONFIGURING CHANNEL 1 ............................................................................................................. 27
Table 2:Selecting the Data Rate for Channel 1, (within the XRT7302), via the "E3_Ch1" and "STS-1/DS3_Ch1"
input pins (Hardware Mode) .............................................................................................................. 28
COMMAND REGISTER, CR4 (ADDRESS = 0X04) ......................................................................... 28
Table 3:Selecting the Data Rate for Channel 1 (within the XRT7302); via the "STS-1/DS3_Ch1" and the
"E3_Ch1" bit-fields, within Command Register CR4 (Host Mode) ..................................................... 28
1.2 CONFIGURING CHANNEL 2 ............................................................................................................. 28
Table 4:Selecting the Data Rate for Channel 2 (within the XRT7302) via the "E3_Ch2" and "STS-1/DS3_Ch2"
input pins (Hardware Mode) .............................................................................................................. 28
COMMAND REGISTER, CR12 (ADDRESS = 0X0C) ...................................................................... 29
Table 5:Selecting the Data Rate for Channel 2 (within the XRT7302) via the "E3_Ch2" and "STS-1/DS3_Ch2"
Bit Fields, within Command Register CR4 (Host Mode) .................................................................... 29
2.0 THE TRANSMIT SECTION ............................................................................................................... 29
2.1 THE TRANSMIT LOGIC BLOCK ......................................................................................................... 29
Accepting "Dual-Rail" Data from the Terminal Equipment ................................................................. 29
Figure 7. Illustration of the typical interface for the Transmission of Data in a Dual Rail Format, from the "Transmitting" Terminal Equipment to the "Transmit Section" of a channel within the XRT7302 ............... 30
Figure 8.Illustration on how the XRT7302 Samples the data on the TPData and TNData input pins ............ 30
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
áç
REV. 1.1.5
Accepting "Single-Rail" Data from the Terminal Equipment .............................................................. 30
COMMAND REGISTER 1 (ADDRESS = 0X01) ............................................................................... 31
COMMAND REGISTER 9 (ADDRESS = 0X09) ............................................................................... 31
Figure 9.Illustration of the Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is
Accepting Single-Rail Data from the Terminal Equipment ................................................................ 31
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................. 31
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................... 32
B3ZS Encoding .................................................................................................................................. 32
Figure 10.An Example of B3ZS Encoding ...................................................................................................... 32
HDB3 Encoding .................................................................................................................................. 32
Figure 11.An Example of HDB3 Encoding ...................................................................................................... 33
Disabling the "HDB3/B3ZS" Encoder ................................................................................................. 33
COMMAND REGISTER, CR2 (ADDRESS = 0X02) ......................................................................... 33
COMMAND REGISTER, CR10 (ADDRESS = 0X0A) ....................................................................... 33
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY ....................................................................................
Figure 12.The "Bellcore GR-499-CORE" Transmit Output Pulse Template for DS3 Applications ..................
Figure 13.The "Bellcore GR-253-CORE" Transmit Output Pulse Template for SONET STS-1 Applications .
Enabling the Transmit Line Build-Out Circuit .....................................................................................
33
34
35
35
COMMAND REGISTER, CR1 (ADDRESS = 0X01) ......................................................................... 35
Disabling the Transmit Line Build-Out Circuit .................................................................................... 36
Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... 36
COMMAND REGISTER, CR9 (ADDRESS = 0X09) ......................................................................... 36
COMMAND REGISTER, CR1 (ADDRESS = 0X01) ......................................................................... 36
COMMAND REGISTER, CR9 (ADDRESS = 0X09) ......................................................................... 36
The Transmit Line Build-Out Circuit and E3 Applications ..................................................................
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT7302 TO THE LINE ...........................................
Figure 14.Recommended Schematic for Interfacing the Transmit Section of the XRT7302 to the Line .........
TRANSFORMER VENDOR INFORMATION ...........................................................................................
36
36
37
37
3.0 THE RECEIVE SECTION ................................................................................................................... 38
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT7302 TO THE LINE ............................................. 38
Figure 15.Recommended Schematic for Interfacing the Receive Section of the XRT7302 to the Line (Transformer-Coupling) ...................................................................................................................................... 38
TRANSFORMER VENDOR INFORMATION ........................................................................................... 39
Figure 16.Recommended Schematic for Interfacing the Receive Section of the XRT7302 to the Line (Capacitive-Coupling) - (typical channel shown) ........................................................................................... 39
Figure 17.Illustration of the Typical Application for the System Installer ......................................................... 40
3.2 THE RECEIVE EQUALIZER BLOCK .................................................................................................... 40
COMMAND REGISTER CR2 (ADDRESS = 0X02) .......................................................................... 41
COMMAND REGISTER CR10 (ADDRESS = 0X0A) ........................................................................ 41
3.3 PEAK DETECTOR AND SLICER .........................................................................................................
3.4 CLOCK RECOVERY PLL ..................................................................................................................
3.5 THE HDB3/B3ZS DECODER ..........................................................................................................
B3ZS Decoding (DS3/STS-1 Applications) ........................................................................................
Figure 18.An Example of B3ZS Decoding ......................................................................................................
HDB3 Decoding (E3 Applications) .....................................................................................................
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áç
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
Figure 19.An Example of HDB3 Decoding ..................................................................................................... 43
Configuring the HDB3/B3ZS Decoder ............................................................................................... 43
COMMAND REGISTER CR2 (ADDRESS = 0X02) .......................................................................... 43
COMMAND REGISTER CR10 (ADDRESS = 0X0A) ....................................................................... 43
3.6 LOS DECLARATION/CLEARANCE .................................................................................................... 43
The LOS Declaration/Clearance Criteria for E3 Applications ............................................................ 44
Figure 20.Illustration of the Signal Levels that the XRT7302 will declare and clear LOS ............................... 44
Figure 21.The Behavior the LOS Output Indicator, in response to the Loss of Signal, and the Restoration of Signal ..................................................................................................................................................... 45
The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications ....................................... 45
Table 6:The ALOS (Analog LOS) Declaration and Clearance Thresholds for a given setting of LOSTHR and
REQEN (DS3 and STS-1 Applications) ............................................................................................. 45
COMMAND REGISTER 0, (ADDRESS = 0X00) .............................................................................. 46
COMMAND REGISTER 8, (ADDRESS = 0X08) .............................................................................. 46
COMMAND REGISTER CR2 (ADDRESS = 0X02) .......................................................................... 46
COMMAND REGISTER CR10 (ADDRESS = 0X0A) ....................................................................... 46
COMMAND REGISTER CR0, (ADDRESS = 0X00) ......................................................................... 47
COMMAND REGISTER CR8, (ADDRESS = 0X08) ......................................................................... 47
COMMAND REGISTER CR2 (ADDRESS = 0X02 ........................................................................... 47
COMMAND REGISTER CR10 (ADDRESS = 0X0A ......................................................................... 47
Muting the Recovered Data while the LOS is being Declared ........................................................... 47
COMMAND REGISTER CR3 (ADDRESS = 0X03) .......................................................................... 48
COMMAND REGISTER CR11 (ADDRESS = 0X0B) ....................................................................... 48
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE "RECEIVING TERMINAL EQUIPMENT"
............................................................................................................................................................. 48
Routing "Dual-Rail" Format Data to the Receiving Terminal Equipment ........................................... 48
Figure 22.Illustration of the typical interface for the Transmission of Data in a Dual-Rail Format, from the "Receive Section" of the XRT7302" to the Receiving Terminal Equipment ........................................... 49
Figure 23.Illustration on how the XRT7302 outputs data on the RPOS and RNEG output pins .................... 49
Figure 24.Illustration of the Behavior of the RPOS, RNEG, and RxClk(n) signals, when RxClk(n) is inverted 50
Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment ........... 50
COMMAND REGISTER CR3 (ADDRESS = 0X03) .......................................................................... 50
COMMAND REGISTER CR11 (ADDRESS = 0X0B) ....................................................................... 50
COMMAND REGISTER CR3 (ADDRESS = 0X03) .......................................................................... 50
COMMAND REGISTER 11 (ADDRESS = 0X0B) ............................................................................. 50
Figure 25.Illustration of the typical interface for the Transmission of Data in a Single-Rail Format, from the Receive Section of the XRT7302 to the Receiving Terminal Equipment .............................................. 51
Figure 26.Illustration of the behavior of the RPOS and RxClk output signals, while the XRT7302 is transmitting
"Single-Rail" data to the Receiving Terminal Equipment ................................................................. 51
3.8 SHUTTING OFF THE RECEIVE SECTION .......................................................................................... 51
COMMAND REGISTER CR3 (ADDRESS = 0X03) .......................................................................... 52
COMMAND REGISTER CR11 (ADDRESS = 0X0B) ....................................................................... 52
4.0 DIAGNOSTIC FEATURES OF THE XRT7302 .................................................................................. 53
4.1 THE ANALOG LOCAL LOOP-BACK MODE ......................................................................................... 53
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.1.5
Figure 27.Illustration of a Typical Channel(n) (within the XRT7302) operating in the Analog Local Loop-back
Mode ................................................................................................................................................. 53
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. .......................................................................................... 54
Figure 28.Illustration of the "Digital Local Loop-back" path in a Typical Channel(n) (of the XRT7302) .......... 54
COMMAND REGISTER CR4 (ADDRESS = 0X04) .......................................................................... 55
COMMAND REGISTER CR12 (ADDRESS = 0X0C) ........................................................................ 55
4.3 THE REMOTE LOOP-BACK MODE .................................................................................................... 55
Figure 29.Illustration of the "Remote Loop-back" path, within a Typical Channel(n) (of the XRT7302) .......... 56
COMMAND REGISTER CR4 (ADDRESS = 0X04) .......................................................................... 56
COMMAND REGISTER CR12 (ADDRESS = 0X0C) ........................................................................ 56
4.4 TXOFF FEATURES ......................................................................................................................... 56
COMMAND REGISTER CR1 (ADDRESS = 0X01) .......................................................................... 57
COMMAND REGISTER CR9 (ADDRESS = 0X09) .......................................................................... 57
Table 7:The Relationship Between the “TxOFF” Input Pin, the “TxOFF” Bit Field and the State of the Transmitter
.............................................................................................................................................................57
4.5 THE TRANSMIT DRIVE MONITOR FEATURES .................................................................................... 57
Figure 30.Illustration of a Typical Channel of the XRT7302 employing the Transmit Drive Monitor Features 58
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .................................................................................. 58
COMMAND REGISTER CR1 (ADDRESS = 0X01) .......................................................................... 58
5.0 THE MICROPROCESSOR SERIAL INTERFACE ............................................................................. 59
COMMAND REGISTER CR9 (ADDRESS = 0X09) .......................................................................... 59
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................. 59
Table 8:Addresses and Bit Formats of XRT7302 Command Registers .......................................................... 60
Command Register - CR0 .................................................................................................................. 60
COMMAND REGISTER CR0, (ADDRESS = 0X00) ......................................................................... 60
COMMAND REGISTER CR1 (ADDRESS = 0X01) .......................................................................... 61
Command Register CR2 .................................................................................................................... 62
COMMAND REGISTER CR2 (ADDRESS = 0X02) .......................................................................... 62
COMMAND REGISTER CR3 (ADDRESS = 0X03) .......................................................................... 63
COMMAND REGISTER CR4 (ADDRESS = 0X04) .......................................................................... 63
Table 9:Contents of "LLB1" and "RLB1" and the Corresponding Loop-Back Mode for Channel 1 ................. 64
Command Register - CR8 .................................................................................................................. 64
COMMAND REGISTER 8, (ADDRESS = 0X08) .............................................................................. 64
Command Register CR9 .................................................................................................................... 64
COMMAND REGISTER CR9 (ADDRESS = 0X09) .......................................................................... 65
Command Register CR10 .................................................................................................................. 65
COMMAND REGISTER CR10 (ADDRESS = 0X0A) ........................................................................ 65
5.2 COMMAND REGISTER CR11 ........................................................................................................... 66
COMMAND REGISTER CR11 (ADDRESS = 0X0B) ........................................................................ 66
Command Register CR12 .................................................................................................................. 67
COMMAND REGISTER CR 12 (ADDRESS = 0X0C) ....................................................................... 67
Table 10:Contents of "LLB2" and "RLB2" and the Corresponding Loop-Back Mode for Channel 2 ............... 67
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IV
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................. 67
Figure 31.Microprocessor Serial Interface Data Structure ............................................................................. 68
Figure 32.Timing Diagram for the Microprocessor Serial Interface ................................................................ 69
Ordering information ....................................................................................................... 70
Package dimensions ....................................................................................................... 70
REVISION HISTORY ............................................................................................................................... 71
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTIONS
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
1
TxLEV1
I
DESCRIPTION
Transmit Line Build-Out Enable/Disable Select - Channel 1:
This input pin permits the user to enable or disable the Transmit Line Build-Out
circuit, within Channel 1 of the XRT7302.
Setting this pin to "HIGH" disables the Line Build-Out circuit within Channel 1.
In this mode, Channel 1 will output unshaped (e.g., square-wave) pulses onto
the line via the TTIP1 and TRing1 output pins.
Setting this pin to "LOW" enables the Line Build-Out circuit within Channel 1.
In this mode, Channel 1 will output shaped pulses onto the line via the TTIP1
and TRing1 output pins.
In order to comply with the "Isolated DSX-3/STSX-1 Pulse Template Requirements (per Bellcore GR-499-CORE or Bellcore GR-253-CORE), the user
should:
1. Set this input pin to "1", if the cable length (between the Cross-Connect and
the transmit output of Channel 1) is greater than 225 feet.
2. Set this input pin to "0", if the cable length (between the Cross-Connect and
the transmit output of Channel 1) is less than 225 feet.
This pin is active only if the following two conditions are true:
a. The XRT7302 is configured to operate in either the DS3 or SONET STS-1
Modes.
b. The XRT7302 is configured to operate in the "Hardware" Mode.
NOTE: Note: The user should tie this pin to GND if the XRT7302 is going to be
operating in the "Host" Mode
2
TAOS1
I
Transmit All Ones Select - Channel 1:
A "high" on this pin causes the Transmit Section, within Channel 1 to generate
and transmit a continuous AMI "All 1s" pattern onto the line. The frequency of
this "1s" pattern is determined by TxClk.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
3
DVDD
****
4
DMO1
O
Transmit Digital VDD (for Transmitter 1)
Drive Monitor Output - Channel 1:
If no transmitted AMI signal is present on MTIP1 and MRing1 input pins for
128±32 TxClk periods, then DMO1 will toggle and remain "high" until the next
AMI signal is detected.
5
DGND
6
AGND
7
DVDD
****
Transmit Digital GND (for Transmitter 1)
Analog GND (Substrate Connection) - Channel 1
****
Receive Digital VDD (for Receiver 1)
3
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
8
Host/(HW)
I
DESCRIPTION
Host/HW Mode Select:
This input pin permits the user to enable or disable the Microprocessor Serial
Interface (e.g., consisting of the SDI, SDO, SClk, and CSB pins).
Setting this input pin "high" enables the Microprocessor Serial Interface (or
configures the XRT7302 to operate in the "Host" Mode). In this mode, the
user is expected to configure the XRT7302 via the Microprocessor Serial Interface. As a consequence, when the XRT7302 is operating in the "Host" Mode,
then it will ignore the states of many of the discrete input pins. Setting this
input pin "low" disables the Microprocessor Serial Interface (e.g., configures
the XRT7302 to operate in the "Hardware" Mode). In this mode, many of the
external input control pins will be functional and therefore the unsued input
pins should not be left floating.
9
RxClk1
O
Receive Clock Output pin - Channel 1:
This output pin is the Recovered Clock signal from the incoming line signal,
which is being received by Channel 1. The receive section of Channel 1 will
output data via the RPOS1 and RNEG1 output pins, on the rising edge of this
clock signal.
NOTE: The user can configure the Receive Section of Channel 1 to update the
data on the RPOS1 and RNEG1 output pins, on the falling edge of RxClk1, by
doing one of the following:
1. If the XRT7302 is operating in the Hardware Mode
Pulling the "RClkINV" pin (pin 42) to "high".
2. If the XRT7302 is operating in the Host Mode
Writing a "1" into the "RClk(n)INV" bit-field within the Command Register.
10
RNEG1
O
Receive Negative Pulse Output - Channel 1:
This output pin will pulse "high" whenever Channel 1, within the XRT7302 has
received a "Negative Polarity" pulse, in the incoming line signal, at the RTIP1/
RRing1 inputs.
NOTE: Note: If the B3ZS/HDB3 Decoder (within Channel 1) is "enabled" then
the "zero suppression" patterns, in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") will not be reflected at this output.
11
RPOS1
O
Receive Positive Pulse Output - Channel 1:
This output pin will pulse "high" whenever Channel 1, within the XRT7302 has
received a "Positive Polarity" pulse, in the incoming line signal, at the RTIP1/
RRing1 inputs.
NOTE: If the B3ZS/HDB3 Decoder (within Channel 1) is "enabled" then the
"zero suppression" patterns, in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") will not be reflected at this output.
12
DGND
****
13
RLOS1
O
Receive Digital GND - Channel 1
Receive Loss of Signal Output Indicator - Channel 1:
This output pin toggles "high" if Channel 1, within the XRT7302 has detected a
"Loss of Signal" Condition in the incoming line signal.
The exact criteria that the XRT7302 uses to declare an "LOS Condition"
depends upon whether the device is operating in the E3 or DS3/STS-1 Mode
and the state of the LOSTHR1 pin.
4
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XRT7302
áç
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
14
LCV1
O
DESCRIPTION
Line Code Violation Indicator - Channel 1:
Whenever the Receive Section of Channel 1 detects a Line Code Violation,
then it will pulse this output pin "high". This output pin will remain "low" at all
other times.
The XRT7302 will output an NRZ pulse via this output pin. Hence, the user is
advised to sample this output pin via the RxClk2 clock output signal.
15
RLOL1
O
Receive Loss of Lock Output Indicator - Channel 1:
This output pin toggles "high" if Channel 1, within the XRT7302 has detected a
"Loss of Lock" Condition. Channel 1 will declare an LOL (Loss of Lock) Condition if the recovered clock frequency deviates from the Reference Clock frequency (available at the ExClk input pin) by more than 0.5%.
16
EXClk1
I
External Reference Clock Input - Channel 1:
The user is expected to apply a 34.368 MHz clock signal (for E3 applications),
a 44.736 MHz clock signal (for DS3 applications), or a 51.84 MHz clock signal
(for SONET STS-1 applications).
NOTES:
1. It is permissible for one to use the same clock, which is also driving
the "TxClk" input pin.
2. It is permissible to operate Channel 1 at a different data rate than from
Channel 2.
17
CS/(ENDECDIS)
I
Microprocessor Serial Interface - Chip Select Input/Encoder-Decoder
Disable Input:
The exact functionality of this pin depends upon whether the XRT7302 is operating in the Host or Hardware Mode.
Host Mode Operation - Chip Select Input (for the Microprocessor Serial
Interface):
The Local Microprocessor must assert this pin (e.g., set it to "0") in order to
enable communication with the XRT7302, via the Microprocessor Serial Interface. (Note: This pin is internally pulled "high".)
Hardware Mode - B3ZS/HDB3 Encoder & Decoder Disable:
Setting this input pin "high" disables the "B3ZS/HDB3 Encoder & Decoder"
blocks (within the XRT7302) and configures the XRT7302 to transmit and
receive the line signal in an AMI format. Conversely, setting this input pin
"low" enables the "B3ZS/HDB3 Encoder & Decoder" blocks and configures the
XRT7302 to transmit and receive the line signal in the B3ZS format, (for DS3/
STS-1 operation) or in the HDB3 format, (for E3 operation).
NOTE: If the XRT7302 is operating in the "Hardware" Mode, then this pin setting configures the "B3ZS/HDB3" Encoder and Decoder Blocks for both Channels 1 and 2.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
18
SClk/(RxOFF2)
I
DESCRIPTION
Microprocessor Serial Interface Clock Signal/"Channel 2 Receiver Shut
OFF" Input:
The exact role that this particular pin plays depends upon whether the
XRT7302 is operating in the "Host" Mode or in the "Hardware" Mode.
Host Mode - Microprocessor Serial Interface Clock Signal:
This signal will be used to sample the data, on the SDI pin, on the rising edge.
Additionally, during "Read" operations, the Microprocessor Serial Interface will
update the SDO output on the falling edge of this signal.
Hardware Mode - Channel 2 Receiver Shut OFF input pin:
Setting this input pin "high" shuts off the Receive Section within Channel 2.
Conversely, setting this input pin "low" enables the Receive Section for full
operation.
19
SDI/(RxOFF1)
I
Serial Data Input for the Microprocessor Serial Interface/Channel 1 Receiver Shut OFF Input pin:
The exact function of this input depends upon whether the XRT7302 is operating in the "Host" Mode or in the "Hardware" Mode.
Host Mode - Serial Data Input for the Microprocessor Serial Interface:
Whenever the user wishes to read or write data into the Command Registers,
over the Microprocessor Serial Interface; the user is expected to apply the
"Read/Write" bit, the Address Values (of the Command Registers) and Data
Value to be written (during "Write" Operations) to this pin.
This input will be sampled on the rising edge of the SClk pin (pin 18).
Hardware Mode - Channel 1 Receiver Shut OFF Input pin:
Setting this input pin "high" shuts off the Receive Section within Channel 1.
Conversely, setting this input pin "low" enables the Receive Section for full
operation.
20
SDO/(E3_Ch1)
I/O
Serial Data Output from the Microprocessor Serial Interface/E3_Mode
Select - Channel 1:
The exact functionality of this pin depends upon whether the XRT7302 is operating in the "Host" Mode or in the "Hardware" Mode.
Host Mode Operation - Serial Data Output for the Microprocessor Serial
Interface:
This pin will serially output the contents of the specified Command Register,
during "Read" Operations. The data, on this pin, will be updated on the falling
edge of the SClk input signal. This pin will be tri-stated upon completion of
data transfer.
Hardware Mode Operation - E3 Mode Select - Channel 1:
This input pin permits the user to configure Channel 1 (within the XRT7302) to
operate in the E3 or STS/DS3 Modes. Setting this input pin to "HIGH" configures Channel 1 to operate in the "E3" Mode. Setting this input pin to "LOW"
configures Channel 1 to operate in either the DS3 or STS-1 Modes (depending upon the state of the "STS-1/DS3_Ch1 input pin (pin 21).
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
21
STS-1/DS3_Ch1
I
DESCRIPTION
STS-1/DS3 Select Input - Channel 1:
A "high" on this pin configures the Clock Recovery Phase Locked Loop (within
Channel 1) to set its VCO Center frequency to around 51.84 MHz (optimal for
SONET STS-1 operations). A "low" on this pin configures the Clock Recovery
Phase Locked Loop to set the VCO Center frequency to 44.736 MHz (optimal
for DS3 operations).
NOTES:
1. The XRT7302 will ignore this pin if the "E3_Ch1" pin (pin 20) is set to
"1".
2. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
3. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
22
ICT
I
In-Circuit Test Input
Setting this pin "low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. Hence, the user should set this
pin "high" for normal operation.
NOTE: This pin is internally pulled "high".
23
LOSTHR1
I
Loss of Signal Threshold Control - Channel 1
The voltage forced on this pin controls the input loss of signal threshold for
Channel 1. Forcing the LOSTHR1 pin to GND or VDD provides two settings.
This pin must be set to the desired level upon power up and should not be
changed during operation.
NOTE: This pin is only applicable during DS3 or STS-1 operations.
24
LLB1
I
Local Loop-back - Channel 1
This input pin, along with "RLB1" dictates which loop-back mode Channel 1
(within the XRT7302) will be operating in.
A "high" on this pin (with "RLB1" being set to "low") configures Channel 1,
within the XRT7302 to operate in the "Analog Local Loop-back" Mode.
A "high" on this pin (with "RLB1" also being set to "high") configures Channel
1, within the XRT7302, to operate in the "Digital Local Loop-back" Mode and
tristates the channel 1 transmitter output.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
25
RLB1
I
DESCRIPTION
Remote Loop-back - Channel 1:
This input pin, along with "LLB1" dictates which loop-back mode "Channel 1
(within the XRT7302) will be operating in.
A "high" on this pin (with "LLB1" being set to "low") configures Channel 1,
within the XRT7302 to operate in the Remote Loop-back Mode.
A "high" on this pin (with "LLB1" also being set to "high") configures Channel
1, within the XRT7302, to operate in the "Digital Local Loop-back" Mode and
tristates the channel 1 transmitter output.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
26
AVDD
****
27
RRing1
I
Receive Analog VDD - Channel 1:
Receive Ring Input - Channel 1:
This input pin, along with RTIP1 is used to receive the bipolar line signal from
the "Remote DS3/E3 Terminal".
28
RTIP1
I
Receive TIP Input - Channel 1:
This input pin, along with RRing1 is used to receive the bipolar line signal from
the "Remote DS3/E3/STS-1 Terminal".
29
AGND
****
30
REQEN1
I
Receive Analog GND - Channel 1
Receive Equalization Enable Input - Channel 1:
Setting this input pin "low" disables the Internal Receive Equalizer, within
Channel 1. Setting this pin "high" enables the Internal Receive Equalizer.
The guidelines for enabling and disabling the Receive Equalizer are described
in Section 3.2
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
31
REQEN2
I
Receive Equalization Enable Input - Channel 2:
Setting this input pin "high" enables the Internal Receive Equalizer, within
Channel 2. Setting this pin "low" disables the Internal Receive Equalizer. The
guidelines for enabling and disabling the Receive Equalizer are described in
Section 3.2.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
32
AGND
****
Receive Analog GND - Channel 2
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
33
RTIP2
I
DESCRIPTION
Receive TIP Input - Channel 2:
This input pin, along with RRing2 is used to receive the bipolar line signal from
the "Remote DS3/E3/STS-1 Terminal".
34
RRing2
I
Receive Ring Input - Channel 2:
This input pin, along with RTIP2 is used to receive the bipolar line signal from
the "Remote DS3/E3 Terminal".
35
AVDD
****
36
RLB2
I
Receive Analog VDD - Channel 2
Remote Loop-back - Channel 2:
This input pin, along with "LLB2" dictates which loop-back mode "Channel 2"
(within the XRT7302) will be operating in.
A "high" on this pin (with "LLB2" being set to "low") configures Channel 2,
within the XRT7302 to operate in the "Remote Loop-back" Mode.
A "high" on this pin (with "LLB1" also being set to "high") configures Channel
2, within the XRT7302, to operate in the "Analog Local Loop-back" Mode and
tristates the channel 2 transmitter output.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
37
LLB2
I
Local Loop-back - Channel 2:
This input pin, along with "RLB2" dictates which loop-back mode Channel 2
(within the XRT7302) will be operating in.
A "high" on this pin (with "RLB2" being set to "low") configures Channel 2
within the XRT7302 to operate in the "Analog Local Loop-back" Mode.
A "high" on this pin (with "RLB2" also being set to "high") configures Channel
2, within the XRT7302, to operate in the "Digital Local Loop-back" Mode and
tristates the channel 2 transmitter output.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
38
LOSTHR2
I
Loss of Signal Threshold Control - Channel 2
The voltage forced on this pin controls the input loss of signal threshold for
Channel 2. Two settings are provided by forcing the LOSTHR2 pin to GND or
VDD. This pin must be set to the desired level upon power up and should not
be changed during operation.
NOTE: This pin is only applicable during DS3 or STS-1 operations.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
39
E3_Ch2
I
DESCRIPTION
E3 Select Input - Channel 2:
A "high" on this pin configures Channel 2 of the XRT7302 to operate in the E3
Mode.
A "low" on this pin configures Channel 2 of the XRT7302 to check the state of
the STS-1/(DS3_Ch2) input pin
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
40
SR/DR
I
Receive Output Single-Rail/Dual-Rail Select:
Setting this pin "HIGH" configures the Receive Sections of both Channels, to
output data (in a Single-Rail Manner) to the Terminal Equipment.
Setting this pin "LOW" configures the Receive Section of both Channels, to
output data (in a Dual-Rail Manner) to the Terminal Equipment.
41
STS-1/DS3_Ch2
I
STS-1/DS3 Select Input - Channel 2:
A "high" on this pin configures the Clock Recovery Phase Locked Loop (in
Channel2 ) to set its VCO Center frequency to around 51.84 MHz (optimal for
SONET STS-1 operations).
A "low" on this pin configures the Clock Recovery Phase Locked Loop to set
its VCO Center frequency to around 44.736 MHz (optimal for DS3 operations).
NOTES:
1. The XRT7302 will ignore this pin if the E3_Ch2 pin (pin 39) is set to
"1".
2. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
3. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
42
REGR/
(RClkNV)
I
DESCRIPTION
Register Reset Input pin (Invert RxClk(n) Output - Select):
The exact function of this particular pin depends upon whether the XRT7302 is
operating in the "Host" Mode or in the "Hardware" Mode.
Host-Mode - Register Reset Input pin:
Setting this input pin "low" causes the XRT7302 to reset the contents of the
Command Registers to their default settings. Additionally, it resets the
XRT7302 to its "default" operating configuration.
NOTE: This pin is internally pulled "high".
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "high" configures the Receive Section of both Channels
(within the XRT7302) to invert their "RxClk1 and RxClk2" clock output signals.
Specifically, setting this pin "low" configures Channel 1 to output the recovered
data (via the RPOS1 and RNEG1 output pins) on the "rising" edge of the
RxClk1 output signal. This setting also configures Channel 2 to output the
recovered data (via the RPOS2 and RNEG2 output pins) on the "rising" edge
of the RxClk2 output signal.
Conversely, setting this input pin "high" configures Channel 1 to output the
recovered data (via the RPOS1 and RNEG1 output pins) on the "falling" edge
of the RxClk1 output signal. This setting also configures Channel 2 to output
the recovered data (via the RPOS2 and RNEG2 output pins on the "falling"
edge of the RxClk2 output signal
43
GND
****
ExClk Reference GND
44
VDD
****
ExClk Reference VDD
45
EXClk2
I
External Reference Clock Input:
The user is expected to apply a 34.368 MHz clock signal (for E3 applications),
a 44.736 MHz clock signal (for DS3 applications), or a 51.84 MHz clock signal
(for SONET STS-1 applications).
NOTES:
1. It is permissible for one to use the same clock, which is also driving
the "TxClk" input pin.
2. It is permissible to operate Channel 2 at a different data rate than from
Channel 1.
46
RLOL2
O
Receive Loss of Lock Output Indicator - Channel 2
This output pin toggles "high" if the Receive Section of Channel 2 has
detected a "Loss of Lock" Condition. Channel 2 will declare an LOL (Loss of
Lock) Condition if the recovered clock frequency (at Channel 2) deviates from
the Reference Clock frequency (available at the ExClk input pin) by more than
0.5%.
47
LCV2
O
Line Code Violation Indicator - Channel 2
Whenever the Receive Section of Channel 2 detects a Line Code Violation,
then it will pulse this output pin "high". This output pin will remain "low" at all
other times.
NOTE: The XRT7302 will output an NRZ pulse via this output pin. Hence, the
user is advised to sample this output pin via the RxClk2 clock output signal.
11
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
48
RLOS2
O
DESCRIPTION
Receive Loss of Signal Output Indicator - Channel 2
This output pin toggles "high" if Receive Section of Channel 2 has detected a
"Loss of Signal" Condition in the incoming line signal.
The exact criteria that the XRT7302 uses to declare an "LOS Condition"
depends upon whether the device is operating in the E3 or DS3/STS-1 Mode.
49
DGND
****
50
RPOS2
O
Receive Digital Ground - Channel 2
Receive Positive Pulse Output - Channel 2:
This output pin will pulse "high" whenever the Receive Section of Channel 2
has received a "Positive Polarity" pulse, in the incoming line signal, at the
RTIP/RRing inputs.
NOTE: Note: If the B3ZS/HDB3 Decoder (within Channel 2) is "enabled" then
the "zero suppression" patterns, in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") will not be reflected at this output.
51
RNEG2
O
Receive Negative Pulse Output - Channel 2:
This output pin will pulse "high" whenever the Receive Section of Channel 2
has received a "Negative Polarity" pulse, in the incoming line signal, at the
RTIP/RRing inputs.
NOTE: Note: If the B3ZS/HDB3 Decoder (within Channel 2) is "enabled" then
the "zero suppression" patterns, in the incoming line signal (such as: "00V",
"000V", "B0V", "B00V") will not be reflected at this output.
52
RxClk2
O
Receive Clock Output pin - Channel 2:
This output pin is the Recovered Clock signal from the incoming line signal,
which is being received via Channel 2. The receive section of Channel 2 will
output data via the RPOS2 and RNEG2 output pins, on the rising edge of this
clock signal.
NOTE: The user can configure the Receive Section of Channel 2 to update the
data on the RPOS2 and RNEG2 output pins, on the falling edge of RxClk2, by
doing one of the following:
1. If the XRT7302 is operating in the Hardware Mode
Pulling the "RClkINV" pin (pin 42) to "high".
2. If the XRT7302 is operating in the Host Mode
Writing a "1" into the "RClk(n)INV" bit-field within the Command Register.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
53
LOSMUTEN
I
DESCRIPTION
MUTE-upon-LOS Enable Input (Hardware Mode):
This input pin permits the user to configure the XRT7302 (while it is operating
in the "Hardware Mode") to MUTE the recovered data (via the RPOS1,
RNEG1, RPOS2 and RNEG2 output pins), whenever the corresponding
Channel declares an LOS conditions.
Setting this input pin "high" will configure Channel 1 to automatically pull the
RPOS1 and RNEG1 output pins to "GND", whenever it is declaring an LOS
condition (thereby MUTing the data being output to the Terminal Equipment).
Similarly, Channel 2 will automatically pull the RPOS 2 and RNEG2 output
pins to "GND" whenever it is declaring an LOS condition.
Setting this input pin "low" configures Channels 1 and 2 to NOT automatically
MUTE the recovered data, whenever an LOS condition is declared.
NOTES:
1. This pin will be ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is to be operated
in the "Host" Mode.
3. This pin is internally pulled "High".
54
DVDD
****
Receive Digital VDD - Channel 2
55
AGND
****
Analog Ground (Substrate Connection) - Channel 2
56
DGND
****
Transmit Digital GND - Channel 2
57
DMO2
O
Drive Monitor Output - Channel 2:
If no transmitted AMI signal is present on the MTIP2 and MRing2 input pins for
128±32 TxClk periods, then DMO2 will toggle and remain "high" until the next
AMI signal is detected.
58
DVDD
****
59
TAOS2
I
Transmit Digital VDD - Channel 2
Transmit All Ones Select - Channel 2:
A "high" on this pin causes the Transmit Section, within Channel 2 to generate
and transmit a continuous AMI "All 1s" pattern to be transmitted onto the line.
The frequency of this "1s" pattern is determined by TxClk2.
NOTES:
1. This input pin is ignored if the XRT7302 is operating in the "Host"
Mode.
2. The user should tie this pin to GND, if the XRT7302 is going to be
operating in the "Host" Mode.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
60
TxLEV2
I
DESCRIPTION
Transmit Line Build-Out Enable/Disable Select - Channel 2:
This input pin permits the user to enable or disable the Transmit Line Build-Out
circuit, within Channel 2 of the XRT7302.
Setting this pin to "HIGH" disables the Line Build-Out circuit within Channel 2.
In this mode, Channel 2 will output unshaped (e.g., square-wave) pulses onto
the line via the TTIP2 and TRing2 output pins.
Setting this pin to "LOW" enables the Line Build-Out circuit within Channel 2.
In this mode, Channel 2 will output shaped pulses onto the line via the TTIP2
and TRing2 output pins.
In order to comply with the "Isolated DSX-3/STSX-1 Pulse Template Requirements (per Bellcore GR-499-CORE or Bellcore GR-253-CORE), the user
should:
a. Set this input pin to "1", if the cable length (between the Cross-Connect
and the transmit output of Channel 2) is greater than 225 feet.
b. Set this input pin to "0", if the cable length (between the Cross-Connect
and the transmit output of Channel 2) is less than 225 feet.
This pin is active only if the following two conditions are true:
a. The XRT7302 is configured to operate in either the DS3 or SONET
STS-1 Modes.
b. The XRT7302 is configured to operate in the "Hardware" Mode.
NOTE: The user should tie this pin to GND if the XRT7302 is going to be operating in the "Host" Mode.
61
TxOFF2
I
Transmitter OFF Input - Channel 2:
Setting this input pin "high" configures the XRT7302 to turn off the Transmit
Section within Channel 2. In this mode, the TTIP2 and TRing2 outputs will be
tri-stated.
NOTES:
1. This input pin controls the TTIP2 and TRING2 outputs, even when the
XRT7302 is operating in the "Host" Mode.
2. For Host Mode Operation, the user should tie this pin to GND, to turnON/turn-OFF the Transmitter via the Microprocessor Serial Interface.
62
TxClk2
I
Transmit Clock Input for TPData2 and TNData2 - Channel 2:
This input pin must be driven at 34.368 MHz (for E3 applications), 44.736 MHz
(for DS3 applications), or 51.84 MHz (for SONET STS-1 applications). The
Transmit Section of Channel 2 will use this signal to sample the TPData2 and
TNData2 input pins. By default, Channel 2 will be configured to sample these
two pins on the falling edge of this signal.
If the XRT7302 is operating in the "Host" Mode, then Channel 2 can be configured to sample the TPData2 and TNData2 input pins on either the rising or
falling edge of TxClk2.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
63
TPData2
I
DESCRIPTION
Transmit Positive Data Input - Channel 2:
The Transmit Section of Channel 2 will sample this pin, on the falling edge of
TxClk2. If the Channel samples a "1" at this input pin, then it will generate and
transmit a "positive" polarity pulse to the line.
NOTES:
1. The data should be applied to this input pin if the "Transmit Section" is
configured to accept Single-Rail data from the Terminal Equipment.
2. If the XRT7302 is operating in the "Host" Mode, then the user can (if
desired) configure Channel 2 to sample the TPData2 pin on either the
rising or falling edge of TxClk2.
64
TNData2
I
Transmit Negative Data Input - Channel 2:
The Transmit Section of Channel 2 will sample this pin, on the falling edge of
TxClk2. If the device samples a "1" at this input pin, then it will generate and
transmit a "negative" polarity pulse to the line.
NOTES:
1. This input pin will be ignored and should be tied to GND, if the Transmit Section is configured to accept "Single-Rail" data from the Terminal Equipment.
2. If the XRT7302 is operating in the "Host" Mode, then the user can (if
desired) configure Channel 2 to sample the TNData2 pin on either the
rising or falling edge of TxClk2.
65
MTIP2
I
Monitor Tip Input - Channel 2:
The bipolar line output signal, from TTIP2 can be connected to this pin, via a
270-ohm resistor, in order to check for line driver failure. This pin is internally
pulled "high".
66
MRing2
I
Monitor Ring Input - Channel 2:
The bipolar line output signal, from TRing2 can be connected to this pin, via a
270-ohm resistor, in order to check for line driver failure. This pin is internally
pulled "high".
67
AVDD
****
Transmit Analog VDD - Channel 2:
68
TTIP2
O
Transmit TTIP Output - Channel 2:
The XRT7302 will use this pin, along with TRing2, to transmit a bipolar line
signal, via a 1:1 transformer.
69
TRing2
O
Transmit Ring Output - Channel 2:
The XRT7302 will use this pin, along with TTIP2, to transmit a bipolar line signal, via a 1:1 transformer.
70
AGND
****
Transmit Analog GND - Channel 2
71
AGND
****
Transmit Analog GND - Channel 1
72
TRing1
O
Transmit Ring Output - Channel 1:
The XRT7302 will use this pin, along with TTIP1, to transmit a bipolar line signal, via a 1:1 transformer.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
73
TTIP1
O
DESCRIPTION
Transmit TTIP Output - Channel 1:
The XRT7302 will use this pin, along with TRing1, to transmit a bipolar line
signal, via a 1:1 transformer.
74
AVDD
****
75
MRing1
I
Transmit Analog VDD - Channel 1
Monitor Ring Input - Channel 1:
The bipolar line output signal, from TRing1 can be connected to this pin, via a
270-ohm resistor, in order to check for line driver failure. This pin is internally
pulled "high".
76
MTIP1
I
Monitor Tip Input - Channel 1:
The bipolar line output signal, from TTIP1 can be connected to this pin, via a
270-ohm resistor, in order to check for line driver failure. This pin is internally
pulled "high".
77
TNData1
I
Transmit Negative Data Input - Channel 1:
The XRT7302 will sample this pin, on the falling edge of TxClk1. If the device
samples a "1" at this input pin, then it will generate and transmit a "negative"
polarity pulse to the line.
NOTES:
1. This input pin will be ignored and should be tied to GND, if the Transmit Section is configured to accept "Single-Rail" data from the Terminal Equipment.
2. If the XRT7302 is operating in the "Host" Mode, then the user can (if
desired) configure the XRT7302 to sample the TNData pin on either
the rising or falling edge of TxClk.
78
TPData1
I
Transmit Positive Data Input - Channel 1
The XRT7302 will sample this pin, on the falling edge of TxClk. If the device
samples a "1" at this input pin, then it will generate and transmit a "positive"
polarity pulse to the line.
NOTES:
1. The data should be applied to this input pin if the "Transmit Section" is
configured to accept Single-Rail data from the Terminal Equipment.
2. If the XRT7302 is operating in the "Host" Mode, then the user can (if
desired) configure the XRT7302 to sample the TPData pin on either
the rising or falling edge of TxClk.
79
TxClk1
I
Transmit Clock Input for TPData and TNData - Channel 1:
This input pin must be driven at 34.368 MHz (for E3 applications), 44.736 MHz
(for DS3 applications), or 51.84 MHz (for SONET STS-1 applications). The
XRT7302 will use this signal to sample the TPData and TNData input pins. By
default, the XRT7302 will be configured to sample these two pins on the falling
edge of this signal.
If the XRT7302 is operating in the "Host" Mode, then the device can be configured to sample the TPData and TNData input pins on either the rising or falling
edge of TxClk.
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
PIN DESCRIPTION
PIN #
SIGNAL NAME
TYPE
80
TxOFF1
I
DESCRIPTION
Transmitter OFF Input - Channel 1:
Setting this input pin "high" configures the XRT7302 to turn off the Transmit
Section within Channel 1. In this mode, the TTIP1 and TRing1 outputs will be
tri-stated.
NOTES:
1. This input pin controls the TTIP1 and TRING2 outputs, even when the
XRT7302 is operating in the "Host" Mode.
2. For Host Mode Operation, the user should tie this pin to GND, to turnON/turn-OFF the Transmitter via the Microprocessor Serial Interface.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 650C to + 1500C
Operating Temperature
- 400C to + 850C
Supply Voltage Range
-0.5V to +6.0V
Theta-JA
23° C/W
Theta-JC
5.32° C/W
NOTE: The XRT7302 is assembled in a thermally enhanced
package with an intergral Copper Heat Slug. The heat Slug
is solder plated on the bottom of the package and is electri-
cally connected to the Ground connections of the device.
This Heat Slug can be soldered to the mounting board if
desired, but must be isolated from any VDD connections.
ELECTRICAL CHARACTERISTICS (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
DC Electrical Characteristics
VDDD
DC Supply Voltage (Digital)
4.75
5
5.25
V
VDDA
DC Supply Voltage (Analog)
4.75
5
5.25
V
335
360
400
440
mA
mA
0.8
V
2.0
VDD
V
ICC
Supply Current (Measured while Transmitting and Receiving all "1s"
DS3 Mode
STS-1 Mode
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage, IOUT = -4.0mA
0
0.4
V
VOH
Output High Voltage, IOUT = 4.0mA
2.8
VDD
V
±10
µA
IL
Input Leakage Current*
NOTE: * Not applicable to pins with pull-down resistors.
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
AC ELECTRICAL CHARACTERISTICS (SEE ƒIGURE 1)
TERMINAL SIDE TIMING PARAMETERS (SEE ƒIGURE 2 AND ƒIGURE 3)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
TxClk1, TxClk2 Clock Duty Cycle (DS3/STS-1)
30
50
70
%
TxClk1, TxClk2 Clock Duty Cycle (E3)
30
50
70
%
TxClk1, TxClk2 Frequency (SONET STS-1)
51.84
MHz
TxClk1, TxClk2 Frequency (DS3)
44.736
MHz
TxClk1, TxClk2 Frequency (E3)
34.368
MHz
tRTX
TxClk1, TxClk2 Clock Rise Time (10% to 90%)
4.0
ns
tFTX
TxClk1, TxClk2 Clock Fall Time (90% to 10%)
4.0
ns
tTSU
TPData/TNData to TxClk1, 2 Falling Set up time
3.0
ns
tTHO
TPData/TNData to TxClk1, 2 Falling Hold time
3.0
ns
tLCVO
RxClk1, 2 to rising edge of LCV1, 2 output delay
tTDY
TTIP1, 2/TRing1, 2 to TxClk1, 2 Rising Propagation Delay time
0.6
RxClk1, RxClk2 Clock Duty Cycle
45
2.5
50
ns
14.0
ns
55
%
RxClk1, RxClk2 Frequency (SONET STS-1)
51.84
MHz
RxClk1, RxClk2 Frequency (DS3)
44.736
MHz
RxClk1, RxClk2 Frequency (E3)
34.368
MHz
tCO
RxClk1, 2 to RPOS1, 2/RNEG1, 2 Delay Time
tRRX
RxClk1, RxClk2 Clock Rise Time (10% to 90%)
tFRX
RxClk1, RxClk2 Clock Fall Time (10% to 90%)
4.0
ns
2.0
4.0
ns
1.5
3.0
ns
CI
Input Capacitance
10
pF
CL
Load Capacitance
10
pF
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
FIGURE 1. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL
SHOWN)
Channel (n)
R1
TTIP(n)
TxPOS(n)
TPOS(n)
TxNEG(n)
TNEG(n)
TxLineClk(n)
TxClk(n)
36 Ω
R3
75 Ω
R2
TRing(n)
36 Ω
FIGURE 2. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
t RTX
t FTX
TClk
t TSU
tT H O
TPDATA or
TNDATA
TTIP or
TRING
t TDY
FIGURE 3. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
t RRX
t FRX
RClk
t LCVO
LCV
tC O
RPOS or
RNEG
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T1
1:1
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS E3 APPLICATION
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
Transmit Output Pulse Amplitude
(Measured at Secondary Output of Transformer, see Figure 1)
0.9
1.0
1.1
Vpk
Transmit Output Pulse Amplitude Ratio
0.95
1.00
1.05
Transmit Output Pulse Width
12.5
14.55
16.5
Transmit Output Pulse Width Ratio
0.95
1.00
1.05
0.02
0.05
TRANSMIT CHARACTERISTICS (SEE ƒIGURE 2)
Transmit Output Jitter with jitter-free input @ TxClk(n)
ns
UIpp
Receive Line Characteristics (See ƒigure 3)
Receive Sensitivity (Length of cable)
1100
Interference Margin
-20
feet
-17
Signal Level to Declare Loss of Signal
dB
-35
dB
Signal Level to Clear Loss of Signal
-15
dB
Occurrence of LOS to LOS Declaration Time
10
100
255
UI
Termination of LOS to LOS Clearance Time
10
100
255
UI
Intrinsic Jitter (all “Ones” Pattern)(1)
0.01
UI
Intrinsic Jitter (all “100” Pattern)
0.03
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1kHz
30
UI
Jitter Tolerance @ Jitter Frequency = 10kHz
4
UI
Jitter Tolerance @ Jitter Frequency = 800kHz
0.15
UI
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS SONET STS-1 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 2)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
Transmit Output Pulse Amplitude
(Measured with TxLEV=0, see Figure 1)
0.68
0.75
0.85
Vpk
Transmit Output Pulse Amplitude
(Measured with TxLEV=1, see Figure 1)
0.93
0.98
1.08
Vpk
Transmit Output Pulse Width
8.6
9.65
10.6
ns
Transmit Output Pulse Amplitude Ratio
0.9
1.0
1.1
0.02
0.05
Transmit Output Jitter with jitter-free input @ TxClk(n)
Receive Line Characteristics (See Figure 3)
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UI
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS SONET STS-1 APPLICATION
TRANSMIT CHARACTERISTICS (SEE FIGURE 2)
SYMBOL
PARAMETER
MIN.
Receive Sensitivity (Length of Table)
TYP.
MAX
UNITS
900
feet
Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN =
1)
Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 1)
75
mV
270
mV
Signal Level to Declare Loss of Signal
(LOSTHR = 1, REQ_IN = 1)
25
Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 1)
110
mV
Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN =
0)
Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 0)
55
mV
210
mV
Signal Level to Declare Loss of Signal (LOSTHR = 1, REQ_IN =
0)
Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 0)
mV
90
mV
90
mV
Intrinsic Jitter (all “Ones” Pattern)(2)
0.03
UI
Intrinsic Jitter (all “Ones” Pattern)
0.03
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1kHz
64
UI
Jitter Tolerance @ Jitter Frequency = 10kHz
5
UI
Jitter Tolerance @ Jitter Frequency = 800kHz
0.4
UI
(2) Measured at nominal STSX-1 level with equalizer
enabled, VDD = 5V and TA = 25°C
(1) Measured with Equalizer enabled, 12db Cable
attenuation, VDD = 5V and TA = 25°C
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS DS3 APPLICATION
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
Transmit Output Pulse Amplitude
(Measured a 0 feet, TxLEV=0, see Figure 1)
0.68
0.75
0.85
Vpk
Transmit Output Pulse Amplitude
(Measured a 0 feet, TxLEV=1, see Figure 1)
0.9
1.0
1.1
Vpk
10.10
11.18
12.28
ns
0.9
1.0
1.1
0.02
0.05
TRANSMIT CHARACTERISTICS (SEE ƒIGURE 2)
Transmit Output Pulse Width
Transmit Output Pulse Amplitude Ratio
Transmit Output Jitter with jitter-free input @ TxClk(n)
Receive Line Characteristics (See ƒigure 3)
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UI
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 5V + 5%, UNLESS OTHERWISE SPECIFIED)
LINE SIDE PARAMETERS DS3 APPLICATION
SYMBOL
PARAMETER
MIN.
Receive Sensitivity (Length of Cable)
900
TYP.
MAX
UNITS
feet
Receive Intrinsic Jitter (All One’s Pattern)
0.01
UI
Receive Intrinsic Jitter (Using PRBS 223-1 Pattern)
0.02
UI
Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN =
1)
Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 1)
55
220
mV
Signal Level to Declare Loss of Signal
(LOSTHR = 1, REQ_IN = 1)
22
Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 1)
90
35
155
17
70
Intrinsic Jitter (all “Ones” Pattern)
mV
mV
0.01
Intrinsic Jitter (all “100” Pattern)(1)
mV
mV
Signal Level to Declare Loss of Signal (LOSTHR = 1, REQ_IN =
0)
Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 0)
mV
mV
Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN =
0)
Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 0)
mV
UI
UI
Jitter Tolerance @ Jitter Frequency = 1kHz
64
UI
Jitter Tolerance @ Jitter Frequency = 10kHz
5
UI
Jitter Tolerance @ Jitter Frequency = 800kHz
0.4
UI
(1) Measured at nominal DSX3 level, Equalizer enabled, VDD = 5V, TA = 25°C
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 5 + 5%, UNLESS OTHERWISE SPECIFIED)
MICROPROCESSOR SERIAL INTERFACE TIMING (SEE ƒIGURE 5)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
t21
CS Low to Rising Edge of SClk Setup Time
50
ns
t22
CS High to Rising Edge of SClk Hold Time
20
ns
t23
SDI to Rising Edge of SClk Setup Time
50
ns
t24
SDI to Rising Edge of SClk Hold Time
50
ns
t25
SClk "Low" Time
240
ns
t26
SClk "High" Time
240
ns
t27
SClk Period
500
ns
t28
CS Low to Rising Edge of SClk Hold Time
50
ns
t29
CS "Inactive" Time
250
ns
t30
Falling Edge of SClk to SDO Valid Time
200
ns
t31
Falling Edge of SClk to SDO Invalid Time
100
ns
t32
Falling Edge of SClk, or rising edge of CS to High Z
t33
Rise/Fall time of SDO Output
100
ns
40
ns
FIGURE 4. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
A4
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
High Z
High Z
SDO
3. R/W = "0" for "Write" Operations
NOTES:
1. A4 and A5 are always "0".
4. A shaded pulse, denotes a “don’t care” value.
2. R/W = "1" for "Read" Operations
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 5. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SCLK
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SCLK
t31
t30
SDO
SDI
Hi-Z
D0
t33
Hi-Z
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t32
D2
D1
D7
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
SYSTEM DESCRIPTION
The XRT7302 can be configured to operate in either
the "Hardware" Mode or the "Host" Mode. Each of
these modes will be discussed below.
A functional block diagram of the XRT7302 E3/DS3/
STS-1 Transceiver IC is presented in Figure 6. In
general, the XRT7302 contains three distinct sections:
THE HARDWARE MODE
When the XRT7302 is operating in the "Hardware
Mode", then the following is true.
• The Transmit Section - Channels 1 and 2
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT7302 is configured via input pin settings.
The XRT7302 can be configured to operate in the
"Hardware Mode" by tying the "Host/HW" input pin
(pin 8) to GND.
• The Receive Section - Channels 1 and 2
• The Microprocessor Serial Interface
Each of these sections are briefly discussed below.
THE TRANSMIT SECTION (CHANNELS 1 AND 2)
The Transmit Section, within each Channel, accepts
TTL/CMOS level signals from the "Terminal Equipment" in either a "Single-Rail" or "Dual Rail" format.
The Transmit Section will then take this data and do
the following.
Each of the pins associated with the Microprocessor
Serial Interface will take on their alternative role, as
defined in Table 1.
• Encode this data into the B3ZS format (if the DS3
or SONET STS-1 Modes have been selected) or
into the HDB3 format (if the E3 Mode has been
selected).
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE
PINS WHEN THE XRT7302 IS OPERATING IN THE
"HARDWARE" MODE
• Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
PIN #
PIN NAME
17
CS/(ENDECDIS)
ENDECDIS
18
SClk/(RxOFF2)
RxOFF2
19
SDI/(RxOFF1)
RxOFF1
20
SDO/(E3_CH1)
E3_CH1
42
REGR/(RClkINV)
RCKLKINV
• Drive these pulses onto the line via the TTIP and
TRing output pins, across a 1:1 Transformer.
NOTE: Note: The Transmit Section will drive a "1" (or a
"Mark") onto the line by driving either a positive or negative
polarity pulse across the 1:1 Transformer, within a given bit
period. The Transmit Section will drive a "0" (or a "Space")
onto the line by driving no pulse onto the line.
MODE
Additionally, when the XRT7302 is operating in the
"Hardware" Mode, all of the remaining input pins become active.
THE RECEIVE SECTION (CHANNELS 1 AND 2)
The Receive Section, within each Channel, receives
a bipolar signal from the line, through the RTIP and
RRing pins via a "1:1 Transformer" or via a "0.01µF
Capacitor". The Receive Section will do the following.
THE HOST MODE
The XRT7302 can be configured to operate in the
"Host" Mode by tying the "Host/HW" input pin (pin 8)
to VDD.
• Adjust the signal level through an AGC circuit.
When the XRT7302 is operating in the "Host Mode",
then the following is true.
• Optionally equalize this signal for cable loss.
• The "sliced" data will be routed to the "HDB3/B3ZS"
Decoder; during which the data content (as transmitted by the Remote Terminal Equipment) is
restored to its original content.
1. The Microprocessor Serial Interface block is
enabled. Writing the appropriate data into the
on-chip Command Registers makes many configuration selections.
• The recovered clock and data will be output to the
"Local Terminal Equipment", in the form of CMOS
level signals, via the RPOS, RNEG, RxClk1 and
RxClk2 output pins.
• Pin 1 - TxLEV1
THE MICROPROCESSOR SERIAL INTERFACE
• Pin 21 - STS-1/DS3_Ch1
2. All of the following input pins are disabled.
• Pin 2 - TAOS1
• Pin 24 - LLB1
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FUNCTION, WHILE IN HARDWARE
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
• Pin 25 - RLB1
The user is advised to tie each of these pins to GND
to operate the XRT7302 IC in the "Host" Mode.
• Pin 30 - REQEN1
In Host Mode Operation, the “TxOFF1” and “TxOFF2”
input pins can still be used to turn on or turn off the
“Transmit Output Drivers” within Channels 1 and 2,
respectively. The intent behind this feature is to permit a system (designed for redundancy) to quickly
switch out a defective line card, and switch-in the
back-up line card.
• Pin 31 - REQEN2
• Pin 36 - RLB2
• Pin 37 - LLB2
• Pin 39 - E3_Ch2
• Pin 41 - STS-1/DS3_Ch2
• Pin 59 - TAOS2
The remainder of this document presents a detailed
description of the features associated with the
XRT7302.
• Pin 60 - TxLEV2
FIGURE 6. FUNCTIONAL BLOCK DIAGRAM OF THE XRT7302
E3_Ch(n)
RTIP(n)
RRing(n)
STS-1/DS3_Ch(n)
AGC/
Equalizer
REQEN(n)
Host/HW
RLOL(n) ExClk(n)
RxClkINV
Clock
Recovery
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
Slicer
Data
Recovery
Peak Detector
RxOFF(n)
LOS Detector
LOSTHR(n)
RNEG(n)
LCV(n)
ENDECDIS
SDI
SDO
SClk
CS
RLOS(n)
Serial
Processor
Interface
LLB(n)
Loop MUX
RLB(n)
REGR
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TRing(n)
MTIP(n)
MRing(n)
TAOS(n)
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
Device
Monitor
Tx
Control
TxClk(n)
TxLEV(n)
TxOFF(n)
Channel 1
DMO(n)
Channel 2
Notes: 1. (n) = 1 or 2 for the respective channel.
2. Serial Processor Interface pins are shared by both Channels in Host Mode and are redefined in Hardware Mode.
1.0 SELECTING THE DATA RATE
The XRT7302 permits the user to select the data rate
(for each Channel) via one of two ways.
Each channel within the XRT7302 can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Further,
each channel can be configured to operate in a
mode/data rate that is independent of the other channel.
1.1 CONFIGURING CHANNEL 1
a. When operating in the "Hardware" Mode.
In order to configure Channel 1 into the appropriate
mode, the user must set the "E3_Ch1", and the
"STS-1/DS3_Ch1 input pins to the appropriate logic
states, as presented below in Table 2.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
TABLE 2: SELECTING THE DATA RATE FOR CHANNEL 1, (WITHIN THE XRT7302), VIA THE "E3_CH1" AND "STS-1/
DS3_CH1" INPUT PINS (HARDWARE MODE)
STATE OF E3_CH1 PIN
(PIN 20)
STATE OF STS-1/(DS3_CH1)
PIN
(PIN 21)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps)
1
X (Don't Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
STS-1 (51.84 Mbps)
0
1
B3ZS
DATA RATE
By making these selections, the user is doing the
following:
b. When operating in the "Host" Mode.
In order to configure Channel 1 into the appropriate
mode, the user must write the appropriate values into
the "STS-1/DS3_Ch1" and "E3_Ch1" bit-fields, within
Command Register CR4, as illustrated below.
• Configuring the VCO Center Frequency of the
Clock Recovery Phase-Locked-Loop (within Channel 1) to match the selected data rate.
• Configuring the "B3ZS/(HDB3)" Encoder and
Decoder blocks to support B3ZS Encoding/Decoding, if the DS3 or STS-1 data rates were selected;
or
COMMAND REGISTER, CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/(DS3_Ch1)
E3_Ch1
LLB1
RLB1
x
x
x
x
x
• Configuring the "B3ZS/(HDB3)" Encoder and
Decoder blocks to support HDB3 Encoding/Decoding, if the E3 data rate was selected.
Table 3 relates the values of these two bit-fields to the
selected data rates.
• Configuring the on-chip "Pulse-Shaping" circuitry to
generate Transmit Output pulses, of the appropriate
shape and width to meet the applicable pulse template requirement.
TABLE 3: SELECTING THE DATA RATE FOR CHANNEL 1
(WITHIN THE XRT7302); VIA THE "STS-1/DS3_CH1"
AND THE "E3_CH1" BIT-FIELDS, WITHIN COMMAND
REGISTER CR4 (HOST MODE)
SELECTED
DATA RATE
STS-1/(DS3_CH1)
(D3)
"E3_CH1" (D2)
E3
X (Don't Care)
1
DS3
0
0
STS-1
1
0
• Establishes the LOS Declaration/Clearance Criteria
(for Channel 1). (See section 3.6)
1.2 CONFIGURING CHANNEL 2
a. When operating in the "Hardware" Mode
In order to configure Channel 2 into the appropriate
mode, the user must set the “E3_Ch2” and the
“STS-1/(DS3_Ch2)” input pins to the appropriate
logic states as presented below in Table 4.
TABLE 4: SELECTING THE DATA RATE FOR CHANNEL 2 (WITHIN THE XRT7302) VIA THE "E3_CH2" AND "STS-1/
DS3_CH2" INPUT PINS (HARDWARE MODE)
STATE OF E3_CH2 PIN
(PIN 39)
STATE OF STS-1/
(DS3_CH2) PIN
(PIN 41
MODE OF B3ZS/(HDB3) ENCODER/DECODER
BLOCKS
E3 (34.368 Mbps)
1
X (Don't Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
STS-1 (51.84 Mbps)
0
1
B3ZS
DATA RATE
b. When operating in the "Host" Mode.
In order to configure Channel 2 into the appropriate
mode, the user must write the appropriate values into
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
the "STS-1/(DS3_Ch2)" and "E3_Ch2" bit-fields, within Command Register CR12, as illustrated below.
Table 5 relates the values of these two bit-fields to the
selected data rates.
COMMAND REGISTER, CR12 (ADDRESS = 0X0C)
D4
D3
D2
D1
D0
X
STS-1(/DS3_Ch2)
E3_Ch2
LLB2
RLB2
x
x
x
x
x
TABLE 5: SELECTING THE DATA RATE FOR CHANNEL 2 (WITHIN THE XRT7302) VIA THE "E3_CH2" AND "STS-1/
DS3_CH2" BIT FIELDS, WITHIN COMMAND REGISTER CR4 (HOST MODE)
STATE OF E3_CH2 PIN
(PIN 39)
STATE OF STS-1/
(DS3_CH2) PIN
(PIN 41
MODE OF B3ZS/(HDB3) ENCODER/DECODER
BLOCKS
E3 (34.368 Mbps)
1
X (Don't Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
STS-1 (51.84 Mbps)
0
1
B3ZS
DATA RATE
• Pulse Shaping Block
By making these selections, the user is doing the
following:
Each of these blocks will be discussed in some detail
below
• Configuring the VCO Center Frequency of the
Clock Recovery Phase-Locked-Loop (within Channel 2) to match the selected data rate.
In general, the purpose of the "Transmit Section",
within each Channel of the XRT7302, is to take TTL/
CMOS level data, from the terminal equipment, and
encode it into a format such that it can:
• Configuring the "B3ZS/(HDB3)" Encoder and
Decoder blocks to support B3ZS Encoding/Decoding, if the DS3 or STS-1 data rates were selected;
or
1. Be efficiently transmitted over coaxial cable; at
E3, DS3, or STS-1 data rates; and
• Configuring the "B3ZS/(HDB3)" Encoder and
Decoder blocks to support HDB3 Encoding/Decoding, if the E3 data rate was selected.
2. Be reliably received by the Remote Terminal
Equipment at the other end of the E3, DS3, or
STS-1 data link.
• Configuring the on-chip "Pulse-Shaping" circuitry to
generate Transmit Output pulses, of the appropriate
shape and width to meet the applicable pulse template requirement.
3. Comply with the applicable pulse template
requirements.
The circuitry that the Transmit Section, (within each
Channel of the XRT7302) takes to accomplish this
goal is discussed below.
• Establishes the LOS Declaration/Clearance Criteria
(for Channel 2). (See section 3.6)
NOTE: The following discussion applies equally to both
Channels 1 and 2. Hence, the Transmit Section signals will
be referred to via their generic rates (e.g., TxClk) as
opposed to "TxClk1" and "TxClk2".
NOTE: The user is required to apply the appropriate clock
signals to both the EXClk1 and EXClk2 input pins, in order
for the "Receive Sections" (of Channels 1 and 2) to function
properly.
2.1 THE TRANSMIT LOGIC BLOCK
2.0 THE TRANSMIT SECTION
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single Rail (e.g., a binary data
stream) TTL/CMOS level data and timing information
from the Terminal Equipment.
Figure 6 indicates that the Transmit Section, within
each Channel of the XRT7302 consists of the following blocks:
• Transmit Logic Block
2.1.1 Accepting "Dual-Rail" Data from the Terminal Equipment
• The TxClk Duty Cycle Adjust Block
• HDB3/(B3ZS) Encoder
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
• TxClk
Whenever the XRT7302 accepts dual-rail data from
the Terminal Equipment, it does so via the following
input signals.
Figure 7 presents an illustration of the typical interface for the transmission of data in a "Dual-Rail" Format between the Terminal Equipment and the Transmit Section of the XRT7302.
• TPData
• TNData
FIGURE 7. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL RAIL FORMAT, FROM THE "TRANSMITTING" TERMINAL EQUIPMENT TO THE "TRANSMIT SECTION" OF A CHANNEL WITHIN
THE XRT7302
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
TxPOS
TPData
TxNEG
TNData
TxLineClk
TxClk
Transmit
Logic
Block
XRT7302 E3/DS3/STS-1 LIU
The manner that the LIU handles "Dual-Rail" data is
described below and is illustrated in Figure 8. The
Transmit Section (of a Channel) will typically sample
the data on the TPData and TNData input pins on the
falling edge of TxClk.
FIGURE 8. ILLUSTRATION ON HOW THE XRT7302 SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT
PINS
Data
1
1
0
TPData
TNData
TxClk
1:1 transformer). Conversely, if the Transmit Section
samples a "1" on the TNData input pin, then the
"Transmit Section" of the device will ultimately generate a negative polarity pulse via the TTIP and TRing
output pins (across a 1:1 transformer).
TxClk is typically a clock signal that is of the selected
data rate frequency. For the E3 data rate, TxClk is
34.368 MHz. For the DS3 data rate, TxClk is 44.736
MHz, and for the SONET STS-1 rate, TxClk is 51.84
MHz. If the Transmit Section samples a "1" on the
TPData input pin, then the "Transmit Section" of the
device will ultimately generate a positive polarity
pulse via the TTIP and TRing output pins (across a
2.1.2 Accepting "Single-Rail" Data from the
Terminal Equipment
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
If the user wishes to transmit data from the "Terminal
Equipment" to the Transmit Section within a given
channel in a "single-rail" format (e.g., a binary data
stream), without having to convert it into a "dual-rail"
format; the user can do the following.
COMMAND REGISTER 9 (ADDRESS = 0X09)
a. Configure the XRT7302 to operate in the "Host"
Mode.
b. Access the Microprocessor Serial Interface, and
execute the following steps, for each Channel.
D4
D3
D2
D1
D0
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
x
x
x
x
1
NOTE: Executing this write operating to Command Register
CR9 will not configure the Transmit Section (within Channel
2) to accept Single-Rail data from the Terminal Equipment.
To Configure Channel 1 to accept Single-Rail Data
from the Terminal Equipment:
The Transmit Section (of each channel) will sample
this input pin on the "falling" edge of the TxClk clock
signal, and will encode this data into the appropriate
bipolar line signal across the TTIP and TRing output
pins.
Write a "1" into the "TxBIN1" (TRANSMIT BINary) bitfield, within Command Register 1 (for Channel 1), as
depicted below.
COMMAND REGISTER 1 (ADDRESS = 0X01)
NOTES:
D4
D3
D2
D1
D0
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
x
x
x
x
1
1. In this mode, the Transmit Logic Block will ignore
the TNData input pin.
2. If the user configures the Transmit Section (within a
given channel) to accept "Single-Rail" data from the
Terminal Equipment, then the user must enable the
"B3ZS/HDB3" Encoder.
NOTE: Executing this write operating to Command Register
1 will not configure the Transmit Section (within Channel 2)
to accept "Single-Rail" data from the Terminal Equipment.
Figure 9 Illustrates the behavior of the TPData and
TxClk signals, when the Transmit Logic Block has
been configured to accept "single-rail" data from the
Terminal Equipment
To Configure Channel 2 to accept Single-Rail Data
from the Terminal Equipment:
Write a "1" into the "TxBIN2" bit-field, within Command Register 9 (for Channel 2), as depicted below.
FIGURE 9. ILLUSTRATION OF THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT
LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
TPData
TxClk
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
could jeopardize the chip's ability to generate Transmit Output pulses of the appropriate width, and thereby failing the applicable "Pulse Template" requirement
specification. As consequence, the chip's ability to
generate compliant pulses could depend upon the
duty cycle of the clock signal, applied to the TxClk input pin.
CUITRY
The on-chip "Pulse-Shaping" circuitry (within the
Transmit Section of each Channel in the XRT7302)
generates pulses of the appropriate shapes and
width, in order to meet the applicable pulse template
requirement. The widths of these "output" pulses are
defined by the width of the "half-period" pulses within
the TxClk signal.
The Transmit Clock Duty Cycle Adjust Circuitry accepts clock pulses from the TxClk input pin with duty
cycles ranging from 30% to 70%, and to regenerate
these signals at a 50% duty cycle.
However, if the widths of the pulses, within the TxClk
clock signal are allowed to vary significantly, this
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
Where:
2.3 THE HDB3/B3ZS ENCODER BLOCK
"B" represents a "Bipolar" pulse that is compliant with
the "Alternating Polarity" requirements of the AMI (Alternate Mark Inversion) line code; and
The purpose of the "HDB3/B3ZS" Encoder Block is to
aid in the "Clock Recovery" process (at the Remote
Terminal Equipment) by ensuring an upper limit on
the number of consecutive zeros that can exist within
the line signal.
2.3.1
"V" represents a "bipolar Violation" (e.g., a "bipolar"
pulse that violates the "Alternating Polarity" requirements of the AMI line code).
B3ZS Encoding
The B3ZS Encoder will decide whether to substitute
with either the "00V" or the "B0V" pattern in order to
insure that an odd number of "bipolar" pulses exist
between any two consecutive "violation" pulses.
If the user has configured the XRT7302 to operate in
the DS3 or SONET STS-1 Modes, then the "HDB3/
B3ZS" Encoder blocks will operate in the "B3ZS"
Mode. When the Encoder is operating in this mode, it
will parse through and search the "Transmit Binary
Data Stream" (from the Transmit Logic Block) for the
occurrence of three (3) consecutive zeros (e.g.,
"000"). If the "B3ZS Encoder" finds an occurrence of
three consecutive zeros, then it will substitute these
three "0s", with either a "00V" or a "B0V" pattern.
Figure 10 illustrates the "B3ZS Encoder" operation,
with two separate strings of three (or more) consecutive zeros.
FIGURE 10. AN EXAMPLE OF B3ZS ENCODING
Data
1
0
1
1
0
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
1
0
0
0
1
TPData
TNData
TxClk
0
0
V
Line Signal
B
2.3.2
HDB3 Encoding
V
then it will substitute these four "0s", with either a
"000V" or a "B00V" pattern. The HDB3 Encoder will
decide whether to substitute with either the "000V" or
the "B00V" pattern in order to insure that an odd number of "bipolar" pulses exist between any two consecutive "violation" pulses.
If the user has configured the XRT7302 to operate in
the "E3 Mode", then the "HDB3/B3ZS" Encoder
blocks will operate in the "HDB3" Mode. When the
Encoder is operating in this mode, it will parse
through and search the "Transmit Data Stream" (from
the Transmit Logic Block) for the occurrence of four
(4) consecutive zeros (e.g., "0000"). If the "HDB3 Encoder" finds an occurrence of four consecutive zeros,
Figure 11 illustrates the "HDB3 Encoder" operation,
with two separate strings of four (or more) consecutive zeros.
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 11. AN EXAMPLE OF HDB3 ENCODING
Data
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
TPData
TNData
TxClk
0
0
0
V
Line Signal
B
2.3.3
Disabling the "HDB3/B3ZS" Encoder
0
0
V
When the XRT7302 is operating in the "Host"
Mode.
The XRT7302 permits the user to disable the "HDB3/
B3ZS" Encoder by two means.
Configuring Channel 1
When the XRT7302 is operating in the "Host" Mode,
then the "HDB3/B3ZS" Encoders (within each channel) can be individually enabled or disabled. The user can disable the "HDB3/B3ZS Encoder" block within
Channel 1 by setting the "ENDECDIS1" bit-field, within Command Register (CR2), to "1" as illustrated below.
When the XRT7302 is operating in the "Hardware"
Mode.
The "HBD3/B3ZS Encoder" blocks (within both channels) are disabled by setting the "ENDECDIS (Encoder/Decoder Disable)" input pin (pin 17) to "0".
NOTE: By executing this step, the user will globally disable
the "HDB3/B3ZS" Encoder and Decoder blocks within each
channel of the XRT7302.
COMMAND REGISTER, CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
X
1
X
X
X
Configuring Channel 2
"ENDECDIS2" bit-field within Command Register
CR10, as illustrated below.
Likewise, the user can disable the "HDB3/B3ZS Encoder" block within Channel 2 by writing a "1" into the
COMMAND REGISTER, CR10 (ADDRESS = 0X0A)
D4
D3
D2
D1
D0
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
X
1
X
X
X
NOTE: Note: This method can only be used if the XRT7302
is operating in the "Host" Mode.
or disabled, by setting the TxLEV input pin (or "TxLEV" bit-field) to "HIGH" or "LOW". The purpose of
the "Transmit Line Build-Out" circuit is to permit the
user to configure each channel within the XRT7302 to
transmit an output pulse which is compliant to either
of the following pulse template requirements (when
measured at the Digital Cross Connect System).
Each of these Bellcore specifications further state
that the cable length (between the Transmit Output
If the user employs either of these two methods to
disable the "HDB3/B3ZS" Encoder, then the LIU will
be transmitting the data, onto the line, as it is received
via the TPData and TNData input pins.
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY
The Transmit Pulse Shaper Circuitry consists of a
Transmit Line Build-Out circuit which can be enabled
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
and the Digital Cross Connect system) can range
anywhere from 0 to 450 feet.
The Isolated DSX-3 Pulse Template Requirement
(per Bellcore GR-499-CORE) is illustrated in
Figure 12.
FIGURE 12. THE "BELLCORE GR-499-CORE" TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
D S 3 P u ls e T e m p la te
1.2
1
N o rm a l iz e d Am p l itu d e
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
2
3
4
1.
9
1.
8
0.
1.
7
0.
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1
6
0.
The Isolated STSX-1 Pulse Template Requirement
(per Bellcore GR-253-CORE), is illustrated in
Figure 13.
1
5
0.
T i m e , in U I
1.
4
0.
3
0.
0.
2
0.
0
1
0.
.2
.3
.4
.5
.6
.7
.8
.9
.1
-0
-0
-0
-0
-0
-0
-0
-0
-0
-1
-0.2
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 13. THE "BELLCORE GR-253-CORE" TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1
APPLICATIONS
ST S-1 Pulse T em p late
1.2
1
Norm a lize d Am plitude
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
3
4
1.
2
1.
9
1.
8
0.
1
7
0.
1
6
0.
1.
5
4
0.
0.
3
0.
0.
2
0.
0
1
0.
.2
.3
.4
.5
.6
.1
-0
-0
-0
-0
-0
.7
-0
.8
-0
-0
-1
-0
.9
-0.2
Tim e , in UI
2.4.1
cuit
Enabling the Transmit Line Build-Out Cir-
• Set the "TxLEV1" bit-field to "0", as illustrated
below.
COMMAND REGISTER, CR1 (ADDRESS = 0X01)
If the user enables the "Transmit Line Build-Out" Circuit, then the "Transmit Section" of the Channel (within the XRT7302) will output shaped pulses onto the
line via the TTIP and TRing output pins.
D4
D3
D2
D1
D0
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
0
X
X
0
X
The user enables the Transmit Line Build-Out circuit
(for each channel within the XRT7302) by doing the
following:
Channel 2
Channel 1
In the "Hardware" Mode
In the "Hardware" Mode
• Set the "TxLEV2" input pin (pin 60) to "LOW".
• Set the "TxLEV1" input pin (pin 1) to "LOW"
In the "Host" Mode
And;
And;
In the "Host" Mode
• Set the "TxLEV2" bit-field to "0", as illustrated
below.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
system (where the pulse template measurements are
made).
COMMAND REGISTER, CR9 (ADDRESS = 0X09)
D4
D3
D2
D1
D0
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0
X
X
0
X
2.4.2
cuit
If the cable length (between the Transmitting Terminal and the DSX-3 or STSX-1) is less than 225
feet
The user is advised to enable the "Transmit Line
Build-Out circuit" by setting the "TxLEV" input pin or
bit-field to "0".
Disabling the Transmit Line Build-Out Cir-
NOTE: In this case, the configured channel (within the
XRT7302) will output shaped (e.g., not square-wave)
pulses onto the line via its TTIP and TRing output pins. The
shape of this output pulse is such that it will comply with the
pulse template requirements even when subjected to cable
loss ranging from 0 to 225 feet.
If the user disables the "Transmit Line Build-Out" circuit, then the XRT7302 will output un-shaped (e.g.,
square-wave) pulses onto the line via the TTIP and
TRing output pins.
If the cable length (between the Transmitting Terminal and the DSX-3 or STSX-1) is greater than
225 feet.
The user is advised to disable the "Transmit Line
Build-Out circuit" by setting the "TxLEV" input pin or
bit-field to "1".
The user disables the Transmit Line Build-Out circuit
(within the XRT7302) by doing the following:
Channel 1
In the "Hardware" Mode.
• Set the "TxLEV1" input pin (pin 1) to "HIGH".
NOTE: In this case, the configured channel (within the
XRT7302) will output un-shaped (e.g., square-wave) pulses
onto the line via the TTIP and TRing output pins. The cable
loss, that these pulses will experience over long cable
lengths (e.g., greater than 225 feet) will cause these pulses
to be "properly shaped" and comply with the appropriate
pulse template requirement.
And;
In the "Host" Mode.
• Set the "TxLEV1" bit-field to "1" as illustrated below.
COMMAND REGISTER, CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
0
X
X
1
X
2.4.4 The Transmit Line Build-Out Circuit and
E3 Applications
The "ITU-T G.703 Pulse Template Requirements for
E3" states that the E3 transmit output pulse should be
measured at the Secondary Side of the Transmit Output Transformer, for "Pulse Template" compliance. In
other words, there is no "Digital Cross Connect System" pulse template requirement for E3. As a consequence, the "Transmit Line Build-Out" circuit, within a
given Channel (within the XRT7302), is disabled
whenever that channel has been configured to operate in the E3 Mode.
Configuring Channel 2
If the XRT7302 is operating in the "Hardware" Mode.
• Set the "TxLEV2" input pin (pin 60) to "HIGH".
And;
In the "Host" Mode.
• Set the "TxLEV2" bit-field to "1", as illustrated
below.
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE
XRT7302 TO THE LINE
COMMAND REGISTER, CR9 (ADDRESS = 0X09)
D4
D3
D2
D1
D0
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0
X
X
1
X
The E3, DS3, and SONET STS-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 Ohm resistor.
As a consequence, the user is encouraged to interface the "Transmit Section" of the XRT7302, in the
manner as illustrated in Figure 14. Figure 14 indicates that the user should connect two 36 Ohm resistors in series with the primary side of the transformer.
These two 36 Ohm resistors will closely match the 75
Ohm load termination resistor; thereby maximizing
"Transmit Return Loss".
2.4.3 Design Guideline for Setting the Transmit
Line Build-Out Circuit
The "TxLEV" input pins or bit-fields should be set
based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 14. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT7302 TO THE LINE
TTIP(n)
R1
36Ω
Channel (n)
TxPOS(n)
TxNEG(n)
TxLineClk(n)
J1
BNC
TPData(n)
TNData(n)
TxClk(n)
1:1
R2
36Ω
TRing(n)
Only One Channel Shown
Transmit Transformer Recommendations
PARAMETER
VALUE
Turns Ratio
1:1
Primary Inductance
4µH
Isolation Voltage
1500Vrms
Leakage Inductance
0.06µH
PART #
INSULATION
PACKAGE TYPE
T3001
1500V
Small, SMT
TRANSFORMER VENDOR INFORMATION
Pulse
Corporate Office
12220 World Trade Drive
San Diego, CA 92128
Tel: (619)-674-8100
FAX: (619)-674-8262
PART #
INSULATION
PACKAGE TYPE
PE-68629
3000V
Large Thru-Hole
1 & 2 Huxley Road
PE-65966
1500V
Small Thru-Hole
The Surrey Research Park
PE-65967
1500V
Small, SMT
Europe
Guildford, Surrey GU2 5RE
United Kingdom
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
Asia
• HDB3/B3ZS Decoder
150 Kampong Ampat
Each of these blocks will be discussed in some detail
below.
#07-01/02
In general, the purpose of the "Receive Section” within the XRT7302 is to take an incoming attenuated/distorted bipolar signal, from the line, and to encode it
back into the TTL/CMOS format where it can be received and processed by the Terminal Equipment.
KA Centre
Singapore 368324
Tel: 65-287-8998
FAX: 65-280-0080
3.1 INTERFACING THE RECEIVE SECTIONS OF THE
XRT7302 TO THE LINE
3.0 THE RECEIVE SECTION
Figure 6 indicates that the Receive Section, within the
XRT7302 consists of the following blocks:
The design of the Receive Circuitry within the
XRT7302 permits the user to transformer-couple or
capacitive-couple the Receive Section to the line. As
mentioned earlier, the specification documents for
E3, DS3, and STS-1 all specify 75 Ohm termination
loads, when transmitting over coaxial cable. As a result, it is recommended to interface the "Receive Section" of the XRT7302 to the line in a manner as shown
in Figure 15 and Figure 16.
• Attenuator/Equalizer
• Peak Detector
• Slicer
• Clock Recovery PLL
• Data Recovery
FIGURE 15. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT7302 TO THE LINE
(TRANSFORMER-COUPLING)
RTIP(n)
Channel (n)
RxPOS(n)
RxNEG(n)
RxClk(n)
R1
37.5Ω
RPOS(n)
RNEG(n)
RxClk(n)
T1
J1
BNC
C1
0.01uf
R2
37.5Ω
1:1
RRing(n)
Only One Channel Shown
Receive Transformer Recommendations
PART #
INSULATION
PACKAGE TYPE
PARAMETER
VALUE
PE-68629
3000V
Large Thru-Hole
Turns Ratio
1:1
PE-65966
1500V
Small Thru-Hole
Primary Inductance
40µH
PE-65967
1500V
Small, SMT
Isolation Voltage
1500Vrms
T3001
1500V
Small, SMT
Leakage Inductance
0.6µH
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
TRANSFORMER VENDOR INFORMATION
Tel: 44-1483-401700
Pulse
FAX: 44-1483-401701
Corporate Office
Asia
12220 World Trade Drive
150 Kampong Ampat
San Diego, CA 92128
#07-01/02
Tel: (619)-674-8100
KA Centre
FAX: (619)-674-8262
Singapore 368324
Europe
Tel: 65-287-8998
1 & 2 Huxley Road
FAX: 65-280-0080
The Surrey Research Park
Figure 16 presents the recommended schematic for
capacitive-coupling each Receive Section of the
XRT7302 to the line.
Guildford, Surrey GU2 5RE
United Kingdom
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT7302 TO THE LINE
(CAPACITIVE-COUPLING) - (TYPICAL CHANNEL SHOWN)
J1
BNC
C1
0.01uf
RTIP(n)
R1
75Ω
Channel (n)
RxPOS(n)
RxNEG(n)
RxClk(n)
RPOS(n)
RNEG(n)
RxClk(n)
C2
0.01uf
RRing(n)
Only One Channel Shown
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
.
FIGURE 17. ILLUSTRATION OF THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
Digital Cross-Connect
System
Transmitting
Terminal
0 to 450 feet of
Cable
Pulses that are
compliant to the
Isolated DSX-3 or
STSX-1 Pulse Template
Requirement
DSX-3
or
STSX-1
0 to 450 feet of Cable
Receiving
Terminal
3.2 THE RECEIVE EQUALIZER BLOCK
a. That the length of cable between the Transmitting
Terminal and the Digital Cross-Connect system can
range between 0 and 450 feet.
Design Considerations (for DS3 and STS-1 Applications)
b. That the length of cable between the Digital CrossConnect system and the Receive Terminal can range
between 0 and 450 feet.
When installing equipment into environments as depicted in Figure 17, we recommend that the user enable the Receive Equalizer, by setting the "REQEN1"
input pin (for Channel 1) or the "REQEN2" input pin
(for Channel 2) “high”, or the respective bit-fields to
"1". In fact, the only time that the user should disable
the Receive Equalizer is when an off-chip equalizer is
in the Receive path between the Digital Cross-Connect system and the RTIP/RRing input pins, or in applications where the Receiver is monitoring the transmit output signal directly.
As a consequence, the overall cable length (between
the Transmitting Terminal and the Receiving Terminal)
can range between very short cable length (e.g., near
0 feet) up to 900 feet.
If, during System Installation, the overall cable length
is known, then (in order to optimize the performance
of the XRT7302, in terms of receive jitter performance, etc.) the user should enable or disable the
Receive Equalizer, based upon the following recommendations.
Design Considerations (for E3 Applications or if
the Overall Cable Length is known)
As a guideline, the Receive Equalizer should be
"turned ON", if the Receive Section (of a given channel) is going to receive a line signal with an overall cable length of 300 feet or greater. Conversely, the Re-
Figure 17 indicates the following.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
However, Receive Equalizer was not designed to
counter "flat loss" (e.g., where all of the Fourier frequency components within the line signal are subject to the same amount of attenuation). Flat loss is
handled by the AGC block.
ceive Equalizer should be "turned OFF" if the Receive
Section (of a given channel) is going to receive a line
signal over a cable length of less than 300 feet.
NOTES:
1. If the user turns "ON" the Receive Equalizer block
(within a given Receive Section that is receiving a
line signal over short cable length), he/she runs the
risks of "over-equalizing" the received line signal
which could degrade performance by increasing
the amount of jitter that exists within the recovered
data and clock signals, or by creating bit-errors.
The user can disable the Receive Equalizer block by
doing either of the following.
Configuring Channel 1
1. Setting the "REQEN1" input pin "low" (when
operating in the "Hardware" Mode); or
2. Writing a "0" to the "REQEN1" bit-field within
Command Register, CR2 (when operating the
XRT7302 in the "Host" Mode), as illustrated
below.
2. The Receive Equalizer has been designed to
counter the "frequency-dependent" (e.g., cable
loss) that a line signal experiences as it travels from
the transmitting terminal to the receiving terminal.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
RESERVED
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
X
X
X
X
0
Configuring Channel 2
2. Writing a "0" to the "REQEN2" bit-field within
Command Register, CR9 (when operating the
XRT7302 in the "Host" Mode), as illustrated
below.
1. Setting the "REQEN2" input pin "low" (when
operating in the "Hardware" Mode); or
COMMAND REGISTER CR10 (ADDRESS = 0X0A)
D4
D3
D2
D1
D0
RESERVED
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
X
X
X
X
0
3.3 PEAK DETECTOR AND SLICER
Each of these modes will be briefly discussed below.
1. The Training Mode
After the incoming line signal has passed through the
Receive Equalizer block, it will next be routed to the
"Slicer" block. The purpose of the "Slicer" block is to
quantify a given bit-period (or symbol) within the incoming line signal as either a "1" or a "0".
If a given channel (within the XRT7302) is not receiving a line signal (via the "RTIP" and "RRing" input
pins), or if the frequency difference between the line
signal and that applied via the EXClk input pin exceeds 0.5%, then the channel will be operating in the
"Training Mode". When the channel is operating in
the "Training Mode", it will do the following:
3.4 CLOCK RECOVERY PLL
The output of the "Slicer" block (which is now dual-rail
digital pulses) is routed to the Clock Recovery PLL.
The purpose of the Clock Recovery PLL is to track
the incoming "dual-rail" data stream and to derive and
generate a "recovered clock signal".
a. Declare a "Loss of Lock" indication, by toggling its
respective "RLOL" output pin "high".
b. Output a clock signal (via the RxClk1 and RxClk2
output pins) which is derived from the signal
applied to the "EXClk" input pin.
It is important to note that the "Clock Recovery PLL"
requires a "line rate" clock signal at the "EXClk" input
pin.
2. The "Data/Clock Recovery" Mode
The "Clock Recovery PLL" operates in one of two
modes:
If the frequency difference between the line signal
and that applied via the EXClk input pin is less than
0.5%, then the channel will be operating in the "Data/
Clock Recovery" mode. In this mode, the "Clock Re-
• The "Training" Mode.
• The "Data/Clock Recovery" Mode
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
If the XRT7302 is configured to operate in the DS3 or
STS-1 Modes, then the "HDB3/B3ZS" Decoding
Blocks will perform "B3ZS" Decoding. When the Decoders are operating in this mode, each of the Decoders will parse through its respective incoming "Dual
Rail" data and check for the occurrence of either a
"00V" or a "B0V" pattern. If the B3ZS Decoder detects this particular pattern, then it will substitute
these bits with a "000" pattern.
covery" PLL will be "locked" onto the line signal (via
the RTIP and RRing input pins).
3.5 THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal, typically encodes
the line signal into some sort of "Zero Suppression"
Line Code (e.g., HDB3 for E3, and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process, of this data, within
the "Near-End" Receiving Terminal. However, once
the data has made it across the E3, DS3 or STS-1
Transport Medium, and has been "recovered" by the
Clock Recovery PLL, it is now necessary to restore
the original content of the data. Hence, the purpose
of the "HDB3/B3ZS Decoding" block is to restore the
data (transmitted over the E3, DS3 or STS-1 line) to
its original content prior to "Zero Suppression" Coding.
3.5.1
NOTE: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the"B3ZS Line Code" format;
or if the "B3ZS Decoder" detects a string of 3 (or more) consecutive "0s", in the incoming line signal, then the "B3ZS
Decoder" will flag this event as a "Line Code Violation" by
pulsing the "LCV" output pin "high".
Figure 18 presents an illustration of the "B3ZS Decoder" at work, with two separate "Zero Suppression"
patterns, in the incoming "Dual Rail Data Stream".
B3ZS Decoding (DS3/STS-1 Applications)
FIGURE 18. AN EXAMPLE OF B3ZS DECODING
0
0
V
Line Signal
B
0
V
1
0
0
RxClk
RPOS
RNEG
Data
3.5.2
0
1
0
1
1
0
0
0
1
0
1
1
1
HDB3 Decoding (E3 Applications)
0
1
1
0
1
1
0
0
1
1
0
1
"B00V" pattern. If the HDB3 Decoder detects this
particular pattern, then it will substitute these bits with
a "0000" pattern.
If the XRT7302 is configured to operate in the "E3
Mode" then each of the "HDB3/B3ZS" Decoding
Blocks will perform "HDB3" Decoding. When the Decoders are operating in this mode, they will each
parse through the incoming "Dual Rail" data and
check for the occurrence of either a "000V" or a
Figure 19 presents an illustration of the "HDB3 Decoder" at work, with two separate "Zero Suppression"
patterns, in the incoming "Dual Rail Data Stream".
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 19. AN EXAMPLE OF HDB3 DECODING
0
0
0
V
Line Signal
B
0
0
V
0
0
RxClk
RPOS
RNEG
Data
0
1
0
1
1
0
0
0
0
0
1
1
1
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the "HDB3
Line Code" format, or if the "HDB3 Decoder" detects a
string of 4 (or more) "0's" in the incoming line signal, then
the "HDB3 Decoder" will flag this event as a "Line Code
Violation" by pulsing the "LCV" output pin "high".
3.5.3
1
0
1
1
0
1
1
0
0
1
1
0
0
1
If the XRT7302 is configured to operate in the
"Host" Mode
Configuring Channel 1
The user can enable the "HDB3/B3ZS Decoder"
block within Channel 1 by writing a "0" into the
"ENDECDIS1" bit-field within Command Register
CR2, as illustrated below.
Configuring the HDB3/B3ZS Decoder
The "HDB3/B3ZS Decoder" blocks (within each
Channel of the XRT7302) can be enable or disable by
either of the following means.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Rserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
X
0
X
X
1
Likewise, the user can to disable the "HDB3/B3ZS
Decoder" block within Channel 1, by writing a "1" into
this bit-field.
The user can enable the "HDB3/B3ZS Decoder"
block within Channel 2 by writing a "0" into the
"ENDECDIS2" bit-field within Command Register
CR10, as illustrated below.
Configuring Channel 2
COMMAND REGISTER CR10 (ADDRESS = 0X0A)
D4
D3
D2
D1
D0
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
X
0
X
X
1
blocks (within the XRT7302) by pulling the "ENDECDIS" input pin "high".
Likewise, the user can to disable the "HDB3/B3ZS
Decoder" block within Channel 2 by writing a "1" into
this bit-field.
3.6 LOS DECLARATION/CLEARANCE
If the XRT7302 is configured to operate in the
"Hardware" Mode
Each channel (within the XRT7302) contains circuitry
that will monitor the following two parameters associated with the incoming line signals.
The user can globally enable both "HDB3/B3ZS Decoder" blocks (within the XRT7302) by pulling the
"ENDECDIS" input pin "low". Conversely, the user
can globally disable both "HDB3/B3ZS Decoder"
1. The amplitude of the incoming line signal via the
RTIP and RRing inputs; and
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
2. The number of pulses, detected (in the incoming
line signal) within a certain amount of time.
"low" and setting its corresponding "RLOS" bit-field to
"0".
If a given channel (within the XRT7302) determines
that the incoming line signal is missing (either due to
insufficient amplitude or a lack of pulses in the incoming line signal), then it will declare a "Loss of Signal"
(LOS) condition. The channel (within the XRT7302)
declares the LOS condition by toggling its respective
RLOS output pin "high", and by setting its corresponding "RLOS" bit field, within Command Register
0 (or Command Register 8) to "1".
In general, the LOS Declaration/Clearance scheme
that is employed within the XRT7302 is based upon
ITU-T Recommendation G.775 for both E3 and DS3
applications.
3.6.1 The LOS Declaration/Clearance Criteria
for E3 Applications
When the XRT7302 is operating in the "E3 Mode", a
given channel will declare an LOS Condition if its "receive line" signal amplitude drops to -35dB or below.
Further, the channel will clear the LOS Condition if its
"receive line" signal amplitude rises back up to -15dB
or above. Figure 20 presents an illustration of the signal levels at which each channel (within the
XRT7302) will declare and clear LOS.
Conversely, if the channel (within the XRT7302) determines that the incoming line signal has been restored (e.g., there is sufficient amplitude and pulses
in the incoming line signal); then it will clear the LOS
condition by toggling its respective RLOS output pin
FIGURE 20. ILLUSTRATION OF THE SIGNAL LEVELS THAT THE XRT7302 WILL DECLARE AND CLEAR LOS
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
Timing Requirements associated with Declaring
and Clearing the LOS Indicator
the LOS condition occurred. Further, the channel will
clear the LOS indicator within 10 to 255 UI after restoration of the incoming line signal. Figure 21, illustrates the LOS Declaration and Clearance behavior,
in response to first, the "Loss of Signal" event and
then afterwards, the restoration of the signal.
The XRT7302 was designed to meet the ITU-T G.775
specification timing requirements for declaring and
clearing the LOS indicator. In particular, a channel
(within the XRT7302) will declare an LOS, between
10 and 255 UI (or E3 bit-periods) after the actual time
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 21. THE BEHAVIOR THE LOS OUTPUT INDICATOR, IN RESPONSE TO THE LOSS OF SIGNAL, AND THE RESTOSIGNAL
RATION OF
Actual Occurrence
of LOS Condition
Line Signal
is Restored
RxIN
10 UI
255 UI
Time Range for
LOS Declaration
10 UI
255 UI
RLOS Output Pin
0 UI
0 UI
G.775
Time Range for
LOS Clearance
G.775
3.6.2 The LOS Declaration/Clearance Criteria
for DS3 and STS-1 Applications
1. The Analog LOS (ALOS) Declaration/Clearance
Criteria
When the XRT7302 is operating in the DS3 or STS-1
Mode, then each channel (within the XRT7302) will
declare and clear LOS based upon the following two
criteria.
A channel (within the XRT7302) will declare an "Analog LOS (ALOS) Condition if the amplitude of the incoming line signal drops below a specific amplitude
as defined by the voltage at the LOSTHR input pin,
and by whether the Receive Equalizer is enabled or
not.
Analog LOS (ALOS) Declaration/Clearance Criteria
Digital LOS (DLOS) Declaration/Clearance Criteria
Table 6 presents the various voltage levels at the
LOSTHR input pin, the state of the Receive Equalizer,
and the corresponding ALOS (Analog LOS) threshold
amplitudes.
In the DS3 Mode, the LOS output (RLOS) is simply
the logical "OR" of the ALOS and DLOS states. The
Declaration/Clearance criteria for ALOS and DLOS
are discussed below.
TABLE 6: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION
REQEN SETTING
LOSTHR SETTING
SIGNAL LEVEL TO
DECLARE ALOS
SGNAL LEVEL TO CLEAR
ALOS
DS3
1
0
<55mV
>220mV
STS-1
1
1
<22mV
>90mV
0
0
<35mV
>155mV
0
1
<17mV
>70mV
1
0
<75mV
>270mV
1
1
<25mV
>115mV
0
0
<55mV
>210mV
0
1
<20mV
>90mV
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
NOTE: There is approximately a 2dB hysteresis in the
received signal level that exists between declaring and
clearing ALOS, in order to prevent "chattering" in the RLOS
output signal.
Declaring ALOS
A channel (within the XRT7302) will declare ALOS
whenever the amplitude of the receive line signal falls
below the "Signal Level to Declare ALOS" levels
specified in Table 6.
Monitoring the State of ALOS
If the XRT7302 is operating in the "Host" Mode, then
the user can poll or monitor the state of ALOS, within
Channel 1 by reading in the contents of Command
Register 0. The bit-field of Command Register 0 is
presented below.
Clearing ALOS
A channel (within the XRT7302) will clear ALOS
whenever the amplitude of the receive line signal increases above the "Signal Level to Clear ALOS" levels specified in Table 6.
COMMAND REGISTER 0, (ADDRESS = 0X00)
D4
D3
D2
D1
D0
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
Read Only
Read Only
Read Only
Read Only
Read Only
Likewise, the user can also poll or monitor the state of
ALOS, within Channel 2, by reading in the contents of
Command Register 8. The bit-field of Command
Register 8 is presented below.
COMMAND REGISTER 8, (ADDRESS = 0X08)
D4
D3
D2
D1
D0
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
Read Only
Read Only
Read Only
Read Only
Read Only
Disabling the ALOS Detector
If the "ALOS" bit-field contains a "1", then the corresponding channel is currently declaring an ALOS
condition. Conversely, if the ALOS bit-field contains a
"0", then the channel is not currently declaring an
ALOS condition.
For debugging purposes, it may be useful to be able
to disable the ALOS Detector, within the XRT7302. If
the XRT7302 is operating in the "Host" Mode, then
the user can disable the ALOS Detector, (within
Channel 1) by writing a "1" into the "ALOSDIS1" bitfield, within Command Register 2; as shown below.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
X
X
1
X
X
Likewise, the user can disable the ALOS Detector
(within Channel 2) by writing a "1" into the
"ALOSDIS2" bit-field, within Command Register 10;
as depicted below.
COMMAND REGISTER CR10 (ADDRESS = 0X0A)
D4
D3
D2
D1
D0
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
X
X
1
X
X
2. The Digital LOS (DLOS) Declaration/Clearance
Criteria
160±32 or more consecutive "0s" in the incoming data.
A given channel (within the XRT7302) will declare a
Digital LOS (DLOS) condition if the XRT7302 detects
The channel (within the XRT7302) will clear DLOS if it
detects four consecutive sets of 32 bit-periods, each
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
of which containing at least 10 "1s" (e.g., average
pulse density of greater than 33%).
Command Register 8. The bit-field of Command
Register 8 is presented below.
Monitoring the State of DLOS
COMMAND REGISTER CR8, (ADDRESS = 0X08)
If the XRT7302 is operating in the "Host" Mode, then
the user can poll or monitor the state of DLOS, within
Channel 1 by reading in the contents of Command
Register 0. The bit-field of Command Register 0 is
presented below.
D3
D2
D1
D0
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
D3
D2
D1
D0
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
Read Only Read Only Read Only Read Only Read Only
COMMAND REGISTER CR0, (ADDRESS = 0X00)
D4
D4
If the “DLOS” bit-field contains a “1”, then the corresponding channel is currently declaring a DLOS condition. Conversely, if the DLOS bit-field contains a
“0”, then the channel is currently declaring the DLOS
condition.
Read Only Read Only Read Only Read Only Read Only
Disabling the DLOS Detector
For debugging purposes, it is useful to be able to disable the DLOS detector, within the XRT7302. If the
XRT7302 is operating in the “Host” Mode, the user
can disable the DLOS Detector, (within Channel 1) by
writing a “1” into the “DLOSDIS1” bit-field, within
Command Register 2, as depicted below.
Likewise, the user can also poll or monitor the state of
DLOS within Channel 2, by reading in the contents of
COMMAND REGISTER CR2 (ADDRESS = 0X02
D4
D3
D2
D1
D0
Reserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
X
X
X
1
X
NOTE: Setting both the "ALOSDIS1" and "DLOSDIS1" bitfields to "1" will disable LOS Declaration by Channel 1.
"DLOSDIS2" bit-field, within Command Register 10,
as depicted below.
Likewise, the user can disable the DLOS Detector
(within Channel 2) by writing a "1" into the
COMMAND REGISTER CR10 (ADDRESS = 0X0A
D4
D3
D2
D1
D0
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
X
X
X
1
X
NOTE: Setting both the "ALOSDIS2" and "DLOSDIS2" bitfields to "1" will disable LOS Declaration by Channel 2.
has been cleared, then the channel (within the
XRT7302) will resume normal transmission of the recovered data to the "Receiving Terminal.
3.6.3 Muting the Recovered Data while the LOS
is being Declared
This feature is available whenever XRT7302 is operating in the Host Mode or Hardware Mode. The approach for configuring the "MUTing upon LOS" feature for both the Hardware and Host Modes are presented below.
In some applications it is not desirable for a channel
(within the E3/DS3/STS-1 LIU) to recover data and
route it to the "Receiving Terminal", while the channel
is declaring an LOS condition. Consequently, the
XRT7302 includes an "LOS Muting" feature. This
feature (if enabled) will cause a given channel (within
the XRT7302) to halt transmission of the recovered
data (to the Receiving Terminal) while the LOS condition is "true". In this case, the RPOS and RNEG output pins will be forced to "0". Once the LOS condition
Enabling and Disabling the "MUTing upon LOS"
feature if the XRT7302 is operating in the Hardware Mode.
To enable the "MUTing upon LOS" feature, pull the
"LOSMUTEN" output pin (pin 53) "high". Then, the
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
The "MUTing upon LOS" feature for Channel 1can be
enabled by writing a "1" into the "LOSMUT1" bit-field,
within Command Register 3, as shown below.
"MUTEing upon LOS" feature will be enabled globally
for both channels within the XRT7302.
Enabling and Disabling the "MUTing upon LOS"
feature if the XRT7302 is operating in the Host
Mode.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
D0
SR/DR_1
LOSMUT1
RxOFF1
RClk1_INV
Reserved
X
1
x
x
x
Back” Modes. Consequently, the user the user
must disable the “MUTing-upon-LOS” feature, prior
to configuring the chip to operate in either of these
local loop-back modes.
NOTES:
1. This step only enables the "MUTing upon LOS" feature within Channel 1.
2. Each channel, within the XRT7302, automaticallly
declares an “LOS” (Loss of Signal) condition anytime it has been configured to operate in either the
“Analog Local Loop-Back or “Digital Local Loop-
The "MUTing upon LOS" feature for Channel 2 can
be enabled by writing a "1" into the "LOSMUT2" bitfield, within Command Register 11, as shown below.
COMMAND REGISTER CR11 (ADDRESS = 0X0B)
D4
D3
D2
D1
D0
SR/DR_2
LOSMUT2
RxOFF2
RClk2_INV
Reserved
X
1
x
x
x
NOTES:
Each channel, within the XRT7302 can "deliver" the
recovered data and clock information (to the "Receiving Terminal") in either a "Single-Rail" or "Dual-Rail"
format. Each of these methods are discussed below.
1. This step only enables the "MUTing upon LOS" feature within Channel 1.
2. Each channel, within the XRT7302, automaticallly
declares an “LOS” (Loss of Signal) condition anytime it has been configured to operate in either the
“Analog Local Loop-Back or “Digital Local LoopBack” Modes. Consequently, the user the user
must disable the “MUTing-upon-LOS” feature, prior
to configuring the chip to operate in either of these
local loop-back modes.
3.7.1 Routing "Dual-Rail" Format Data to the
Receiving Terminal Equipment
Whenever a channel (within the XRT7302) delivers
dual-rail format to the Terminal Equipment, it does so
via the following signals.
• RPOS(n)
3.7 ROUTING THE RECOVERED TIMING AND DATA
INFORMATION TO THE "RECEIVING TERMINAL
EQUIPMENT"
• RNEG(n)
• RxClk(n)
Figure 22 presents an illustration of the typical interface for the transmission of data in a "Dual-Rail" Format from the Receive Section of a channel (within the
XRT7302) to the "Receiving Terminal Equipment"
Each channel, within the XRT7302, ultimately takes
the Recovered Timing and Data information, converts
it into CMOS levels and routes it to the Receiving Terminal Equipment via the RPOS, RNEG and RxClk
output pins.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.1.5
.
FIGURE 22. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL
FORMAT, FROM THE "RECEIVE SECTION" OF THE XRT7302" TO THE RECEIVING TERMINAL EQUIPMENT
Terminal Equipment
(E3/DS3 or STS-1
Framer)
RxPOS
RPOS
RxNEG
RNEG
RxClk
RxClk
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
channel (within the XRT7302) will typically update the
data (on the RPOS and RNEG output pins) on the rising edge RxClk.
The manner that a given channel transmits "DualRail" data (to the Receiving Terminal Equipment) is
described below and is illustrated in Figure 23. Each
FIGURE 23. ILLUSTRATION ON HOW THE XRT7302 OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RPOS
RNEG
RxClk
(via the RTIP and RRing input pins), then the channel
will pulse its corresponding RNEG output pin "high".
RxClk, is the Recovered Clock signal, from the incoming "Received" line signal. As a result, these
clock signals are typically 34.368 MHz for E3 applications; 44.736 MHz for DS3 applications, and 51.84
MHz for SONET STS-1 applications.
Inverting the RxClk1 and RxClk2 outputs
Both channels (within the XRT7302) can invert RxClk(n) signals, with respect to the "delivery" of the
"RPOS" and RNEG" output signals to the "Receiving
Terminal Equipment". This feature may be useful for
those customer whose "Receiving Terminal Equipment" logic design is such that the RPOS and RNEG
data must be sampled on the rising edge of RxClk.
Figure 24 illustrates the behavior of the RPOS,
In general, if a given channel (within the XRT7302)
received a "positive-polarity" pulse in the incoming
line signal (via the RTIP and RRing input pins), then
the channel will pulse its corresponding RPOS output
pin "high". Conversely, if the channel received a
"negative-polarity" pulse in the incoming line signal
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
RNEG, and RxClk signals, when the RxClk signal has
been inverted.
FIGURE 24. ILLUSTRATION OF THE BEHAVIOR OF THE RPOS, RNEG, AND RXCLK(N) SIGNALS, WHEN RXCLK(N)
IS INVERTED
RPOS
RNEG
RxClk
Inverting the RxClk Signals via the Host Mode
of a channel (within the XRT7302), to the "Receiving
Terminal Equipment", he/she can do the following.
In order to configure a single channel (within the
XRT7302) to invert the RxClk output signal; the user
must be operating the XRT7302 in the "Host" Mode.
If the XRT7302 is operating in the "Host" Mode
If the XRT7302 is operating in the "Host" Mode, then
the user has the option to configure each channel (individually) to output data in a Single-Rail or Dual-Rail
manner to the Terminal Equipment.
If the user wishes to invert RxClk1, associated with
Channe1, then the user should write a "1" into the
"RClk1_INV" bit-field within Command Register 3.
a. In order to configure Channel 1 to output "SingleRail" data to the Terminal Equipment: Write a "1" into
the "SR/DR_1" bit-field, within Command Register 3;
as depicted below.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
D0
SR/DR_1 LOSMUT1 RxOFF1 RClk1_INV Reserved
X
X
X
1
COMMAND REGISTER CR3 (ADDRESS = 0X03)
X
D4
Similarly, if the user wishes to invert RxClk2, associated with Channel 2, then the user should write a "1"
into the "RClk2_INV" bit-field within Command Register 11; as illustrated below.
D3
D2
SR/DR_2 LOSMUT2 RxOFF2
X
X
X
D1
1
D0
X
X
X
D0
Reserved
X
COMMAND REGISTER 11 (ADDRESS = 0X0B)
X
D4
Inverting the RxClk signals via the Hardware
Mode
The user also has the ability to invert both the RxClk1
and RxClk2 output signals while the XRT7302 is operating in the "Hardware" Mode. Setting the "RClkINV" input pin (pin 42) "high" will invert both the
RxClk1 and RxClk2 output signals.
D3
D2
SR/DR_2 LOSMUT2 RxOFF2
1
X
X
D1
D0
RClk2_INV
Reserved
X
X
After the user has taken these steps, then the configured channel (within the XRT7302) will output "Single-Rail" data to the "Receiving Terminal Equipment"
via its corresponding RPOS and RxClk output pins,
as illustrated below in Figure 25 and Figure 26.
3.7.2 Routing Single-Rail Format (Binary Data
Stream) data to the Receive Terminal Equipment
If the XRT7302 is operating in the Hardware Mode
If the user wishes to route "Single-Rail" format data
(e.g., a binary data stream), from the Receive Section
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D1
b. In order to configure Channel 2 to output "SingleRail" data to the Terminal Equipment: Write a "1" into
the "SR/DR_2" bit-field, within Command Register
11, as depicted below.
RClk2_INV Reserved
1
D2
SR/DR_1 LOSMUT1 RxOFF1 RClk1_INV
COMMAND REGISTER CR11 (ADDRESS = 0X0B)
D4
D3
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
NOTE: When the XRT7302 is operating in the Hardware
Mode, the setting of the "SR/DR" input pin applies to globally to both channels.
The user can configure the XRT7302 to output "Single-Rail" data from the Receive Sections of both
channels by pulling the "SR/DR" pin (pin 40) to VDD.
FIGURE 25. ILLUSTRATION OF THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL
FORMAT, FROM THE RECEIVE SECTION OF THE XRT7302 TO THE RECEIVING TERMINAL EQUIPMENT
RxPOS
Terminal Equipment
(E3/DS3 or STS-1
Framer)
RxClk
RPOS
RxClk
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
FIGURE 26. ILLUSTRATION OF THE BEHAVIOR OF THE RPOS AND RXCLK OUTPUT SIGNALS, WHILE THE
XRT7302 IS TRANSMITTING "SINGLE-RAIL" DATA TO THE RECEIVING TERMINAL EQUIPMENT
RPOS
RxClk
NOTE: The RNEG output pin will be internally tied to
Ground, whenever this feature is implemented.
If the XRT7302 is operating in the "Hardware"
Mode
3.8 SHUTTING OFF THE RECEIVE SECTION
Configuring Channel 1
The Receive Section of each channel of the XRT7302
can be turned off. This feature may be useful in some
"redundant system designs". Particularly, in those
designs where the Receive Termination within the
Secondary LIU Line Card, has been "switched-out"
and is not receiving any traffic in parallel with the "Primary Line Card". In this case, having the LIU (on the
"Secondary Line Card) consume the normal amount
of current is a waste of power. Hence, this feature
can permit the user to power down the "Receive Section" of the LIUs on the Secondary Line Card, which
will reduce their power consumption by approximately
80%.
The user can shut off the Receive Section of Channel
1 (within the XRT7302) by pulling the "RxOFF1" input
pin (pin 19) "high". Conversely, the user can turn on
the Receive Section of Channel 1 by pulling the
"RxOFF1" input pin to "low".
The user can implement the "RxOFF1" by the following means:
Configuring Channel 1
Configuring Channel 2
The user can shut off the Receive Section of Channel
2 (within the XRT7302) by pulling the "RxOFF2" input
pin (pin 18) "high". Conversely, the user can turn on
the Receive Section of Channel 2 by pulling the
"RxOFF2" input pin “low".
If the XRT7302 is operating in the "Host" Mode
The user can shut off the Receive Section of Channel
1 (within the XRT7302) by writing a "1" into the
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XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
"RxOFF1" bit-field (within Command Register CR3),
as illustrated below.
The user can shut off the Receive Section of Channel
2 (within the XRT7302) by writing a "1" into the
"RxOFF2" bit-field (within Command Register, CR11)
as illustrated below.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
SR/DR_1 LOSMUT1 RxOFF1 RClk1_INV
X
X
1
X
D0
COMMAND REGISTER CR11 (ADDRESS = 0X0B)
Reserved
D4
X
D2
D1
SR/DR_2 LOSMUT2 RxOFF2 RClk2_INV
Conversely, the user can turn on the Receive Section
of Channel 1 by writing a "0" into the "RxOFF1" bitfield, within Command Register CR3.
X
X
1
X
D0
Reserved
X
Conversely, the user can turn on the Receive Section
of Channel 2 by writing a "0" into the "RxOFF2" bitfield, within Command Register CR11.
Configuring Channel 2
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XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
4.0 DIAGNOSTIC FEATURES OF THE XRT7302
input pins. This data will be processed through the
"Transmit Clock Duty Cycle Circuit" and the "HDB3/
B3ZS Encoder". Finally, this data will be output to
the line via the TTIP and TRing output pins. Additionally, this data (which is being output via the TTIP and
TRing output pins) will also be looped back into the
"Receive Equalizer Block". As a consequence, this
data will be processed through the entire "Receive
Section" of the channel. After this "post-loop-back"
data has been processed through the "Receive Section" it will be output, to the "Near-End Receiving Terminal Equipment" via the RPOS, RNEG and RxClk
output pins.
The XRT7302 supports equipment diagnostic activities by supporting the following loop-back modes
within each channel (within the XRT7302).
• Analog Local Loop-back.
• Digital Local Loop-back
• Remote Loop-back
The next two sections briefly discussed each of these
Loop-back schemes.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When a given channel (within the XRT7302) is configured to operate in the "Analog Local Loop-back"
Mode, the channel will ignore any signals that are input to its RTIP and RRing input pins. The "Transmitting Terminal Equipment" will transmit clock and data
into this channel via the TPData, TNData, and TxClk
Figure 27 illustrates the path that the data takes (within a given channel of the XRT7302), when the channel is configured to operate in the "Analog Local
Loop-back" Mode.
FIGURE 27. ILLUSTRATION OF A TYPICAL CHANNEL(N) (WITHIN THE XRT7302) OPERATING IN THE ANALOG LOCAL
LOOP-BACK MODE
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
AGC/
Equalizer
REQEN(n)
Clock
Recovery
Slicer
Peak
Detector
Data
Recovery
LOS Detector
LOSTHR(n)
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
SDI
SDO
SClk
CS
Serial
Processor
Interface
RLOS(n)
Analog Local
Loopback Path
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TxLEV(n)
TNData(n)
Duty Cycle Adjust
TRing(n)
TxOFF(n)
TPData(n)
Transmit
Logic
TxClk(n)
MTIP(n)
Device
Monitor
MRing(n)
DMO(n)
field and a "0" into the "RLB1" bit-field within Command Register 4, as illustrated below.
The user can configure a given channel, (within the
XRT7302) to operate in the Analog Local Loop-back
Mode, by employing either one of the following two
steps
COMMAND REGISTER CR4 (ADDRESS = 0X04)
a. If the XRT7302 is operating in the "Host" Mode
D4
D3
To configure Channel 1 to operate in the "Analog Local Loop-Back" Mode, write a "1" into the "LLB1" bit-
X
STS-1/DS3_Ch1
X
X
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D2
D1
E3_Ch1 LLB1
X
1
D0
RLB1
0
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
4.2 THE DIGITAL LOCAL LOOP-BACK MODE.
Likewise, to configure Channel 2 to operate in the
"Analog Local Loop-Back" Mode, write a "1" into the
"LLB2" bit-field and a "0" into the "RLB2" bit-field within Command Register 12, as illustrated below.
When a given channel, within the XRT7302 is configured to operate in the "Digital Local Loop-back"
Mode, the channel will ignore any signals that are input to the RTIP and RRing input pins. The "Transmitting Terminal Equipment" will transmit clock and data
into the XRT7302 via the "TPData", "TNData" and
"TxClk" input pins. This data will be processed
through the "Transmit Clock Duty Cycle Circuit" and
the "HDB3/B3ZS Encoder" block. At this point, this
data will be looped back to the "HDB3/B3ZS Decoder" block. After this "post-loop back" data has been
processed through the "HDB3/B3ZS Decoder" block,
it will be output to the "Near-End" Receiving Terminal
Equipment" via the RPOS, RNEG and RxClk output
pins.
COMMAND REGISTER CR12 (ADDRESS = 0X0C)
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch2
E3_Ch2
LLB2
RLB2
X
X
X
1
0
b. If the XRT7302 is operating in the "Hardware"
Mode
To configure Channel 1 to operate in the "Analog Local Loop-back" Mode, set the "LLB1" input pin (pin
24) "high" and the "RLB1" input pin (pin 25) "low".
Likewise, to configure Channel 2 to operate in the
"Analog Local Loop-back" Mode, set the "LLB2" input
pin (pin 37) "high" and the "RLB2" input pin (pin 36)
"low".
Figure 28 illustrates the path that the data takes (within the XRT7302), when the chip is configured to operate in the "Digital Local Loop-back" Mode.
NOTE: The “Analog Local Loop-back” Mode does not work
if the user has turned off the transmitter via the “TxOFF”
feature.
FIGURE 28. ILLUSTRATION OF THE "DIGITAL LOCAL LOOP-BACK" PATH IN A TYPICAL CHANNEL(N) (OF THE
XRT7302)
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
AGC/
Equalizer
REQEN(n)
Peak
Detector
SDI
SClk
CS
Data
Recovery
LOS Detector
LOSTHR(n)
SDO
Clock
Recovery
Slicer
Serial
Processor
Interface
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
Digital Local
Loopback Path
RLOS(n)
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
TRing(n)
TxLEV(n)
TxOFF(n)
Device
Monitor
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TxClk(n)
MTIP(n)
MRing(n)
DMO(n)
The user can configure a channel (within the
XRT7302) to operate in the "Digital Local Loop-back"
Mode, by employing either one of the following twosteps:
a. If the XRT7302 is operating in the "Host" Mode
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REV. 1.1.5
To configure Channel 1 to operate in the "Digital Local
Loop-Back" Mode, write a "1" into both the "LLB1"
and "RLB1" bit-fields within Command Register 4, as
illustrated below.
Likewise, to configure Channel 2 to operate in the
"Digital Local Loop-back" Mode, pull both the "LLB2"
input pin (pin 37) and the "RLB2" input pin (pin 36)
"high".
COMMAND REGISTER CR4 (ADDRESS = 0X04)
NOTE: The ““Digital Local Loop-back” Mode will work even
if the user has turned off the transmitter via the “TxOFF”
feature.
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch1
E3 Ch1
LLB1
RLB1
X
X
X
1
1
4.3 THE REMOTE LOOP-BACK MODE
When a given channel (within the XRT7302) is configured to operate in the Remote Loop-back Mode, the
channel will ignore any signals that are input to the
TPData and TNData input pins. The channel will receive the incoming line signal, via the RTIP and
RRing input pins. This data will be processed
through the entire Receive Section (within the channel) and will be output to the "Receive Terminal
Equipment" via the RPOS, RNEG and RxClk output
pins. Additionally, this data will also be internally
looped back into the "Pulse-Shaping" block within the
"Transmit Section". At this point, this data will be routed through the remainder of the "Transmit Section" of
the channel and will be transmitted out onto the line
via the TTIP and TRing output pins.
Likewise, configure Channel 2 to operate in the "Digital Local Loop-back" Mode, write a "1" into both the
"LLB2" and the "RLB2" bit-fields, within Command
Register 12, as illustrated below.
COMMAND REGISTER CR12 (ADDRESS = 0X0C)
D4
D3
D2
D1
D0
X
STS-1/DS3_Ch2
E3_Ch2
LLB2
RLB2
X
X
X
1
1
b. If the XRT7302 is operating in the "Hardware"
Mode.
To configure Channel 1 to operate in the "Digital Local
Loop-back" Mode, pull both the "LLB1" input pin (pin
24) and the "RLB1" input pin (pin 25) "high".
Figure 29 illustrates the path that the data takes (within the configured channel of the XRT7302), when the
chip is configured to operate in the "Remote Loopback" Mode.
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
FIGURE 29. ILLUSTRATION OF THE "REMOTE LOOP-BACK" PATH, WITHIN A TYPICAL CHANNEL(N) (OF THE
XRT7302)
RLOL(n) EXClk(n)
RTIP(n)
AGC/
Equalizer
RRing(n)
REQEN(n)
Clock
Recovery
Slicer
Peak
Detector
Data
Recovery
LOS Detecto r
LOSTHR(n)
Invert
RxClk(n)
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
SDI
SDO
Serial
Processor
Interface
SClk
CS
RLOS(n)
Remote
Loopback Path
LLB(n)
Loop MUX
RLB(n)
REGR
TAOS(n)
TTIP(n)
HDB3/
B3ZS
Encoder
Pulse
Shaping
TPData(n)
Transmit
Logic
TNData(n)
Duty Cycle Adjust
TRing(n)
TxLEV(n)
TxClk(n)
MTIP(n)
Device
Monitor
TxOFF(n)
MRing(n)
DMO(n)
COMMAND REGISTER CR12 (ADDRESS = 0X0C)
The user can configure a channel (within the
XRT7302) to operate in the "Remote Loop-back"
Mode, by employing either one of the following two
steps
a. If the XRT7302 is operating in the "Host" Mode
To configure Channel 1 to operate in the "Remote
Loop-back" Mode, write a "1" into the "RLB1" bit-field,
and a "0" into the "LLB1" bit-field, within Command
Register 4, as illustrated below.
D3
X
STS-1/DS3_Ch1
X
X
D2
D1
E3_Ch1 LLB1
X
0
1
D0
X
STS-1/DS3_Ch2
E3_Ch2
LLB2
RLB2
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X
X
X
0
1
The XRT7302 permits the user to shut off the "Transmit Section of each Channel (within the XRT7302).
When this feature is invoked the Transmit Section (of
the configured channel) will be shut-off, and the
Transmit Output signals (e.g., TTIP and TRing) will be
tri-stated. This feature can come in handy for system
redundancy conditions or during diagnostic testing.
COMMAND REGISTER CR12 (ADDRESS = 0X0C)
D1
D0
4.4 TXOFF FEATURES
Likewise, to configure Channel 2 to operate in the
"Remote Loop-back" Mode, write a "1" into the
"RLB2" bit-field, and a "0" into the "LLB2" bit-field,
within Command Register 12, as illustrated below.
D2
D1
Likewise, to configure Channel 2 to operate in the
"Remote Loop-back" Mode, pull both the "RLB2" input pin (pin 36) to "high", and the "LLB2" input pin (pin
37) to "low".
RLB1
D3
D2
To configure Channel 1 to operate in the "Remote
Loop-back" Mode, pull both the "RLB1" input pin (pin
25) to "high", and the "LLB1" input pin (pin 24) to
"low".
D0
D4
D3
b. If the XRT7302 is operating in the "Hardware"
Mode
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D4
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
The user can activate this feature by either of the following ways.
Conversely, writing a "0" into this bit-field enables the
"Transmit Driver within Channel 1.
When the XRT7302 is operating in the "Hardware"
Mode
Shutting off the Transmitter of Channel 2
The user can turn off the Transmit Driver (within
Channel 2) by setting the "TxOFF2" bit-field (within
Command Register CR9) to "1", as illustrated below.
Shutting off the Transmitter of Channel 1
The user can shut off the Transmit Driver (within
Channel 1) by toggling the "TxOFF1" input pin (pin
80) "high". Conversely, the user can turn on the
"Transmit Driver" by toggling the "TxOFF1" input pin
"low".
COMMAND REGISTER CR9 (ADDRESS = 0X09)
Shutting off the Transmitter of Channel 2
The user can shut off the Transmit Driver (within
Channel 2) by toggling the "TxOFF2" input pin (pin
61) "high". Conversely, the user can turn on the
"Transmit Driver" by toggling the "TxOFF2" input pin
"low".
The user can turn off the Transmit Driver (within
Channel 1) by setting the "TxOFF1" bit-field (within
Command Register CR1) to "1", as illustrated below.
D1
D0
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
1
X
X
X
X
D1
D0
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
1
X
X
X
X
Table 7 presents a “Truth Table” which relates the setting of the “TxOFF” external pin and bit-field (for a
channel) to the state of the Transmitter. Please note
that this table applies to both Channels 1 and 2.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D2
D2
NOTE: In order to permit a system (designed for redundancy) to quickly shut-off a defective line card and turn-on
the “back-up” line card, the XRT7302 was designed such
that either Transmitter can quickly be turned-on or turnedoff by toggling the “TxOFF1” or “TxOFF2” input pins. This
approach is much quicker then setting the “TxOFF1” and
“TxOFF2” bit-fields via the Microprocessor Serial Interface.
Shutting off the Transmitter of Channel 1
D3
D3
Conversely, writing a "0" into this bit-field enables the
"Transmit Driver within Channel 2.
When the XRT7302 is operating in the "Host"
Mode
D4
D4
TABLE 7: THE RELATIONSHIP BETWEEN THE “TXOFF” INPUT PIN, THE “TXOFF” BIT FIELD AND THE STATE OF THE
TRANSMITTER
STATE OF THE “TXOFF” STATE OF THE “TXOFF”
INPUT PIN
BIT FIELD
STATE OF THE TRANSMITTER
LOW
0
ON (Transmitter is Active)
LOW
1
OFF (Transmitter is Tri-Stated)
HIGH
0
OFF (Transmitter is Tri-Stated)
HIGH
1
OFF (Transmitter is Tri-Stated)
As a consequence, if the user wishes to control the
state of each transmitter, via the Microprocessor Serial interface, then he/she must connect the “TxOFF1”
and “TxOFF2” input pins to GND.
the line), or a defective Transmit Drive in the
XRT7302 or even another LIU device.
The user activates the Transmit Drive Monitor, within
Channel 1 by connecting the MTIP1 pin (pin 76) to
the TTIP1 line (through a 270 Ohm resistor connected in series); and by connecting the MRing1 pin (pin
75) to the TRing1 line (through a 270 Ohm resistor
connected in series). Likewise, the user also activates the Transmit Drive Monitor, within Channel 2 by
connecting the MTIP2 pin (pin 65) to the TTIP2 line
4.5 THE TRANSMIT DRIVE MONITOR FEATURES
The Transmit Drive Monitor permits the user to monitor the line, in the Transmit Direction, for the occurrence of fault conditions such as a short circuit (on
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REV. 1.1.5
(through a 270 Ohm resistor connected in series);
and by connecting the MRing2 pin (pin 66) to the
TRing2 line (through a 270 Ohm resistor connected in
series). Such an approach is illustrated in Figure 30.
FIGURE 30. ILLUSTRATION OF A TYPICAL CHANNEL OF THE XRT7302 EMPLOYING THE TRANSMIT DRIVE MONITOR
FEATURES
J1
BNC
TTIP(n)
R1 = 36Ω
TRing(n)
TxPOS(n)
TxNEG(n)
TxLineClk(n)
R2 = 36Ω
TPData(n)
TNData(n)
TxClk(n)
1:1
MTIP(n)
R3 = 270Ω
Drive_Failure (n)
DMO(n)
MRing(n)
R4 = 270Ω
Channel (n)
ly, the user can terminate the "All Ones" pattern by
toggling the "TAOS1" input pin "low".
When the Transmit Drive Monitor circuitry (within a
given line) is connected to the line, as illustrated in
Figure 30, then it will monitor the line for transitions.
As long as the Transmit Drive Monitor circuitry detects transitions on the line (via the MTIP and MRing
pins), then it will keep the DMO (Drive Monitor Output) signal "low". However, if the Transmit Drive Monitor circuit detects no transitions on the line for 128(32
TxClk periods, then the DMO (Drive Monitor Output)
signal will toggle "high".
Configuring Channel 2
The user can configure Channel 2 (within the
XRT7302) to transmit an "All Ones" pattern by toggling the "TAOS2" input pin (pin 59) "high". Conversely, the user can terminate the "All Ones" pattern
by toggling the "TAOS2" input pin "low".
When the XRT7302 is operating in the "Host"
Mode.
NOTE: The user does not have to use the Transmit Drive
Monitor circuit in order to operate the Transmit Section of
the XRT7302. This is purely a diagnostic feature.
Configuring Channel 1
The user can configure Channel 1 (within the
XRT7302) to transmit an "All Ones" pattern by writing
to Command Register CR1 and setting the "TAOS1"
bit-field (bit D3) to "1", as illustrated below.
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE
The XRT7302 permits the user to command either
channel to transmit an "All Ones" pattern onto the line
by toggling a single input pin, or by setting a single
bit-field (within one of the Command Registers) to "1".
Please note that when this feature is activated, the
Transmit Section of the configured channel (within the
XRT7302) will overwrite the "Terminal Equipment" data with this "All Ones" pattern. The user can activate
this feature by either of the following ways.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D3
D2
D1
D0
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
0
1
X
X
X
Conversely, the user can terminate the "All Ones" pattern by writing to Command Register, CR1 and setting the "TAOS" bit-field (D3) to "0".
When the XRT7302 is operating in the "Hardware"
Mode.
Configuring Channel 1
The user can configure Channel 1 (within the
XRT7302) to transmit an "All Ones" pattern by toggling the "TAOS1" input pin (pin 2) "high". Converse-
Configuring Channel 2
The user can configure Channel 2 (within the
XRT7302) to transmit an "All Ones" pattern by writing
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.1.5
The XRT7302 DS3/E3/STS-1 Line Interface Unit IC
permits the user to have access to the "on-chip"
Command Registers. Through these Command Registers, the user can configure the XRT7302 into a
wide-variety of modes. This section discusses the
following:
to Command Register CR9 and setting the "TAOS1"
bit-field (bit D3) to "1"; as illustrated below.
COMMAND REGISTER CR9 (ADDRESS = 0X09)
D4
D3
D2
D1
D0
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0
1
X
X
X
1. The description of the Command Registers.
2. A description on how to use the Microprocessor
Serial Interface.
5.1 DESCRIPTION OF THE COMMAND REGISTERS
Conversely, the user can terminate the "All Ones" pattern by writing to Command Register, CR9 and setting the "TAOS" bit-field (D3) to "0".
Table 8 lists the Command Registers, their Addresses, and their bit-formats.
5.0 THE MICROPROCESSOR SERIAL INTERFACE
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REV. 1.1.5
TABLE 8: ADDRESSES AND BIT FORMATS OF XRT7302 COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND
REGISTER
TYPE
D4
D3
D2
D1
D0
0x00
CR0
RO
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
0x01
CR1
R/W
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
0x02
CR2
R/W
Reserved
ENDECDIS1
ALOSDIS1
DLOSDIS1
REQEN1
0x03
CR3
R/W
SR/DR_1
LOSMUT1
RxOFF1
RxClk1_INV
Reserved
0x04
CR4
R/W
Reserved
STS-1/DS3_Ch1
E3_Ch1
LLB1
RLB1
0x05
CR5
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x06
CR6
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x07
CR7
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x08
CR8
R/W
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
0x09
CR9
R/W
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0x0A
CR10
R/W
Reserved
ENDECDIS2
ALOSDIS2
DLOSDIS2
REQEN2
0x0B
CR11
R/W
SR/DR_2
LOSMUT2
RxOFF2
RxClk2_INV
Reserved
0x0C
CR12
R/W
Reserved
STS-1/DS3_Ch2
E3_Ch2
LLB2
RLB2
0x0D
CR13
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x0E
CR14
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x0F
CR15
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
The bit-format and default values for Command Register CR0 are listed below.
The "role/meaning" associated with each of these bitfields is presented below.
COMMAND REGISTER CR0, (ADDRESS = 0X00)
Address
The register addresses presented in the "hexadecimal" format.
Type:
The Command Registers are either "Read-Only"
(RO) type of registers, or are "Read/Write" (R/W) type
of registers.
D3
D2
D1
D0
RLOL1
RLOS1
ALOS1
DLOS1
DMO1
1
1
1
1
1
The function of each of these bit-fields are presented
below.
NOTE: The default value for each of the bit-fields, within
these register will be "0".
Bit D4 - RLOL1 (Receive Loss of Lock Status Channel 1)
Description of Bit-Fields for each Command Register
5.1.1
D4
This "Read-Only" bit-field reflects the "lock" status of
the "Clock Recovery Phase-Locked-Loop", within
Channel 1 of the XRT7302.
Command Register - CR0
This bit-field will be set to "0" if the "Clock Recovery
PLL" (within Channel 1) is in "lock" with the incoming
line signal. Conversely, this bit-field will be set to "1" if
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
the "Clock Recovery PLL" (within Channel 1) is "out
of lock" with the incoming line signal.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
Bit D3 - RLOS1 (Receive Loss of Signal Status Channel 1)
This "Read-Only" bit-field indicates whether or not the
Receiver, within Channel 1 is currently declaring an
LOS (Loss of Signal) Condition.
This bit-field will be set to "0" if Channel 1 is not (currently) declaring the LOS Condition. Conversely, this
bit-field will be set to "1" if Channel 1 is declaring an
LOS Condition.
D4
D3
D2
D1
D0
TxOFF1
TAOS1
TxClkINV1
TxLEV1
TxBIN1
0
0
0
0
0
The function of each of these bit-fields are presented
below.
Bit D4 - TxOFF1 (Transmitter OFF - Channel 1)
This "Read/Write" bit-field permits the user to turn off
the Transmitter (within Channel 1).
Bit D2 - ALOS1 (Analog Loss of Signal Status Channel 1)
Writing a "1" to this bit field will turn off the Transmitter
and tri-state the Transmit Output. Conversely, writing
a "0" to this bit-field will turn-on the Transmitter.
This "Read-Only" bit-field indicates whether or not the
"Analog LOS Detector", within Channel 1, is currently
declaring an LOS condition.
Bit D3 - TAOS1 (Transmit All OneS - Channel 1)
This bit-field will be set to "0" if the "Analog LOS Detector", within Channel 1, is NOT (currently) declaring
an LOS condition. Conversely, this bit-field will be set
to "1" if the "Analog LOS Detector", within Channel 1,
is currently declaring an LOS condition.
This "Read/Write" bit-field permits the user to command the Transmitter (within Channel 1) to generate
and transmit an "All Ones" pattern onto the line.
Writing a "1" to this bit-field commands the Transmitter to transmit an "All Ones" pattern onto the line.
Writing a "0" to this bit-field commands normal operation.
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the "Analog LOS" or the "Digital LOS" detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes
Bit D2 - TxClkINV1 (Transmit Clock Invert - Channel 1)
Bit D1 - DLOS1 (Digital Loss of Signal Status Channel 1)
This "Read/Write" bit-field permits the user to configure the "Transmitter" (within the XRT7302) to sample
the signal (at the TPData and TNData pins) on the
"rising edge" or "falling edge" of TxClk (the Transmit
Line Clock signal).
This "Read-Only" bit-field indicates whether or not the
"Digital LOS Detector", within Channel 1, is currently
declaring an LOS condition.
This bit-field will be set to "0" if the "Digital LOS Detector", within Channel 1, is NOT (currently) declaring
an LOS condition. Conversely, this bit-field will be set
to "1" if the "Digital LOS Detector", within Channel 1,
is currently declaring an LOS condition.
Writing a "1" to this bit-field configures the Transmitter
to sample the TPData and TNData input pins, on the
"rising edge" of TxClk. Conversely, writing a "0" to
this bit-field configures the Transmitter to sample the
TPData and TNData input pins, on the "falling edge"
of TxClk.
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the "Analog LOS" or the "Digital LOS" detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes.
Bit D1 - TxLEV1 (Transmit Line Build-Out Enable/
Disable Select - Channel 1)
Bit D0 - DMO1 (Drive Monitor Output Status Channel 1)
This "Read/Write" bit-field permits the user to enable
or disable the Transmit Line Build-Out circuit, within
Channel 1 of the XRT7302.
This "Read-Only" bit-field reflects the status of the
DMO1 output pin.
Setting this bit-field "HIGH" disables the Line BuildOut circuit within Channel 1. In this mode, Channel 1
will output unshaped (e.g., square-wave) pulses onto
the line via the TTIP1 and TRing1 output pins.
5.1.2 Command Register CR1
The bit-format and default values for Command Register CR1 are listed below.
Setting this bit-field "LOW" enables the Line Build-Out
circuit within Channel 1. In this mode, Channel 1 will
output shaped pulses onto the line via the TTIP1 and
TRing1 output pins.
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XRT7302
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This "Read/Write" bit-field permits the user to configure the "Transmitter" (within Channel 1) to accept an
(un-encoded) binary data stream (via the TPData input) and converts this data into the appropriate bipolar signal (to the line).
In order to comply with the "Isolated DSX-3/STSX-1
Pulse Template Requiremnts (per Bellcore GR-499CORE or GR-253-CORE), the user should:
a. Set this bit-field to "1", if the cable length (between
the Cross-Connect and the transmit output of Channel 1) is greater than 225 feet.
Writing a "1" configures the "Transmitter" to accept a
binary data stream via the TPData input. (Note: The
TNData input will be ignored). This form of data acceptance is sometimes referred to as "Single-rail"
mode operation. The Transmitter will then encode
this data into the appropriate line code (e.g., B3ZS or
HDB3) prior to its transmission over the line.
b. Set this bit-field to "0", if the cable length (between
the Cross-Connect and the transmit output of Channel 1) is less than 225 feet.
This bit-field is active only if the XRT7302 is configured to operate in the DS3 or SONET STS-1 Modes.
If the cable length is greater than 225 feet, then the
user should set this bit-field to "1" (in order to increase the amplitude of the Transmit Output Signal).
Conversely, if the cable length is less than 225 feet,
then the user should set this bit-field to "0".
Writing a "0" configures the "Transmitter" to accept
data in a "dual-rail" manner (e.g., via both the TPData
and TNData inputs).
NOTE: This option is only available when the XRT7302 is
operating in the DS3 or STS-1 Mode.
The bit-format and default values for Command Register CR2 are listed below.
5.1.3
Command Register CR2
Bit D0 - TxBIN1 (Transmit Binary Data - Channel 1)
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved
ENDEC_DIS1
ALOSDIS1
DLOSDIS1
REQ_EN1
X
0
0
0
0
The function of each of these bit-fields are presented
below.
Bit D4 - Reserved
Note: If the user disables the Analog LOS Detector,
then the RLOS input pin will only be asserted by the
DLOS (Digital LOS Detector).
Bit D3 - ENDEC_DIS1 (B3ZS/HDB3 Encoder/Decoder-Disable - Channel 1)
Bit D1 - DLOSDIS1 (Digital LOS Disable - Channel
1)
This "Read/Write" bit-field permits the user to enable
or disable the B3ZS/HDB3 Encoder and Decoder
blocks, within Channel 1.
This "Read/Write" bit-field permits the user to disable
the Digital LOS Detector within Channel 1.
Writing a "0" to this bit-field enables the Digital LOS
Detector. Writing a "1" to this bit-field disables the
Digital LOS Detector.
Writing a "1" to this bit-field disables the B3ZS/HDB3
Encoder and Decoder blocks. Writing a "0" to this bitfield enables the B3ZS/HDB3 Encoder and Decoder
blocks.
NOTE: If the user disables the Digital LOS Detector, then
the RLOS input pin will only be asserted by the ALOS (Analog LOS Detector).
NOTE: This Encoder/Decoder will perform HDB3 Encoding/
Decoding if the XRT7302 is operating in the "E3 Mode".
Otherwise, it will perform B3ZS Encoding/Decoding.
Bit D0 - REQ_EN1 (Receive Equalization Enable Channel 1)
Bit D2 - ALOSDIS1 (Analog LOS Disable - Channel
1)
This "Read/Write" bit-field permits the user to either
enable or disable the internal Receive Equalizer, within Channel 1 of the XRT7302.
This "Read/Write" bit-field permits the user to disable
the Analog LOS Detector, within Channel 1.
Writing a "1" to this bit-field enables the "Internal
Equalizer". Conversely, writing a "0" to this bit-field
disables the "Internal Equalizer".
Writing a "0" to this bit-field enables the Analog LOS
Detector. Writing a "1" to this bit-field disables the
Analog LOS Detector.
5.1.4
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Command Register CR3
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
This "Read/Write" bit-field permits the user to configure the "Receiver" (within Channel 1 of the XRT7302)
to output the recovered data on either the "rising
edge" or the "falling edge" of the RxClk1 clock signal.
The bit-format and default values for Command Register CR3 are listed below.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
D0
Writing a "0" to this bit-field configures the Receiver to
output the recovered data on the "rising edge" of the
RxClk1 output signal. Writing a "1" to this bit-field
configures the Receiver to output the recovered data
on the "falling edge" of the RxClk1 output signal.
SR/DR_1 LOSMUT1 RxOFF1 RxClk1_INV Reserved
0
1
0
0
0
The function of each of these bit-fields are presented
below.
Bit D0 - Reserved
This bit-field has no defined functionality
Bit D4 - SR/DR_1 (Single-Rail/Dual-Rail Data Output - Channel 1)
Command Register CR4
The bit-format and default values for Command Register CR4 are listed below.
This "Read/Write" bit-field permits the user to configure Channel 1 (within the XRT7302) to output the "received" data (from the Remote Terminal) in a binary
or "dual-rail" format.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
Writing a "1" to this bit-field configures Channel 1 to
output data (to the Terminal Equipment) in a binary
(single-rail) format via the RPOS1 output pin, RNEG1
will be grounded. Conversely, a "0" to this bit-field
configures Channel 1 to output data (to the Terminal
Equipment) in a "Dual Rail" format via both the
RPOS1 and RNEG1 output pins.
D3
Reserved
STS-1/DS3_Ch1
0
0
D2
D1
E3_Ch1 LLB1
0
D0
RLB1
0
0
The function of each of these bit-fields are presented
below.
Bit D3 - LOSMUT1 (Recovered Data MUTing, during LOS Condition - Channel 1)
Bit D4 - Reserved
This bit-field has no defined functionality
This "Read/Write" bit-field permits the user to configure Channel 1 (within the XRT7302) to not output any
recovered data (from the line), while it is declaring an
LOS condition.
Bit D3 - STS-1/DS3 - Channel 1 - Mode Select
This "Read/Write" bit field permits the user to configure Channel 1, (within the XRT7302) to operate in either the SONET STS-1 Mode or the DS3 Mode.
Writing a "0" to this bit-field configures the chip to output recovered data, even while the XRT7302 is declaring an "LOS" condition. Writing a "1" to this bitfield configures the chip to NOT output the recovered
data, while an LOS condition is being declared.
(Note: in this mode, RPOS1 and RNEG1 will be set
to "0", asynchronously.)
Writing a "0" into this bit-field configures Channel 1 to
operate in the "DS3 Mode". Writing a "1" into this bitfield configures Channel 1 to operate in the SONET
STS-1 Mode.
Note: This bit-field is ignored if the "E3_Ch_1" bitfield (e.g., "D2" within this Command Register) is set
to "1".
Bit D2 - RxOFF1 (Receive Section - Shut OFF Select)
Bit D2 - E3 Mode Select - Channel 1
This "Read/Write" bit-field permits the user to shut-off
the "Receive Section of Channel 1 (within the
XRT7302). The purpose of this feature is to permit
the user to conserve power consumption when this
device is the back-up device in a "Redundancy System".
This "Read/Write" bit-field permits the user to configure Channel 1 (within the XRT7302) to operate in the
E3 Mode.
Writing a "0" into this bit-field configures Channel 1 to
operate in either the DS3 or SONET STS-1 Mode (as
specified by the setting of the "DS3" bit-field within
this Command Register). Writing a "1" into this bitfield configures Channel 1 to operate in the E3 Mode.
Writing a "1" into this bit-field shuts off the Receive
Section of Channel 1. Conversely, writing a "0" into
this bit-field turns on the Receive Section of Channel
1.
Bit D1 - LLB1 (Local Loop-back - Channel 1)
Bit D1 - RxClk1_INV (Invert RxClk1)
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
Bit D0 - RLB1 (Remote Loop-back - Channel 1)
This "Read/Write" bit-field, along with "RLB1" permits
the user to configure Channel 1 (within the XRT7302)
to operate in any one of a variety of loop-back modes.
This "Read/Write" bit-field, along with "LLB1" permits
the user to configure Channel 1 (within the XRT7302)
to operate in any one of a variety of loop-back modes.
Table 9 relates the contents of "LLB1" and "RLB1" to
the corresponding loop-back mode for Channel 1.
Table 9 relates the contents of "LLB1" and "RLB1" to
the corresponding loop-back mode for Channel 1.
TABLE 9: CONTENTS OF "LLB1" AND "RLB1" AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL 1
5.1.5
LLB1
RLB1
LOOP-BACK MODE (FOR CHANNEL 1)
0
0
None
1
0
Analog Loop-Back Mode (See Section 4.1 for Details)
1
1
Digital Loop-Back Mode (See Section 4.2 for Details
0
1
Remote Loop-Back Mode (See Section 4.3 for Details
Bit D2 - ALOS2 (Analog Loss of Signal Status Channel 2)
Command Register - CR8
The bit-format and default values for Command Register CR8 are listed below.
This "Read-Only" bit-field indicates whether or not the
"Analog LOS Detector", within Channel 2, is currently
declaring an LOS condition.
COMMAND REGISTER 8, (ADDRESS = 0X08)
D4
D3
D2
D1
D0
RLOL2
RLOS2
ALOS2
DLOS2
DMO2
1
1
1
1
1
This bit-field will be set to "0" if the "Analog LOS Detector", within Channel 2, is NOT (currently) declaring
an LOS condition. Conversely, this bit-field will be set
to "1" if the "Analog LOS Detector", within Channel 2,
is currently declaring an LOS condition.
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the "Analog LOS" or the "Digital LOS" detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes.
The function of each of these bit-fields are presented
below.
Bit D4 - RLOL2 (Receive Loss of Lock Status Channel 2)
Bit D1 - DLOS2 (Digital Loss of Signal Status Channel 2)
This "Read-Only" bit-field reflects the "lock" status of
the "Clock Recovery Phase-Locked-Loop", within
Channel 2 of the XRT7302.
This "Read-Only" bit-field indicates whether or not the
"Digital LOS Detector", within Channel 2, is currently
declaring an LOS condition.
This bit-field will be set to "0" if the "Clock Recovery
PLL" (within Channel 2) is in "lock" with the incoming
line signal. Conversely, this bit-field will be set to "1" if
the "Clock Recovery PLL" (within Channel 2) is "out
of lock" with the incoming line signal.
This bit-field will be set to "0" if the "Digital LOS Detector", within Channel 2, is NOT (currently) declaring
an LOS condition. Conversely, this bit-field will be set
to "1" if the "Digital LOS Detector", within Channel 2,
is currently declaring an LOS condition.
Bit D3 - RLOS2 (Receive Loss of Signal Status Channel 2)
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the "Analog LOS" or the "Digital LOS" detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes.
This "Read-Only" bit-field indicates whether or not the
Receiver, within Channel 2 is currently declaring an
LOS (Loss of Signal) Condition.
Bit D0 - DMO2 (Drive Monitor Output Status Channel 2)
This bit-field will be set to "0" if Channel 2 is not (currently) declaring the LOS Condition. Conversely, this
bit-field will be set to "1" if Channel 2 is declaring an
LOS Condition.
This "Read-Only" bit-field reflects the status of the
DMO2 output pin.
5.1.6
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Command Register CR9
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
This "Read/Write" bit-field permits the user to enable
or disable the Transmit Line Build-Out circuit, within
Channel 2 of the XRT7302.
The bit-format and default values for Command Register CR9 are listed below.
COMMAND REGISTER CR9 (ADDRESS = 0X09)
D4
D3
D2
D1
D0
TxOFF2
TAOS2
TxClkINV2
TxLEV2
TxBIN2
0
0
0
0
0
Setting this bit-field "HIGH" disables the Line BuildOut circuit within Channel 2. In this mode, Channel 2
will output unshaped (e.g., square-wave) pulses onto
the line via the TTIP2 and TRing2 output pins.
Setting this bit-field "LOW" enables the Line Build-Out
circuit within Channel 2. In this mode, Channel 2 will
output shaped pulses onto the line via the TTIP2 and
TRing2 output pins.
The function of each of these bit-fields are presented
below.
Bit D4 - TxOFF2 (Transmitter OFF - Channel 2)
This "Read/Write" bit-field permits the user to turn off
the Transmitter (within Channel 2).
In order to comply with the "Isolated DSX-3/STSX-1
Pulse Template Requiremnts (per Bellcore GR-499CORE or GR-253-CORE), the user should:
Writing a "1" to this bit field will turn off the Transmitter
and tri-state the Transmit Output. Conversely, writing
a "0" to this bit-field will turn-on the Transmitter.
c. Set this bit-field to "1", if the cable length (between
the Cross-Connect and the transmit output of Channel 2) is greater than 225 feet.
Bit D3 - TAOS2 (Transmit All OneS - Channel 2)
d. Set this bit-field to "0", if the cable length (between
the Cross-Connect and the transmit output of Channel 2) is less than 225 feet.
This "Read/Write" bit-field permits the user to command the Transmitter (within Channel 2) to generate
and transmit an "All Ones" pattern onto the line.
This bit-field is active only if the XRT7302 is configured to operate in the DS3 or SONET STS-1 Modes.
Writing a "1" to this bit-field commands the Transmitter to transmit an "All Ones" pattern onto the line.
Writing a "0" to this bit-field commands normal operation.
Bit D0 - TxBIN2 (Transmit Binary Data - Channel 2)
This "Read/Write" bit-field permits the user to configure the "Transmitter" (within Channel 2) to accept an
(un-encoded) binary data stream (via the TPData2 input) and converts this data into the appropriate bipolar signal (to the line).
Bit D2 - TxClkINV2 (Transmit Clock Invert - Channel 2)
This "Read/Write" bit-field permits the user to configure the "Transmitter" (within the XRT7302) to sample
the signal (at the TPData2 and TNData2 pins) on the
"rising edge" or "falling edge" of TxClk2 (the Transmit
Line Clock signal).
Writing a "1" configures the "Transmitter" to accept a
binary data stream via the TPData2 input. (Note:
The TNData2 input will be ignored). This form of data
acceptance is sometimes referred to as "Single-rail"
mode operation. The Transmitter will then encode
this data into the appropriate line code (e.g., B3ZS or
HDB3) prior to its transmission over the line.
Writing a "1" to this bit-field configures the Transmitter
to sample the TPData2 and TNData2 input pins, on
the "rising edge" of TxClk2. Conversely, writing a "0"
to this bit-field configures the Transmitter to sample
the TPData2 and TNData2 input pins, on the "falling
edge" of TxClk2.
Writing a "0" configures the "Transmitter" to accept
data in a "dual-rail" manner (e.g., via both the
TPData2 and TNData2 inputs).
Bit D1 - TxLEV2 (Transmit Line Build-Out Enable/
Disable Select - Channel 2)
5.1.7
Command Register CR10
The bit-format and default values for Command Register CR10 are listed below.
COMMAND REGISTER CR10 (ADDRESS = 0X0A)
D4
D3
D2
D1
D0
Reserved
ENDEC_DIS2
ALOSDIS2
DLOSDIS2
REQ_EN2
X
0
0
0
0
Bit D4 - Reserved
The function of each of these bit-fields are presented
below.
This bit-field has no defined functionality
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
Bit D3 - ENDEC_DIS2 (B3ZS/HDB3 Encoder/Decoder-Disable - Channel 1)
The function of each of these bit-fields are presented
below.
This "Read/Write" bit-field permits the user to enable
or disable the B3ZS/HDB3 Encoder and Decoder
blocks, within Channel 2.
Bit D4 - SR/DR_2 (Single-Rail/Dual-Rail Data Output - Channel 2)
This "Read/Write" bit-field permits the user to configure Channel 2 (within the XRT7302) to output the "received" data (from the Remote Terminal) in a binary
or "dual-rail" format.
Writing a "1" to this bit-field disables the B3ZS/HDB3
Encoder and Decoder blocks. Writing a "0" to this bitfield enables the B3ZS/HDB3 Encoder and Decoder
blocks.
Writing a "1" to this bit-field configures Channel 2 to
output data (to the Terminal Equipment) in a binary
(single-rail) format via the RPOS2 output pin, RNEG2
will be grounded. Conversely, a "0" to this bit-field
configures Channel 2 to output data (to the Terminal
Equipment) in a "Dual Rail" format via both the
RPOS2 and RNEG2 output pins.
NOTE: This Encoder/Decoder will perform HDB3 Encoding/
Decoding if the XRT7302 is operating in the "E3 Mode".
Otherwise, it will perform B3ZS Encoding/Decoding.
Bit D2 - ALOSDIS2 (Analog LOS Disable - Channel
2)
This "Read/Write" bit-field permits the user to disable
the Analog LOS Detector, within Channel 2.
Bit D3 - LOSMUT2 (Recovered Data MUTing, during LOS Condition - Channel 2)
Writing a "0" to this bit-field enables the Analog LOS
Detector. Writing a "1" to this bit-field disables the
Analog LOS Detector.
This "Read/Write" bit-field permits the user to configure Channel 2 (within the XRT7302) to not output any
recovered data (from the line), while it is declaring an
LOS condition.
NOTE: If the user disables the Analog LOS Detector, then
the RLOS input pin will only be asserted by the DLOS (Digital LOS Detector).
Writing a "0" to this bit-field configures the chip to output recovered data, even while the XRT7302 is declaring an "LOS" condition. Writing a "1" to this bitfield configures the chip to NOT output the recovered
data, while an LOS condition is being declared.
(Note: in this mode, RPOS2 and RNEG2 will be set
to "0", asynchronously.)
Bit D1 - DLOSDIS2 (Digital LOS Disable - Channel
2)
This "Read/Write" bit-field permits the user to disable
the Digital LOS Detector within Channel 2.
Writing a "0" to this bit-field enables the Digital LOS
Detector. Writing a "1" to this bit-field disables the
Digital LOS Detector.
Bit D2 - RxOFF2 (Receive Section - Shut OFF Select)
NOTE: If the user disables the Digital LOS Detector, then
the RLOS input pin will only be asserted by the ALOS (Analog LOS Detector).
This "Read/Write" bit-field permits the user to shut-off
the "Receive Section of Channel 2 (within the
XRT7302). The purpose of this feature is to permit
the user to converse power consumption when this
device is the back-up device in a "Redundancy System".
Bit D0 - REQ_EN2 (Receive Equalization Disable Channel 2)
This "Read/Write" bit-field permits the user to either
enable or disable the internal Receive Equalizer
(within Channel 2).
Writing a "1" into this bit-field shuts off the Receive
Section of Channel 2. Conversely, writing a "0" into
this bit-field turns on the Receive Section of Channel
2.
Writing a "1" to this bit-field enables the "Internal
Equalizer". Conversely, writing a "0" to this bit-field
disables the "Internal Equalizer".
Bit D1 - RxClk2_INV (Invert RxClk2)
5.2 COMMAND REGISTER CR11
This "Read/Write" bit-field permits the user to configure the "Receiver" (within Channel 2 of the XRT7302)
to output the recovered data on either the "rising
edge" or the "falling edge" of the RxClk2 clock signal.
The bit-format and default values for Command Register CR11 are listed below.
COMMAND REGISTER CR11 (ADDRESS = 0X0B)
D4
D3
D2
D1
Writing a "0" to this bit-field configures the Receiver to
output the recovered data on the "rising edge" of the
RxClk2 output signal. Writing a "1" to this bit-field
configures the Receiver to output the recovered data
on the "falling edge" of the RxClk2 output signal.
D0
SR/DR_1 LOSMUT1 RxOFF1 RxClk1_INV Reserved
0
1
0
0
0
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
NOTE: This bit-field is ignored if the "E3_Ch_2" bit-field
(e.g., "D2" within this Command Register) is set to "1".
Bit D0 - Reserved
This bit-field has no defined functionality.
5.2.1
Bit D2 - E3 Mode Select - Channel 2
Command Register CR12
This "Read/Write" bit-field permits the user to configure Channel 2 (within the XRT7302) to operate in the
E3 Mode.
The bit-format and default values for Command Register CR12 are listed below.
Writing a "0" into this bit-field configures Channel 2 to
operate in either the DS3 or SONET STS-1 Mode (as
specified by the setting of the "DS3" bit-field within
this Command Register). Writing a "1" into this bitfield configures Channel 2 to operate in the E3 Mode.
COMMAND REGISTER CR 12 (ADDRESS = 0X0C)
D4
D3
Reserved
STS-1/DS3_Ch2
0
0
D2
D1
E3_Ch2 LLB2
0
D0
RLB2
0
Bit D1 - LLB2 (Local Loop-back - Channel 2)
0
This "Read/Write" bit-field, along with "RLB2" permits
the user to configure Channel 2 (within the XRT7302)
to operate in any one of a variety of loop-back modes.
The function of each of these bit-fields are presented
below.
Bit D4 - Reserved
Table 10 relates the contents of "LLB2" and "RLB2"
and the corresponding loop-back mode for Channel
2.
This bit-field has no defined functionality
Bit D3 - STS-1/DS3 - Channel 2 - Mode Select
Bit D0 - RLB2 (Remote Loop-back - Channel 2)
This "Read/Write" bit field permits the user to configure Channel 2, (within the XRT7302) to operate in either the SONET STS-1 Mode or the DS3 Mode.
This "Read/Write" bit-field, along with "LLB2" permits
the user to configure Channel 2 (within the XRT7302)
to operate in any one of a variety of loop-back modes.
Writing a "0" into this bit-field configures Channel 2 to
operate in the "DS3 Mode". Writing a "1" into this bitfield configures Channel 2 to operate in the SONET
STS-1 Mode.
Table 10 relates the contents of "LLB2" and "RLB2"
and the corresponding loop-back mode for Channel
2.
TABLE 10: CONTENTS OF "LLB2" AND "RLB2" AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL 2
LLB2
RLB2
LOOP-BACK MODE (FOR CHANNEL 2)
0
0
None
1
0
Analog Loop-Back Mode (See Section 4.1 for Details)
1
1
Digital Loop-Back Mode (See Section 4.2 for Details
0
1
Remote Loop-Back Mode (See Section 4.3 for Details
5.3 OPERATING THE MICROPROCESSOR SERIAL
INTERFACE .
The following instructions, for using the Microprocessor Serial Interface, are best understood by referring
to the diagram in Figure 31.
The XRT7302 Serial Interface is a simple four wire interface that is compatible with many of the microcontrollers available in the market. This interface consists of the following signals:
In order to use the Microprocessor Serial Interface
the user must first provide a clock signal to the SClk
input pin. Afterwards, the user will initiate a "Read" or
"Write" operation by asserting the "active-low" Chip
Select input pin (CS). It is important to assert the CS
pin (e.g., toggle it "low") at least 50ns prior to the very
first rising edge of the clock signal.
• CS - Chip Select (Active Low)
• SClk - Serial Clock
• SDI - Serial Data Input
Once the CS input pin has been asserted the type of
operation and the target register address must now
be specified by the user. The user provides this information to the Microprocessor Serial Interface by writing eight serial bits of data into the SDI input. Note:
• SDO - Serial Data Output
Using the Microprocessor Serial Interface
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
this point the user can begin reading the data contents of the addressed Command Register (at Address [A3, A2, A1, A0]) via the SDO output pin. The
Microprocessor Serial Interface will output this five bit
data word (D0 through D4) in ascending order (with
the LSB first), on the falling edges of the SClk pin. As
a consequence, the data (on the SDO output pin) will
be sufficiently stable for reading (by the Microprocessor), on the very next rising edge of the SClk pin.
each of these bits will be "clocked" into the SDI input,
on the rising edge of SClk. These eight bits are identified and described below.
Bit 1 - "R/W" (Read/Write) Bit
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
"Read" or "Write" operation. A "1" in this bit specifies
a "Read" operation; whereas, a "0" in this bit specifies
a "Write" operation.
Write Operation
The next four rising edges of the SClk signal will clock
in the 4-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register, within the XRT7302 that the user will either
be reading data from, or writing data to. The user
must supply the address bits to the SDI input pin, in
ascending order with the LSB (least significant bit)
first.
Once the last address bit (A3) has been clocked into
the SDI input, the "Write" operation will proceed
through an idle period, lasting three SClk periods.
Prior to the rising edge of SClk Cycle # 9 (see
Figure 31) the user must begin to apply the eight bit
data word, that he/she wishes to write to the Microprocessor Serial Interface, onto the SDI input pin.
The Microprocessor Serial Interface will latch the value on the SDI input pin, on the rising edge of SClk.
The user must apply this word (D0 through D7) serially, in ascending order with the LSB first.
Bits 6 and 7:
Simplified Interface Option
The next two bits, A4 and A5 must be set to "0", as
shown in Figure 31.
The user can simplify the design of the circuitry connecting to the Microprocessor Serial Interface by tying both the SDO and SDI pins together, and reading
data from and/or writing data to this "combined" signal. This simplification is possible because only one
of these signals are active at any given time. The inactive signal will be tri-stated.
Bits 2 through 5: The four (4) bit Address Values
(labeled A0, A1, A2 and A3)
Bit 8 - A6
The value of "A6" is a "don't care".
Once these first 8 bits have been written into the Microprocessor Serial Interface, the subsequent action
depends upon whether the current operation is a
"Read" or "Write" operation.
NOTES:
1. A4 and A5 are always "0"
Read Operation
2. R/W = "1" for "Read" Operations
Once the last address bit (A3) has been clocked into
the SDI input, the "Read" operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 31) the
serial data output signal (SDO) becomes active. At
3. R/W = "0" for "Write" Operations
4.
- Denotes a "don't care" value
FIGURE 31. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
0
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
High Z
High Z
SDO
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
FIGURE 32. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SCLK
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SCLK
t31
t30
SDO
SDI
Hi-Z
D0
t33
D2
D1
Hi-Z
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t32
D7
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.5
ORDERING INFORMATION
PART #
PACKAGE
OPERATING TEMPERATURE RANGE
XRT7302IV
80 Pin Thermally Enhanced TQFP
-40oC to +85oC
THERMAL INFORMATION
Theta - JA = 23° C/W
Theta JC = 5.32° C/W
PACKAGE DIMENSIONS
80 LEAD THIN QUAD FLAT PACK
WITH Cu HEAT SLUG
(14X14X1.4mm, TQFP)
Rev. 1.0
D
D1
Heat Slug
Pure Copper
OFHC 0.9999
Solder Plated
(package bottom)
41
60
40
61
β
D1
80
D
21
1
20
A2
e
B
C
A
α
L
A1
SYMBOL
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.055
0.063
1.40
1.60
A1
0.002
0.006
0.05
0.15
A2
0.053
0.057
1.35
1.45
B
0.009
0.015
0.22
0.38
C
0.004
0.008
0.09
0.20
D
0.622
0.638
15.80
16.20
D1
0.547
0.555
13.90
14.10
e
L
α
0.0256BSC
0.018
0o
0.65BSC
0.030
0.45
0.75
7o
0o
7o
β
0.340
0.370
8.64
Note: the control dimension is the millimeter column
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9.40
XRT7302
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2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.5
REVISION HISTORY
Rev. 1.0.1: Pin naming conventions standardized with use of uppercase and lowercase letters. Modified
and added title to Pin Out diagram for readability.
The pin descriptions for pins 30 (“REQ_EN1”), 31 (“REQ_EN2”), 61 (“TxOFF2”), 80 (“TxOFF1”) have been
revised. Added Table 7.
Rev. 1.0.2: Added Absolute Maximum Ratings and Test Conditions. Book marked PDF file.
Rev. 1.0.3: Minor formatting changes for readability
Rev. 1.1.0: Standardize pin names, updated block diagram, updated Electrical Characteristics, minor
grammar edits, removed “Preliminary”.
Rev. 1.1.1: Pin 7 - Receive Analog VDD to Receive Digital VDD and pin 56 - Transmit Digital GND instead
of Receive. Nomenclature for GND and VDD changed to include A-for analog, and D-for Digital. Package
designation from IQ to IV.
Rev. 1.1.2: Added Tx Control title in block diagram.
Rev. 1.1.3: Modified package dimensions drawing adding Heat Slug integral to package bottom.
Rev. 1.1.4: Modified figures 3 & 4
Rev. 1.1.5: Modified figure 4, LCV signal
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2000 EXAR Corporation
Datasheet August 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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