EXAR XRT73L00A

áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
AUGUST 2002
REV. 2.0.1
FEATURES
• Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L00
GENERAL DESCRIPTION
The XRT73L00A DS3/E3/STS-1 Line Interface Unit is
an improved version of the XRT73L00 and consists of
a line transmitter and receiver integrated on a single
chip and is designed for DS3, E3 or SONET STS-1
applications.
• Meets E3/DS3/STS-1 Jitter Tolerance Requirements
• Full Loop-Back Capability
XRT73L00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
• Transmit and Receive Power Down Modes
• Full Redundancy Support
• Contains a 4-Wire Microprocessor Serial Interface
In the transmit direction, the XRT73L00A encodes input data to either B3ZS (for DS3/STS-1 applications)
or HDB3 (for E3 applications) format and converts the
data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer.
• Uses Minimum External components
• Single +3.3V Power Supply
• 5 V Tolerant pins
• -40°C to +85°C Operating Temperature Range
In the receive direction the XRT73L00A performs
equalization on incoming signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects
and declares the occurrence of line code violations.
• Available in a 44 pin TQFP package
The XRT73L00A also contains a 4-Wire Microprocessor Serial Interface for accessing the on-chip Command registers.
• Fiber Optic Terminals
APPLICATIONS
• Interfaces to E3, DS3 or SONET STS-1 Networks
• CSU/DSU Equipment
• PCM Test Equipment
• Multiplexers
FIGURE 1. BLOCK DIAGRAM OF THE XRT73L00A
E3
R T IP
R R IN G
S T S -1 /D S 3
H o s t/(H W )
AGC/
E qualizer
RLO L EXCLK
R C L K IN V
RCLK1
C lock
R ecovery
S licer
P eak
D etecto r
R E Q D IS
IC T
Invert
L C V /(R C L K 2 )
D ata
R ecovery
LO S D etector
H D B 3/
B 3Z S
D ecode r
RPOS
RNEG
LOSTHR
D R /S R
SDI
S D O /(L C V )
S C lk
CS
S erial
P rocesso r
Interface
RLO S
LLB
Loop M U X
RLB
E N D E C D IS
REGRESET
TAOS
T T IP
P ulse
S haping
T R IN G
M T IP
M R IN G
D evice
M onitor
Tx
C ontro l
H D B 3/
B 3Z S
E ncoder
TPD ATA
Tra nsm it
Logic
TND ATA
D uty C ycle A dju st
T C lk
TXLEV
TXO FF
DMO
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
ORDERING INFORMATION
PART NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRT73L00AIV
44 Pin TQFP (10mm x 10mm)
-40°C to +85°C
MRING
TxAVDD
TTIP
TRING
TxAGND
TNDATA
TPDATA
TCLK
TXOFF
44
43
42
41
40
39
38
37
36
35
ICT
MTIP
FIGURE 2. PIN OUT OF THE XRT73L00A IN THE 44 PIN TQFP
34
TxLEV
1
33
RPOS
TAOS
2
32
RNEG
TxAVDD
3
31
RCLK1
DMO
4
30
LCV/(RCLK2)
TxAGND
5
29
RxDVDD
AGND
6
28
RxDGND
RxAGND
7
27
EXCLK
RTIP
8
26
DVDD
RRING
9
25
DGND
RxAVDD
10
24
RLOS
REGRESET/
RCLK2INV
11
23
RLOL
LLB
RLB
STS1/DS3
18
19
20
21
22
CS/(DR/SR)
LOSTHR
17
SCLK/(ENDECDIS)
16
SDO/(LCV)
15
SDI/(LOSMUTEN)
14
HOST/HW
13
E3
12
REQDIS
XRT73L00A
(Top View)
2
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1. Block Diagram of the XRT73L00A .................................................................................................... 1
ORDERING INFORMATION ............................................................................................... 2
Figure 2. Pin Out of the XRT73L00A in the 44 Pin TQFP ................................................................................ 2
TABLE OF CONTENTS .........................................................................................................I
PIN DESCRIPTION ............................................................................................................. 3
ELECTRICAL CHARACTERISTICS ................................................................................. 11
ABSOLUTE MAXIMUM RATINGS ...................................................................................................
DC ELECTRICAL CHARACTERISTICS ............................................................................................................
AC ELECTRICAL CHARACTERISTICS ............................................................................................................
Figure 3. Timing Diagram of the Transmit Terminal Input Interface ...............................................................
Figure 4. Timing Diagram of the Receive Terminal Output Interface .............................................................
Figure 5. Transmit Pulse Amplitude Test Circuit for DS3, E3 and STS-1 Rates ............................................
AC ELECTRICAL CHARACTERISTICS (CONT’D) LINE SIDE PARAMETERS ...........................................
Figure 6. ITU-T G.703 Transmit Output Pulse Template for E3 Applications .................................................
Figure 7. Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................
Figure 8. Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ...........
Figure 9. Microprocessor Serial Interface Data Structure ..............................................................................
AC ELECTRICAL CHARACTERISTICS (CONT.) ...................................................................................
Figure 10. Timing Diagram for the Microprocessor Serial Interface ...............................................................
11
11
12
13
13
13
16
17
17
18
18
19
19
SYSTEM DESCRIPTION ................................................................................................... 20
THE TRANSMIT SECTION ............................................................................................................................ 20
THE RECEIVE SECTION .............................................................................................................................. 20
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................ 20
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L00A IS OPERATING IN THE HARDWARE MODE ...................................................................................................................................... 20
1.0 Selecting the Data Rate ............................................................................................. 21
TABLE 2: SELECTING THE DATA RATE FOR THE XRT73L00A VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE
MODE) ............................................................................................................................................... 21
COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 21
TABLE 3: SELECTING THE DATA RATE FOR THE XRT73L00A VIA THE STS-1/DS3 AND THE E3 BIT-FIELDS WITHIN
COMMAND REGISTER CR4 (HOST MODE) .......................................................................................... 21
2.0 The Transmit Section ................................................................................................ 22
2.1 THE TRANSMIT LOGIC BLOCK .............................................................................................................. 22
Figure 11. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Transmitting Terminal Equipment to the Transmit Section of the XRT73L00A ...................................................... 22
Figure 12. How the XRT73L00A Samples the Data on the TPDATA and TNDATA Input Pins ..................... 22
2.1.1 Accepting Single-Rail Data from the Terminal Equipment ................................................. 23
COMMAND REGISTER CR1 (ADDRESS = 0X01) ........................................................................................... 23
Figure 13. The Behavior of the TPDATA and TCLK Input Signals While the Transmit Logic Block is Accepting
Single-Rail Data From the Terminal Equipment ........................................................................... 23
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ...................................................................... 23
2.3 THE HDB3/B3ZS ENCODER BLOCK .................................................................................................... 24
2.3.1 B3ZS Encoding ....................................................................................................................... 24
Figure 14. An Example of B3ZS Encoding ..................................................................................................... 24
2.3.2 HDB3 Encoding ...................................................................................................................... 24
Figure 15. An Example of HDB3 Encoding .................................................................................................... 24
2.3.3 Enabling/Disabling the HDB3/B3ZS Encoder ...................................................................... 25
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY ........................................................................................... 25
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 2.0.1
COMMAND REGISTER CR2 (ADDRESS = 0X02) ............................................................................................
2.4.1 Enabling the Transmit Line Build-Out Circuit ......................................................................
COMMAND REGISTER CR1 (ADDRESS = 0X01) ............................................................................................
2.4.2 Disabling the Transmit Line Build-Out Circuit .....................................................................
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit .....................................
COMMAND REGISTER CR1 (ADDRESS = 0X01) ............................................................................................
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications ..................................................
2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT73L00A TO THE LINE ..............................................
Figure 16. Recommended Schematic for Interfacing the Transmit Section of the XRT73L00A to the Line ...
TRANSFORMER RECOMMENDATIONS ...............................................................................................
25
25
25
26
26
26
26
26
26
27
3.0 The Receive Section ................................................................................................. 28
3.1 INTERFACING THE RECEIVE SECTION OF THE XRT73L00A TO THE LINE ................................................ 28
Figure 17. Recommended Schematic for Interfacing the Receive Section of the XRT73L00A to the Line (Transformer-Coupling) ........................................................................................................................... 28
Figure 18. Recommended Schematic for Interfacing the Receive Section of the XRT73L00A to the Line (Capacitive-Coupling) ............................................................................................................................... 28
3.2 THE RECEIVE EQUALIZER BLOCK ......................................................................................................... 28
3.2.1 Guidelines for Setting the Receive Equalizer ....................................................................... 29
Figure 19. The Typical Application for the System Installer ........................................................................... 30
3.3 PEAK DETECTOR AND SLICER ............................................................................................................... 31
3.4 CLOCK RECOVERY PLL ....................................................................................................................... 31
COMMAND REGISTER CR2 (ADDRESS = 0X02) ............................................................................................ 31
3.5 THE HDB3/B3ZS DECODER ................................................................................................................ 31
3.5.1 B3ZS Decoding DS3/STS-1 Applications .............................................................................. 31
Figure 20. An Example of B3ZS Decoding ..................................................................................................... 32
3.5.2 HDB3 Decoding E3 Applications ........................................................................................... 32
Figure 21. An Example of HDB3 Decoding ..................................................................................................... 32
3.5.3 Enabling/Disabling the HDB3/B3ZS Decoder ....................................................................... 32
3.6 LOS DECLARATION/CLEARANCE .......................................................................................................... 33
COMMAND REGISTER CR2 (ADDRESS = 0X02) ............................................................................................ 33
3.6.1 The LOS Declaration/Clearance Criteria for E3 Applications ............................................. 33
Figure 22. The Signal Levels that the XRT73L00A Declares and Clears LOS (E3 Mode Only) ..................... 33
Figure 23. The Behavior of the LOS Output Indicator In Response to the Loss of Signal and the Restoration of
Signal ............................................................................................................................................ 34
3.6.2 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications ........................ 34
TABLE 4: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND
REQEN FOR DS3 AND STS-1 APPLICATIONS ..................................................................................... 34
COMMAND REGISTER CR0 (ADDRESS = 0X00) ............................................................................................ 35
COMMAND REGISTER CR2 (ADDRESS = 0X02) ............................................................................................ 35
3.6.3 Muting the Recovered Data while the LOS is being Declared ............................................ 35
COMMAND REGISTER CR0 (ADDRESS = 0X00) ............................................................................................ 35
COMMAND REGISTER CR2 (ADDRESS = 0X02) ............................................................................................ 35
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .. 36
COMMAND REGISTER CR3 (ADDRESS = 0X03) ............................................................................................ 36
Figure 24. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Receive Section
of the XRT73L00A to the Receiving Terminal Equipment ............................................................ 36
Figure 25. How the XRT73L00A Outputs Data on the RPOS and RNEG Output Pins .................................. 37
Figure 26. The Behavior of the RPOS, RNEG and RCLK1 Signals When RCLK1 is Inverted ....................... 37
COMMAND REGISTER CR3 (ADDRESS = 0X03) ............................................................................................ 37
3.7.1 Routing Single-Rail Format data (Binary Data Stream) to the Receive Terminal Equipment
37
COMMAND REGISTER CR3 (ADDRESS = 0X03) ............................................................................................ 38
Figure 27. The Typical Interface for the Transmission of Data in a Single-Rail Format From the Receive Section
of the XRT73L00A to the Receiving Terminal Equipment ............................................................ 38
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
Figure 28. The Behavior of the RPOS and RCLK1 Output Signals While the XRT73L00A is Transmitting SingleRail Data to the Receiving Terminal Equipment ........................................................................... 38
4.0 Diagnostic Features of the XRT73L00A ................................................................... 38
4.1 THE ANALOG LOCAL LOOP-BACK MODE ..............................................................................................
Figure 29. The Analog Local Loop-Back in the XRT73L00A ..........................................................................
COMMAND REGISTER CR4 (ADDRESS = 0X04) ...........................................................................................
4.2 THE DIGITAL LOCAL LOOP-BACK MODE ...............................................................................................
Figure 30. The Digital Local Loop-Back path in the XRT73L00A ...................................................................
COMMAND REGISTER CR4 (ADDRESS = 0X04) ...........................................................................................
4.3 THE REMOTE LOOP-BACK MODE .........................................................................................................
Figure 31. The Remote Loop-Back Path in the XRT73L00A ..........................................................................
4.4 TXOFF FEATURES ..............................................................................................................................
COMMAND REGISTER CR4 (ADDRESS = 0X04) ...........................................................................................
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ..........................................................................................
COMMAND REGISTER CR1 (ADDRESS = 0X01) ...........................................................................................
Figure 32. The XRT73L00A Employing the Transmit Drive Monitor Features ...............................................
Figure 33. Two LIU’s, Each Monitoring the Transmit Output Signal of the Other LIU IC ..............................
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE .......................................................................................
COMMAND REGISTER CR1 (ADDRESS = 0X01) ...........................................................................................
38
39
39
39
40
40
40
41
41
41
41
41
42
43
43
43
5.0 The Microprocessor Serial Interface ........................................................................ 44
5.1 DESCRIPTION OF THE COMMAND REGISTERS ........................................................................................
TABLE 5: ADDRESSES AND BIT FORMATS OF XRT73L00A COMMAND REGISTERS ..............................................
DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER .....................................................................
5.1.1 Command Register - CR0 ......................................................................................................
5.1.2 Command Register - CR1 ......................................................................................................
5.1.3 Command Register - CR2 ......................................................................................................
5.1.4 Command Register - CR3 ......................................................................................................
5.1.5 Command Register - CR4 ......................................................................................................
5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ......................................................................
TABLE 6: LOOP-BACK MODES ...........................................................................................................................
Figure 34. Microprocessor Serial Interface Data Structure ............................................................................
ORDERING INFORMATION ............................................................................................................................
44
44
44
44
45
46
46
46
47
47
48
49
PACKAGE DIMENSIONS ................................................................................................. 49
REVISION HISTORY ..................................................................................................................................... 50
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
1
TXLEV
I
Transmit Line Build-Out Enable/Disable Select:
This input pin is used to enable or disable the Transmit Line Build-Out circuit in
the XRT73L00A.
Setting this pin to “High” disables the Line Build-Out circuit. In this mode, the
XRT73L00A outputs partially shaped pulses onto the line via the TTIP and
TRING output pins.
Setting this pin to “Low” enables the Line Build-Out circuit. In this mode, the
XRT73L00A outputs partially-shaped pulses onto the line via the TTIP and
TRING output pins.
To comply with the isolated DSX-3/STSX-1 Pulse Template Requirements per
Bellcore GR-499-Core or Bellcore GR-253-Core:
1. Set this input pin to a "1" if the cable length between the Cross-Connect and
the transmit output of the XRT73L00A is greater than 225 feet.
2. Set this input pin to a "0" if the cable length between the Cross-Connect and
the transmit output of the XRT73L00A is less than 225 feet.
This pin is active only if both of the following are true:
(a) The XRT73L00A is configured to operate in either the DS3 or SONET STS-1
modes and
(b) The XRT73L00A is configured to operate in the Hardware Mode.
NOTE: This pin should be tied to GND if the XRT73L00A is to be operated in the
HOST mode.
2
TAOS
I
Transmit All Ones Select:
A “High” on this pin causes a continuous AMI all “1’s” pattern to be transmitted
onto the line. The frequency of this “1’s” pattern is determined by TCLK.
NOTES:
1. This input pin is ignored if the XRT73L00A is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
3
TxAVDD
****
4
DMO
O
5
TxAGND
****
Transmit Analog Ground
6
AGND
****
Analog Ground (Substrate)
7
RxAGND
****
Receive Analog Ground
8
RTIP
I
Receive TIP Input:
This input pin along with RRING is used to receive the line signal from the
Remote DS3/E3/STS-1 Terminal.
9
RRING
I
Receive RING Input:
This input pin along with RTIP is used to receive the line signal from the Remote
DS3/E3/STS-1 Terminal.
Transmit Analog Power Supply
Drive Monitor Output:
If no bipolar line signal is detected on the TTIP/TRING output pins via the MTIP
and MRING input pins for 128±32 TCLK periods, then the DMO output pin toggles and remains “High” until the next bipolar pulse is detected.
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
10
RxAVDD
****
REGRESET/
I
Register Reset Input pin (Invert RCLK2 Output - Select):
The function of this pin depends upon whether the XRT73L00A is operating in
the HOST Mode or in the Hardware Mode.
HOST Mode - Register Reset Input pin:
Setting this input pin “Low” causes the XRT73L00A to reset the contents of the
Command Registers to their default settings and operating configuration. This
pin is internally pulled “High”.
Hardware Mode - Invert RCLK2 Output Select:
Setting this input pin “Low” configures the Receive Section of the XRT73L00A to
output the recovered data via the RPOS and RNEG output pins on the rising
edge of the RCLK2 output signal.
Setting this input pin “High” configures the Receive Section to output the recovered data on the falling edge of the RCLK2 output signal.
11
(RCLK2INV)
DESCRIPTION
Receive Analog Power Supply
12
REQDIS
I
Receive Equalization Disable Input:
Setting this input pin “High” disables the Internal Receive Equalizer in the
XRT73L00A. Setting this pin “Low” enables the Internal Receive Equalizer. The
guidelines for enabling and disabling the Receive Equalizer are described in
Section 3.2.
NOTES:
1. This input pin is ignored if the XRT73L00A is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
13
LOSTHR
I
Loss of Signal Threshold Control:
This input pin is used to select the LOS (Loss of Signal) Declaration and Clearance thresholds for the Analog LOS Detector circuit. Two settings are provided
by forcing this signal to either GND or VDD.
NOTE: This pin is only applicable during DS3 or STS-1 operations.
14
LLB
I
Local Loop-Back Select:
This input pin along with RLB dictates which Loop-Back mode the XRT73L00A is
operating in.
A “High” on this pin with RLB being set to “Low” configures the XRT73L00A to
operate in the Analog Local Loop-Back Mode.
A “High” on this pin with RLB also being set to “High” configures the XRT73L00A
to operate in the Digital Local Loop-Back Mode.
NOTES:
1. This input pin is ignored if the XRT73L00A is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
15
RLB
I
Remote Loop-Back Select:
This input pin along with LLB dictates which Loop-Back mode the XRT73L00A is
operating in.
A “High” on this pin with LLB being set to “Low” configures the XRT73L00A to
operate in the Remote Loop-Back Mode.
A “High” on this pin with LLB also being set to “High” configures the XRT73L00A
to operate in the Digital Local Loop-Back Mode.
NOTES:
1. This input pin is ignored if the XRT73L00A is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
16
STS-1/DS3
I
STS-1/DS3 Select Input:
A “High” on this pin configures the Clock Recovery Phase Locked Loop to set its
VCO Center frequency to around 51.84 MHz for SONET STS-1 operations. A
“Low” on this pin configures the Clock Recovery Phase Locked Loop to set its
VCO Center frequency to around 44.736 MHz for DS3 operations.
NOTES:
1. The XRT73L00A ignores this pin if the E3 pin (pin 17) is set to “1”.
2. This input pin is ignored if the XRT73L00A is operating in the HOST
Mode.
3. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
17
E3
I
E3 Select Input:
A “High” on this pin configures the XRT73L00A to operate in the E3 Mode.
A “Low” on this pin configures the XRT73L00A to check the state of the STS-1/
DS3 input pin.
NOTES:
1. This input pin is ignored if the XRT73L00A is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
18
HOST/HW
I
HOST/HW Mode Select:
This input pin is used to enable or disable the Microprocessor Serial Interface
(e.g., consisting of the SDI, SDO, SCLK, CS and REGRESET pins).
Setting this input pin “High” enables the Microprocessor Serial Interface (e.g.
configures the XRT73L00A to operate in the HOST Mode). In this mode, the
XRT73L00A is configured by writing data into the on-chip Command Registers
via the Microprocessor Serial Interface. When the XRT73L00A is operating in
the HOST Mode, it ignores the states of many of the discrete input pins.
Setting this input pin “Low” disables the Microprocessor Serial Interface (e.g.,
configures the XRT73L00A to operate in the Hardware Mode). In this mode,
many of the external input control pins are functional.
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
19
SDI/
(LOSMUTEN)
I
Serial Data Input for the Microprocessor Serial Interface (HOST Mode) or
MUTE-upon-LOS Enable Input (Hardware Mode):
The function of this input pin depends upon whether the XRT73L00A is operating in the HOST or the Hardware Mode.
Serial Data Input for the Microprocessor Serial Interface (HOST Mode):
This pin is used to read or write data into the Command Registers of the Microprocessor Serial Interface. The Read/Write bit, the Address Values of the Command Registers and Data Value to be written during Write Operations are
applied to this pin.
This input is sampled on the rising edge of the SCLK pin (pin 21).
MUTE-upon-LOS Enable Input (Hardware Mode):
In the Hardware Mode this input pin is used to configure the XRT73L00A to Mute
the recovered data via the RPOS and RNEG output pins whenever it declares an
LOS condition.
Setting this input pin “High” configures the XRT73L00A to automatically pull the
RPOS and RNEG output pins to GND whenever it is declaring an LOS condition,
thereby Muting the data being output to the Terminal Equipment.
Setting this input pin “Low” configures the XRT73L00A to NOT automatically
Mute the recovered data whenever an LOS condition is declared.
20
SDO/(LCV)
O
Serial Data Output from the Controller Port/(Line Code Violation Output
(LCV) Indicator.):
The function of this input pin depends upon whether the XRT73L00A is operating in the HOST or the Hardware Mode.
HOST Mode - Microprocessor Serial Interface - Serial Data Output.
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data on this pin is updated on the falling edge of the
SCLK input signal. This pin is tri-stated upon completion of data transfer.
Hardware Mode - Line Code Violation Output Indicator.
This pin pulses “High” for one bit period any time the Receive Section of the
XRT73L00A detects a Line Code Violation in the incoming E3, DS3 or STS-1
Data Stream.
21
SCLK/
(ENDECDIS)
I
Microprocessor Serial Interface Clock Signal/Encoder Disable:
HOST Mode - Microprocessor Serial Interface Clock Signal
This signal is used to sample the data on the SDI pin on the rising edge of this
signal. During Read operations, the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
Hardware Mode - B3ZS/HDB3 Encoder/Decoder Disable
Setting this input pin “High” disables both the B3ZS/HDB3 Encoder and
Decoder. This setting configures the Transmit Section of the XRT73L00A to
transmit data to the remote terminal equipment via the AMI Line Code. This setting also configures the Receive Section to receive a line signal via the AMI Line
Code.
Setting this input pin “Low” enables both the B3ZS/HDB3 Encoder and Decoder.
This setting configures the Transmit Section of the XRT73L00A to transmit data
in the B3ZS format for DS3/STS-1 applications or the HDB3 format for E3 applications. This setting configures the Receive Section to receive a line signal that
has been encoded into the B3ZS or HDB3 line code.
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
22
CS/(DR/SR)
I
Microprocessor Serial Interface - Chip Select/Encoder and Decoder Disable
The function of this input pin depends upon whether the XRT73L00A is operating in the HOST or the Hardware Mode.
HOST Mode - Chip Select Input:
The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to
enable communication with the XRT73L00A via the Microprocessor Serial Interface.
Hardware Mode - Dual-Rail/Single-Rail Select Input:
Setting this input pin “High” configures the XRT73L00A to operate in the DualRail Mode. When the XRT73L00A is operating in this mode, then the Receive
Section of the LIU IC outputs the Recovered Data via both RPOS and RNEG
output pins.
Setting this input pin “Low” configures the XRT73L00A to operate in the SingleRail Mode. When the XRT73L00A is operating in this mode, the Receive Section of the LIU IC outputs the Recovered Data via the RPOS output pin in a
binary data stream. No data will output via the RNEG output pin.
23
RLOL
O
Receive Loss of Lock Output Indicator
This output pin toggles “High” if the XRT73L00A has detected a Loss of Lock
Condition. The XRT73L00A declares an LOL (Loss of Lock) Condition if the
recovered clock frequency deviates from the Reference Clock frequency (available at the EXCLK input pin) by more than 0.5%.
NOTE: The RCLK1/2 output pins are sourced by the signal applied at the EXCLK
input pin anytime the XRT73L00A declares an LOL condition.
24
RLOS
O
Receive Loss of Signal Output Indicator
This output pin toggles “High” if the XRT73L00A has detected a Loss of Signal
Condition in the incoming line signal.
The criteria the XRT73L00A uses to declare an LOS Condition depends upon
whether the device is operating in the E3 or DS3/STS-1 Mode.
25
DGND
****
Digital Ground
26
DVDD
****
Digital Power Supply
27
EXCLK
I
28
RxDGND
****
Receiver Digital Ground
29
RxDVDD
****
Receiver Digital Power Supply
External Reference Clock Input:
Apply a line-rate clock signal to this input pin. This signal is a 34.368MHz clock
signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a
51.84 MHz clock signal for SONET STS-1 applications.
NOTE: This input pin functions as the source of the RxCLK output clock signal
any time the XRT73L00A declares an LOL condition.
7
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
30
LCV/(RCLK2)
O
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT73L00A is operating in
the HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT73L00A is configured to operate in the HOST Mode, then this pin functions as the LCV output pin by default. However, by using the on-chip Command
Registers, this pin can be configured to function as the second Receive Clock
signal output pin RCLK2.
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73L00A outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT73L00A is operating in the HOST Mode and this pin is configured to function as the additional Receive Clock signal output pin, then the
XRT73L00A can be configured to update the data on the RPOS and RNEG output pins on the falling edge of this clock signal.
31
RCLK1
O
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73L00A outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
NOTE: If the XRT73L00A is operating in the HOST Mode, the device can be configured to update the data on the RPOS and RNEG output pins on the falling
edge of this clock signal.
32
RNEG
O
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT73L00A has received a Negative
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTES:
1. If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
2. This output pin is inactive if the XRT73L00A has been configured to
operate in the Single-Rail Mode.
33
RPOS
O
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT73L00A has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
NOTE: If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in
the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not
reflected at this output.
34
ICT
I
In-Circuit Test Input:
Setting this input pin “Low” causes all digital and analog outputs to go into a
high-impedance state in order to permit in-circuit testing. Set this pin “High” for
normal operation.
NOTE: This pin is internally pulled “High”.
8
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
35
TXOFF
I
Transmitter OFF Input:
Setting this input pin “High” configures the XRT73L00A to turn off the Transmitter
in the device. When the Transmitter is shut-off, the TTIP and TRING output pins
will be tri-stated in the XRT73L00A.
NOTES:
1. This input pin is NOT ignored if the XRT73L00A is operating in the
HOST Mode.
2. Tie this pin to GND if the XRT73L00A is going to be operating in the
HOST Mode.
36
TCLK
I
Transmit Clock Input for TPDATA and TNDATA:
This input pin must be driven at 34.368 MHz for E3 applications, 44.736MHz for
DS3 applications, or 51.84MHz for SONET STS-1 applications. The
XRT73L00A uses this signal to sample the TPDATA and TNDATA input pins.
The XRT73L00A is configured to sample these two pins on the falling edge of
this signal.
If the XRT73L00A is operating in the HOST Mode, then the device can be configured to sample the TPDATA and TNDATA input pins on the rising edge of TCLK.
37
TPDATA
I
Transmit Positive Data Input:
The XRT73L00A samples this pin on the falling edge of TCLK. If the device
samples a “1” at this input pin, then it generates and transmits a positive polarity
pulse to the line.
NOTES:
1. The data should be applied to this input pin if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
2. If the XRT73L00A is operating in the HOST Mode, then the XRT73L00A
can be configured to sample the TPDATA pin on either the rising or falling edge of TCLK.
38
TNDATA
I
Transmit Negative Data Input:
The XRT73L00A samples this pin on the falling edge of TCLK. If the device
samples a “1” at this input pin, then it generates and transmits a negative polarity
pulse to the line.
NOTES:
1. This input pin is ignored and should be tied to GND if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment.
2. If the XRT73L00A is operating in the HOST Mode, then the XRT73L00A
can be configured to sample the TNDATA pin on either the rising or falling edge of TCLK.
39
TxAGND
-
Transmit Analog Ground
40
TRING
O
Transmit TIP Output:
The XRT73L00A uses this pin along with TTIP to transmit a bipolar line signal
via a 1:1 transformer.
NOTE: This output pin along with TTIP is tri-stated anytime the TxOFF input pin
or bit-field is set “high”.
9
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
PIN DESCRIPTION
PIN #
SYMBOL
TYPE
DESCRIPTION
41
TTIP
O
Transmit RING Output:
The XRT73L00A uses this pin along with TRING to transmit a bipolar line signal
via a 1:1 transformer.
NOTE: This output pin along with TRING is tri-stated anytime the TxOFF input
pin or bit-field is set “high”.
42
TxAVDD
-
Transmit Analog Power Supply
43
MRING
I
Monitor Ring Input:
This input pin along with the MTIP pin function as the input pins for the Transmit
Drive Monitor. These two input pins are used to determine whether or not a
bipolar line signal is being output via the TTIP and TRING output pins. The
Transmit Drive Monitor circuit will toggle the DMO output pin “high” denoting a
Transmit Line Fault condition if no bipolar pulses are detected via the TTIP/
TRING output pins for 128 bit-periods.
Connect this input pin to the TRING output pin via a 270 ohm resistor.
NOTE: Tie this input pin to GND if you do not intend to use the Transmit Drive
Monitor.
44
MTIP
I
Monitor Tip Input:
This input pin along with the MRING pin function as the input pins for the Transmit Drive Monitor. These two input pins are to be used to determine whether or
not a bipolar line signal is being output via the TTIP and TRING output pins. The
Transmit Drive Monitor circuit will toggle the DMO output pin “high” denoting a
Transmit Line Fault condition if no bipolar pulses are detected via the TTIP/
TRING output pins for 128 bit periods.
Connect this input pin to the TTIP output pin via a 270 ohm resistor.
NOTE: Tie this input pin to GND if you do not intend to use the Transmit Drive
Monitor.
10
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
POWER SUPPLY
-0.5 TO +3.465V
STORAGE TEMPERATURE
-65°C TO 150°C
INPUT VOLTAGE AT ANY PIN
-0.5V TO 5.0V
POWER DISSIPATION TQFP PACKAGE
1.2W
INPUT CURRENT AT ANY PIN
+100MA
ESD RATING (MIL-STD-883, M-3015)
1500V
DC ELECTRICAL CHARACTERISTICS
(TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
VDDD
DC Supply Voltage
3.135
3.3
3.465
V
VDDA
DC Supply Voltage
3.135
3.3
3.465
V
ICC
Supply Current (Measured while Transmitting and Receiving all “1’s”)
180
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
5.0
V
VOL
Output Low Voltage, IOUT = -4.0mA
0.4
V
VOH
Output High Voltage, IOUT = 4.0mA
IL
2.0
2.8
Input Leakage Current*
V
±10
* Not applicable to pins with pull-up/pull-down resistors.
11
µA
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
TCLK Clock Duty Cycle (DS3/STS-1)
30
50
70
%
TCLK Clock Duty Cycle (E3)
30
50
70
%
Terminal Side Timing Parameters (See Figure 3 & Figure 4)
TCLK Frequency (SONET STS-1)
51.84
MHz
TCLK Frequency (DS3)
44.736
MHz
TCLK Frequency (E3)
34.368
MHz
tRTX
TCLK Clock Rise Time (10% to 90%)
4
ns
tFTX
TCLK Clock Fall Time (90% to 10%)
4
ns
tTSU
TPDATA/TNDATA to TCLK Falling Set up time
3
ns
tTHO
TPDATA/TNDATA to TCLK Falling Hold time
3
ns
tLCVO
RCLK to rising edge of LCV output delay
tTDY
2.5
TTIP/TRING to TCLK Rising Propagation Delay time
0.6
RCLK Clock Duty Cycle
45
50
ns
14
ns
55
%
RCLK Frequency (SONET STS-1)
51.84
MHz
RCLK Frequency (DS3)
44.736
MHz
RCLK Frequency (E3)
34.368
MHz
tCO
RCLK to RPOS/RNEG Delay Time
tRRX
RCLK Clock Rise Time (10% to 90%)
tFRX
RCLK Clock Fall Time (10% to 90%)
4
ns
2
4
ns
1.5
3
ns
Ci
Input Capacitance
10
pF
CL
Load Capacitance
10
pF
12
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 3. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
t RTX
t FTX
TClk
t TSU
tT H O
TPDATA or
TNDATA
TTIP or
TRING
t TDY
FIGURE 4. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
t RRX
t FRX
RClk
t LCVO
LCV
tC O
RPOS or
RNEG
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR DS3, E3 AND STS-1 RATES
TTIP
R1
31.6Ω
T1
R3
75Ω
1:1
R2
31.6Ω
TRING
13
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
AC ELECTRICAL CHARACTERISTICS (CONT’D) Line Side Parameters
(TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
0.9
1.0
1.1
Vpk
Transmit Output Pulse Amplitude Ratio
0.95
1.00
1.05
Transmit Output Pulse Width
12.5
14.55
16.5
Transmit Output Pulse Width Ratio
0.95
1.00
1.05
0.02
0.05
E3 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Pulse Amplitude (Measured at Secondary Output of Transformer)
Transmit Output Jitter with jitter-free input clock at TCLK
ns
UIpp
Receive Line Characteristics
Receive Sensitivity (Length of cable)
Interference Margin
1200
1400
feet
-20
-17
dB
Signal Level to Declare Loss of Signal
-35
dB
Signal Level to Clear Loss of Signal
-15
Occurrence of LOS to LOS Declaration Time
10
100
255
UI
Termination of LOS to LOS Clearance Time
10
100
255
UI
Intrinsic Jitter (all "1’s" Pattern)
dB
0.01
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1KHz
30
UI
Jitter Tolerance @ Jitter Frequency = 10KHz
4
UI
Jitter Tolerance @ Jitter Frequency = 800KHz
0.15
14
0.20
UI
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
AC ELECTRICAL CHARACTERISTICS (CONT’D) Line Side Parameters
(TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Transmit Output Pulse Amplitude (Measured with TXLEV = 0)
0.65
0.75
0.90
Vpk
Transmit Output Pulse Amplitude (Measured with TXLEV = 1)
0.93
0.98
1.08
Vpk
Transmit Output Pulse Width
8.6
9.65
10.6
ns
Transmit Output Pulse Amplitude Ratio
0.9
1.0
1.1
0.02
0.05
SONET STS-1 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Jitter with jitter-free clock input at TCLK
UIpp
Receive Line Characteristics
Receive Sensitivity (Length of cable)
900
1100
Signal Level to Declare or Clear Loss of Signal (see Table 4)
feet
mV
Intrinsic Jitter (all "1’s" Pattern)
0.03
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1KHz
64
UI
Jitter Tolerance @ Jitter Frequency = 10KHz
5
UI
Jitter Tolerance @ Jitter Frequency = 400KHz
0.15
15
0.35
UI
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
AC ELECTRICAL CHARACTERISTICS (CONT’D) LINE SIDE PARAMETERS
(TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Transmit Output Pulse Amplitude (Measured at 0 feet, TXLEV = 0)
0.65
0.75
0.85
Vpk
Transmit Output Pulse Amplitude (Measured at 0 feet, TXLEV = 1)
0.9
1.0
1.1
Vpk
10.10
11.18
12.28
ns
0.9
1.0
1.1
0.02
0.05
DS3 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Pulse Width
Transmit Output Pulse Amplitude Ratio
Transmit Output Jitter with jitter-free input clock at TCLK
UIpp
Receive Line Characteristics
Receive Sensitivity (Length of Cable)
900
1100
Signal Level to Declare or Clear Loss of Signal (see Table 4)
feet
mV
Intrinsic Jitter (All One’s Pattern)
0.01
UI
Jitter Tolerance @ Jitter Frequency = 100Hz
64
UI
Jitter Tolerance @ Jitter Frequency = 1KHz
64
UI
Jitter Tolerance @ Jitter Frequency = 10KHz
5
UI
Jitter Tolerance @ Jitter Frequency = 300KHz -- (Cat II)
16
0.35
0.45
UI
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
Figure 6, Figure 7 and Figure 8 present the Pulse
Template requirements for the E3, DS3 and STS-1
Rates.
FIGURE 6. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS
17 ns
(14.55 + 2.45)
8.65 ns
V = 100%
Nominal Pulse
50%
14.55ns
12.1ns
(14.55 - 2.45)
10%
0%
10%
20%
FIGURE 7. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
DS3 Pulse Template
1.2
1
0.6
Lower Curve
Upper Curve
0.4
0.2
0
17
4
3
1.
2
1.
1.
1
1
1.
9
8
0.
7
0.
6
0.
5
0.
4
Time, in UI
0.
3
0.
2
0.
0.
0
1
0.
.1
.2
-0
.3
-0
.4
-0
.5
-0
.6
-0
.7
-0
.8
-0
-0
-0
.9
-0.2
-1
Normalized Amplitude
0.8
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 8. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
STS-1 Pulse Template
1.2
1
Normalized Amplitude
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
3
4
1.
2
1.
1
9
1.
8
0.
1.
7
0.
1
6
5
0.
4
0.
0.
3
0.
2
1
0.
0.
0
0.
.1
.2
-0
.3
-0
.4
-0
.5
-0
.6
-0
.7
-0
.8
-0
.9
-0
-0
-1
-0.2
Time, in UI
FIGURE 9. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
0
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
0
0
0
High Z
High Z
SDO
3. R/W = "0" for "Write" Operations
NOTES:
1. A4 and A5 are always "0".
A shaded pulse, denotes a “don’t care” value.
2. R/W = "1" for "Read" Operations
18
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
AC ELECTRICAL CHARACTERISTICS (CONT.)
(TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNITS
Microprocessor Serial Interface Timing (see Figure 10)
t21
CS Low to Rising Edge of SCLK Setup Time
5
ns
t22
CS High to Rising Edge of SCLK Hold Time
20
ns
t23
SDI to Rising Edge of SCLK Setup Time
50
ns
t24
SDI to Rising Edge of SCLK Hold Time
50
ns
t25
SCLK “Low” Time
240
ns
t26
SCLK “High” Time
240
ns
t27
SCLK Period
500
ns
t28
CS Low to Rising Edge of SCLK Hold Time
5
ns
t29
CS Inactive Time
250
ns
t30
Falling Edge of SCLK to SDO Valid Time
200
ns
t31
Falling Edge of SCLK to SDO Invalid Time
100
ns
t32
Falling Edge of SCLK or Rising Edge of CS to High Z
t33
Rise/Fall time of SDO Output
100
ns
40
FIGURE 10. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SCLK
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SCLK
t31
t30
SDO
SDI
Hi-Z
D0
t33
t32
D2
D1
Hi-Z
19
D7
ns
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
SYSTEM DESCRIPTION
• Adjusts the signal level through an AGC circuit.
A functional block diagram of the XRT73L00A E3/
DS3/STS-1 Transceiver IC (see Figure 1) shows that
the device contains three distinct sections:
• Optionally equalizes this signal for cable loss.
• Attempts to quantify a bit-interval within the line signal as either a “1”, “-1” or a “0” by slicing this data.
This sliced data is used by the Clock Recovery PLL
to recover the timing element within the line signal.
• The Transmit Section
• The Receive Section
• The sliced data is routed to the HDB3/B3ZS
Decoder, during which the original data content as
transmitted by the Remote Terminal Equipment is
restored to its original content.
• The Microprocessor Serial Interface
THE TRANSMIT SECTION
The Transmit Section accepts TTL/CMOS level signals from the Terminal Equipment in either a SingleRail or Dual-Rail format. The Transmit Section then
takes this data and does the following:
• Outputs the recovered clock and data to the Local
Terminal Equipment in the form of CMOS level signals via the RPOS, RNEG, RCLK1 and RCLK2 output pins.
• Encodes the data into the B3ZS format if the DS3
or SONET STS-1 Modes have been selected or
into the HDB3 format if the E3 Mode has been
selected.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT73L00A can be configured to operate in either the Hardware Mode or the HOST Mode.
• Converts the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
The Hardware Mode
Connect the HOST/HW input pin (pin 18) to GND to
configure the XRT73L00A to operate in the Hardware
Mode.
• Drives these pulses onto the line via the TTIP and
TRING output pins across a 1:1 Transformer.
When the XRT73L00A is operating in the Hardware
Mode, the following is true:
NOTE: The Transmit Section drives a "1" (or a Mark) on the
line by driving either a positive or negative polarity pulse
across the 1:1 Transformer within a given bit period. The
Transmit Section drives a "0" (or a Space) onto the line by
driving no pulse onto the line.
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT73L00A is configured via input pin settings.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as defined in Table 1.
THE RECEIVE SECTION
The Receive Section receives a bipolar signal from
the line either via a 1:1 Transformer or a 0.01mF Capacitor. As the Receive Section receives this line signal it does the following:
3. All of the remaining input pins become active.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L00A IS OPERATING IN THE
HARDWARE MODE
PIN #
PIN NAME
FUNCTION WHILE IN THE HARDWARE MODE
11
REGRESET/(RCLK2INV)
RCLK2INV
19
SDI/(LOSMUTEN)
LOSMUTEN
20
SDO/(LCV)
LCV
21
SCLK/(ENDECDIS)
ENDECDIS
22
CS/(DR/SR)
DR/SR
30
LCV/(RCLK2)
RCLK2
20
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
The HOST Mode
• Pin 15 - RLB
To configure the XRT73L00A to operate in the HOST
Mode, connect the HOST/HW input pin (pin 18) to
VDD.
• Pin 16 - STS-1/DS3
• Pin 17 - E3
• Pin 35 - TXOFF
When the XRT73L00A is operating in the HOST
Mode, the following is true:
Tie each of these pins to GND if the XRT73L00A IC is
to be operated in the HOST Mode.
1. The Microprocessor Serial Interface block is
enabled. Many configuration selections are
made by writing the appropriate data into the onchip Command Registers via the Microprocessor
Serial Interface.
2. All of the following input pins are disabled:
• Pin 1 - TXLEV
Please see Section 5.0 for a detailed description on
operating the Microprocessor Serial Interface or the
on-chip Command Registers.
1.0 SELECTING THE DATA RATE
The XRT73L00A can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates. Selection of the data rate
is dependent on whether the XRT73L00A is operating
in the Hardware or HOST Mode.
• Pin 2 - TAOS
• Pin 12 - REQDIS
• Pin 14 - LLB
TABLE 2: SELECTING THE DATA RATE FOR THE XRT73L00A VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE
MODE)
DATA RATE
STATE OF E3 PIN
(PIN 17)
STATE OF STS-1/DS3 PIN
(PIN 16)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps)
VDD
X (Don’t Care)
HDB3
DS3 (44.736 Mbps)
0
0
B3ZS
STS-1 (51.84 Mbps)
0
VDD
B3ZS
A. When operating in the Hardware Mode.
TABLE 3: SELECTING THE DATA RATE FOR THE
XRT73L00A VIA THE STS-1/DS3 AND THE E3 BITFIELDS WITHIN COMMAND REGISTER CR4 (HOST
MODE)
To configure the XRT73L00A for the desired data
rate, the E3 and the STS-1/DS3 pins must be set to
the appropriate logic states shown in Table 2.
B. When operating in the HOST Mode.
To configure the XRT73L00A for the desired data
rate, appropriate values need to be written into the
STS-1/DS3 and E3 bit-fields in Command Register
CR4.
SELECTED DATA RATE
STS-1/DS3
E3
E3
Don't Care
1
DS3
0
0
COMMAND REGISTER CR4 (ADDRESS = 0X04)
STS-1
1
0
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
X
X
The results of making these selections are:
1. The VCO Center Frequency of the Clock Recovery Phase-Locked-Loop is configured to match
the selected data rate.
2. The B3ZS/HDB3 Encoder and Decoder blocks
are configured to support B3ZS Encoding/Decoding if the DS3 or STS-1 data rates were selected
or,
3. The B3ZS/HDB3 Encoder and Decoder blocks
are configured to support HDB3 Encoding/
Decoding if the E3 data rate was selected.
Table 3 relates the values of these two bit-fields with
respect to the selected data rates.
21
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
2. be reliably received by the Remote Terminal at
the other end of the E3, DS3 or STS-1 data link.
3. comply with the applicable pulse template
requirements.
4. The on-chip Pulse-Shaping circuitry is configured
to generate Transmit Output pulses of the correct
shape and width to meet the applicable pulse
template requirement.
5. The LOS Declaration/Clearance Criteria is established.
2.1 THE TRANSMIT LOGIC BLOCK
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single-Rail (a binary data stream)
TTL/CMOS level data and timing information from the
Terminal Equipment.
2.0 THE TRANSMIT SECTION
Figure 1 indicates that the Transmit Section of the
XRT73L00A consists of the following blocks:
Accepting Dual-Rail Data from the Terminal
Equipment
• Transmit Logic Block
• Duty Cycle Adjust Block
The XRT73L00A accepts Dual-Rail data from the Terminal Equipment via the following input signals:
• HDB3/B3ZS Encoder
• Pulse Shaping Block
• TPDATA
The purpose of the Transmit Section in the
XRT73L00A is to take TTL/CMOS level data from the
terminal equipment and encode it into a format that
can:
• TNDATA
• TCLK
Figure 11 illustrates the typical interface for the transmission of data in a Dual-Rail Format between the
Terminal Equipment and the Transmit Section of the
XRT73L00A.
1. be efficiently transmitted over coaxial cable at E3,
DS3 or STS-1 data rates.
FIGURE 11. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF THE XRT73L00A
Terminal
Terminal
Equipment
Equipment
(E3/DS3
or STS-1
(E3/DS3
or STS-1
Framer)
Framer)
TxPOS
TPDATA
TxNEG
TNDATA
TxLineClk
TCLK
Transmit
Transmit
Logic
Logic
Block
Block
Exar E3/DS3/STS-1 LIU
FIGURE 12. HOW THE XRT73L00A SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
Data
1
1
TPDATA
TNDATA
TCLK
22
0
0
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
B. access the Microprocessor Serial Interface and
write a “1” into the TXBIN (TRANSMIT BINary)
bit-field in Command Register 1.
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 12. The
XRT73L00A typically samples the data on the TPDATA and TNDATA input pins on the falling edge of
TCLK.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
TCLK is typically a clock signal that is of the selected
data rate frequency. For the E3 data rate, TCLK is
34.368 MHz. For the DS3 data rate, TCLK is 44.736
MHz and for the SONET STS-1 rate, TCLK is 51.84
MHz. In general, if the XRT73L00A samples a “1” on
the TPDATA input pin, the Transmit Section of the device ultimately generates a positive polarity pulse via
the TTIP and TRING output pins across a 1:1 transformer. If the XRT73L00A samples a “1” on the
TNDATA input pin, the Transmit Section of the device
ultimately generates a negative polarity pulse via the
TTIP and TRING output pins across a 1:1 transformer.
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
X
X
X
X
1
After taking these steps, the Transmit Logic Block accepts Single-Rail data via the TPDATA input pin. The
XRT73L00A samples this input pin on the falling edge
of the TCLK clock signal and encodes it into the appropriate bipolar line signal across the TTIP and
TRING output pins.
NOTES:
1. In this mode the Transmit Logic Block ignores the
TNDATA input pin.
2. If the Transmit Section of the XRT73L00A is configured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
2.1.1 Accepting Single-Rail Data from the Terminal Equipment
Do the following if data is to be transmited from the
Terminal Equipment to the XRT73L00A in Single-Rail
format (a binary data stream) without having to convert it into a Dual-Rail format.
Figure 13 illustrates the behavior of the TPDATA and
TCLK signals when the Transmit Logic Block has
been configured to accept Single-Rail data from the
Terminal Equipment.
A. Configure the XRT73L00A to operate in the
HOST Mode or,
FIGURE 13. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
1
1
0
0
TPDATA
TCLK
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
Template Requirement Specification. The chips ability to generate compliant pulses could depend upon
the duty cycle of the clock signal applied to the TCLK
input pin.
CUITRY
The on-chip Pulse-Shaping circuitry in the Transmit
Section of the XRT73L00A has the responsibility for
generating pulses of the shape and width to comply
with the applicable pulse template requirement. The
widths of these output pulses are defined by the width
of the half-period pulses in the TCLK signal.
In order to combat this phenomenon, the Transmit
Clock Duty Cycle Adjust circuit was designed into the
XRT73L00A. The Transmit Clock Duty Cycle Adjust
Circuitry is a PLL that was designed to accept clock
pulses via the TCLK input pin at duty cycles ranging
from 30% to 70% and to regenerate these signals
with a 50% duty cycle.
Allowing the widths of the pulses in the TCLK clock
signal to vary significantly could jeopardize the chip’s
ability to generate Transmit Output pulses of the appropriate width, thereby failing the applicable Pulse
23
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
The XRT73L00A Transmit Clock Duty Cycle Adjust
circuit alleviates the need to supply a signal with a
50% duty cycle to the TCLK input pin.
finds an occurrence of three consecutive zeros, it
substitutes these three “0’s” with either a "00V" or a
"B0V" pattern.
2.3 THE HDB3/B3ZS ENCODER BLOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remote Terminal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist in the line
signal.
“B” represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Alternate Mark Inversion) line code and “V” represents
a bipolar Violation (e.g., a bipolar pulse that violates
the Alternating Polarity requirements of the AMI line
code).
2.3.1 B3ZS Encoding
If the XRT73L00A is configured to operate in the DS3
or SONET STS-1 Modes, then the HDB3/B3ZS Encoder block operates in the B3ZS Mode. When the
Encoder is operating in this mode, it parses through
and searches the Transmit Binary Data Stream from
the Transmit Logic Block for the occurrence of three
(3) consecutive zeros (“000”). If the B3ZS Encoder
The B3ZS Encoder decides whether to substitute
with either a "00V" or a "B0V" pattern to insure that
an odd number of bipolar pulses exist between any
two consecutive violation pulses.
Figure 14 illustrates the B3ZS Encoder at work with
two separate strings of three (or more) consecutive
zeros.
FIGURE 14. AN EXAMPLE OF B3ZS ENCODING
TClk
TPOS
SR data
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
Encoded
PDATA
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Encoded
NDATA
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
V
Line signal
0
B
2.3.2 HDB3 Encoding
If the XRT73L00A is configured to operate in the E3
Mode, then the HDB3/B3ZS Encoder block operates
in the HDB3 Mode. When the Encoder is operating in
this mode, it parses through and searches the Transmit Data Stream from the Transmit Logic Block for the
occurrence of four (4) consecutive zeros (“0000”). If
the HDB3 Encoder finds an occurrence of four con-
V
secutive zeros, then it substitutes these four “0’s” with
either a “000V” or a “B00V” pattern to insure that an
odd number of bipolar pulses exist between any two
consecutive violation pulses.
Figure 15 illustrates the HDB3 Encoder at work with
two separate strings of four (or more) consecutive zeros.
FIGURE 15. AN EXAMPLE OF HDB3 ENCODING
TClk
TPOS
SR data
1
0
1
1
0
0
0
0
0
1
1
1
1
0
Encoded
PDATA
1
0
0
1
0
0
0
1
0
0
1
0
1
0
Encoded
NDATA
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
0
V
Line signal
B
24
0
0
V
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
2.3.3 Enabling/Disabling the HDB3/B3ZS
Encoder
The XRT73L00A allows two methods to enable or
disable the HDB3/B3ZS Encoder.
to “High” or “Low”. The purpose of the Transmit Line
Build-Out circuit is to permit configuring of the
XRT73L00A to transmit an output pulse which is compliant to either of the following Bellcore pulse template requirements when measured at the Digital
Cross Connect System. Each of these Bellcore specifications further state that the cable length between
the Transmit Output and the Digital Cross Connect
system can range anywhere from 0 to 450 feet.
If the XRT73L00A is operating in the Hardware
Mode.
To enable the HDB3/B3ZS Encoder, set the ENDECDIS input pin (pin 21) to “0”. To disable the HDB3/
B3ZS Encoder, set the ENDECDIS input pin (pin 21)
to “1”.
The Isolated DSX-3 Pulse Template Requirement per
Bellcore GR-499-CORE is illustrated in Figure 7.
If the XRT73L00A is operating in the HOST Mode.
The Isolated STSX-1 Pulse Template Requirement
per Bellcore GR-253-CORE is illustrated in Figure 8.
To enable the HDB3/B3ZS Encoder, set the ENDECDIS bit-field in Command Register (CR2) to “0”.
2.4.1 Enabling the Transmit Line Build-Out Circuit
If the Transmit Line Build-Out Circuit is enabled, the
XRT73L00A outputs shaped pulses onto the line via
the TTIP and TRING output pins.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
0
X
X
Do the following to enable the Transmit Line Build-Out
circuit in the XRT73L00A:
X
• If the XRT73L00A is operating in the Hardware
Mode, set theTXLEV input pin (pin 1) to “Low”
To disable the HDB3/B3ZS Encoder, set the ENDECDIS bit-field in Command Register (CR2) to “1”.
• If the XRT73L00A is operating in the HOST Mode,
set the TXLEV bit-field to “0” as illustrated below.
If either of these two methods is employed to disable
the HDB3/B3ZS Encoder, the LIU transmits the data
onto the line as it is received via the TPDATA and
TNDATA input pins.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY
The Transmit Pulse Shaper Circuitry consists of a
Transmit Line Build-Out circuit which can be enabled
or disabled by setting the TXLEV input pin or bit-field
25
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0
X
X
0
X
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
that it complies with the pulse template requirements even
when subjected to cable loss ranging from 0 to 225 feet.
2.4.2 Disabling the Transmit Line Build-Out Circuit
If the Transmit Line Build-Out circuit is disabled, then
the XRT73L00A outputs partially-shaped pulses onto
the line via the TTIP and TRING output pins.
If the cable length between the Transmitting
Terminal and the DSX-3 or STSX-1 is greater than
225 feet, it is advisable to disable the Transmit Line
Build-Out circuit by setting the TXLEV input pin or bitfield to "1".
Disable the Transmit Line Build-Out circuit in the
XRT73L00A by doing the following:
NOTE: In this case the XRT73L00A outputs partiallyshaped pulses onto the line via the TTIP and TRING output
pins. The cable loss that these pulses experience over long
cable lengths (e.g., greater than 225 feet) causes these
pulses to be properly shaped and comply with the appropriate pulse template requirement.
• If the XRT73L00A is operating in the Hardware
Mode, set the TXLEV input pin (pin 1) to “High”
• If the XRT73L00A is operating in the HOST Mode,
set the TXLEV bit-field to “1” as illustrated below.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0
X
X
1
X
2.4.4 The Transmit Line Build-Out Circuit and
E3 Applications
The ITU-T G.703 Pulse Template Requirements for
E3 states that the E3 transmit output pulse should be
measured at the Secondary Side of the Transmit Output Transformer for Pulse Template compliance.
There is no Digital Cross Connect System pulse template requirement for E3 and the Transmit Line BuildOut circuit in the XRT73L00A is disabled whenever it
is operating in the E3 Mode.
2.4.3 Design Guideline for Setting the Transmit
Line Build-Out Circuit
The setting ofTXLEV input pin or bit-field should be
based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect
system where the pulse template measurements are
made.
2.5 INTERFACING THE TRANSMIT SECTION OF THE
XRT73L00A TO THE LINE
The E3, DS3 and SONET STS-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 Ohms. Therefore, interface the Transmit Section of the
XRT73L00A, as illustrated in Figure 16 which shows
two 31.6 Ohm resistors in series with the primary side
of the transformer. These two 31.6Ohm resistors
closely match the 75Ohm load termination resistor
thereby minimizing Transmit Return Loss.
If the cable length between the Transmitting Terminal
and the DSX-3 or STSX-1 is less than 225 feet, it is
advisable to enable the Transmit Line Build-Out circuit
by setting the TXLEV input pin or bit-field to "0".
NOTE: In this case the XRT73L00A outputs shaped (e.g.,
not square-wave) pulses onto the line via the TTIP and
TRING output pins. The shape of this output pulse is such
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73L00A TO THE
LINE
TTIP
R1
31.6Ω
T1
1:1
R2
31.6Ω
TRING
26
BNC
áç
XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
TRANSFORMER RECOMMENDATIONS
PARAMETER
VALUE
Turns Ratio
1:1
Primary Inductance
40µH
Isolation Voltage
1500Vrms
Leakage Inductance
0.6µH
PART NUMBER
VENDOR
INSULATION
PACKAGE TYPE
PE-68629
Pulse
3000V
Large Thru-Hole
PE-65966
Pulse
1500V
Small Thru-Hole
PE-65967
Pulse
1500V
Small SMT
T3001
Pulse
1500V
Small SMT
TG01-0406NS
Halo
1500V
Small SMT
TTI 7601-SM
Trans-Power
1500V
Small SMT
TRANSFORMER VENDOR INFORMATION
Pulse
Halo Electronics
Corporate Office
Corporate Office
12220 World Trade Drive
P.O. Box 5826
San Diego, CA 92128
Redwood City, CA 94063
Tel: (858)-674-8100
Tel: (650)568-5800
FAX: (858)-674-8262
FAX: (650)568-6165
Europe
Email: [email protected]
1 & 2 Huxley Road
Website: http://www.haloelectronics.com
The Surrey Research Park
Guildford, Surrey GU2 5RE
Transpower Technologies, Inc.
United Kingdom
Corporate Office
Tel: 44-1483-401700
Park Center West Building
FAX: 44-1483-401701
9805 Double R Blvd, Suite # 100
Asia
Reno, NV 89511
150 Kampong Ampat
(800)500-5930 or (775)852-0140
#07-01/02
Email: [email protected]
KA Centre
Website: http://www.trans-power.com
Singapore 368324
Tel: 65-287-8998
FAX: 65-280-0080
Website: http://www.pulseeng.com
27
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
3.0 THE RECEIVE SECTION
Figure 1 indicates that the XRT73L00A Receive Section consists of the following blocks:
from the line and encode it back into the TTL/CMOS
format where it can be received and processed by
digital circuitry in the Terminal Equipment.
• AGC/Equalizer
3.1 INTERFACING THE RECEIVE SECTION OF THE
XRT73L00A TO THE LINE
By design, the Receive Section of the XRT73L00A
can be transformer-coupled or capacitive-coupled to
the line. The specification documents for E3, DS3
and STS-1 all specify 75Ohm termination loads when
transmitting over coaxial cable. It is recommended to
interface the Receive Section of the XRT73L00A to
the line as shown in Figure 17 or Figure 18.
• Peak Detector
• Slicer
• Clock Recovery PLL
• Data Recovery
• HDB3/B3ZS Decoder
The purpose of the XRT73L00A Receive Section is to
take an incoming attenuated/distorted bipolar signal
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L00A TO THE
LINE (TRANSFORMER-COUPLING)
RTIP
RxPOS
RxNEG
RxLineClk
RxLOS
RxLOL
RPOS
RNEG
RCLK1
R1
37.4Ω
RLOS
RLOL
R2
37.4Ω
T2
BNC
C1
0.01uf
1:1
RRING
FIGURE 18. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT73L00A TO THE
LINE (CAPACITIVE-COUPLING)
C1
0.01uF
Receive Line Signal
RTIP
R1
75Ω
C2
0.01uF
RRING
3.2 THE RECEIVE EQUALIZER BLOCK
After the XRT73L00A has received the incoming line
signal via the RTIP and RRING input pins, the first
block that this signal passes through is the AGC (Automatic Gain Control) circuit followed by the Receive
Equalizer.
28
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
cable-length from the local Receiving Terminal to the
remote Transmitting Terminal is NOT known. For
DS3, STS-1 and E3 applications, enable the Receive
Equalizer by setting either the REQDIS input pin “low”
or the REQDIS bit-field to “0”. The remainder of this
section provides an explanation why we recommend
enabling the Receive Equalizer for these applications.
As the line signal is transmitted from a given transmitting terminal, the pulse shapes at that location are basically square. These pulses consist of a combination of “Low” and “High” frequency Fourier components. As this line signal travels from the transmitting
terminal via the coaxial cable to the receiving terminal, it is subjected to frequency-dependent loss. The
higher-frequency components of the signal is subjected to a greater amount of attenuation than the lowerfrequency components. If this line signal travels over
reasonably long cable lengths (e.g., greater than 450
feet), then the shape of the pulses which were originally square is distorted and inter-symbol interference
increases.
3.2.1.1.1 The Use of the Receive Equalizer in a
Typical DS3 or STS-1 Application
Most System Manufacturers of equipment supporting
DS3 and STS-1 lines interface their equipment to either a DSX-3 or STSX-1 Cross-Connect. While installing their equipment the Transmit Line Build-Out
circuit is set to the proper setting that makes the
transmit output pulse compliant with the Isolated
DSX-3 or STSX-1 Pulse Template requirements. For
the XRT73L00A this is achieved by setting the TXLEV input pin or bit-field to the appropriate level.
The purpose of the Receive Equalizer is to equalize
the distortion of the incoming signal due to cable loss.
The Receive Equalizer accomplishes this by subjecting the received line signal to frequency-dependent
amplification which attempts to counter the frequency
dependent loss that the line signal has experienced
and to restore the shape of the line signal so that the
transmitted data and clock can be recovered reliably.
When the System Manufacturer is interfacing the Receive Section of the XRT73L00A to the Cross-Connect, they should keep aware of the following facts:
1. All DS3 or STS-1 line signals that are present at
either the DSX-3 or the STSX-1 Cross-Connect
are required to meet the Isolated Pulse Template
Requirements per Bellcore GR-499-CORE for
DS3 applications or Bellcore GR-253-CORE for
STS-1 applications.
2. Bellcore documents state that the amplitude of
these pulses at the DSX-3 or STSX-1 can range
in amplitude from 360mVpk to 850mVpk.
3. Bellcore documents stipulate that the Receiving
Terminal must be able to receive this pulse-template compliant line signal over a cable length of
0 to 450 feet from the DSX-3 or the STSX-1
Cross Connect.
These facts are reflected in Figure 19.
3.2.1 Guidelines for Setting the Receive Equalizer
This data sheet presents guidelines for setting the
Receive Equalizer, for the following conditions.
1. If the overall cable length from the local Receiving
Terminal to the remote Transmitting Terminal is
NOT known.
2. If the overall cable length from the local Receiving
Terminal to the remote Transmitting Terminal is
known.
3.2.1.1
If the Overall Cable Length is NOT
Known
This section presents recommendations on what
state to set the Receive Equalizer when the overall
29
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 19. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
Transmitting
Terminal
Digital CrossConnect System
0 to 450 feet of
Cable
DSX-3
or
STSX-1
Pulses that are
compliant to the
Isolated DSX-3 or
STSX-1 Pulse
Template
Requirement
0 to 450 feet of
Cable
Receiving
Terminal
3.2.1.1.2 Design Considerations for E3 Applications
In E3 system installation, it is recommended that the
Receive Equalizer of the XRT73L00A be enabled by
pulling the REQDIS input pin to GND or by setting the
REQDIS bit-field to “0”.
Design Considerations for DS3 and STS-1 Applications
When installing equipment into environments as depicted in Figure 18, the system installation personnel
may be able to determine the cable length between
the local terminal equipment and the DSX-3/STSX-1
Cross-Connect Patch-Panel. The cable length between the local terminal equipment and the DSX-3/
STSX-1 Cross-Connect Patch Panel ranges between
0 and 450 feet.
NOTE: The results of extensive testing indicates that when
the Receive Equalizer is enabled, the XRT73L00A is capable of receiving an E3 line signal with anywhere from 0 to
12dB of cable loss over the Industrial Temperature range.
It is extremely unlikely that the system installation
personnel will know the cable length between the
DSX-3/STSX-1 Cross-Connect Patch-Panel and the
remote terminal equipment. We recommend that the
Receive Equalizer be enabled by setting the REQDIS
input pin or bit-field to "0".
Design Considerations if the Overall Cable
Length is known
The only time the Receive Equalizer should be disabled is when there is an off-chip equalizer in the Receive path between the DSX-3/STSX-1 Cross-Connect and the RTIP/RRING input pins or, in applications where the Receiver is monitoring the transmit
output signal directly.
The Receive Equalizer should be turned ON if the
Receive Section is going to receive a line signal with
an overall cable length of 300 feet or greater. The
Receive Equalizer should be turned OFF if the Receive Section is going to receive a line signal over a
cable length of less than 300 feet.
If during system installation the overall cable length is
known, then in order to optimize the performance of
the XRT73L00A in terms of receive intrinsic jitter, etc.,
the Receive Equalizer should be enabled or disabled
based upon the following recommendations:
30
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
NOTES:
1. If the Receive Equalizer block is turned ON in a
given Receive Section that is receiving a line signal
over short cable length, there is the risk of overequalizing the received line signal which could
degrade performance by increasing the amount of
jitter that exists in the recovered data and clock signals or by creating bit-errors.
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the Transmitting Terminal to the Receiving Terminal. However, Receive Equalizer was not designed to
counter flat loss where all of the Fourier frequency
components in the line signal are subject to the
same amount of attenuation. Flat loss is handled
by the AGC block.
ence between the line signal and that applied via the
EXCLK input pin exceeds 0.5%, then the XRT73L00A
LIU IC is operating in the Training Mode. When the
LIU is operating in the Training Mode it does the following:
A. declares a Loss of Lock indication by toggling the
RLOL output pin “High” and
B. outputs a clock signal via the RCLK1 and RCLK2
output pins which is derived from the signal applied to the EXCLK input pin.
2. The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXCLK input pin is less than
0.5%, the XRT73L00A LIU IC is operating in the Data/Clock Recovery Mode. In this mode, the Clock Recovery PLL is locked onto the line signal via the RTIP
and RRING input pins.
The Receive Equalizer block can be disabled setting
the REQDIS input pin “High” when operating in the
Hardware Mode or writing a "1" to the REQDIS bitfield in Command Register CR2 when operating the
XRT73L00A in the HOST Mode.
3.5 THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data in the
Near-End Receiving Terminal. Once the data has
made it across the E3, DS3 or STS-1 Transport Medium and has been recovered by the Clock Recovery
PLL, it is now necessary to restore the original content of the data. The purpose of the HDB3/B3ZS Decoding block is to restore the data transmitted over
the E3, DS3 or STS-1 line to its original content prior
to Zero Suppression encoding.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
X
X
X
1
3.3 PEAK DETECTOR AND SLICER
After the incoming line signal has passed through the
Receive Equalizer, it is routed to the Slicer block. The
purpose of the Slicer is to quantify a given bit-period
or symbol within the incoming line signal as either a
“1” or a “0”.
3.5.1 B3ZS Decoding DS3/STS-1 Applications
If the XRT73L00A is configured to operate in the DS3
or STS-1 Modes, then the HDB3/B3ZS Decoding
Block performs B3ZS Decoding. When the Decoder
is operating in this mode it parses through the incoming Dual-Rail data and checks for the occurrence of
either a “00V” or a “B0V” pattern. If the B3ZS Decoder detects this particular pattern it substitutes these
bits with a “000” pattern.
3.4 CLOCK RECOVERY PLL
The output of the Slicer, which is now Dual-Rail digital
pulses, is routed to the Clock Recovery PLL. The
purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate a recovered clock signal.
It is important to note that the Clock Recovery PLL requires a line rate clock signal at the EXCLK input pin.
NOTE: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the”B3ZS Line Code” format,
or if the B3ZS Decoder detects a string of 3 (or more) consecutive “0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by pulsing the LCV output pin “High”.
The Clock Recovery PLL operates in one of two
modes:
• The Training Mode.
• The Data/Clock Recovery Mode
Figure 20 illustrates the B3ZS Decoder at work with
two separate Zero Suppression patterns in the incoming Dual-Rail Data Stream.
1. The Training Mode
If the XRT73L00A is not receiving a line signal via the
RTIP and RRING input pins or if the frequency differ-
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 20. AN EXAMPLE OF B3ZS DECODING
0 0 V
Line Signal
B 0 V
RCLK
RPOS
RNEG
Data
0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
3.5.2 HDB3 Decoding E3 Applications
If the XRT73L00A is configured to operate in the E3
Mode, the HDB3/B3ZS Decoding Block performs
HDB3 Decoding. When the Decoder is operating in
this mode it parses through the incoming Dual-Rail
data and checks for the occurrence of either a “000V”
or a “B00V” pattern. If the HDB3 Decoder detects
this particular pattern, it substitutes these bits with a
“0000” pattern.
Figure 21 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns in the incoming Dual-Rail Data Stream.
FIGURE 21. AN EXAMPLE OF HDB3 DECODING
0 0 0 V
Line Signal
B 0 0 V
RCLK
RPOS
RNEG
Data
0
1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., “V”) pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) “0’s” in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High”.
If the XRT73L00A is operating in the Hardware
Mode:
Enable the HDB3/B3ZS Encoder/Decoder by pulling
the ENDECDIS input pin (pin 21) to GND. To disable
the HDB3/B3ZS Encoder/Decoder, pull the ENDECDIS input pin to VDD.
3.5.3 Enabling/Disabling the HDB3/B3ZS
Decoder
The HDB3/B3ZS Decoder of the XRT73L00A can be
enabled or disabled by either of the following means:
If the XRT73L00A is operating in the HOST Mode:
Enable the XRT73L00A HDB3/B3ZS Encoder/Decoder by writing a “0” into the ENDECDIS bit-field in
Command Register CR2. To disable the HDB3/B3ZS
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
Encoder/Decoder, write a “1” into the ENDECDIS bitfield.
the RLOS output pin “High” and by setting the RLOS
bit field in Command Register 0 to “1”.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
If the XRT73L00A determines that the incoming line
signal has been restored (e.g., there is sufficient amplitude and pulses in the incoming line signal) then it
clears the LOS condition by toggling the RLOS output
pin “Low” and setting the RLOS bit-field to “0”.
D4
D3
D2
D1
D0
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
0
X
X
X
The LOS Declaration/Clearance scheme that is employed in the XRT73L00A is based upon ITU-T Recommendation G.775 for both E3 and DS3 applications. The LOS Declaration and Clearance criteria
that the XRT73L00A uses for each of these modes
(e.g., E3 and DS3) are presented below.
3.6 LOS DECLARATION/CLEARANCE
The XRT73L00A contains circuitry that monitors the
following two parameters associated with the incoming line signals.
3.6.1 The LOS Declaration/Clearance Criteria
for E3 Applications
When the XRT73L00A is operating in the E3 Mode, it
declares an LOS Condition if the signal amplitude
drops to -35dB or below. The XRT73L00A clears the
LOS Condition if the signal amplitude rises back up to
-15dB or above. Figure 22 illustrates the signal levels
at which the XRT73L00A asserts and clears LOS.
1. The amplitude of the incoming line signal via the
RTIP and RRING inputs; and
2. The number of pulses detected in the incoming
line signal within a certain amount of time.
If the XRT73L00A determines that the incoming line
signal is missing due to insufficient amplitude or a
lack of pulses in the incoming line signal) then it declares a Loss of Signal (LOS) condition. The
XRT73L00A declares the LOS condition by toggling
FIGURE 22. THE SIGNAL LEVELS THAT THE XRT73L00A DECLARES AND CLEARS LOS (E3 MODE ONLY)
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
Timing Requirements associated with Declaring
and Clearing the LOS Indicator for E3 Applications
and clearing the LOS indicator. The XRT73L00A declares an LOS between 10 and 255 UI or E3 bit-periods after the actual time the LOS condition occurred. The XRT73L00A clears the LOS indicator
within 10 to 255 UI after restoration of the incoming
The XRT73L00A was designed to meet the ITU-T
G.775 specification timing requirements for declaring
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
line signal. Figure 23 illustrates the LOS Declaration
and Clearance behavior in response to the first loss
of signal event and then afterwards to the restoration
of the signal.
FIGURE 23. THE BEHAVIOR OF THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RESTORATION OF SIGNAL
Actual Occurrence
of LOS Condition
Line Signal
is Restored
RTIP/
RRing
10 UI
255 UI
Time Range for
LOS Declaration
10 UI
255 UI
RLOS Output Pin
0 UI
0 UI
Time Range for
LOS Clearance
G.775
Compliance
3.6.2 The LOS Declaration/Clearance Criteria
for DS3 and STS-1 Applications
When the XRT73L00A is operating in the DS3 or
STS-1 Modes it declares and clears LOS based on
either:
G.775
Compliance
In the DS3 or STS-1 Modes the LOS output (RLOS)
is simply the logical OR of the ALOS and DLOS
states.
1. The Analog LOS (ALOS) Declaration/Clearance Criteria
The XRT73L00A declares an Analog LOS (ALOS)
Condition if the amplitude of the incoming line signal
drops below a specific amplitude as defined by the
state of the LOSTHR input pin.
• Analog LOS (ALOS) Declaration/Clearance Criteria
or,
• Digital LOS (DLOS) Declaration/Clearance Criteria
TABLE 4: THE ALOS (ANALOG LOS) DECLARE AND CLEAR THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND
REQEN FOR DS3 AND STS-1 APPLICATIONS
APPLICATION
REQEN SETTING
LOSTHR SETTING
SIGNAL LEVEL TO
DECLARE ALOS
SIGNAL LEVEL TO CLEAR
ALOS
DS3
1
1
<22mV
>90mV
0
1
<17mV
<70mV
1
1
<25mV
>115mV
0
1
<20mV
<90mV
STS-1
Declaring ALOS
The XRT73L00A clears ALOS whenever the amplitude of the input signal rises above the Signal Level
to Clear ALOS levels specified in Table 4.
The XRT73L00A declares an ALOS (Analog LOS)
condition whenever the amplitude of the input signal
falls below the Signal Level to Declare ALOS levels
specified in Table 4.
NOTE: There is approximately a 2dB hysteresis in the
received signal level that exists between declaring and
clearing ALOS in order to prevent chattering in the RLOS
output signal.
Clearing ALOS
Monitoring the State of ALOS
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
reading in the contents of Command Register 0 as
shown.
If the XRT73L00A is operating in the HOST Mode,
the state of ALOS can be polled or monitored by
reading in the contents of Command Register 0. The
bit-format of Command Register 0 is presented below.
COMMAND REGISTER CR0 (ADDRESS = 0X00)
COMMAND REGISTER CR0 (ADDRESS = 0X00)
D4
D3
D2
D1
D0
RLOL
RLOS
ALOS
DLOS
DMO
Read
Only
Read
Only
Read
Only
Read
Only
Read
Only
D4
D3
D2
D1
D0
RLOL
RLOS
ALOS
DLOS
DMO
Read
Only
Read
Only
Read
Only
Read
Only
Read
Only
If the DLOS bit-field contains a “1”, the XRT73L00A is
currently declaring a DLOS condition. If the DLOS
bit-field contains a “0”, the device is NOT currently declaring the DLOS condition.
If the ALOS bit-field contains a “1”, the XRT73L00A is
currently declaring an ALOS condition. If the ALOS
bit-field contains a “0”, the device is NOT currently declaring an ALOS condition.
Disabling the DLOS Detector
It is useful to disable the DLOS Detector in the
XRT73L00A for debugging purposes. If the
XRT73L00A is operating in the HOST Mode, the
DLOS Detector can be disabled by writing a “1” into
the DLOSDIS bit-field in Command Register 2.
Disabling the ALOS Detector
It is useful to disable the ALOS Detector in the
XRT73L00A for debugging purposes. If the
XRT73L00A is operating in the HOST Mode, the
ALOS Detector can be disabled by writing a “1” into
the ALOSDIS bit-field in Command Register 2 as depicted below.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
X
D3
D2
D1
X
1
X
D1
D0
X
X
1
X
D0
NOTE: Setting both the ALOSDIS and DLOSDIS bit-fields
to a “1” disables LOS Declaration in the XRT73L00A.
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
X
D2
Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
X
3.6.3 Muting the Recovered Data while the LOS
is being Declared
In some applications it is not desirable for the
XRT73L00A E3/DS3/STS-1 LIU to recover data and
route it to the Receiving Terminal while the LIU is declaring a LOS condition. The LOS Muting feature, if
enabled, causes the XRT73L00A to halt transmission
of the recovered data to the Receiving Terminal while
the LOS condition is True. In this case, the RPOS
and RNEG output pins are forced to “0”. Once the
LOS condition has been cleared, the XRT73L00A resumes the transmission of the recovered data to the
Receiving Terminal. The XRT73L00A allows enabling of the Muting Upon LOS feature by either of
the following means.
NOTE: Setting both the ALOSDIS and DLOSDIS bit-fields
to “1” disables LOS Declaration in the XRT73L00A.
2. The Digital LOS (DLOS) Declaration/Clearance Criteria
The XRT73L00A declare a Digital LOS (DLOS) condition if the XRT73L00A detects 160±32 or more consecutive “0’s” in the incoming data.
The XRT73L00A clears DLOS if it detects four consecutive sets of 32 bit-periods each of which contains
at least 10 “1’s” (e.g., average pulse density of greater
than 33%).
Monitoring the State of DLOS
If the XRT73L00A is operating in the HOST Mode,
the state of DLOS can be polled or monitored by
If the XRT73L00A is Operating in the Hardware
Mode:
The Muting Upon LOS feature is enabled by pulling
the LOSMUTEN input pin (pin 19) to VDD.
If the XRT73L00A is Operating in the HOST Mode:
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
To enable this feature, access the Microprocessor Serial Interface and write a “1” into the LOSMUT bit-field
in Command Register 3.
els and routes it to the Receiving Terminal Equipment
via the RPOS, RNEG, RCLK1 and RCLK2 output
pins.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
The XRT73L00A can deliver the recovered data and
clock information to the Receiving Terminal in either a
Single-Rail or Dual-Rail format.
D4
D3
RNRZ
LOSMUT
X
1
D2
D1
D0
Routing Dual-Rail Format Data to the Receiving
Terminal Equipment
CLK2DIS RCLK2INV CLK1INV
X
X
X
Whenever the XRT73L00A delivers Dual-Rail format
to the Terminal Equipment it does so via the following
output signals.
NOTE: The XRT73L00A automatically declares an LOS
Condition any time it has been configured to operate in
either the Analog Local Loop-Back or Digital Local LoopBack Modes. Muting -upon -LOS must be disabled prior to
configuring the device to operate in either of these local
Loop-Back modes.
• RPOS
• RNEG
• RCLK1
• RCLK2
3.7 ROUTING THE RECOVERED TIMING AND DATA
INFORMATION TO THE RECEIVING TERMINAL
EQUIPMENT
The XRT73L00A ultimately takes the Recovered Timing and Data information, converts it into CMOS lev-
Figure 24 illustrates the typical interface for the transmission of data in a Dual-Rail Format from the Receive Section of the XRT73L00A to the Receiving
Terminal Equipment.
FIGURE 24. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT73L00A TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RxPOS
RPOS
RxNEG
RNEG
RCLK1, 2
RCLK1, 2
Receive
Logic
Block
Exar E3/DS3/STS-1 LIU
The manner that the LIU transmits Dual-Rail data to
the Receiving Terminal Equipment is described below
and illustrated in Figure 25. The XRT73L00A typical-
ly updates the data on the RPOS and RNEG output
pins on the rising edge RCLK1 (or RCLK2).
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 25. HOW THE XRT73L00A OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RPOS
RNEG
RCLK1
Inverting the RCLK1 or RCLK2 outputs
RCLK1 (or RCLK2) is the Recovered Clock signal
from the incoming Received line signal. These clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.84 MHz for
SONET STS-1 applications.
When using the XRT73L00A, either of the RCLK1 or
RCLK2 signals can be inverted with respect to the delivery of the RPOS and RNEG output signals to the
Receiving Terminal Equipment. This feature may be
useful for those customers whose Receiving Terminal
Equipment logic design is such that the RPOS and
RNEG data must be sampled on the rising edge of
RCLK1 or RCLK2. Figure 26 illustrates the behavior
of the RPOS, RNEG and RCLK signals when the
RCLK signal has been inverted.
If the XRT73L00A received a positive-polarity pulse in
the incoming line signal via the RTIP and RRING input pins, then the XRT73L00A pulses the RPOS output pin “High”. If the XRT73L00A received a negative-polarity pulse in the incoming line signal via the
RTIP and RRING input pins, then the XRT73L00A
pulses the RNEG output pin “High”.
FIGURE 26. THE BEHAVIOR OF THE RPOS, RNEG AND RCLK1 SIGNALS WHEN RCLK1 IS INVERTED
RPOS
RNEG
RCLK1
The RCLK2 output signal can also be inverted when
the XRT73L00A is operating in the Hardware Mode
by setting the RCLK2INV input pin “High”.
To configure the XRT73L00A to invert the RCLK1 output signal, the XRT73L00A must be operating in the
HOST Mode. This configuration can be implemented
by accessing the Microprocessor Serial Interface
block and writing a “1” into the RCLK1INV bit-field in
Command Register CR3 to invert RCLK1.
3.7.1 Routing Single-Rail Format data (Binary
Data Stream) to the Receive Terminal Equipment
To route Single-Rail format data (e.g., a binary data
stream) from the Receive Section of the XRT73L00A
to the Receiving Terminal Equipment, do the following:
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
RNRZ
LOSMUT
CLK2DIS
X
X
X
D1
D0
A. configure the XRT73L00A to operate in the
HOST Mode and
RCLK2INV RCLK1INV
1
1
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
B. access the Microprocessor Serial Interface and
write a “1” into the RNRZ bit-field in Command
Register CR3.
After these steps are taken, the XRT73L00A outputs
Single-Rail data to the Receiving Terminal Equipment
via the RPOS and RCLK1 (or RCLK2) output pins as
illustrated in Figure 27 and Figure 28.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
RNRZ
D3
D2
D1
LOSMUT CLK2DIS RCLK2INV
1
X
X
X
NOTE: The RNEG output pin is internally tied to GND
whenever this feature is enabled.
D0
RCLK1INV
X
FIGURE 27. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT73L00A TO THE RECEIVING TERMINAL EQUIPMENT
RxPOS
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RPOS
Receive
Logic
Block
RCLK1, 2
RCLK1, 2
Exar E3/DS3/STS-1 LIU
FIGURE 28. THE BEHAVIOR OF THE RPOS AND RCLK1 OUTPUT SIGNALS WHILE THE XRT73L00A IS TRANSMITTING SINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT
RPOS
RCLK1
4.0 DIAGNOSTIC FEATURES OF THE
XRT73L00A
The XRT73L00A supports equipment diagnostic activities by supporting the following Loop-Back modes
in the chip:
RRING input pins. The Transmitting Terminal Equipment transmits clock and data into the XRT73L00A
via the TPDATA, TNDATA and TCLK input pins. This
data is processed through the Transmit Clock Duty
Cycle Adjust PLL and the HDB3/B3ZS Encoder. Finally, this data outputs to the line via the TTIP and
TRING output pins and is looped back into the AGC/
Receive Equalizer Block. Consequently, this data is
also processed through the Receive Section of the
XRT73L00A. After this post-loop-back data has been
processed through the Receive Section it outputs to
the Near-End Receiving Terminal Equipment via the
RPOS, RNEG, RCLK1 and RCLK2 output pins.
• Analog Local Loop-Back
• Digital Local Loop-Back
• Remote Loop-Back.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When the XRT73L00A is configured to operate in the
Analog Local Loop-Back Mode, the XRT73L00A ignores any signals that are input to the RTIP and
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E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
Figure 29 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT73L00A can be configured to operate in the
Analog Local Loop-Back Mode by employing either
one of the following two steps:
FIGURE 29. THE ANALOG LOCAL LOOP-BACK IN THE XRT73L00A
RLOL EXCLK
RTIP
AGC/
Equalizer
RRING
REQDIS
Clock
Recovery
Slicer
Peak
Detector
Invert
Data
Recovery
LOS Detector
LOSTHR
HDB3/
B3ZS
Decoder
RCLK1
RCLK2
RPOS
RNEG
DR/SR
SDI
SDO/LCV
Serial
Processor
Interface
SCLK
CS
RLOS
Analog Local
Loop-Back Path
LLB
Loop MUX
RLB
ENDECDIS
REGRESET
TAOS
TTIP
HDB3/
B3ZS
Encoder
Pulse
Shaping
TRING
TXLEV
Device
Monitor
TXOFF
TPDATA
Transmit
Logic
TNDATA
Duty Cycle Adjust
TCLK
MTIP
MRING
DMO
2. The XRT73L00A automatically Declares an LOS
Condition anytime it has been configured to operate in either the Analog Local Loop-Back or Digital
Local Loop-Back Modes. Consequently, the Muting
-upon -LOS must be disabled prior to configuring
the device to operate in either of these local LoopBack modes.
If the XRT73L00A is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the LLB bit-field and a “0” into the RLB bitfield in Command Register 4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
1
0
4.2 THE DIGITAL LOCAL LOOP-BACK MODE
When the XRT73L00A is configured to operate in the
Digital Local Loop-Back Mode, it ignores any signals
that are input to the RTIP and RRING input pins. The
Transmitting Terminal Equipment transmits clock and
data into the XRT73L00A via the TPDATA, TNDATA
and TCLK input pins. This data is processed through
the Transmit Clock Duty Cycle Adjust PLL and the
HDB3/B3ZS Encoder block and then looped back to
the HDB3/B3ZS Decoder block.
If the XRT73L00A is operating in the Hardware
Mode:
The LLB input pin (pin 14) must be set to “High” and
the RLB input pin (pin 15) must be set to “Low”.
NOTES:
1. The Analog Local Loop-Back Mode does not work
if the transmitter is turned off via the TXOFF feature.
Figure 30 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 30. THE DIGITAL LOCAL LOOP-BACK PATH IN THE XRT73L00A
RLOL EXCLK
RTIP
RRING
AGC/
Equalizer
REQDIS
Peak
Detector
SDI
SCLK
CS
Invert
Serial
Processor
Interface
RCLK1
RCLK2
Data
Recovery
LOS Detector
LOSTHR
SDO/LCV
Clock
Recovery
Slicer
HDB3/
B3ZS
Decoder
RPOS
RNEG
DR/SR
Digital Local
Loop-Back Path
RLOS
LLB
Loop MUX
RLB
ENDECDIS
REGRESET
TAOS
TTIP
HDB3/
B3ZS
Encoder
Pulse
Shaping
TRING
TXLEV
TNDATA
Duty Cycle Adjust
Device
Monitor
TXOFF
TPDATA
Transmit
Logic
TCLK
MTIP
MRING
DMO
NOTES:
1. The Digital Local Loop-Back Mode feature works
even if the transmitter is turned off via the TXOFF
feature.
2. The XRT73L00A automatically declares an LOS
Condition any time it has been configured to operate in either the Analog Local Loop-Back or Digital
Local Loop-Back Modes. Consequently, the Muting
-upon -LOS must be disabled prior to configuring
the device to operate in either of these local LoopBack modes.
The Digital Local Loop-Back Mode, along with the TxOFF feature, is useful in Redundancy System Design. These two features permit the system to execute some diagnostic tests in the Back-up Line Card
without transmitting data onto the line and interfering
with the DS3/E3/STS-1 traffic from the Primary Line
Card.
The XRT73L00A can be configured to operate in the
Digital Local Loop-Back Mode by employing either
one of the following two-steps.
A. If the XRT73L00A is operating in the HOST
Mode
4.3 THE REMOTE LOOP-BACK MODE
When the XRT73L00A is configured to operate in the
Remote Loop-Back Mode, it ignores any signals that
are input to the TPDATA and TNDATA input pins. The
XRT73L00A receives the incoming line signal via the
RTIP and RRING input pins. This data is processed
through the Receive Section of the XRT73L00A and
outputs to the Receive Terminal Equipment via the
RPOS, RNEG, RCLK1 and RCLK2 output pins. Additionally, this data is internally looped back into the
Pulse-Shaping block in the Transmit Section. At this
point, this data is routed through the remainder of the
Transmit Section of the XRT73L00A and transmitted
out onto the line via the TTIP and TRING output pins.
Access the Microprocessor Serial Interface and write
a “1” into both the LLB and RLB bit-fields in Command Register 4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
1
1
B. If the XRT73L00A is operating in the Hardware
Mode
Figure 31 illustrates the path that the data takes in the
XRT73L00A when the chip is configured to operate in
the Remote Loop-Back Mode.
Set both the LLB input pin (pin 14) and the RLB input
pin (pin 15) to “High”.
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E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 31. THE REMOTE LOOP-BACK PATH IN THE XRT73L00A
RLOL EXCLK
RTIP
RRING
AGC/
Equalizer
Clock
Recovery
Slicer
REQDIS
RCLK2/LCV
Peak
Detector
Data
Recovery
RPOS
HDB3/
B3ZS
Decoder
LOS Detector
LOSTHR
RCLK1
Invert
RNEG
DR/SR
SDI
SDO/LCV
SCLK
CS
Serial
Processor
Interface
RLOS
Remote
Loop-Back Path
LLB
Loop MUX
RLB
ENDECDIS
REGRESET
TAOS
TTIP
Pulse
Shaping
HDB3/
B3ZS
Encoder
TNDATA
Duty Cycle Adjust
TRING
TXLEV
TPDATA
Transmit
Logic
TCLK
MTIP
Device
Monitor
TXOFF
MRING
DMO
During Remote Loop-Back operation, any data which
is inputted via the RTIP and RRING input pins is also
outputted to the Terminal Equipment via the RPOS,
RNEG and RCLK output pins.
conditions or during diagnostic testing. This feature
can be activated by either of the following ways.
The XRT73L00A can be configured to operate in the
Remote Loop-Back Mode by employing either one of
the following two steps
Shut off the Transmit Driver by toggling the TXOFF input pin (pin 35) “High”. Turn on the Transmit Driver by
toggling the TXOFF input pin “Low”.
If the XRT73L00A is operating in the HOST Mode:
When the XRT73L00A is operating in the HOST
Mode
When the XRT73L00A is operating in the Hardware Mode
Access the Microprocessor Serial Interface and write
a “1” into the RLB bit-field and a “0” in the LLB bit-field
in Command Register CR4.
If the XRT73L00A is operating in the HOST Mode,
the TXOFF input pin is disabled. Consequently, theTransmit Driver is turned off by writing to Command
Register CR1 and setting the TXOFF bit-field (bit D4)
to “1”.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
0
1
COMMAND REGISTER CR1 (ADDRESS = 0X01)
If the XRT73L00A is operating in the Hardware
Mode:
Set the RLB input pin (pin 15) to “High” and the LLB
input pin (pin 16) to “Low”.
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
1
X
X
X
X
NOTE: If the Transmitter is shut off via the TXOFF feature,
the XRT73L00A can NOT be configured to operate in the
Analog Local Loop-Back Mode. To perform diagnostics on
the chip and still invoke the TXOFF feature as in System
Redundancy Applications, use the Digital Local Loop-Back
feature instead.
4.4 TXOFF FEATURES
The XRT73L00A allows the Transmit Driver in the
Transmit Section of the chip to be shut off. This feature can be advantageous for system redundancy
4.5 THE TRANSMIT DRIVE MONITOR FEATURES
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E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
The Transmit Drive Monitor is activated by connecting
the MTIP pin (pin 44) to the TTIP line through a 270 Ω
resistor connected in series and by connecting the
MRING pin (pin 43) to the TRING line through a 270
Ω resistor connected in series, as illustrated in
Figure 32.
The Transmit Drive Monitor feature performs monitoring of the line in the Transmit Direction for the occurrence of fault conditions such as a short circuit on the
line or a defective Transmit Drive in the XRT73L00A.
FIGURE 32. THE XRT73L00A EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES
T1
TTIP
R1 = 31.6 Ω
TRING
R2 = 31.6 Ω
R5 = 75Ω
1:1
MTIP
R3 = 270 Ω
MRING
R4 = 270 Ω
When the Transmit Drive Monitor circuitry is connected to the line as illustrated in Figure 26, then it monitors the line for transitions. As long as the Transmit
Drive Monitor circuitry detects transitions on the line
via the MTIP and MRING pins, it keeps the DMO
(Drive Monitor Output) signal “Low”. However, if the
Transmit Drive Monitor circuit detects no transitions
on the line for 128±32 TCLK periods, then the DMO
signal toggles “High”.
NOTES:
1. The Transmit Drive Monitor circuit does not have to
be used to operate the Transmit Section of the
XRT73L00A. This is purely a diagnostic feature.
2. The Transmit Drive Monitor feature can also be
used to monitor the Transmit Output Line Signal of
another LIU IC as illustrated in Figure 33.
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E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 33. TWO LIU’S, EACH MONITORING THE TRANSMIT OUTPUT SIGNAL OF THE OTHER LIU IC
U1
TTIP
DMO_Channel_2
R1
31.6Ω
DMO
R2
31.6Ω
T1
BNC
PE-68629
TRING
TXOFF
MTIP
R3
270 Ω
R4
270 Ω
MRING
U2
MRING
R5
270 Ω
R6
270 Ω
TXOFF
MTIP
TRING
T2
R7
31.6Ω
DMO_Channel_1
DMO
R8
31.6Ω
TTIP
BNC
PE-68629
When the XRT73L00A is operating in the Hardware Mode:
Presented in Figure 33, if LIU # 1 (U1) fails, then LIU
# 2 (U2) drives its DMO output pin “High”. Likewise, if
LIU # 2 (U2) fails, then LIU # 1 (U1) drives its DMO
output pin “High”.
Configure the device to transmit an all “1’s” pattern by
toggling the TAOS input pin (pin 2) “High”. Terminate
the all “1’s” pattern by toggling the TAOS input pin
“Low”.
The scheme presented in Figure 33 is a better design
approach. It overcomes situations in which a LIU
monitoring its own signal (Figure 32) may experience
a failure mode such that it cannot drive a bipolar signal onto the line. That same failure mode may prevent the LIU from driving the DMO output pin “High”.
When the XRT73L00A is operating in the HOST
Mode:
If the XRT73L00A is operating in the HOST Mode,
the TAOS input pin is disabled. Consequently, the
XRT73L00A can be configured to transmit an all “1’s”
pattern by writing to Command Register CR1 and setting the TAOS bit-field (bit D3) to “1”.
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE
The XRT73L00A can transmit an all “1’s” pattern onto
the line by toggling a single input pin or by setting a
single bit-field in one of the Command Registers to
“1”.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
NOTE: When this feature is activated, the Transmit Section
of the XRT73L00A overwrites the Terminal Equipment data
with this all “1’s” pattern.
This feature can be activated by either of the following
methods.
D4
D3
D2
D1
D0
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0
1
X
X
X
The all “1’s” pattern can be terminated by writing to
Command Register CR1 and setting the TAOS bitfield (D3) to “0".
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REV. 2.0.1
5.0 THE MICROPROCESSOR SERIAL INTERFACE
The on-chip Command Registers of the XRT73L00A
DS3/E3/STS-1 Line Interface Unit IC are accessed to
configure the XRT73L00A into a variety of modes.
This section describes the Command Registers and
how to use the Microprocessor Serial Interface.
5.1 DESCRIPTION OF THE COMMAND REGISTERS
A listing of these Command Registers, their Addresses and their Bit-Formats are listed in Table 5.
TABLE 5: ADDRESSES AND BIT FORMATS OF XRT73L00A COMMAND REGISTERS
REGISTER BIT-FORMAT
ADDRESS
COMMAND REGISTER
TYPE
D4
D3
D2
D1
D0
0x00
CR0
RO
RLOL
RLOS
ALOS
DLOS
DMO
0x01
CR1
R/W
TXOFF
TAOS
TXCLKINV
TXLEV
TXBIN
0x02
CR2
R/W
Reserved
ENDECDIS
ALOSDIS
DLOSDIS
REQDIS
0x03
CR3
R/W
RNRZ
LOSMUT
RCLK2/LCV
RCLK2INV
RCLK1INV
0x04
CR4
R/W
Reserved
STS-1/DS3
E3
LLB
RLB
0x05
CR5
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x06
CR6
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x07
CR7
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x08
CR8
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x09
CR9
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x10
CR10
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x11
CR11
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x12
CR12
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x13
CR13
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x14
CR14
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
0x15
CR15
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Address:
Bit D4 - RLOL (Receive Loss of Lock Status)
The register addresses are in Hexadecimal format.
This Read-Only bit-field reflects the lock status of the
Clock Recovery Phase-Locked-Loop in the
XRT73L00A.
Type:
The Command Registers are either Read-Only (RO)
or Read/Write (R/W) registers.
This bit-field is set to “0” if the Clock Recovery PLL is
in lock with the incoming line signal. This bit-field is
set to “1” if the Clock Recovery PLL is out of lock with
the incoming line signal.
NOTES:
1. The default value for each of the bit-fields in these
registers is “0”.
2. If the REGRESET input pin is asserted, then the
contents of the command registers is reset to all
"0's" resulting in the XRT73L00A operating in the
mode corresponding to the default values of the
Command Registers.
Bit D3 - RLOS (Receive Loss of Signal Status)
This Read-Only bit-field indicates whether or not the
Receiver in the XRT73L00A is currently declaring an
LOS (Loss of Signal) Condition.
This bit-field is set to “0” if the XRT73L00A is not currently declaring the LOS Condition. This bit-field is
set to “1” if the XRT73L00A is declaring an LOS Condition.
DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER
5.1.1
Command Register - CR0
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Bit D2 - ALOS (Analog Loss of Signal Status)
TPDATA and TNDATA pins on the rising or falling
edge of TCLK (the Transmit Line Clock signal).
This Read-Only bit-field indicates whether or not the
Analog LOS Detector in the XRT73L00A is currently
declaring an LOS condition.
Writing a “1” to this bit-field configures the Transmitter
to sample the TPDATA and TNDATA input pins on the
rising edge of TCLK. Writing a “0” to this bit-field configures the Transmitter to sample the TPDATA and
TNDATA input pins on the falling edge of TCLK.
This bit-field is set to “0” if the Analog LOS Detector in
the XRT73L00A is NOT currently declaring an LOS
condition. Conversely, this bit-field is set to “1” if the
Analog LOS Detector is currently declaring an LOS
condition.
Bit D1 - TXLEV (Transmit Level Select)
This Read/Write bit-field is used to enable or disable
the XRT73L00A Transmit Line Build-Out circuit.
The purpose of this feature is to isolate either the Analog LOS or the Digital LOS detector that is declaring
the LOS condition. This feature may be useful for
troubleshooting/debugging purposes.
Setting this bit-field "High" disables the Line Build-Out
circuit of the XRT73L00A. In this mode, the
XRT73L00A outputs partially-shaped pulses onto the
line via the TTIP and TRING output pins. Setting this
bit-field "Low" enables the Line Build-Out circuit of the
XRT73L00A. In this mode the XRT73L00A outputs
shaped pulses onto the line via the TTIP and TRING
output pins.
Bit D1 - DLOS (Digital Loss of Signal Status)
This Read-Only bit-field indicates whether or not the
Digital LOS Detector in the XRT73L00A is currently
declaring an LOS condition.
This bit-field is set to “0” if the Digital LOS Detector in
the XRT73L00A is NOT currently declaring an LOS
condition. Conversely, this bit-field is set to “1” if the
Digital LOS Detector is currently declaring an LOS
condition.
To comply with the Isolated DSX/STSX-1 Pulse Template Requirements per Bellcore GR-499-CORE or
GR-253-CORE, either:
Bit D0 - DMO (Drive Monitor Output Status)
1. set this input pin to "1" if the cable length between
the Cross-Connect and the transmit output of the
XRT73L00A is greater than 225 feet or
2. set this input pin to "0" if the cable length between
the Cross-Connect and the transmit output of the
XRT73L00A is less than 225 feet.
This Read-Only bit-field reflects the status of the
DMO output pin.
NOTE: This option is only available when the XRT73L00A is
operating in the DS3 or STS-1 Mode.
NOTE: The purpose of this feature is to isolate the Detector
(e.g., either the Analog LOS or the Digital LOS detector)
that is declaring the LOS condition. This feature may be
useful for troubleshooting/debugging purposes.
Bit D0 - TXBIN (Transmit Binary Data)
5.1.2 Command Register - CR1
Bit D4 - TXOFF (Transmitter OFF)
This Read/Write bit-field permits configuring of the
Transmitter in the XRT73L00A to accept an un-encoded binary data stream via the TPDATA input and
converts this data into the appropriate bipolar signal
to the line.
This Read/Write bit-field is used to turn off the Transmitter in the XRT73L00A.
Writing a “1” to this bit-field turns off the Transmitter
and tri-states the Transmit Output. Writing a “0” to
this bit-field turns on the Transmitter.
Writing a “1” configures the Transmitter to accept a binary data stream via the TPDATA input.
Bit D3 - TAOS (Transmit All OneS)
NOTE: The TNDATA input is ignored.
This Read/Write bit-field is used to command the
XRT73L00A Transmitter to generate and transmit an
all “1’s” pattern onto the line.
This form of data acceptance is sometimes referred
to as Single-Rail mode operation. The Transmitter
then encodes this data into the appropriate line code
(e.g., B3ZS or HDB3) prior to its transmission over
the line.
Writing a “1” to this bit-field commands the Transmitter to transmit an all “1’s” pattern onto the line. Writing a “0” to this bit-field commands normal operation.
Writing a “0” configures the Transmitter to accept data
in a Dual-Rail manner (e.g., via both the TPDATA and
TNDATA inputs).
Bit D2 - TXCLKINV (Transmit Clock Invert)
This Read/Write bit-field is used to configure the
XRT73L00A Transmitter to sample the signal at the
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REV. 2.0.1
5.1.3 Command Register - CR2
Bit D4 - Reserved
minal Equipment in a Dual-Rail format via both the
RPOS and RNEG output pins.
This bit-field has no defined functionality
Bit D3 - LOSMUT (Recovered Data Muting during
LOS Condition)
Bit D3 - ENDECDIS (B3ZS/HDB3 Encoder/Decoder-Disable)
This Read/Write bit-field is used to configure the
XRT73L00A to NOT output any recovered data while
it is declaring an LOS condition to the terminal equipment.
This Read/Write bit-field is used to enable or disable
the B3ZS/HDB3 Encoder/Decoder in the
XRT73L00A.
Writing a “0” to this bit-field configures the chip to output recovered data even while the XRT73L00A is declaring an LOS condition. Writing a “1” to this bit-field
configures the chip to NOT output the recovered data
while an LOS condition is being declared.
Writing a “1” to this bit-field disables the B3ZS/HDB3
Encoder. Writing a “0” to this bit-field enables the
B3ZS/HDB3 Encoder.
NOTE: This Encoder performs HDB3 Encoding if the
XRT73L00A is operating in the E3 Mode. Otherwise, it performs B3ZS Encoding.
NOTE: In this mode, RPOS and RNEG is set to “0” asynchronously.
Bit D2 - ALOSDIS (Analog LOS Disable)
Bit D2 - RCLK2/LCV (Receive Clock Output 2/Line
Code Violation)
This Read/Write bit-field is used to disable the Analog
LOS Detector.
This Read/Write bit-field is used to select the function
of pin 30 (RCLK2/LCV). Pin 30 can be configured to
function as the Line Code Violation output indicator or
as the additional Receive Clock Output (RCLK2).
Writing a “0” to this bit-field enables the Analog LOS
Detector. Writing a “1” to this bit-field disables the
Analog LOS Detector.
NOTE: If the Analog LOS Detector is disabled, then the
RLOS input pin is only asserted by the DLOS (Digital LOS
Detector).
Writing a “0” to this bit-field configures the pin to function as the Line Code Violation output pin. Writing a
“1” to this bit-field configures this pin to function as
the RCLK2 output pin.
Bit D1 - DLOSDIS (Digital LOS Disable)
This Read/Write bit-field is used to disable the Digital
LOS Detector.
Bit D1 - RCLK2INV (Invert RCLK2)
This Read/Write bit-field is used to configure the Receiver in the XRT73L00A to output the recovered data
on either the rising edge or the falling edge of the
RCLK2 clock signal.
Writing a “0” to this bit-field enables the Digital LOS
Detector. Writing a “1” to this bit-field disables the
Digital LOS Detector.
NOTE: If the Digital LOS Detector is disabled, then the
RLOS input pin is only asserted by the ALOS (Analog LOS
Detector).
Writing a “0” to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RCLK2 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK2 output signal.
Bit D0 - REQDIS (Receive Equalization Disable)
This Read/Write bit-field is used to either enable or
disable the internal Receive Equalizer in the
XRT73L00A.
Bit D0 - RCLK1INV (Invert RCLK1)
This Read/Write bit-field is used to configure the Receiver in the XRT73L00A to output the recovered data
on either the rising edge or the falling edge of the
RCLK1 clock signal.
Writing a “0” to this bit-field enables the Internal
Equalizer. Writing a “1” to this bit-field disables the
Internal Equalizer.
5.1.4 Command Register - CR3
Bit D4 - RNRZ (Receive Binary Data)
Writing a “0” to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RCLK1 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK1 output signal.
This Read/Write bit-field is used to configure the
XRT73L00A to output the received data from the Remote Terminal in a binary or Dual-Rail format.
Writing a “1” to this bit-field configures the
XRT73L00A to output data to the Terminal Equipment
in a Single-Rail (binary) format via the RPOS output
pin. The RNEG is grounded. A “0” to this bit-field
configures the XRT73L00A to output data to the Ter-
5.1.5 Command Register - CR4
Bit D4 - Reserved
This bit-field has no defined functionality
Bit D3 - STS-1/DS3 Mode Select
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This Read/Write bit-field is used to configure the
XRT73L00A to operate in either the SONET STS-1
Mode or the DS3 Mode.
controllers available in the market. This interface
consists of the following signals:
CS
-
Chip Select (Active Low)
Writing a “0” into this bit-field configures the
XRT73L00A to operate in the DS3 Mode. Writing a
“1” into this bit-field configures the XRT73L00A to operate in the SONET STS-1 Mode.
SCLK
-
Serial Clock
SDI
-
Serial Data Input
SDO
-
Serial Data Output
NOTE: This bit-field is ignored if the E3 bit-field (D2 in this
Command Register) is set to “1”.
Using the Microprocessor Serial Interface
The following instructions for using the Microprocessor Serial Interface are best understood by referring
to the diagram in Figure 34.
Bit D2 - E3 Mode Select
This Read/Write bit-field is used to configure the
XRT73L00A to operate in the E3 Mode.
In order to use the Microprocessor Serial Interface, a
clock signal must be supplied to the SCLK input pin.
A Read or Write operation can then be initiated by asserting the active-low Chip Select input pin (CS). It is
important to assert the CS pin (e.g., toggle it “Low”) at
least 5ns prior to the very first rising edge of the clock
signal.
Writing a “0” into this bit-field configures the
XRT73L00A to operate in either the DS3 or SONET
STS-1 Mode specified by the setting of the DS3 bitfield in this Command Register. Writing a “1” into this
bit-field configures the XRT73L00A to operate in the
E3 Mode.
Once the CS input pin has been asserted, the type of
operation and the target register address must now
be specified. This information is supplied to the Microprocessor Serial Interface by writing eight serial
bits of data into the SDI input.
Bit D1 - LLB (Local Loop-Back)
This Read/Write bit-field along with RLB (bit D0 in this
Command Register) is used to select which LoopBack mode the XRT73L00A operates in. Table 6 relates the state of the LLB and RLB to the selected
Loop-Back mode.
NOTE: Each of these bits is clocked into the SDI input on
the rising edge of SCLK. These eight bits are identified and
described below.
Bit D0 - RLB (Remote Loop-Back)
This Read/Write bit-field along with LLB (bit D1 in this
Command Register) is used to select which LoopBack mode the XRT73L00A operate in. Table 6 relates the state of the LLB and RLB bits to the selected
Loop-Back mode.
Bit 1 - R/W (Read/Write) Bit
TABLE 6: LOOP-BACK MODES
This bit is clocked into the SDI input on the first rising
edge of SCLK after CS has been asserted. This bit
indicates whether the current operation is a Read or
Write operation. A “1” in this bit specifies a Read operation, a “0” in this bit specifies a Write operation.
LLB
(BIT D1)
RLB
(BIT D0)
Bits 2 through 5: The four (4) bit Address Values
(labeled A0, A1, A2 and A3)
0
0
No Loop-Back Mode (Normal
Operation)
0
1
Remote Loop-Back Mode
1
0
Analog Loop-Back Mode
1
1
Digital Loop-Back Mode
LOOP-BACK MODE
The next four rising edges of the SCLK signal clock in
the 4-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register in the XRT73L00A that the user is either
reading data from or writing data to. The address bits
must be supplied to the SDI input pin in ascending order with the LSB (least significant bit) first.
Bits 6 and 7:
5.2 OPERATING THE MICROPROCESSOR SERIAL
INTERFACE .
The XRT73L00A Serial Interface is a simple four wire
interface that is compatible with many of the micro-
The next two bits, A4 and A5 must be set to “0” as
shown in Figure 34.
Bit 8:
The value of A6 is a “don’t care”.
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
FIGURE 34. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
0
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
High Z
High Z
SDO
Notes:
Notes:
- -Denotes
a “don’t
care”
valuevalue
Denotes
a “don’t
care”
A4 and A5 are always “0”.
A4 and A5 are always “0”.
R/W = “1” for “Read” Operations
R/W= =“0”“1”
“Read”
Operations
R/W
forfor
“Write”
Operations
R/W = “0” for “Write” Operations
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
ORDERING INFORMATION
PART NO.
PACKAGE
OPERATING TEMPERATURE RANGE
XRT73L00AIV
44 Pin TQFP (10mm x 10mm)
-40°C to +85°C
PACKAGE DIMENSIONS
44 LEAD THIN QUAD FLAT PACK
(10 x 10 x 1.4 mm TQFP)
rev. 1.00
D
D1
33
23
22
34
D1
44
12
1
11
B
A2
e
C
A
α
Seating Plane
A1
SYMBOL
A
A1
A2
B
C
D
D1
e
L
α
L
INCHES
MIN
MAX
0.055
0.063
0.002
0.006
0.053
0.057
0.012
0.018
0.004
0.008
0.465
0.48
0.39
0.398
0.0315 BSC
0.018
0.03
0o
7o
MILLIMETERS
MIN
MAX
1.4
1.6
0.05
0.15
1.35
1.45
0.3
0.45
0.09
0.2
11.8
12.2
9.9
10.1
0.80 BSC
0.45
0.75
0o
7o
Note: The control dimension is the millimeter column
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D
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XRT73L00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 2.0.1
REVISION HISTORY
REV #
DATE
1.3.0
September
2001
2.0.0
February 2002
2.0.1
August 2002
CHANGES MADE
Redesigned 73L00 with improved performance and added timing recovery circuit.
Added typical E3 Jitter tolerance @800kHz. Receiver Sensitivity (cable length)
increased. Part Number changed to XRT73L00A, ordering information changed to
XRT73L00AIV.
Added connection points to various drawings.
Changed sentence, ”It is important to assert the CS pin (e.g., toggle it “Low") at least
5ns (from 50ns), prior to the very first rising edge of the clock signal.”, on page 47.
Changed values of t21 and t28 in electrical tables on page 19, from 50 to 5ns.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2001 EXAR Corporation
Datasheet August 2002.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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