AD AD5752RBREZ

Complete, Dual, 12-/14-/16-Bit, Serial Input,
Unipolar/Bipolar, Voltage Output DACs
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
FEATURES
GENERAL DESCRIPTION
Complete, dual, 12-/14-/16-bit D/A converter
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V
INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 µs maximum
Integrated reference: 5 ppm/°C typ.
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero-/mid-scale
DSP-/microcontroller-compatible serial interface
24-lead TSSOP
Operating temperature range: −40°C to +85°C
iCMOS™ process technology1
The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit,
serial input, voltage output, digital-to-analog converters. They
operate from single supply voltages of +4.5 V up to +16.5 V or
dual supply voltages from ±4.5 V up to ±16.5 V. Nominal fullscale output range is software-selectable from the options of
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output
amplifiers, reference buffers, and proprietary power-up/powerdown control circuitry are also provided.
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
The parts offer guaranteed monotonicity, integral nonlinearity
(INL) of ±16 LSB maximum, low noise, 10 µs maximum settling
time, and an on-chip +2.5 V reference.
The AD5722R/AD5732R/AD5752R use a serial interface that
operates at clock rates up to 30 MHz and are compatible with
DSP and microcontroller interface standards. Double buffering
allows the simultaneous updating of all DACs. The input coding
is user-selectable twos complement or offset binary for a bipolar
output (depending on the state of pin BIN/2sComp), and
straight binary for a unipolar output. The asynchronous clear
function clears all DAC registers to a user-selectable zero-scale
or mid-scale output. The parts are available in a 24-lead TSSOP
and offer guaranteed specifications over the −40°C to +85°C
industrial temperature range.
Table 1. Pin Compatible Devices
Part Number
AD5722/AD5732/AD5752
AD5724/AD5734/AD5754
AD5724R/AD5734R/AD5754R
1
Description
AD5722R/AD5732R/AD5752R
without internal reference.
Complete, quad, 12-/14-/16-bit,
serial input, unipolar/bipolar,
voltage output DAC.
AD5724/AD5734/AD5754 with
internal reference.
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased AC and DC performance.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Configuring the AD5722R/AD5732R/AD5752R .................. 23
Applications....................................................................................... 1
Transfer Function....................................................................... 23
General Description ......................................................................... 1
Input Register.............................................................................. 27
Functional Block Diagram .............................................................. 3
Data Register............................................................................... 27
Dual Supply Specifications .............................................................. 4
Output Range Select Register ................................................... 28
Single Supply Specifications ............................................................ 6
Control Register ......................................................................... 28
AC Performance Characteristics ................................................ 7
Power Control Register ............................................................. 29
Timing Characteristics ................................................................ 8
Features ............................................................................................ 30
Absolute Maximum Ratings.......................................................... 11
Analog Output Control ............................................................. 30
ESD Caution................................................................................ 11
Overcurrent Protection ............................................................. 30
Pin Configuration and Function Descriptions........................... 12
Thermal Shutdown .................................................................... 30
Typical Performance Characteristics ........................................... 13
Internal Reference ...................................................................... 30
Terminology .................................................................................... 19
Applications Information .............................................................. 31
Theory of Operation ...................................................................... 21
Layout Guidelines....................................................................... 31
Architecture................................................................................. 21
Galvanically Isolated Interface ................................................. 31
Serial Interface ............................................................................ 21
Microprocessor Interfacing....................................................... 31
Load DAC (LDAC)..................................................................... 23
Outline Dimensions ....................................................................... 32
Asynchronous Clear (CLR)....................................................... 23
Ordering Guide .......................................................................... 32
REVISION HISTORY
PrC – Preliminary Revision, November 16, 2007
Rev. PrC | Page 2 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
FUNCTIONAL BLOCK DIAGRAM
AVSS
AD5722R/AD5732R/AD5752R
2.5V
REFERENCE
CLR
BIN/2sCOMP
SDIN
SCLK
SYNC
REFIN/REFOUT
16
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
REFERENCE
BUFFERS
INPUT
REGISTER A
DAC
REGISTER A
INPUT
REGISTER B
DAC
REGISTER B
16
DAC A
VOUTA
DAC B
VOUTB
16
SDO
GND
LDAC
Figure 1.
Rev. PrC | Page 3 of 32
DAC_GND (2)
SIG_GND (2)
06466-001
DVCC
AVDD
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
SPECIFICATIONS
DUAL SUPPLY SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V, AVSS = −4.5 V1 to −16.5 V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, ±10 V range unless otherwise noted.
Table 2.
Parameter
ACCURACY
Bipolar Output
Resolution
AD5752R
AD5732R
AD5722R
Total Unadjusted Error (TUE)
Relative Accuracy (INL)
B Grade
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero TC2
Zero-Scale Error
Zero-Scale TC2
Gain Error
Gain TC2
DC Crosstalk2
Unipolar Output
Resolution
AD5752R
AD5732R
AD5722R
Total Unadjusted Error (TUE)
Relative Accuracy (INL)
B Grade
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale TC2
Offset Error
Gain Error
Gain TC2
DC Crosstalk2
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output
Output Voltage
Reference TC
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Voltage Drift vs. Time2
Value
Unit
Test Conditions/Comments
Outputs unloaded
16
14
12
0.1
Bits
Bits
Bits
% FSR max
±16
±1
±5
±8
±1
±8
±0.05
±8
0.6
LSB max
LSB max
mV max
ppm FSR/°C max
mV max
ppm FSR/°C max
% FSR max
ppm FSR/°C max
LSB max
16
14
12
0.1
Bits
Bits
Bits
% FSR max
±16
±1
+10
±4
±10
±0.05
±4
0.6
LSB max
LSB max
mV max
ppm FSR/°C max
mV max
% FSR max
ppm FSR/°C max
LSB max
@ 16-bit resolution
Guaranteed monotonic (@ 16 bit-resolution)
@ 25°C, error at other temperatures obtained using Zero-Scale TC
2.5
1
±10
2 to 3
V nom
MΩ min
µA max
V min to V max
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
2.498 to 2.502
±5
±10
18
75
±40
±50
V min to V max
ppm/°C typ
ppm/°C max
µV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr
typ
@ 25°C
Over temperature, supplies, and time
@ 16-bit resolution
Guaranteed monotonic (@ 16-bit resolution)
@ 25°C, error at other temperatures obtained using Bipolar Zero TC
@ 25°C, error at other temperatures obtained using Zero-Scale TC
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
AVSS = 0 V
Over temperature, supplies, and time
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
@ 10 kHz
Rev. PrC | Page 4 of 32
Preliminary Technical Data
Parameter
OUTPUT CHARACTERISTICS2
Output Voltage Range
Headroom
Output Voltage TC
Output Voltage Drift vs. Time
Value
Unit
Test Conditions/Comments
±10.8
±12
0.9
0.5
±8
±12
AVDD/AVSS = ±11.7 V min , REFIN = +2.5 V
AVDD/AVSS = ±12.9 V min, REFIN = +3 V
20
2
4000
0.5
V min to V max
V min to V max
V max
V typ
ppm FSR/°C max
ppm FSR/500 hr
typ
ppm FSR/1000
hr typ
mA max
kΩ min
pF max
Ω typ
2
0.8
±1
10
V min
V max
µA max
pF typ
0.4
DVCC − 1
0.4
DVCC − 0.5
±1
V max
V min
V max
V min
µA max
5
pF typ
4.5 to 16.5
-4.5 to -16.5
2.7 to 5.5
V min to V max
V min to V max
V min to V max
−75
2
±15
Short-Circuit Current
Load
Capacitive Load Stability
DC Output Impedance
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS (SDO) 2
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage
Current
High Impedance Output
Capacitance
POWER REQUIREMENTS
AVDD
AVSS
DVCC
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
AIDD
1
2
AD5722R/AD5732R/AD5752R
For specified performance
DVCC = 2.7 V to 5.5 V, JEDEC compliant
AISS
1.5
DICC
Power Dissipation
Power-Down Currents
AIDD
AISS
DICC
1
TBD
dB typ
mA/channel
max
mA/channel
max
µA max
mW typ
TBD
TBD
TBD
µA typ
µA typ
µA typ
Per pin
Per pin
DVCC = 5 V ± 10%, sinking 200 µA
DVCC = 5 V ± 10%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = GND, 0.5 µA typ
±12 V operation, outputs unloaded
For specified performance minimum headroom requirement is 0.9V
Guaranteed by characterization. Not production tested.
Rev. PrC | Page 5 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
SINGLE SUPPLY SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V, AVSS = 0 V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, 10 V range unless otherwise noted.
Table 3.
Parameter
ACCURACY
Resolution
AD5752R
AD5732R
AD5722R
Total Unadjusted Error (TUE)
Relative Accuracy (INL)
B Grade
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale TC2
Offset Error
Gain Error
Gain TC2
DC Crosstalk2
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output
Output Voltage
Reference TC
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Drift vs. Time2
OUTPUT CHARACTERISTICS2
Output Voltage Range
Headroom
Output Voltage TC
Output Voltage Drift vs. Time
Short Circuit Current
Load
Capacitive Load Stability
DC Output Impedance
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS (SDO)2
VOL, Output Low Voltage
VOH, Output High Voltage
Value
Unit
Test Conditions/Comments
Outputs unloaded
16
14
12
0.1
Bits
Bits
Bits
% FSR max
±16
±1
+10
±4
±10
±0.02
±8
0.6
LSB max
LSB max
mV max
ppm FSR/°C max
mV max
% FSR max
ppm FSR/°C max
LSB max
@ 16-bit resolution
Guaranteed monotonic (@ 16-bit resolution)
@ 25°C, error at other temperatures obtained using Zero-Scale TC
2.5
1
±10
2 to 3
V nom
MΩ min
µA max
V min to V max
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
2.498 to 2.502
±5
18
75
±40
±50
V min to V max
ppm/°C max
µV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr typ
@ 25°C
10.8
12
0.9
0.5
±8
±12
±15
20
2
4000
0.5
V max
V max
V max
V typ
ppm FSR/°C max
ppm/500 hr typ
ppm/1000 hr typ
mA typ
KΩ max
pF max
Ω typ
2
0.8
±1
5
V min
V max
µA max
pF max
Per pin
Per pin
0.4
DVCC − 1
V max
V min
DVCC = 5 V ± 10%, sinking 200 µA
DVCC = 5 V ± 10%, sourcing 200 µA
Across temperature and supplies
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
@ 10 kHz
AVDD = 11.7 V min, REFIN = 2.5 V
AVDD = 12.9 V min, REFIN = 3.75 V
For specified performance
DVCC = 2.7 V to 5.5 V, JEDEC compliant
Rev. PrC | Page 6 of 32
Preliminary Technical Data
Parameter
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
AVDD
DVCC
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
AIDD
DICC
Power Dissipation
1
2
AD5722R/AD5732R/AD5752R
Value
0.4
DVCC − 0.5
±1
5
Unit
V max
V min
µA max
pF typ
4.5 to 16.5
2.7 to 5.5
V min to V max
V min to V max
−75
2.75
1
TBD
dB typ
mA/channel max
µA max
mW typ
Test Conditions/Comments
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
Outputs unloaded
VIH = DVCC, VIL = GND, 0.5 µA typ
12 V operation, outputs unloaded
For specified performance minimum headroom requirement is 0.9V
Guaranteed by characterization. Not production tested.
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.5 V1 to 16.5 V, AVSS = −4.5 V to −16.5 V / 0V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, ±10 V range unless otherwise noted.
Table 4.
Parameter2
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz Bandwidth)
Output Noise (100 kHz Bandwidth)
1/f Corner Frequency
Output Noise Spectral Density
1
2
B Grade
Unit
Test Conditions/Comments
8
10
5
4.5
35
25
10
10
0.1
0.05
80
1
120
µs typ
µs max
µs max
V/µs typ
nV-sec typ
mV typ
nV-sec typ
nV-sec typ
nV-sec typ
LSB p-p typ
µV rms max
kHz typ
nV/√Hz typ
Full-scale step (20 V) to ±0.03 % FSR
512 LSB step settling (@ 16 bits)
Measured at 10 kHz
For specified performance minimum headroom requirement is 0.9V
Guaranteed by design and characterization, not production tested.
Rev. PrC | Page 7 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V, AVSS = −4.5 V to −16.5 V / 0V, GND = 0 V, REFIN = 2.5 V external, DVCC = 2.7 V to 5.5 V
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t174
t184
t19
Limit at TMIN, TMAX
33
13
13
13
13
100
5
0
20
20
20
1.5
10
1.5
20
2.5
13
40
200
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
µs max
µs max
ns min
µs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
SYNC rising edge to output response time (LDAC = 0)
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK rising edge
SCLK rising edge to SDO valid (CL SDO5 = 15 pF)
Minimum SYNC high time (readback/daisy-chain mode)
1
Guaranteed by characterization. Not production tested.
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, and Figure 4.
4
Daisy-chain and Readback mode.
5
CL SDO = Capacitive load on SDO output.
2
Rev. PrC | Page 8 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
t1
SCLK
1
2
24
t2
t3
t6
t5
t4
SYNC
t8
t7
SDIN
DB23
DB0
t9
t11
t10
LDAC
t13
t12
VOUTX
t13
t14
VOUTX
t15
CLR
t16
VOUTX
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
t3
t19
48
t2
t5
t17
t4
SYNC
t8
t7
SDIN
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t18
INPUT WORD FOR DAC N – 1
DB0
DB23
SDO
UNDEFINED
INPUT WORD FOR DAC N
t10
t11
06466-003
LDAC
Figure 3. Daisy Chain Timing Diagram
Rev. PrC | Page 9 of 32
AD5722R/AD5732R/AD5752R
SCLK
Preliminary Technical Data
1
24
1
24
t19
SYNC
DB23
DB0
DB23
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB23
DB0
DB0
DB23
UNDEFINED
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. PrC | Page 10 of 32
06466-004
SDIN
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 6.
Parameter
AVDD to GND
AVSS to GND
DVCC to GND
Digital Inputs to GND
Digital Outputs to GND
REFIN/REFOUT to GND
VOUTA, VOUTB to GND
DAC_GND to GND
SIG_GND to GND
Operating Temperature Range, TA
Industrial
Storage Temperature Range
Junction Temperature, TJ max
24-Lead TSSOP Package
θJA Thermal Impedance
Power Dissipation
Lead Temperature
Soldering
Rating
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to +17 V
AVSS to AVDD
-0.3V to +0.3V
-0.3V to +0.3V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
105°C
90°C/W
(TJ max – TA)/ θJA
JEDEC Industry Standard
J-STD-020
Rev. PrC | Page 11 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 AVDD
AVSS
1
NC
2
VOUTA
3
NC
4
BIN/2sCOMP
5
NC
6
20 SIG_GND
TOP VIEW
(Not to Scale) 19 DAC_GND
SYNC
7
18 DAC_GND
SCLK
8
17 REFIN/REFOUT
SDIN
9
16 SDO
LDAC 10
15 GND
NC 12
22 NC
21 SIG_GND
14 DVCC
13 NC
NC = NO CONNECT
06466-005
CLR 11
23 VOUTB
AD5722R/
AD5732R/
AD5752R
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
AVSS
2, 4, 6, 12,
13, 22
3
5
NC
VOUTA
BIN/2sCOMP
7
SYNC
8
SCLK
9
10
SDIN
LDAC
11
14
15
16
CLR1
DVCC
GND
SDO
17
REFIN/REFOUT
18, 19
20, 21
23
24
Exposed
Paddle
DAC_GND
SIG_GND
VOUTB
AVDD
AVSS
1
Description
Negative Analog Supply Pin. Voltage ranges from –4.5 V to –16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
Do not connect to these pins.
Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND.
When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary).
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog output. When
tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the DAC input register is updated, but the output update is held off until the falling
edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.
The LDAC pin should not be left unconnected.
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or mid-scale code (user-selectable).
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Ground Reference Pin.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.
REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV.
Ground reference pins for the four digital-to-analog converters.
Ground reference pins for the four output amplifiers.
Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Positive Analog Supply Pin. Voltage ranges from 4.5 V to 16.5 V.
Negative Analog Supply connection. Voltage ranges from -4.5V to -16.5V. This paddle can be connected to 0V
if output ranges are unipolar.
Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high.
Rev. PrC | Page 12 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. AD5752R Integral Nonlinearity Error vs. Code (Four Traces)
Figure 9. AD5752R Differential Nonlinearity Error vs. Code (Four Traces)
Figure 7. AD5732R Integral Nonlinearity Error vs. Code (Four Traces)
Figure 10. AD5732R Differential Nonlinearity Error vs. Code (Four Traces)
Figure 8. AD5722R Integral Nonlinearity Error vs. Code (Four Traces)
Figure 11. AD5722R Differential Nonlinearity Error vs. Code (Four Traces)
Rev. PrC | Page 13 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
Figure 12. AD5752R Integral Nonlinearity Error vs. Temperature (Four Traces)
Figure 15. AD5752R Differential Nonlinearity Error vs. Supply Voltage (Four Traces)
Figure 13. AD5752R Differential Nonlinearity Error vs. Temperature (Four Traces)
Figure 16. AD5752R Integral Nonlinearity Error vs. Reference Voltage (Four Traces)
Figure 14. AD5752R Integral Nonlinearity Error vs. Supply Voltage (Four Traces)
Figure 17. AD5752R Differential Nonlinearity vs. Reference Voltage (Four Traces)
Rev. PrC | Page 14 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
Figure 18. AD5752R Total Unadjusted Error vs. Reference Voltage (Four Traces)
Figure 21. AIDD vs. AVDD
Figure 19. AD5752R Total Unadjusted Error vs. Supply Voltage (Four Traces)
Figure 22. Zero-Scale Error vs. Temperature (Four Traces)
Figure 20. AIDD/AISS vs. AVDD/AVSS
Figure 23. Bipolar Zero Error vs. Temperature (Two Traces)
Rev. PrC | Page 15 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
Figure 24. Gain Error vs. Temperature (Four Traces)
Figure 27. Full-Scale Settling Time, ±10 V Range (Two Traces)
Figure 25. DICC vs. Logic Input Voltage Increasing and Decreasing
Figure 28. Full-Scale Settling Time, ±5 V Range (Two Traces)
Figure 26. Output Amplifier Source and Sink Capability (Four Traces)
Figure 29. Full-Scale Settling Time, +10 V Range (Two Traces)
Rev. PrC | Page 16 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
Figure 30. Full-Scale Settling Time, +5 V Range (Two Traces)
Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth (Four Traces)
Figure 31. Digital-to-Analog Glitch Energy (Four Traces)
Figure 34. VOUT vs. AVDD/AVSS on Power Up (Two Traces)
Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth (Four Traces)
Figure 35. REFOUT Turn-On Transient
Rev. PrC | Page 17 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
Figure 36. REFOUT Output Noise (100 kHz Bandwidth)
Figure 39. REFOUT Load Transient (Two Traces)
Figure 37. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
Figure 40. REFOUT Histogram of Thermal Hysteresis
Figure 38. REFOUT Line Transient (Two Traces)
Figure 41. REFOUT Voltage vs. Load Current
Rev. PrC | Page 18 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation in LSBs from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 6.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 9.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5722R/
AD5732R/AD5752R are monotonic over their full operating
temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 23.
Bipolar Zero TC
Bipolar Zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm FSR/°C.
Zero-Scale Error/Negative Full-Scale Error
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
should be negative full-scale − 1 LSB. A plot of zero-scale error
vs. temperature can be seen in Figure 22.
Zero-Scale TC
This is a measure of the change in zero-scale error with a change in
temperature. Zero-Scale TC is expressed in ppm FSR/°C.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input change.
A plot of full-scale settling time can be seen in Figure 27.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage output
D/A converter is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10% to 90% of the
output signal and is given in V/µs.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % FSR. A plot of gain error vs. temperature can be
seen in Figure 24.
Gain TC
This is a measure of the change in gain error with changes in
temperature. Gain TC is expressed in ppm FSR/°C.
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FSR.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5722R/AD5732R/AD5752R power on. It is
normally specified as the area of the glitch in nV-sec. See Figure 34.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LSB at the major
carry transition (0x7FFF to 0x8000). See Figure 31.
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition (0x7FFF to
0x8000). See Figure 31.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
Rev. PrC | Page 19 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
DC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in LSBs.
Digital Crosstalk
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus.
DAC-to-DAC Crosstalk
DAC-to-DAC Crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change(all 1s to all 0s and vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-sec.
Voltage Reference TC
Reference TC is a measure of the change in the reference output
voltage with a change in temperature. It is expressed in ppm/°C.
Rev. PrC | Page 20 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
THEORY OF OPERATION
REFIN
The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit,
serial input, unipolar/bipolar, voltage output DACs. They
operate from unipolar supply voltages of +4.5 V to +16.5 V or
bipolar supply voltages of ±4.5 V to ±16.5 V. In addition, the
parts have software-selectable output ranges of +5 V, +10 V,
+10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the
AD5722R/AD5732R/AD5752R in a 24-bit word format via a
3-wire serial interface. The devices also offer an SDO pin to
facilitate daisy chaining or readback.
R
R
TO OUTPUT
AMPLIFIER
R
The AD5722R/AD5732R/AD5752R incorporate a power-on
reset circuit to ensure that the DAC registers power up loaded
with 0x0000. When powered on, the outputs are clamped to 0 V
via a low impedance path. The parts also feature on-chip
reference and reference buffers.
R
R
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 42 shows a block diagram of the DAC
architecture. The reference input is buffered before being
applied to the DAC.
REF (+)
RESISTOR
STRING
VOUTX
CONFIGURABLE
OUTPUT
AMPLIFIER
GND
OUTPUT
RANGE CONTROL
06466-006
REF (–)
Figure 43. Resistor String Structure
Output Amplifiers
REFIN
DAC REGISTER
06466-007
ARCHITECTURE
Figure 42. DAC Architecture Block Diagram
The resistor string structure is shown in Figure 43. It is a string
of resistors, each of value R. The code loaded to the DAC
register determines the node on the string where the voltage is
to be tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 4000 pF to GND. The source and sink
capabilities of the output amplifiers can be seen in Figure 26.
The slew rate is 4.5 V/µs with a full-scale settling time of 10 µs.
Reference Buffers
The AD5722R/AD5732R/AD5752R can operate with either an
external or internal reference. The reference input has an input
range of 2 V to 3 V with 2.5 V for specified performance. This
input voltage is then buffered before it is applied to the DAC cores.
SERIAL INTERFACE
The AD5722R/AD5732R/AD5752R are controlled over a
versatile 3-wire serial interface that operates at clock rates up to
30 MHz. It is compatible with SPI®, QSPI™, MICROWIRE™, and
DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits. The timing diagram for this operation is shown in Figure 2.
Rev. PrC | Page 21 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be
used if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid. The input register addressed is updated on the rising
edge of SYNC. For another serial transfer to take place, SYNC
must be brought low again. After the end of the serial data
transfer, data is automatically transferred from the input shift
register to the addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low while SYNC is high.
68HC11*
SDIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
SDO
MISO
A continuous SCLK source can only be used if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
Readback Operation
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. (If the SDO output is disabled via the
SDO DISABLE bit in the control register, it is automatically
enabled for the duration of the read operation after which it is
disabled again). With R/W = 1, Bit A2 to Bit A0 in association
with Bit REG2 to Bit REG0 select the register to be read. The
remaining data bits in the write sequence are don’t care bits.
During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO. The
readback diagram in Figure 4 shows the readback sequence. For
example, to read back the data register of Channel A, the
following sequence should be implemented:
AD5722R/
AD5732R/
AD5752R*
MOSI
write cycle. SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5722R/AD5732R/AD5752R devices in the chain. When the
serial transfer to all devices is complete, SYNC is taken high.
This latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or a gated clock.
SDIN
AD5722R/
AD5732R/
AD5752R*
SCLK
SYNC
LDAC
1.
SDO
SDIN
AD5722R/
AD5732R/
AD5752R*
2.
SCLK
Write 0x800000 to the AD5722R/AD5732R/AD5752R
input register. This configures the part for read mode with
the data register of Channel A selected. Note that all the
data bits, DB15 to DB0, are don’t care bits.
Follow this with a second write, a NOP condition, 0x180000.
During this write, the data from the register is clocked out
on the SDO line.
SYNC
LDAC
*ADDITIONAL
PINS OMITTED FOR CLARITY.
06466-008
SDO
Figure 44. Daisy Chaining the AD5722R/AD5732R/AD5752R
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
of serial interface lines. The first falling edge of SYNC starts the
Rev. PrC | Page 22 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
LOAD DAC (LDAC)
CONFIGURING THE AD5722R/AD5732R/AD5752R
After data has been transferred into the input register of the
DACs, there are two ways to update the DAC registers and DAC
outputs. Depending on the status of both SYNC and LDAC, one
of two update modes is selected, individual DAC updating or
simultaneous updating of all DACs.
When the power supplies are applied to the AD5722R/AD5732R/
AD5752R, the power-on reset circuit ensures that all registers
default to 0. This places all channels and the internal reference in
power-down mode. The first communication to the
AD5722R/AD5732R/AD5752R should be to set the required
output range on all channels (default range is the 5 V unipolar
range) by writing to the range select register. The user should then
write to the power-control register to power-on the required
channels and the internal reference, if required. If an external
reference source is being used, the internal reference must
remain in power-down mode. To program an output value on a
channel, that channel must first be powered up; any writes to a
channel while it is in power-down mode are ignored. The
AD5722R/AD5732R/AD5752R operate with a wide power supply
range. It is important that the power supply applied to the parts
provides adequate headroom to support the chosen output
ranges.
OUTPUT
AMPLIFIER
VREFIN
12-/14-/16-BIT
DAC
LDAC
DAC
REGISTER
VOUT
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
06466-009
INPUT
REGISTER
Figure 45. Simplified Diagram of Input Loading Circuitry for One DAC
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are
asynchronously updated by taking LDAC low after SYNC has
been taken high. The update now occurs on the falling edge of
LDAC.
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low clear that allows the outputs to be cleared
to either zero-scale code or mid-scale code. The clear code
value is user-selectable via the CLR SELECT bit of the control
register (see the Control Register section). It is necessary to
maintain CLR low for a minimum amount of time to complete
the operation (see Figure 2). When the CLR signal is returned
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
while the CLR pin is low. A clear operation can also be
performed via the clear command in the control register.
TRANSFER FUNCTION
Table 9 to Table 17 show the relationships of the ideal input code
to output voltage for the AD5752R, AD5732R, and AD5722R,
respectively, for all output voltage ranges. For unipolar output
ranges, the data coding is straight binary. For bipolar output
ranges, the data coding is user-selectable via the BIN/2sCOMP
pin and can be either offset binary or twos complement.
For a unipolar output range, the output voltage expression is
given by
D
VOUT = VREFIN × Gain ⎡⎢ N ⎤⎥
2
⎣ ⎦
For a bipolar output range, the output voltage expression is given by
Gain × VREFIN
D
VOUT = VREFIN × Gain ⎡⎢ N ⎤⎥ −
2
⎣2 ⎦
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
VREFIN is the reference voltage applied at the REFIN pin.
Gain is an internal gain whose value depends on the output
range selected by the user as shown in Table 8.
Table 8.
Output Range (V)
+5
+10
+10.8
±5
±10
±10.8
Rev. PrC | Page 23 of 32
Gain Value
2
4
4.32
4
8
8.64
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
Ideal Output Voltage to Input Code Relationship—AD5752R
Table 9. Bipolar Output, Offset Binary Coding
Digital Input
MSB
1111
1111
–
1000
1000
0111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
±5 V Output Range
+2 REFIN(32767/32768)
+2 REFIN(32766/32768)
–
+2 REFIN(1/32768)
0V
−2 REFIN(1/32768)
–
−2 REFIN(32766/32768)
−2 REFIN(32767/32768
Analog Output
±10 V Output Range
+4 REFIN(32767/32768)
+4 REFIN(32766/32768)
–
+4 REFIN(1/32768)
0V
−4 REFIN(1/32768)
–
−4 REFIN(32766/32768)
−4 REFIN(32767/32768)
±10.8 V Output Range
+4.32 REFIN(32767/32768)
+4.32 REFIN(32766/32768)
–
+4.32 REFIN(1/32768)
0V
−4.32 REFIN(32766/32768)
–
−4.32 REFIN(32766/32768)
−4.32 REFIN(32767/32768)
Analog Output
±10 V Output Range
+4 REFIN(32767/32768)
+4 REFIN(32766/32768)
–
+4 REFIN(1/32768)
0V
−4 REFIN(1/32768)
–
−4 REFIN(32766/32768)
−4 REFIN(32767/32768)
±10.8 V Output Range
+4.32 REFIN(32767/32768)
+4.32 REFIN(32766/32768)
–
+4.32 REFIN(1/32768)
0V
−4.32 REFIN(1/32768)
–
−4.32 REFIN(32766/32768)
−4.32 REFIN(32767/32768)
Analog Input
+10 V Output Range
+4 REFIN(65535/65536)
+4 REFIN(65534/65536)
–
+4 REFIN(32769/65536)
+4 REFIN(32768/65536)
+4 REFIN(32767/65536)
–
+4 REFIN(1/65536)
0V
+10.8 V Output Range
+4.32 REFIN(65535/65536)
+4.32 REFIN(65534/65536)
–
+4.32 REFIN(32769/65536)
+4.32 REFIN(32768/65536)
+4.32 REFIN(32767/65536)
–
+4.32 REFIN(1/65536)
0V
Table 10. Bipolar Output, Twos Complement Coding
Digital Input
MSB
0111
0111
–
0000
0000
1111
–
1000
1000
1111
1111
–
0000
0000
1111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
±5 V Output Range
+2 REFIN(32767/32768)
+2 REFIN(32766/32768)
–
+2 REFIN(1/32768)
0V
−2 REFIN(1/32768)
–
−2 REFIN(32766/32768)
−2 REFIN(32767/32768)
Table 11. Unipolar Output, Straight Binary Coding
Digital Input
MSB
1111
1111
–
1000
1000
0111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
+5 V Output Range
+2 REFIN(65535/65536)
+2 REFIN(65534/65536)
–
+2 REFIN(32769/65536)
+2 REFIN(32768/65536)
+2 REFIN(32767/65536)
–
+2 REFIN(1/65536)
0V
Rev. PrC | Page 24 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
Ideal Output Voltage to Input Code Relationship—AD5732R
Table 12. Bipolar Output, Offset Binary Coding
Digital Input
MSB
11
11
–
10
10
01
–
00
00
1111
1111
–
0000
0000
1111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
±5 V Output Range
+2 REFIN(8191/8192)
+2 REFIN(8190/8192)
–
+2 REFIN(1/8192)
0V
−2 REFIN(1/8192)
–
−2 REFIN(8190/8192)
−2 REFIN(8191/8191)
Analog Output
±10 V Output Range
+4 REFIN(8191/8192)
+4 REFIN(8190/8192)
–
+4 REFIN(1/8192)
0V
−4 REFIN(1/8192)
–
−4 REFIN(8190/8192)
−4 REFIN(8191/8192)
±10.8 V Output Range
+4.32 REFIN(8191/8192)
+4.32 REFIN(8190/8192)
–
+4 REFIN(1/8192)
0V
−4.32 REFIN(1/8192)
–
−4.32 REFIN(8190/8192)
−4.32 REFIN(8191/8192)
Analog Output
±10 V Output Range
+4 REFIN(8191/8192)
+4 REFIN(8190/8192)
–
+4 REFIN(1/8192)
0V
−4 REFIN(1/8192)
–
−4 REFIN(8190/8192)
−4 REFIN(8191/8192)
±10.8 V Output Range
+4.32 REFIN(8191/8192)
+4.32 REFIN(8190/8192)
–
+4 REFIN(1/8192)
0V
−4.32 REFIN(1/8192)
–
−4.32 REFIN(8190/8192)
−4.32 REFIN(8191/8192)
Table 13. Bipolar Output, Twos Complement Coding
Digital Input
MSB
01
01
–
00
00
11
–
10
10
1111
1111
–
0000
0000
1111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
±5 V Output Range
+2 REFIN(8191/8192)
+2 REFIN(8190/8192)
–
+2 REFIN(1/8192)
0V
−2 REFIN(1/8192)
–
−2 REFIN(8190/8192)
−2 REFIN(8191/8192)
Table 14. Unipolar Output, Straight Binary Coding
Digital Input
MSB
11
11
–
10
10
01
–
00
00
1111
1111
–
0000
0000
1111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
±5 V Output Range
+2 REFIN(16383/16384)
+2 REFIN(16382/16384)
–
+2 REFIN(8193/16384)
+2 REFIN(8192/16384)
+2 REFIN(8191/16384)
–
+2 REFIN(1/16384)
0V
Analog Output
±10 V Output Range
+4 REFIN(16383/16384)
+4 REFIN(16382/16384)
–
+4 REFIN(8193/16384)
+4 REFIN(8192/16384)
+4 REFIN(8191/16384)
–
+4 REFIN(1/16384)
0V
Rev. PrC | Page 25 of 32
±10.8 V Output Range
+4.32 REFIN(16383/16384)
+4.32 REFIN(16382/16384)
–
+4.32 REFIN(8193/16384)
+4.32 REFIN(8192/16384)
+4.32 REFIN(8191/16384)
–
+4.32 REFIN(1/16384)
0V
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
Ideal Output Voltage to Input Code Relationship—AD5722R
Table 15. Bipolar Output, Offset Binary Coding
Digital Input
MSB
1111
1111
–
1000
1000
0111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
±5 V Output Range
+2 REFIN(2047/2048)
+2 REFIN(2046/2048)
–
+2 REFIN(1/2048)
0V
−2 REFIN(1/2048)
–
−2 REFIN(2046/2048)
−2 REFIN(2047/2047)
Analog Output
±10 V Output Range
+4 REFIN(2047/2048)
+4 REFIN(2046/2048)
–
+4 REFIN(1/2048)
0V
−4 REFIN(1/2048)
–
−4 REFIN(2046/2048)
−4 REFIN(2047/2048)
±10.8 V Output Range
+4.32 REFIN(2047/2048)
+4.32 REFIN(2046/2048)
–
+4 REFIN(1/2048)
0V
−4.32 REFIN(1/2048)
–
−4.32 REFIN(2046/2048)
−4.32 REFIN(2047/2048)
Analog Output
±10 V Output Range
+4 REFIN(2047/2048)
+4 REFIN(2046/2048)
–
+4 REFIN(1/2048)
0V
−4 REFIN(1/2048)
–
−4 REFIN(2046/2048)
−4 REFIN(2047/2048)
±10.8 V Output Range
+4.32 REFIN(2047/2048)
+4.32 REFIN(2046/2048)
–
+4 REFIN(1/2048)
0V
−4.32 REFIN(1/2048)
–
−4.32 REFIN(2046/2048)
−4.32 REFIN(2047/2048)
Analog Output
+10 V Output Range
+4 REFIN(4095/4096)
+4 REFIN(4094/4096)
–
+4 REFIN(2049/4096)
+4 REFIN(2048/4096)
+4 REFIN(2047/4096)
–
+4 REFIN(1/4096)
0V
+10.8 V Output Range
+4.32 REFIN(4095/4096)
+4.32 REFIN(4094/4096)
–
+4.32 REFIN(2049/4096)
+4.32 REFIN(2048/4096)
+4.32 REFIN(2047/4096)
–
4.32 REFIN(1/4096)
0V
Table 16. Bipolar Output, Twos Complement Coding
MSB
0111
0111
–
0000
0000
1111
–
1000
1000
Digital Output
LSB
1111
1111
1111
1110
–
–
0000
0001
0000
0000
1111
1111
–
–
0000
0001
0000
0000
±5 V Output Range
+2 REFIN(2047/2048)
+2 REFIN(2046/2048)
–
+2 REFIN(1/2048)
0V
−2 REFIN(1/2048)
–
−2 REFIN(2046/2048)
−2 REFIN(2047/2048)
Table 17. Unipolar Output, Straight Binary Coding
Digital Input
MSB
1111
1111
–
1000
1000
0111
–
0000
0000
1111
1111
–
0000
0000
1111
–
0000
0000
LSB
1111
1110
–
0001
0000
1111
–
0001
0000
+5 V Output Range
+2 REFIN(4095/4096)
+2 REFIN(4094/4096)
–
+2 REFIN(2049/4096)
+2 REFIN(2048/4096)
+2 REFIN(2047/4096)
–
+2 REFIN(1/4096)
0V
Rev. PrC | Page 26 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
INPUT REGISTER
The input register is 24 bits wide and consists of a read/write bit, a reserved bit, three register select bits, three DAC address bits, and 12/14-/16 data bits. The register data is clocked in MSB first on the SDIN pin. Table 18 shows the register format while Table 19 describes
the function of each bit in the register. All registers are read/write registers.
Table 18. Input Register Format
MSB
DB23
R/W
DB22
0
DB21
REG2
DB20
REG1
DB19
REG0
DB18
A2
DB17
A1
LSB
DB15 to DB0
DATA
DB16
A0
Table 19. Input Register Bit Functions
Bit Mnemonic
R/W
Description
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a write operation is to the data register, output range
select register, power control register, or control register.
REG2
REG1
REG0
Function
0
0
0
Data Register
0
0
1
Output Range Select Register
0
1
0
Power Control Register
0
1
1
Control Register
These bits are used to decode the DAC channels.
A2
A1
A0
Channel Address
0
0
0
DAC A
0
1
0
DAC B
1
0
0
Both DACs
Data bits.
A2, A1, A0
DB15 to DB0
DATA REGISTER
The data register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer
is to take place (see Table 19). The data bits are in positions DB15 to DB0 for the AD5752R (see Table 20), DB15 to DB2 for the AD5732R
(see Table 21), and DB15 to DB4 for the AD5722R (see Table 22).
Table 20. Programming the AD5752R Data Register
MSB
REG2
0
REG1
0
REG0
0
A2
A1
DAC Address
LSB
DB15 to DB0
16-Bit DAC Data
A0
Table 21. Programming the AD5732R Data Register
MSB
REG2
0
LSB
REG1
0
REG0
0
A2
A1
DAC Address
A0
DB15 to DB2
14-Bit DAC Data
DB1
X
DB0
X
Table 22. Programming the AD5722R Data Register
MSB
REG2
0
LSB
REG1
0
REG0
0
A2
A1
A0
DAC Address
DB15 to DB4
12-Bit DAC Data
Rev. PrC | Page 27 of 32
DB3
X
DB2
X
DB1
X
DB0
X
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
OUTPUT RANGE SELECT REGISTER
The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, while,
the range bits (R2, R1, R0) select the required output range (see Table 23 and Table 24).
Table 23. Programming the Required Output Range
MSB
REG2
0
LSB
REG1
0
REG0
0
A2
A1
A0
DAC Address
DB15 to DB3
Don’t Care
DB2
R2
DB1
R1
DB0
R0
Table 24. Output Range Options
R2
0
0
0
0
1
1
R1
0
0
1
1
0
0
R0
0
1
0
1
0
1
Output Range (V)
+5
+10
+10.8
±5
±10
±10.8
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 25 and Table 26.
Table 25. Control Register Format
MSB
REG2
0
REG1
1
REG0
1
A2
0
A1
0
A0
0
DB15 to DB4
DB3
REG2
0
REG1
1
REG0
1
A2
0
A1
0
A0
1
DB15 to DB4
Don’t Care
DB3
TSD ENABLE
REG2
0
REG1
1
REG0
1
A2
1
A1
0
A0
0
DB15 to DB4
DB3
DB2
DB1
CLEAR, Data = Don’t Care
DB0
REG2
0
REG1
1
REG0
1
A2
1
A1
0
A0
1
DB15 to DB4
DB3
DB2
DB1
LOAD, Data = Don’t Care
DB0
DB2
DB1
NOP, Data = Don’t Care
DB2
CLAMP ENABLE
DB1
CLR SELECT
LSB
DB0
DB0
SDO DISABLE
Table 26. Explanation of Control Register Options
Option
NOP
CLEAR
LOAD
SDO DISABLE
CLR SELECT
CLAMP ENABLE
TSD ENABLE
Description
No operation instruction used in readback operations.
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Addressing this function updates the DAC registers and consequently, the DAC outputs.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
See Table 27 for a description of the CLR SELECT operation.
Set by the user to enable the current limit clamp. The channel does not power down on detection of
overcurrent; the current is clamped at 20 mA (default).
Cleared by the user to enable the current-limit clamp. The channel powers down on detection of overcurrent.
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
Table 27. CLR Select Options
CLR SELECT
Setting
0
1
Unipolar Output Range
0V
Mid-Scale
Output CLR Value
Bipolar Output Range
0V
Negative Full-Scale
Rev. PrC | Page 28 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power
and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 28 and Table 29.
Table 28. Power Control Register Format
MSB
REG2
0
REG1
1
REG0
0
A2
0
A1
0
A0
0
DB15 to DB11
Don’t Care
DB10
X
DB9
OCB
DB8
X
DB7
OCA
DB6
0
DB5
TSD
DB4
PUREF
DB3
X
DB2
PUB
DB1
X
LSB
DB0
PUA
Table 29. Explanation of Status Register Options
Option
PUA
PUB
PUREF
TSD
OCA
OCB
Description
DAC A Power-Up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). If the CLAMP ENABLE bit of the control register is cleared, DAC A will power down autimatically on detection of
an over-current, PUA will be cleared to reflect this.
DAC B Power-Up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). If the CLAMP ENABLE bit of the control register is cleared, DAC B will power down autimatically on detection of an
over-current, PUB will be cleared to reflect this.
Reference Power-Up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
Thermal Shutdown Alert. Read-Only Bit. In the event of an overtemperature situation, this bit is set.
DAC A Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC A, this bit is set.
DAC B Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC B, this bit is set.
Rev. PrC | Page 29 of 32
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
FEATURES
ANALOG OUTPUT CONTROL
Constant Current Clamp (CLAMP ENABLE = 1)
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up. When the
supply voltages change during power-up, the VOUT pins are
clamped to 0 V via a low impedance path (approxiamately
4kΩ). To prevent the output amplifiers from being shorted to
0 V during this time, Transmission Gate G1 is also opened (see
Figure 46). These conditions are maintained until the power
supplies have stabilized and a valid word is written to a DAC
register. At this time, G2 opens and G1 closes.
If a short circuit occurs in this configuration, the current is
clamped at 20 mA. This event is signaled to the user by the
setting of the appropriate overcurrent (OCX) bit in the power
control register. Upon removal of the short-circuit fault, the
OCX bit is cleared.
VOLTAGE
MONITOR
AND
CONTROL
G1
VOUTA
G2
Automatic Channel Power-Down (CLAMP ENABLE =0)
If a short circuit occurs in this configuration, the shorted
channel powers down, and its output is clamped to ground via a
resistance of approxiamately 4kΩ, also at this time the output of
the amplifier is disconnected from the output pin. The shortcircuit event is signaled to the user via the overcurrent (OCX)
bits, while the power-up (PUX ) bits indicate which channels
have powered down. After the fault is rectified, the channels can
be powered up again by setting the PUX bits.
06466-010
THERMAL SHUTDOWN
Figure 46. Analog Output Control Circuitry
OVERCURRENT PROTECTION
Each DAC channel of the AD5722R/AD5732R/AD5752R
incorporates individual overcurrent protection. The user has
two options for the configuration of the overcurrent protection,
constant current clamp or automatic channel power-down. The
configuration of the overcurrent protection is selected via the
CLAMP ENABLE bit in the control register.
The AD5722R/AD5732R/AD5752R incorporate a thermal
shutdown feature that automatically shuts down the device if
the core temperature exceeds approximately 150°C. The thermal
shutdown feature is disabled by default and can be enabled via
the TSD ENABLE bit of the control register. In the event of a
thermal shutdown, the TSD bit of the power control register is set.
INTERNAL REFERENCE
The on-chip voltage reference is powered down by default. If an
external voltage reference source is to be used, the internal
reference must remain powered down at all times. If the
internal reference is to be used as the reference source, it must
be powered up via the PUREF bit of the power control register.
The internal reference voltage is accessible at the REFIN/REFOUT
pin for use as a reference source for other devices within the
system. If the internal reference is to be used external to the
AD5722R/AD5732R/AD5752R, it must first be buffered.
Rev. PrC | Page 30 of 32
Preliminary Technical Data
AD5722R/AD5732R/AD5752R
APPLICATIONS INFORMATION
+5V / ±5V OPERATION
GALVANICALLY ISOLATED INTERFACE
When operating from a single +5V supply or a dual ±5V supply
an output range of +5V or ±5V is not achievable as sufficient
headroom for the output amplifier is not available. In this
situation a reduced reference voltage can be used, for instance a
2V reference voltage will produce an output range of +4V or
±4V, the 1v of headroom is more than rnough for full operation.
A standard value voltage reference of 2.048V can be used to
produce output ranges of +4.096V and ±4.096V. Refer to the
Typical Performance Characteristics plots for performance data
at a range of voltage reference values.
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices provides
voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5722R/AD5732R/AD5752R make them ideal for
isolated interfaces because the number of interface lines is kept
to a minimum. Figure 47 shows a 4-channel isolated interface to
the AD5722R/AD5732R/AD5752R using an ADuM1400. For
further information, visit http://www.analog.com/icouplers.
ADuM1400*
MICROCONTROLLER
The AD5722R/AD5732R/AD5752R should have an ample supply
bypassing of a 10 µF capacitor in parallel with a 0.1 µF capacitor
on each supply located as close to the package as possible,
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. The 0.1 µF capacitor should have low
effective series resistance (ESR) and low effective series
inductance (ESI) such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
The power supply lines of the AD5722R/AD5732R/AD5752R
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply
line. Fast switching signals such as clocks should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs. A
ground line routed between the SDIN and SCLK lines helps
reduce crosstalk between them (this is not required on a
multilayer board that has a separate ground plane, but separating
the lines does help). It is essential to minimize noise on the
REFIN line because it couples through to the DAC output.
SERIAL CLOCK OUT
SERIAL DATA OUT
SYNC OUT
CONTROL OUT
V IA
V IB
V IC
V ID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
V OA
V OB
V OC
V OD
TO SCLK
TO SDIN
TO SYNC
TO LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 47. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5722R/AD5732R/AD5752R
is via a serial bus that uses standard protocol compatible with
microcontrollers and DSP processors. The communications
channel is a 3-wire (minimum) interface consisting of a clock
signal, a data signal, and a synchronization signal. The
AD5722R/AD5732R/AD5752R require a 24-bit data-word with
data valid on the falling edge of SCLK.
For all interfaces, the DAC output update can be initiated
automatically when all the data is clocked in, or it can be
performed under the control of LDAC. The contents of the
registers can be read using the readback function.
AD5722R/AD5732R/AD5752R to Blackfin® DSP interface
Figure 48 shows how the AD5722R/AD5732R/AD5752R can be
interfaced to Analog Devices Blackfin DSP. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5722R/AD5732R/AD5752R and the programmable
I/O pins that can be used to set the state of a digital input such
as the LDAC pin.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.
Rev. PrC | Page 31 of 32
SPISELx
SYNC
SCK
MOSI
SCLK
SDIN
ADSP-BF531
PF10
AD5722R/
AD5732R/
AD5752R
LDAC
06466-012
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5722R/AD5732R/AD5752R are mounted should
be designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the AD5722R/
AD5732R/AD5752R are in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device.
06466-011
LAYOUT GUIDELINES
Figure 48. AD5722R/AD5732R/AD5752R to Blackfin Interface
AD5722R/AD5732R/AD5752R
Preliminary Technical Data
OUTLINE DIMENSIONS
5.02
5.00
4.95
7.90
7.80
7.70
24
13
4.50
4.40
4.30
3.25
3.20
3.15
EXPOSED
PAD
(Pins Up)
6.40 BSC
1
12
BOTTOM VIEW
TOP VIEW
1.20 MAX
0.15
0.05
SEATING
PLANE
0.10 COPLANARITY
0.65
BSC
8°
0°
0.20
0.09
0.30
0.19
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
050806-A
1.05
1.00
0.80
Figure 49. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5722RBREZ1
AD5722RBREZ-REEL71
AD5732RBREZ1
AD5732RBREZ-REEL71
AD5752RBREZ1
AD5752RBREZ-REEL71
1
Resolution
12
12
14
14
16
16
Temperature Range
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
INL
±1 LSB
±1 LSB
±4 LSB
±4 LSB
±16 LSB
±16 LSB
Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06466-0-11/07(PrC)
Rev. PrC | Page 32 of 32
Package Description
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
Package Option
RE-24
RE-24
RE-24
RE-24
RE-24
RE-24