Multiple Range, 16-/12-Bit, Bipolar/Unipolar Voltage Output DACs with 2 ppm/°C Reference AD5761R/AD5721R Data Sheet FEATURES GENERAL DESCRIPTION 8 software-programmable output ranges: 0 V to 5 V, 0 V to 10 V, 0 V to 16 V, 0 V to 20 V, ±3 V, ±5 V, ±10 V, and −2.5 V to +7.5 V; 5% overrange Low drift 2.5 V reference: ±2 ppm/°C typical Total unadjusted error (TUE): 0.1% FSR maximum 16-bit accuracy: ±2 LSB maximum Guaranteed monotonicity: ±1 LSB maximum Single channel, 16-/12-bit DACs Settling time: 7.5 μs typical Integrated reference buffers Low noise: 35 nV/√Hz Low glitch: 1 nV-sec (0 V to 5 V range) 1.7 V to 5.5 V digital supply range Asynchronous updating via LDAC Asynchronous RESET to zero scale/midscale DSP-/microcontroller-compatible serial interface Robust 4 kV HBM ESD rating 16-lead, 3 mm × 3 mm LFCSP package 16-lead TSSOP package Operating temperature range: −40°C to +125°C The AD5761R/AD5721R are single channel, 16-/12-bit serial input, voltage output, digital-to-analog converters (DACs). They operate from single supply voltages from 4.75 V to 30 V or dual supply voltages from −16.5 V to 0 V VSS and 4.75 V to 16.5 V VDD. The integrated output amplifier, reference buffer, and reference provide a very easy to use, universal solution. The devices offer guaranteed monotonicity, integral nonlinearity (INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settling time on selected ranges. The AD5761R/AD5721R use a serial interface that operates at clock rates of up to 50 MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the asynchronous updating of the DAC output. The input coding is user-selectable twos complement or straight binary. The asynchronous reset function resets all registers to their default state. The output range is user selectable, via the RA[2:0] bits in the control register. The devices available in a 3 mm × 3 mm LFCSP package and a 16-lead TSSOP package offer guaranteed specifications over the −40°C to +125°C industrial temperature range. APPLICATIONS Industrial automation Instrumentation, data acquisition Open-/closed-loop servo control, process control Programmable logic controllers FUNCTIONAL BLOCK DIAGRAM VDD AD5761R/AD5721R DVCC ALERT SDI SCLK SYNC SDO INPUT SHIFT 12/16 REGISTER AND CONTROL LOGIC VREFIN/VREFOUT 2.5V REFERENCE INPUT REG DAC REG REFERENCE BUFFERS 12/16 12-BIT/ 16-BIT DAC RESET VOUT 0V TO 5V 0V TO 10V 0V TO 16V 0V TO 20V ±3V ±5V ±10V −2.5V TO +7.5V DNC DGND VSS AGND LDAC NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 12355-001 CLEAR Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5761R/AD5721R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Hysteresis .................................................................... 27 Applications ....................................................................................... 1 Register Details ............................................................................... 28 General Description ......................................................................... 1 Input Shift Register .................................................................... 28 Functional Block Diagram .............................................................. 1 Control Register ......................................................................... 29 Revision History ............................................................................... 2 Readback Control Register ....................................................... 30 Specifications..................................................................................... 3 Update DAC Register from Input Register ............................. 31 AC Performance Characteristics ................................................ 6 Readback DAC Register ............................................................ 31 Timing Characteristics ................................................................ 7 Write and Update DAC Register .............................................. 31 Timing Diagrams.......................................................................... 7 Readback Input Register............................................................ 32 Absolute Maximum Ratings ............................................................ 9 Disable Daisy-Chain Functionality.......................................... 32 ESD Caution .................................................................................. 9 Software Data Reset ................................................................... 32 Pin Configurations and Function Descriptions ......................... 10 Software Full Reset ..................................................................... 33 Typical Performance Characterstics............................................. 12 No Operation Registers ............................................................. 33 Terminology .................................................................................... 23 Applications Information .............................................................. 34 Theory of Operation ...................................................................... 25 Typical Operating Circuit ......................................................... 34 Digital-to-Analog Converter .................................................... 25 Power Supply Considerations ................................................... 34 Transfer Function ....................................................................... 25 Evaluation Board ........................................................................ 34 DAC Architecture ....................................................................... 25 Outline Dimensions ....................................................................... 35 Serial Interface ............................................................................ 26 Ordering Guide .......................................................................... 35 Hardware Control Pins .............................................................. 26 REVISION HISTORY 5/15—Rev. 0 to Rev. A Added LFCSP Package ....................................................... Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 9 Added Figure 6 and Table 6; Renumbered Sequentially ........... 11 Changes to Figure 21 to Figure 24 ................................................ 14 Changes to Figure 35 ...................................................................... 16 Changes to Figure 37 ...................................................................... 17 Changes to Figure 50 ...................................................................... 19 Changes to Figure 58 to Figure 60 ................................................ 20 Changes to Figure 61 to Figure 66 ................................................ 21 Changes to Figure 69 ...................................................................... 22 Added Figure 71 ............................................................................. 22 Changes to Terminology Section ................................................. 23 Changes to Digital-to-Analog Converter Section and Internal Reference Section ........................................................................... 25 Changes to Asynchronous Clear Function (CLEAR) Section ...... 27 Changes to Table 12 ....................................................................... 29 Changes to Power Supply Considerations Section and Figure 77 .......................................................................................... 34 Added Figure 79 ............................................................................. 35 Updated Outline Dimensions ....................................................... 35 Changes to Ordering Guide .......................................................... 35 11/14—Revision 0: Initial Version Rev. A | Page 2 of 35 Data Sheet AD5761R/AD5721R SPECIFICATIONS VDD 1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 2 STATIC PERFORMANCE Programmable Output Ranges AD5761R Resolution Relative Accuracy, INL A Grade B Grade 4 Differential Nonlinearity, DNL AD5721R Resolution Relative Accuracy, INL B Grade Differential Nonlinearity, DNL Zero-Scale Error Min 0 0 0 0 −2.5 −3 −5 −10 Unit 5 10 16 20 +7.5 +3 +5 +10 V V V V V V V V Test Conditions/Comments External reference 3 and internal reference, outputs unloaded Bits −8 −2 +8 +2 LSB LSB −1 +1 LSB 12 External reference3 and internal reference All ranges except 0 V to 16 V and 0 V to 20 V, VREFIN/VREFOUT = 2.5 V external and internal reference Bits −0.5 −0.5 −6 +0.5 +0.5 +6 LSB LSB mV −10 −6 +10 +6 mV mV −8 −9 −13 +8 +9 +13 ±5 mV mV mV µV/°C ±15 µV/°C −5 −7 Bipolar Zero TC5 Offset Error Max 16 Zero-Scale Temperature Coefficient (TC) 5 Bipolar Zero Error Typ +5 +7 ±2 mV mV µV/°C ±5 µV/°C −6 +6 mV −10 −6 +10 +6 mV mV −8 −9 −13 +8 +9 +13 mV mV mV Rev. A | Page 3 of 35 External reference3 and internal reference All ranges except ±10 V and 0 V to 20 V, external reference3 0 V to 20 V, ±10 V ranges, external reference3 All ranges except ±5 V, ±10 V and 0 V to 20 V, internal reference ±5 V range, internal reference 0 V to 20 V range, internal reference ±10 V range, internal reference Unipolar ranges, external reference3 and internal reference Bipolar ranges, external reference3 and internal reference All bipolar ranges except ±10 V ±10 V output range ±3 V range, external reference3 and internal reference All bipolar ranges except ±3 V range, external reference3 and internal reference All ranges except ±10 V and 0 V to 20 V, external reference3 0 V to 20 V, ±10 V ranges, external reference3 All ranges except ±5 V, ±10 V, and 0 V to 20 V; internal reference ±5 V range, internal reference 0 V to 20 V range, internal reference ±10 V range, internal reference AD5761R/AD5721R Parameter 2 Offset Error TC5 Data Sheet Min Typ ±5 Max ±15 Gain Error Gain Error TC5 TUE REFERENCE INPUT (EXTERNAL)5 Reference Input Voltage (VREF) Input Current Reference Range REFERENCE OUTPUT (INTERNAL)5 Output Voltage Voltage Reference TC Output Impedance Output Voltage Noise Noise Spectral Density Line Regulation Thermal Hysteresis Start-Up Time OUTPUT CHARACTERISTICS5 Output Voltage Range −0.1 −0.15 −2 2 2.5 ±0.5 2.5 2 25 6 10 6 80 3.5 +0.1 +0.15 V µA V ±1% for specified performance +2 3 V ppm/°C kΩ µV p-p nV/√Hz µV/V ppm ms ±3 mV, at ambient temperature 5 −VOUT +VOUT −10 −10.5 +10 +10.5 V V 1 1 nF V 1 2 ppm FSR/°C mA kΩ kΩ mV/mA Ω 0.5 Output Voltage TC Short-Circuit Current Resistive Load ±3 25 Load Regulation DC Output Impedance LOGIC INPUTS5 Input Voltage High, VIH Low, VIL Input Current Leakage Current 0.3 0.5 0.7 × DVCC 0.3 × DVCC −1 −1 −55 +1 +1 5 Test Conditions/Comments Unipolar ranges, external reference3 and internal reference Bipolar ranges, external reference3 and internal reference External reference3 Internal reference External reference3 and internal reference External reference3 Internal reference % FSR % FSR ppm FSR/°C % FSR % FSR ±1.5 Capacitive Load Stability Headroom Pin Capacitance µV/°C +0.1 +0.15 −0.1 −0.15 Unit µV/°C 0.1 Hz to 10 Hz At ambient; f = 10 kHz At ambient First temperature cycle Coming out of power-down mode with a 10 nF capacitor on the VREFIN/VREFOUT pin to improve noise performance; outputs unloaded See Table 7 for the different output voltage ranges available VDD/VSS = ±11 V, ±10 V output range VDD/VSS = ±11 V, ±10 V output range with 5% overrange RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V to 20 V ranges (RLOAD = 2 kΩ) ±10 V range, external reference Short on the VOUT pin All ranges except 0 V to16 V and 0 V to 20 V 0 V to 16 V, 0 V to 20 V ranges Outputs unloaded Outputs unloaded DVCC = 1.7 V to 5.5 V, JEDEC compliant V V µA µA µA pF Rev. A | Page 4 of 35 SDI, SCLK, SYNC LDAC, CLEAR, RESET pins held high LDAC, CLEAR, RESET pins held low Per pin, outputs unloaded Data Sheet Parameter 2 LOGIC OUTPUTS (SDO, ALERT)5 Output Voltage Low, VOL High, VOH High Impedance, SDO Pin Leakage Current Pin Capacitance POWER REQUIREMENTS VDD VSS DVCC IDD ISS DICC Power Dissipation DC Power Supply Rejection Ratio (PSRR)5 AC PSRR5 AD5761R/AD5721R Min Typ Max Unit Test Conditions/Comments 0.4 V V DVCC = 1.7 V to 5.5 V, sinking 200 µA DVCC = 1.7 V to 5.5 V, sourcing 200 µA +1 µA pF 30 0 5.5 6.5 3 1 V V V mA mA µA mW mV/V DVCC − 0.5 −1 5 4.75 −16.5 1.7 5.1 1 0.005 67.1 0.1 0.1 65 mV/V dB 65 dB 80 dB 80 dB Outputs unloaded, external reference Outputs unloaded VIH = DVCC, VIL = DGND ±11 V operation, outputs unloaded, TSSOP package VDD ± 10%, VSS = −15 V VSS ±10%, VDD = +15 V VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, internal reference, CLOAD = 100 nF VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, internal reference, CLOAD = 100 nF VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V, external reference, CLOAD = unloaded VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V, external reference, CLOAD = unloaded For specified performance, headroom requirement is 1 V. Temperature range: −40°C to +125°C, typical at +25°C. 3 External reference means 2 V to 2.85 V with overrange and 2 V to 3 V without overrange. 4 Integral nonlinearity error is specified at ±4 LSB (min/max) for 16 V and 20 V ranges with VREFIN/VREFOUT = 2.5 V external and internal, and for all ranges with VREFIN/VREFOUT = 2 V to 2.85 V with overrange and 2 V to 3 V without overrange. 5 Guaranteed by design and characterization, not production tested. 1 2 Rev. A | Page 5 of 35 AD5761R/AD5721R Data Sheet AC PERFORMANCE CHARACTERISTICS VDD 1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN/VREFOUT = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ for all ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 2 DYNAMIC PERFORMANCE 3 Output Voltage Settling Time Digital-to-Analog Glitch Impulse Glitch Impulse Peak Amplitude Power-On Glitch Digital Feedthrough Output Noise 0.1 Hz to 10 Hz Bandwidth 100 kHz Bandwidth Output Noise Spectral Density, at 10 kHz Total Harmonic Distortion (THD) 4 Signal-to-Noise Ratio (SNR) Peak Harmonic or Spurious Noise (SFDR) Signal-to-Noise-and-Distortion (SINAD) Ratio Min Typ Max Unit Test Conditions/Comments 9 7.5 12.5 8.5 5 8 1 15 10 100 0.6 µs µs µs nV-sec nV-sec mV mV mV p-p nV-sec 20 V step to 1 LSB at 16-bit resolution 10 V step to 1 LSB at 16-bit resolution 512 LSB step to 1 LSB at 16-bit resolution ±10 V range 0 V to 5 V range ±10 V range 0 V to 5 V range 15 45 35 25 15 80 µV p-p µV rms µV rms µV rms µV rms nV/√Hz 0 V to 20 V and 0 V to 16 V ranges, 2.5 V external reference 0 V to 10 V, ±10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference ±5 V range, 2.5 V external reference 0 V to 5 V and ±3 V ranges, 2.5 V external reference ±10 V range, 2.5 V external reference 35 70 110 90 45 −87 92 92 nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz dB dB dB ±3 V range, 2.5 V external reference ±5 V, 0 V to 10 V, and −2.5 V to +7.5 V ranges, 2.5 V external reference 0 V to 20 V range, 2.5 V external reference 0 V to 16 V range, 2.5 V external reference 0 V to 5 V range, 2.5 V external reference 2.5 V external reference, 1 kHz tone At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz 85 dB At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz For specified performance, headroom requirement is 1 V. Temperature range: −40°C to +125°C, typical at +25°C. 3 Guaranteed by design and characterization, not production tested. 4 Digitally generated sine wave at 1 kHz. 1 2 Rev. A | Page 6 of 35 Data Sheet AD5761R/AD5721R TIMING CHARACTERISTICS DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 1 2 Limit at TMIN, TMAX 20 10 10 15 10 20 5 5 10 20 20 9 7.5 20 200 10 40 50 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min µs typ µs typ ns min ns typ ns min ns max ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time SCLK falling edge to SYNC rising edge time Minimum SYNC high time (write mode) Data setup time Data hold time LDAC falling edge to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 2) DAC output settling time, 10 V step to 1 LSB at 16-bit resolution CLEAR pulse width low CLEAR pulse activation time SYNC rising edge to SCLK falling edge SCLK rising edge to SDO valid (CL_SDO 2 = 15 pF) Minimum SYNC high time (readback/daisy-chain mode) Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode. CL_SDO is the capacitive load on the SDO output. TIMING DIAGRAMS t1 SCLK 1 2 24 t3 t6 t2 t5 t4 SYNC t8 t7 SDI DB0 DB23 t9 t11 t10 LDAC t12 VOUT t12 VOUT CLEAR t13 t14 12355-002 VOUT Figure 2. Serial Interface Timing Diagram Rev. A | Page 7 of 35 AD5761R/AD5721R Data Sheet t1 SCLK 24 t3 t17 48 t5 t2 t15 t4 SYNC t7 t8 DB23 SDI DB0 DB23 INPUT WORD FOR DAC N DB0 t16 INPUT WORD FOR DAC N – 1 DB23 SDO UNDEFINED DB0 t10 INPUT WORD FOR DAC N t11 12355-003 LDAC Figure 3. Daisy-Chain Timing Diagram SCLK 1 24 1 24 t17 SYNC DB0 DB23 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO NOP CONDITION DB0 DB23 DB0 DB23 UNDEFINED DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram Rev. A | Page 8 of 35 12355-004 SDI Data Sheet AD5761R/AD5721R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 200 mA do not cause silicon controlled rectifier (SCR) latch-up. Table 4. Parameter VDD to AGND VSS to AGND VDD to VSS DVCC to DGND Digital Inputs to DGND Digital Outputs to DGND VREFIN/VREFOUT to DGND VOUT to AGND AGND to DGND Operating Temperature Range, TA Industrial Storage Temperature Range Junction Temperature, TJ MAX 16-Lead TSSOP Package θJA Thermal Impedance θJC Thermal Impedance 16-Lead LFCSP Package θJA Thermal Impedance θJC Thermal Impedance Power Dissipation Lead Temperature Soldering ESD (Human Body Model) 1 2 Rating −0.3 V to +34 V +0.3 V to −17 V −0.3 V to +34 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to +7 V VSS to VDD −0.3 V to +0.3 V −40°C to +125°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −65°C to +150°C 150°C 113°C/W1 28°C/W 75°C/W1 4.5°C/W2 (TJ MAX − TA)/θJA JEDEC industry standard J-STD-020 4 kV JEDEC 2S2P test board, still air (0 m/sec airflow). Measured to exposed paddle, with infinite heat sink on package top surface. Rev. A | Page 9 of 35 AD5761R/AD5721R Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ALERT 1 CLEAR 2 15 DVCC RESET 3 14 SCLK VREFIN/ VREFOUT 4 AD5761R/ AD5721R 13 SYNC AGND 5 TOP VIEW (Not to Scale) 12 SDI VSS 6 11 LDAC VOUT 7 10 SDO VDD 8 16 DGND DNC NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 12355-006 9 Figure 5. 16-Lead TSSOP Pin Configuration Table 5. 16-Lead TSSOP Pin Function Descriptions Pin No. 1 Mnemonic ALERT 2 CLEAR 3 RESET 4 VREFIN/VREFOUT 5 6 AGND VSS 7 8 VOUT VDD 9 10 DNC SDO 11 LDAC 12 13 SDI SYNC 14 SCLK 15 DVCC 16 DGND Description Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or a hardware reset, for which a write to the control register asserts the pin high. Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor. Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status where the output is clamped to ground and the output buffer is powered down. This pin can be left floating because there is an internal pull-up resistor. Internal Reference Voltage Output and External Reference Voltage Input. For specified performance, VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise. Ground Reference Pin for Analog Circuitry. Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND. Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load. Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be decoupled to AGND. Do Not Connect. Do not connect to this pin. Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during the write to the input register, the DAC output register is not updated, and the DAC output update is held off until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor. Serial Data Input. Data must be valid on the falling edge of SCLK. Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds of up to 50 MHz. Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital interface operates. Digital Ground. Rev. A | Page 10 of 35 13 DVCC 14 DGND 16 CLEAR AD5761R/AD5721R 15 ALERT Data Sheet RESET 1 12 SCLK VREFIN/VREFOUT 2 AD5761R/ AD5721R 11 SYNC AGND 3 TOP VIEW (Not to Scale) 10 SDI 9 LDAC NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE MECHANICALLY CONNECTED TO THE PCB COPPER PLANE FOR OPTIMAL THERMAL PERFORMANCE. THE EXPOSED PAD CAN BE LEFT ELECTRICALLY FLOATING. 12335-106 SDO 8 DNC 7 VDD 6 VOUT 5 VSS 4 Figure 6. 16-Lead LFCSP Pin Configuration Table 6. 16-Lead LFCSP Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 VREFIN/VREFOUT 3 4 AGND VSS 5 6 VOUT VDD 7 8 DNC SDO 9 LDAC 10 11 SDI SYNC 12 SCLK 13 DVCC 14 15 DGND ALERT 16 CLEAR EPAD Description Active Low Reset Input. Asserting this pin returns the AD5761R/AD5721R to their default power-on status where the output is clamped to ground and the output buffer is powered down. This pin can be left floating because there is an internal pull-up resistor. Internal Reference Voltage Output and External Reference Voltage Input. For specified performance, VREFIN/VREFOUT = 2.5 V. Connect a 10 nF capacitor with the internal reference to minimize the noise. Ground Reference Pin for Analog Circuitry. Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin. For unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND. Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load. Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin for unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD must be decoupled to AGND. Do Not Connect. Do not connect to this pin. Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied permanently low, the DAC register is updated when the input register is updated. If LDAC is held high during the write to the input register, the DAC output register is not updated, and the DAC output update is held off until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor. Serial Data Input. Data must be valid on the falling edge of SCLK. Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds of up to 50 MHz. Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the digital interface operates. Digital Ground. Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or when an output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full software reset, or a hardware reset, for which a write to the control register asserts the pin high. Falling Edge Clear Input. Asserting this pin sets the DAC register to zero scale, midscale, or full-scale code (user selectable) and updates the DAC output. This pin can be left floating because there is an internal pull-up resistor. Exposed Pad. The exposed pad must be mechanically connected to the PCB copper plane for optimal thermal performance. The exposed pad can be left electrically floating. Rev. A | Page 11 of 35 AD5761R/AD5721R Data Sheet TYPICAL PERFORMANCE CHARACTERSTICS 2.0 1.5 0.5 VDD = +21V VSS = –11V +5V SPAN +10V SPAN +16V SPAN +20V SPAN ±3V SPAN ±5V SPAN ±10V SPAN –2.5V TO +7.5V SPAN 0.4 0.3 VDD = +21V VSS = –11V INL ERROR (LSB) INL ERROR (LSB) 1.0 0.5 0 –0.5 0.2 0.1 0 –0.1 –0.2 –1.0 –0.3 –1.5 10000 20000 30000 40000 50000 60000 DAC CODE –0.5 +5V SPAN +10V SPAN +16V SPAN +20V SPAN 0.4 1.0 VDD = +21V VSS = –11V 0.6 0.1 0 –0.1 –0.2 2500 3000 3500 4000 DAC CODE 4000 VDD = +21V VSS = –11V –0.4 –1.0 12355-008 2000 3500 –0.2 –0.8 1500 3000 0 –0.6 1000 2500 0.2 –0.4 500 2000 0.4 –0.3 0 1500 +5V SPAN +10V SPAN +16V SPAN +20V SPAN 0.8 0.2 –0.5 1000 Figure 10. AD5721R INL Error vs. DAC Code, Bipolar Output DNL ERROR (LSB) INL ERROR (LSB) 0.3 500 DAC CODE Figure 7. AD5761R INL Error vs. DAC Code, Unipolar Output 0.5 0 0 10000 20000 30000 40000 50000 60000 DAC CODE Figure 8. AD5721R INL Error vs. DAC Code, Unipolar Output Figure 11. AD5761R DNL Error vs. DAC Code, Unipolar Output 2.0 0.5 VDD = +21V VSS = –11V ±3V SPAN ±5V SPAN ±10V SPAN –2.5V TO +7.5V SPAN 1.5 +5V SPAN +10V SPAN +16V SPAN +20V SPAN 0.4 0.3 12355-011 0 12355-007 –2.0 12355-010 –0.4 VDD = +21V VSS = –11V DNL ERROR (LSB) 0.5 0 –0.5 0.2 0.1 0 –0.1 –0.2 –1.0 –0.3 –1.5 0 10000 20000 30000 40000 50000 60000 DAC CODE Figure 9. AD5761R INL Error vs. DAC Code, Bipolar Output –0.5 0 500 1000 1500 2000 2500 3000 3500 4000 DAC CODE Figure 12. AD5721R DNL Error vs. DAC Code, Unipolar Output Rev. A | Page 12 of 35 12355-012 –2.0 –0.4 12355-009 INL ERROR (LSB) 1.0 Data Sheet 0.8 0.6 0.8 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 VDD = +21V VSS = –11V 0 10000 20000 30000 40000 50000 60000 DAC CODE –1.0 –40 0.4 2.0 1.5 1.0 0.2 INL ERROR (LSB) DNL ERROR (LSB) 0.3 –20 0 25 +5V U2 EXT MIN DNL ±10V U2 EXT MIN DNL +5V U1 INT MIN DNL ±10V U1 INT MIN DNL 50 85 105 125 Figure 16. DNL Error vs. Temperature VDD = +21V VSS = –11V ±3V SPAN ±5V SPAN ±10V SPAN –2.5V TO +7.5V SPAN +5V U2 EXT MAX DNL ±10V U2 EXT MAX DNL +5V U1 INT MAX DNL ±10V U1 INT MAX DNL TEMPERATURE (°C) Figure 13. AD5761R DNL Error vs. DAC Code, Bipolar Output 0.5 VDD = +21V VSS = –11V 0.6 12355-013 DNL ERROR (LSB) 1.0 ±3V SPAN ±5V SPAN ±10V SPAN –2.5V TO +7.5V SPAN 12355-016 1.0 AD5761R/AD5721R 0.1 0 –0.1 –0.2 +5V U2 EXT MAX INL +5V U1 INT MAX INL ±10V U2 EXT MAX INL ±10V U1 NT MAX INL +5V U2 EXT MIN INL +5V U1 INT MIN INL ±10V U2 EXT MIN INL ±10V U1 INT MIN INL VDD = +21V VSS = –11V TA = 25°C NO LOAD 0.5 0 –0.5 –1.0 –0.3 –1.5 –0.4 –2.0 500 1000 1500 2000 2500 3000 3500 4000 DAC CODE +5V SPAN VDD/VSS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V VDD/VSS = +10V/–1V VDD/VSS = +13.5V/–13.5V VDD/VSS = +7.5V/–1V VDD/VSS = +12.5V/–12.5V VDD/VSS = +16.5V/–1V VDD/VSS = +16.5V/–16.5V VDD/VSS = +12.5V/–1V VDD/VSS = +14.5V/–14.5V SUPPLY VOLTAGE (V) Figure 17. INL Error vs. Supply Voltage Figure 14. AD5721R DNL Error vs. DAC Code, Bipolar Output 1.5 +5V U1 INT MAX INL +5V U2 EXT MAX INL ±10V U1 INT MAX INL ±10V U2 EXT MAX INL 1.0 +5V U1 INT MIN INL +5V U2 EXT MIN INL ±10V U1 INT MIN INL ±10V U2 EXT MIN INL 0.8 DNL ERROR (LSB) 0.6 0.5 0 –0.5 0.4 +5V U2 EXT MAX DNL +5V U1 INT MAX DNL ±10V U2 EXT MAX DNL ±10V U1 NT MAX DNL +5V U2 EXT MIN DNL +5V U1 INT MIN DNL ±10V U2 EXT MIN DNL ±10V U1 INT MIN DNL VDD = +21V VSS = –11V TA = 25°C NO LOAD 0.2 0 –0.2 –0.4 –0.6 –1.0 –0.8 VDD = +21V VSS = –11V –20 –1.0 0 25 50 85 TEMPERATURE (°C) 105 125 +5V SPAN VDD/V SS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V VDD/V SS = +10V/–1V VDD/V SS = +13.5V/–13.5V VDD/V SS = +7.5V/–1V VDD/VSS = +12.5V/–12.5V VDD/V SS = +12.5V/–1V VDD/V SS = +14.5V/–14.5V SUPPLY VOLTAGE (V) Figure 18. DNL Error vs. Supply Voltage Figure 15. INL Error vs. Temperature Rev. A | Page 13 of 35 VDD/V SS = +16.5V/–1V VDD/VSS = +16.5V/–16.5V 12355-018 –1.5 –40 12355-015 INL ERROR (LSB) 1.0 12355-017 0 12355-014 –0.5 AD5761R/AD5721R 3 MAX INL, +5V SPAN MAX INL, ±10V SPAN MIN INL, +5V SPAN MIN INL, ±10V SPAN 0.006 VDD = +21V VSS = –11V VDD = +21V VSS = –11V 1 0 –1 –2 0.002 0 –0.002 2.75 3.00 –0.006 –40 0.8 0.010 FULL-SCALE ERROR (V) 0.2 0 –0.2 –0.4 0.002 0 –0.002 –0.004 –0.006 –0.8 –0.008 2.50 2.75 3.00 REFERENCE VOLTAGE (V) –0.010 –40 0.008 +5V U1 EXT +5V U2 INT ±10V U1 EXT ±10V U2 INT 0.006 0 25 50 85 105 125 Figure 23. Full-Scale Error vs. Temperature 0.15 VDD = +21V VSS = –11V –20 TEMPERATURE (°C) Figure 20. DNL Error vs. Reference Voltage 0.010 125 0.004 –0.6 2.25 105 85 +5V U1 EXT +5V U2 INT ±10V U1 EXT ±10V U2 INT 0.006 0.4 –1.0 2.00 VDD = +21V VSS = –11V 0.008 12355-020 VDD = +21V VSS = –11V +5V U1 EXT +5V U2 INT ±10V U1 EXT ±10V U2 INT 0.10 GAIN ERROR (%FSR) 0.004 0.002 0 –0.002 –0.004 –0.006 0.05 0 –0.05 –0.10 –0.010 –40 –20 0 25 50 85 105 TEMPERATURE (°C) 125 12355-021 –0.008 Figure 21. Zero-Scale Error vs. Temperature –0.15 –40 –20 0 25 50 85 TEMPERATURE (°C) Figure 24. Gain Error vs. Temperature Rev. A | Page 14 of 35 105 125 12355-024 DNL ERROR (LSB) 0.6 50 Figure 22. Midscale Error vs. Temperature MAX DNL, ±10V SPAN MAX DNL, +5V SPAN MIN DNL, ±10V SPAN MIN DNL, +5V SPAN VDD = +21V VSS = –11V 25 TEMPERATURE (°C) Figure 19. INL Error vs. Reference Voltage 1.0 0 –20 12355-023 2.50 REFERENCE VOLTAGE (V) 12355-019 2.25 12355-022 –0.004 –3 2.00 ZERO-SCALE ERROR (V) +5V U1 EXT +5V U2 INT ±10V U1 EXT ±10V U2 INT 0.004 MIDSCALE ERROR (V) 2 INL ERROR (LSB) Data Sheet Data Sheet AD5761R/AD5721R 0.0010 0.030 TA = 25°C VREF = 2.5V 0 0.020 +5V U2 EXT +5V U1 INT ±10V U2 EXT ±10V U1 INT –0.0005 –0.0010 0.015 GAIN ERROR (%FSR) ZERO-SCALE ERROR (V) TA = 25°C VREF = 2.5V 0.025 –0.0015 –0.0020 –0.0025 –0.0030 0.010 0.005 –0.005 –0.010 –0.0035 –0.015 –0.0040 –0.020 –0.0045 –0.025 –0.0050 +5V U2 EXT +5V U1 INT ±10V U2 EXT ±10V U1 INT 0 –0.030 VDD/VSS = +10V/–1V VDD/VSS = +13.5V/–13.5V VDD/VSS = +7.5V/–1V VDD/V SS = +12.5V/–12.5V VDD/V SS = +16.5V/–1V VDD/VSS = +16.5V/–16.5V VDD/V SS = +12.5V/–1V VDD/VSS = +14.5V/–14.5V +5V SPAN VDD/VSS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V SUPPLY VOLTAGE (V) VDD/VSS = +16.5V/–1V VDD/V SS = +16.5V/–16.5V VDD/VSS = +12.5V/–1V VDD/VSS = +14.5V/–14.5V SUPPLY VOLTAGE (V) Figure 25. Zero-Scale Error vs. Supply Voltage Figure 28. Gain Error vs. Supply Voltage 0.005 0.0005 0 VDD/V SS = +10V/–1V VDD/VSS = +13.5V/–13.5V VDD/VSS = +7.5V/–1V VDD/VSS = +12.5V/–12.5V 12355-025 +5V SPAN VDD/VSS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V 12355-028 0.0005 TA = 25°C VREF = 2.5V VDD = +21V VSS = –11V TA = 25⁰C +5V SPAN ±10V SPAN ZERO-SCALE ERROR (V) MIDSCALE ERROR (V) 0.003 –0.0005 –0.0010 +5V U2 EXT +5V U1 INT ±10V U2 EXT ±10V U1 INT –0.0015 –0.0020 0.001 –0.001 –0.003 –0.005 2.0 –0.0030 VDD/VSS = +10V/–1V VDD/VSS = +13.5V/–13.5V VDD/VSS = +7.5V/–1V VDD/VSS = +12.5V/–12.5V VDD/VSS = +16.5V/–1V VDD/VSS = +16.5V/–16.5V VDD/VSS = +12.5V/–1V VDD/V SS = +14.5V/–14.5V SUPPLY VOLTAGE (V) Figure 26. Midscale Error vs. Supply Voltage 3.0 Figure 29. Zero-Scale Error vs. Reference Voltage 0.0010 0.0010 TA = 25°C VREF = 2.5V 0.0008 0.0005 +5V SPAN ±10V SPAN VDD = +21V VSS = –11V TA = 25°C MIDSCALE ERROR (V) 0.0006 0 –0.0005 –0.0010 +5V SPAN VDD/VSS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V VDD/VSS = +10V/–1V VDD/VSS = +13.5V/–13.5V VDD/V SS = +7.5V/–1V VDD/VSS = +12.5V/–12.5V SUPPLY VOLTAGE (V) –0.0002 –0.0004 –0.0008 –0.0010 2.0 VDD/V SS = +16.5V/–1V VDD/VSS = +16.5V/–16.5V VDD/VSS = +12.5V/–1V VDD/V SS = +14.5V/–14.5V 0 2.5 REFERENCE VOLTAGE (V) Figure 27. Full-Scale Error vs. Supply Voltage Figure 30. Midscale Error vs. Reference Voltage Rev. A | Page 15 of 35 3.0 12355-030 –0.0020 0.0002 –0.0006 +5V U2 EXT +5V U1 INT ±10V U2 EXT ±10V U1 INT –0.0015 0.0004 12355-027 FULL-SCALEERROR (V) 2.5 REFERENCE VOLTAGE (V) 12355-026 +5V SPAN VDD/VSS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V 12355-029 –0.0025 AD5761R/AD5721R Data Sheet 0.05 0.005 +5V SPAN ±10V SPAN 0.03 TUE (%FSR) 0.003 0.001 –0.001 0.01 –0.01 –0.03 –0.003 2.5 3.0 REFERENCE VOLTAGE (V) 12355-031 –0.05 –0.005 2.0 ± 5V SPAN_INT –2.5V TO +7.5V SPAN_INT ±5V SPAN_EXT –2.5V TO +7.5V SPAN_EXT 0 +5V SPAN ±10V SPAN 30000 40000 50000 60000 Figure 34. TUE vs. Code, Bipolar Output 0.06 VDD = +21V VSS = –11V TA = 25°C +5V_U1_EXTREF +5V_U2_INTREF +5V_U3_INTREF ±10V_U1_EXTREF ±10V_U2_INTREF ±10V_U3_INTREF 0.05 0.03 VDD = +21V VSS = –11V 0.04 0.01 TUE (%FSR) GAIN ERROR (%FSR) 20000 CODE Figure 31. Full-Scale Error vs. Reference Voltage 0.05 10000 ±10V SPAN_INT ±3V SPAN_INT ±10V SPAN_EXT ±3V SPAN_EXT 12355-034 FULL-SCALE ERROR (V) TA = 25°C VDD = +21V VSS = –11V TA = 25°C –0.01 0.03 0.02 –0.03 2.5 3.0 REFERENCE VOLTAGE (V) 0 –40 12355-032 –0.05 2.0 +5V SPAN_INT +16V SPAN_INT +5V SPAN_EXT +16V SPAN_EXT 0.03 +10V SPAN_INT +20V SPAN_INT +10V SPAN_EXT +20V SPAN_EXT 0 20 40 60 80 100 120 TEMPERATURE (⁰C) Figure 35. TUE vs. Temperature Figure 32. Gain Error vs. Reference Voltage 0.05 –20 12355-035 0.01 0.030 TA = 25°C 0.028 0.026 TA = 25°C VREF = 2.5V 0.024 0.022 TUE (%FSR) –0.01 0.018 0.016 0.014 0.012 0.01 0.008 0.006 +5V U2 EXT +5V U1 INT ±10V U2 EXT ±10V U1 INT 0.004 0.002 –0.05 0 10000 20000 30000 40000 50000 CODE 60000 0 +5V SPAN VDD/VSS = +6V/–1V ±10V SPAN VDD/VSS = +11V/–11V VDD/VSS = +10V/–1V VDD/VSS = +13.5V/–13.5V VDD/VSS = +7.5V/–1V VDD/VSS = +12.5V/–12.5V SUPPLY VOLTAGE (V) Figure 36. TUE vs. Supply Voltage Figure 33. TUE vs. Code, Unipolar Output Rev. A | Page 16 of 35 VDD/VSS = +16.5V/–1V VDD/VSS = +16.5V/–16.5V VDD/VSS = +12.5V/–1V VDD/VSS = +14.5V/–14.5V 12355-036 –0.03 12355-033 TUE (%FSR) 0.020 0.01 Data Sheet AD5761R/AD5721R 0.00001 VOUT 500mV 12355-037 SYNC 5V 5V 200µs/DIV 0.000001 0.0000001 0.00000001 0.000000001 AVDD = 21V AVSS = –11V DVCC = 5V LOAD = 2kΩ||200pF CAP ON VREF = 10nF 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 40. Reference Output Noise Spectral Density vs. Frequency Figure 37. Reference Output Voltage Turn On Transient 2.5014 10 VDD = +21V 8 VSS = –11V TA = 25⁰C 2.5012 2.5010 4 VREFOUT (V) NOISE (µV PEAK) 6 2 0 –2 –4 2.5008 2.5006 2.5004 2.5002 –6 2.5000 –8 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 TIME (Seconds) 8 Figure 41. Reference Output Voltage (VREFOUT) vs. Supply Voltage 3.0 VDD = +21V VSS = –11V TA = 25⁰C INTERNAL REFERENCE (V) 6 4 2 0 –2 –4 VDD = +21V VSS = –11V TA = 25°C 2.5 2.0 BIPOLAR 10V UNIPOLAR 10V BIPOLAR 5V UNIPOLAR 5V –2.5V TO 7.5V BIPOLAR 3V UNIPOLAR 16V UNIPOLAR 20V –6 –8 –10 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 TIME (Second) 12355-039 NOISE (µV PEAK) –13.50 –13.75 –14.00 –14.25 –14.50 –14.75 –15.00 –15.25 –15.50 –15.75 –16.00 –16.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 16.25 SUPPLY VOLTAGE (V) Figure 38. Internal Reference Noise (100 kHz Bandwidth) 10 VSS VDD Figure 39. Internal Reference Noise (0.1 Hz to 10 Hz Bandwidth) 1.5 –10 –8 –6 –4 –2 0 2 4 6 LOAD CURRENT (µA) Figure 42. Internal Reference vs. Load Current Rev. A | Page 17 of 35 8 10 12355-040 –1.2 12355-038 –1.6 12355-139 2.4998 –10 –2.0 12355-138 REFERENCE OUTPUT NOISE SPECTRAL DENSITY (V/√Hz) VREF AD5761R/AD5721R Data Sheet 15000 2.50175 10000 VREFOUT (V) 2.50150 2.50125 2.50100 2.50075 2.50050 ±10V +10V ±5V +5V –2.5V TO +7.5V ±3V +16V +20V 5000 0 –5000 –10000 –15000 2.50000 –40 –20 0 25 55 85 105 125 TEMPERATURE (°C) 12355-041 2.50025 –20000 –30 –20 –10 0 10 20 30 SOURCE/SINK CURRENT (mA) Figure 43. Reference Output Voltage vs. Temperature Figure 46. Source and Sink Capability of Output Amplifier with Negative Full Scale Loaded 70 0.0010 60 0.0008 SUPPLY CURRENT (A) 50 40 30 20 IDVCC 3V IDVCC 5V VDD = +21V VSS = –11V TA = 25⁰C LOAD = 2kΩ || 200pF INTERNAL REFERENCE 0.0009 NUMBER OF UNITS VDD = +21V VSS = –11V TA = 25°C 12355-044 OUTPUT VOLTAGE DELTA (µV) 2.50200 0.0007 0.0006 0.0005 0.0004 0.0003 0.0002 10 0 TEMPERATURE DRIFT (ppm/°C) 15000 6 ±10V +10V ±5V +5V –2.5V TO +7.5V ±3V +16V +20V 4 3 4 5 VDD = +21V VSS = –11V TA = 25°C LOAD = 2kΩ||200pF 2 VOUT (V) 20000 2 Figure 47. Supply Current vs. Logic Input Voltage 10000 5000 0 0 –2 –5000 –20 –10 0 10 20 30 40 SOURCE/SINK CURRENT (mA) Figure 45. Source and Sink Capability of Output Amplifier with Positive Full Scale Loaded –6 –8.0 –6.0 –4.0 –2.0 SYNC ±5V, ZERO SCALE TO FULL SCALE 0 2.0 4.0 TIME (µs) 6.0 8.0 10.0 12.0 14.0 12355-046 –15000 –30 –4 VDD = +21V VSS = –11V TA = 25°C –10000 12355-043 OUTPUT VOLTAGE DELTA (µV) 25000 1 LOGIC INPUT VOLTAGE (V) Figure 44. Reference Output TC 30000 0 12355-042 2.856 2.634 2.412 2.189 1.967 1.745 1.523 1.301 1.078 0.856 0.634 0.412 0 12355-045 0.0001 Figure 48. Full-Scale Settling Time (Rising Voltage Step), ±5 V Range Rev. A | Page 18 of 35 Data Sheet AD5761R/AD5721R 6 0.10 SYNC 500-CODE STEP, ±5V SPAN 0.09 4 0.08 0.07 0.06 VDD =+21V VSS = –11V TA = 25°C LOAD = 2kΩ||200pF 0 VOUT (V) VOUT (V) 2 0.05 0.04 0.03 –2 0.02 2.0 4.0 6.0 8.0 10.0 12.0 14.0 TIME (µs) 8 6 VOUT (V) 0 –2 –4 –6 –8 –10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME (µs) 12355-048 SYNC ±10V, ZERO SCALE TO FULL SCALE –3 –2 –1 0 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.12 0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 –0.01 –2 10 8 6 6 4 4 2 2 VOUT (V) VOUT (V) 12 8 0 –2 –4 SYNC 500-CODE STEP, ±10V SPAN VDD = +21V VSS = –11V TA = 25°C LOAD = 2kΩ||200pF –1 0 1 2 3 4 5 0nF 1nF 5nF 7nF 10nF 0 –2 –6 VDD = +21V VSS = –11V TA = 25°C LOAD = 2kΩ||200pF –12 –3.0 –1.0 1.0 3.0 VDD =+21V VSS = –11V TA = 25°C LOAD = 2kΩ –8 –10 5.0 7.0 TIME (µs) 9.0 11.0 13.0 15.0 –12 12355-049 –10 5 –4 –6 –8 4 Figure 53. 500-Code Step Settling Time, ±10 V Range SYNC ±10V, FULLSCALE TO ZERO SCALE 10 3 TIME (µs) Figure 50. Full-Scale Settling Time (Rising Voltage Step), ±10 V Range 12 2 –5 0 5 10 TIME (µs) Figure 51. Full-Scale Settling Time (Falling Voltage Step), ±10 V Range 15 20 12355-052 VOUT (V) 4 2 1 Figure 52. 500-Code Step Settling Time, ±5 V Range VDD = +21V VSS = –11V TA = 25°C LOAD = 2kΩ||200pF 10 0 TIME (µs) Figure 49. Full-Scale Settling Time (Falling Voltage Step), ±5 V Range 12 –1 12355-051 0 12355-047 –6 –8.0 –6.0 –4.0 –2.0 –0.01 –2 12355-050 0 SYNC ±5V, FULL SCALE TO ZERO SCALE –12 VDD = +21V VSS = –11V TA = 25°C LOAD = 2kΩ||200pF 0.01 –4 Figure 54. Full-Scale Settling Time at Various Capacitive Loads, ±10 V Range Rev. A | Page 19 of 35 AD5761R/AD5721R 6.0 0nF 1nF 5nF 7nF 10nF 5.5 5.0 4.5 VOUT (V) Data Sheet 10V VDD 4.0 10V 3.5 5V VSS VREFIN/VREFOUT 3.0 2.5 VOUT 20mV 2.0 VDD = +21V VSS = –11V TA = 25⁰C LOAD = 2kΩ 0.5 0 –3 –2 –1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME (µs) 2 12355-053 1.0 12355-156 1.5 20ms/DIV Figure 55. Full-Scale Settling Time at Various Capacitive Loads, 0 V to 5 V Range Figure 58. Power-Up Glitch 0.005 5V 0.004 SCLK 0.003 5V 0.002 0.001 5V 0 VOUT (V) SYNC SDI –0.001 –0.002 –0.003 –0.004 –0.005 1V –0.006 –0.007 VDD = 21V VSS = –11V LOAD = 2kΩ||200pF TA = 25°C –0.010 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TIME (µs) VOUT 200µs/DIV Figure 59. Software Full Reset Glitch from Full Scale with Output Loaded, 0 V to 5 V Range 0.004 5V 0.002 5V 0 5V SCLK SYNC SDI –0.002 –0.004 500mV –0.006 VDD = 21V VSS = –11V LOAD = 2kΩ||200pF TA = 25°C –0.010 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TIME (µs) Figure 57. Digital-to-Analog Glitch Energy, ±10 V Range VOUT 200µs/DIV 12355-058 –0.008 12355-055 VOUT (V) Figure 56. Digital-to-Analog Glitch Energy, 5 V Range 12355-057 –0.009 12355-054 –0.008 Figure 60. Software Full Reset Glitch from Midscale with Output Loaded, 5 V Range Rev. A | Page 20 of 35 Data Sheet AD5761R/AD5721R 5V 5V SCLK 5V SCLK 5V SYNC 5V SDI 5V VOUT 2V SYNC SDI 200mV 200µs/DIV 200µs/DIV Figure 61. Software Full Reset Glitch from Zero Scale with Output Loaded, 0 V to 5 V Range 5V 5V Figure 64. Software Full Reset Glitch from Zero Scale with Output Loaded, ±10 V Range SCLK 5V SCLK 5V SYNC 5V 12355-162 12355-059 VOUT SYNC 5V SDI SDI VOUT 1V 2V 200µs/DIV 200µs/DIV Figure 62. Software Full Reset Glitch from Full Scale with Output Loaded, ±10 V Range Figure 65. Output Range Change Glitch, 0 V to 5 V Range 5V 5V SCLK 5V SYNC 5V SDI 5V 5V 12355-263 12355-060 VOUT SCLK SYNC SDI VOUT 200mV 500mV 200µs/DIV Figure 63. Software Full Reset Glitch from Midscale with Output Loaded, ±10 V Range Rev. A | Page 21 of 35 Figure 66. Output Range Change Glitch, ±10 V Range 12355-164 200µs/DIV 12355-161 VOUT AD5761R/AD5721R 0.0015 NOISE INT REF NOISE EXT REF NOISE (µVp-p) 6 4 2 0 0.0010 0.0005 0 TA = 25°C VDD = 21V VSS = –11V DVCC = 5V 2.5V EXT REF LOAD = 2kΩ||200pF –0.0005 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (Seconds) –0.0010 12355-265 –4 –2.0 24.1 24.1 24.2 24.3 24.4 24.5 24.5 24.6 24.7 24.8 24.9 24.9 25.0 25.1 25.2 25.3 25.3 25.4 25.5 25.6 25.7 25.7 25.8 25.9 –2 TIME (µs) Figure 70. Digital Feedthrough Figure 67. Peak-to-Peak Noise (Voltage Output Noise), 0.1 Hz to 10 Hz Bandwidth 30 12355-168 8 VDD = +21V VSS = –11V VREFIN = 2.5V TA = 25⁰C DIGITAL FEEDTHROUGH (V p-p) 10 Data Sheet 0 NOISE EXT REF NOISE INT REF –20 20 THD (dBV) NOISE (µV RMS) –40 10 0 –10 –60 –80 –100 –120 VDD = +21V VSS = –11V VREFIN = 2.5V TA = 25°C –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (Seconds) Figure 68. Peak-to-Peak Noise (Voltage Output Noise), 100 kHz Bandwidth 1600 VDD = +21V VSS = –11V TA = 25°C 1400 NSD (nV/√Hz) 1200 1000 DAC OUTPUT NSD (nV/√Hz), INTREF, ZS DAC OUTPUT NSD (nV/√Hz), INTREF, MS DAC OUTPUT NSD (nV/√Hz), INTREF, FS 800 600 400 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 12355-163 200 Figure 69. DAC Output Noise Spectral Density (NSD) vs. Frequency, ±10 V Range Rev. A | Page 22 of 35 –160 0 2 4 6 8 10 12 14 16 FREQUENCY (kHz) Figure 71. Total Harmonic Distortion 18 20 12355-071 –30 –2.0 –140 12355-266 –20 Data Sheet AD5761R/AD5721R TERMINOLOGY Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature is shown in Figure 24. Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. DAC code plot is shown in Figure 7. Gain Error Temperature Coefficient (TC) Gain error TC is a measure of the change in gain error with changes in temperature. It is expressed in ppm FSR/°C. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. The AD5761R/AD5721R are guaranteed monotonic. A typical DNL error vs. code plot is shown in Figure 11. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5761R/AD5721R are monotonic over their full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding) for the AD5761R/AD5721R. DC Power Supply Rejection Ratio (DC PSRR) DC power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the DAC. It is measured for a given dc change in power supply voltage and is expressed in mV/V. AC Power Supply Rejection Ratio (AC PSRR) AC power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the DAC. It is measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Full-scale settling time is shown in Figure 48 to Figure 51. Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in µV/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (see Figure 56 and Figure 57). Zero-Scale Error Zero-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the DAC register. Ideally, the output voltage is negative full scale. A plot of zero-scale error vs. temperature is shown in Figure 21. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition. Zero-Scale Error Temperature Coefficient (TC) Zero-scale error TC is a measure of the change in zero-scale error with a change in temperature. It is expressed in µV/°C. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset Error Temperature Coefficient (TC) Offset error TC is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Noise Spectral Density (NSD) Noise spectral density is a measurement of the internally generated random noise characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to full scale and measuring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density is shown in Figure 69. Rev. A | Page 23 of 35 AD5761R/AD5721R Data Sheet Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C as follows: V − VREF _ MIN 6 TC = REF _ MAX × 10 VREF _ NOM × Temp Range where: VREF_MAX is the maximum reference output measured over the total temperature range. VREF_MIN is the minimum reference output measured over the total temperature range. VREF_NOM is the nominal reference output voltage, 2.5 V. Temp Range is the specified temperature range, −40°C to +125°C. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD5761R/AD5721R, it is defined as THD (dB) = 20 × log V22 + V32 + V42 + V52 + V62 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Rev. A | Page 24 of 35 Data Sheet AD5761R/AD5721R THEORY OF OPERATION V REFIN DIGITAL-TO-ANALOG CONVERTER The AD5761R/AD5721R are single channel, 16-/12-bit voltage output DACs. The AD5761R/AD5721R output ranges are software selectable and can be configured as follows: Data is written to the AD5761R/AD5721R in a 24-bit word format via a 4-wire, serial peripheral interface (SPI) compatible, digital interface. The devices also offer an SDO pin to facilitate daisy-chaining and readback. TRANSFER FUNCTION The internal reference is on by default. The input coding to the DAC can be straight binary or twos complement (bipolar ranges case only). Therefore, the transfer function is given by D VOUT VREF m c 65 , 536 AGND OUTPUT RANGE CONTROL Figure 72. DAC Architecture R-2R DAC The architecture of the AD5761R consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 73. The 6 MSBs of the 16-bit data-word are decoded to drive 63 switches, E0 to E62, while the remaining 10 bits of the dataword drive the S0 to S9 switches of a 10-bit voltage mode R-2R ladder network. R 2R R R VOUT 2R 2R ... 2R 2R 2R ... 2R S0 S1 ... S9 E62 E61 ... E0 VREF AGND Table 7. m and c Values for Various Output Ranges m 8 4 2.4 4 8 6.4 4 2 CONFIGURABLE OUTPUT AMPLIFIER AGND The code loaded into the DAC register determines which arms of the ladder are switched between VREF and ground (AGND). The output voltage is taken from the end of the ladder and amplified afterwards to provide the selected output voltage. where: VREF is 2.5 V. D is the decimal equivalent of the code loaded to the DAC register as follows: 0 to 4095 for the 12-bit device. 0 to 65,535 for the 16-bit device. The values for m and c are as shown in Table 7. Range ±10 V ±5 V ±3 V −2.5 V to +7.5 V 0 V to 20 V 0 V to 16 V 0 V to 10 V 0 V to 5 V VOUT 12355-061 R- 2R DAC REGISTER Unipolar output voltage: 0 V to 5 V, 0 V to 10 V, 0 V to 16 V, 0 V to 20 V Bipolar output voltage: −2.5 V to +7.5 V, ±3 V, ±5 V, ±10 V 10-BIT R-2R LADDER c 4 2 1.2 1 0 0 0 0 6 MSBs DECODED INTO 63 EQUAL SEGMENTS 12355-062 VREFIN/ VREFOUT Figure 73. DAC Ladder Structure Internal Reference The AD5761R/AD5721R feature an on-chip reference. The on-chip reference is on at power-up, and this reference can be turned off by setting the software-programmable bit, DB5, in the control register. Table 12 shows how the state of the bit corresponds to the mode of operation. DAC ARCHITECTURE The DAC architecture consists of an R-2R DAC followed by an output buffer amplifier. Figure 72 shows a block diagram of the DAC architecture. Note that the reference input is buffered prior to being applied to the DAC. The AD5761R/AD5721R offer a 2.5 V, 5 ppm/°C maximum internal reference on chip. The output voltage range obtained from the configurable output amplifier is selected by writing to the 3 LSBs (RA[2:0]) in the control register. The internal reference is available at the VRFEFIN/VREFOUT pin. A buffer is required if the reference output is used to drive external loads. Place a capacitor in the range of 1 nF to 100 nF between the reference output and DGND to improve the noise performance. Reference Buffer The AD5761R/AD5721R can operate with either an external or internal reference. The reference input has an input range of 2 V to 3 V with 2.5 V for specified performance. This input voltage is then buffered before it is applied to the DAC core. Rev. A | Page 25 of 35 AD5761R/AD5721R Data Sheet DAC Output Amplifier Daisy-Chain Operation The output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 2 kΩ in parallel with 1 nF to AGND. The source and sink capabilities of the output amplifier are shown in Figure 45. For systems that contain several devices, use the SDO pin to daisy chain several devices together. Daisy-chain mode is useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. The AD5761R/AD5721R 4-wire digital interface (SYNC, SCLK, SDI, and SDO) is SPI compatible. The write sequence begins after bringing the SYNC line low, and maintaining this line low until the complete data-word is loaded from the SDI pin. Data is loaded in at the SCLK falling edge transition (see Figure 2). When SYNC is brought high again, the serial data-word is decoded according to the instructions in Table 10. The AD5761R/AD5721R contain an SDO pin to allow the user to daisy-chain multiple devices together or to read back the contents of the registers. Standalone Operation The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only when SYNC is held low for the correct number of clock cycles. By connecting the SDO of the first device to the SDI input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5761R/AD5721R devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high, which latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. CONTROLLER DATA OUT In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. AD5761R/ AD5721R* SDI SERIAL CLOCK SCLK CONTROL OUT SYNC DATA IN SDO SDI AD5761R/ AD5721R* SCLK SYNC SDO The input shift register is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. When the write cycle is complete, the output can be updated by taking LDAC low while SYNC is high. SCLK Readback Operation SYNC The contents of the input, DAC, and control registers can be read back via the SDO pin. Figure 4 shows how the registers are decoded. After a register has been addressed for a read, the next 24 clock cycles clock the data out on the SDO pin. The clocks must be applied while SYNC is low. When SYNC is returned high, the SDO pin is placed in tristate. For a read of a single register, the no operation (NOP) function clocks out the data. Alternatively, if more than one register is to be read, the data of the first register to be addressed clocks out at the same time that the second register to be read is being addressed. The SDO pin must be enabled to complete a readback operation. The SDO pin is enabled by default. SDI AD5761R/ AD5721R* SDO *ADDITIONAL PINS OMITTED FOR CLARITY. 12355-063 SERIAL INTERFACE Figure 74. Daisy-Chain Block Diagram HARDWARE CONTROL PINS Load DAC Function (LDAC) After data transfers into the input register of the DAC, there are two ways to update the DAC register and DAC output. Depending on the status of both SYNC and LDAC, one of two update modes is selected: synchronous DAC update or asynchronous DAC update. Rev. A | Page 26 of 35 Data Sheet AD5761R/AD5721R Synchronous DAC Update In synchronous DAC update mode, LDAC is held low while data is being clocked into the input shift register. The DAC output is updated on the rising edge of SYNC. Asynchronous DAC Update In asynchronous DAC update mode, LDAC is held high while data is being clocked into the input shift register. The DAC output is asynchronously updated by taking LDAC low after SYNC is taken high. The update then occurs on the falling edge of LDAC. In the event of the die temperature exceeding approximately 150°C, the ALERT pin is low and the value of the ETS bit determines the state of the digital supply of the device, whether the internal digital supply is powered on or powered down. If the ETS bit is set to 0, the internal digital supply is powered on when the internal die temperature exceeds approximately 150°C. If the ETS bit is set to 1, the internal digital supply is powered down when the internal die temperature exceeds approximately 150°C, and the device becomes nonfunctional (see Table 11 and Table 12). The AD5761R/AD5721R temperature at power-up must be less than 150°C for proper operation of the devices. Asynchronous Clear Function (CLEAR) The CLEAR pin is a falling edge active input that allows the output to be cleared to a user defined value. The clearcode value is programmed by writing to Bit 10 and Bit 9 in the control register (see Table 11 and Table 12). Maintain CLEAR low for the minimum time of 20 ns to complete the operation (see Figure 2). When the CLEAR signal is returned high, the output remains at the clear value until a new value is loaded to the DAC register. Alert Function (ALERT) When the ALERT pin is asserted low, a readback from the control register is required to clarify whether a short-circuit or brownout condition occurred, depending on the values of Bit 12 and Bit 11, the SC and BO bits, respectively (see Table 15 and Table 16). If neither of these conditions occurred, the temperature exceeded approximately 150°C. THERMAL HYSTERESIS Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. Thermal hysteresis data was tested for the AD5761R as shown in Figure 75. It is measured by sweeping the temperature from ambient to −40°C, then to 125°C, and returning to ambient. The VREF delta is then measured between the two ambient measurements (shown in Figure 75). 5 4 The ALERT pin is low during power-up, a software full reset, or a hardware reset. After the first write to the control register to configure the DAC, the ALERT pin is asserted high. 3 2 1 0 –120 –100 –80 –60 DISTORTION (ppm) Figure 75. Thermal Hysteresis Rev. A | Page 27 of 35 –40 –20 12355-169 The AD5761R/AD5721R can be reset to their power-on state by two means: either by asserting the RESET pin or by using the software full reset registers (see Table 26). NUMBER OF HITS Reset Function (RESET) AD5761R/AD5721R Data Sheet REGISTER DETAILS INPUT SHIFT REGISTER The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at rates of up to 50 MHz. The input shift register consists of three don’t care bits, one fixed value bit (DB20 = 0), four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively. Table 8. AD5761R 16-Bit Input Shift Register Format MSB DB23 X1 1 LSB DB22 X1 DB21 X1 DB20 0 DB19 DB18 DB17 Register address DB16 DB[15:0] Register data DB16 DB[15:4] Register data X is don’t care. Table 9. AD5721R 12-Bit Input Shift Register Format MSB DB23 X1 1 LSB DB22 X1 DB21 X1 DB20 0 DB19 DB18 DB17 Register address X is don’t care. Table 10. Input Shift Register Commands DB19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Register Address DB18 DB17 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 DB16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command No operation Write to input register (no update) Update DAC register from input register Write and update DAC register Write to control register No operation No operation Software data reset Reserved Disable daisy-chain functionality Readback input register Readback DAC register Readback control register No operation No operation Software full reset Rev. A | Page 28 of 35 DB[3:0] XXXX1 Data Sheet AD5761R/AD5721R CONTROL REGISTER The control register controls the mode of operation of the AD5761R/AD5721R. The control register options are shown in Table 11 and Table 12. On power-up, after a full reset, or after a hardware reset, the output of the DAC is clamped to ground through a 1 kΩ resistor and the output buffer remains in power-down mode. A write to the control register is required to configure the device, remove the clamp to ground, and power up the output buffer. When the DAC output range is reconfigured during operation, a software full reset command (see Table 26) must be written to the device before writing to the control register. Table 11. Write to Control Register MSB DB[23:21] DB20 XXX 1 0 1 DB[19:16] Register address 0100 DB[15:11] DB[10:9] DB8 XXXX1 CV[1:0] OVR DB7 DB6 Register data B2C ETS DB5 DB[4:3] LSB DB[2:0] IRO PV[1:0] RA[2:0] X is don’t care. Table 12. Control Register Functions Bit Name CV[1:0] OVR B2C ETS IRO PV[1:0] RA[2:0] Description CLEAR voltage selection. 00: zero scale 01: midscale 10, 11: full scale 5% overrange. 0: 5% overrange disabled 1: 5% overrange enabled Bipolar range. 0: DAC input for bipolar output range is straight binary coded 1: DAC input for bipolar output range is twos complement coded Thermal shutdown alert. The alert may not work correctly if the device powers on with temperature conditions >150°C (greater than the maximum rating of the device). 0: internal digital supply does not power down if die temperature exceeds 150°C. 1: internal digital supply powers down if die temperature exceeds 150°C. Internal reference. 0: internal reference turned off 1: internal reference turned on Power up voltage. 00: zero scale 01: midscale 10, 11: full scale Output range. After an output range configuration, the device must be reset. 000: −10 V to +10 V 001: 0 V to +10 V 010: −5 V to +5 V 011: 0 V to 5 V 100: −2.5 V to +7.5 V 101: −3 V to +3 V 110: 0 V to 16 V 111: 0 V to 20 V Rev. A | Page 29 of 35 AD5761R/AD5721R Data Sheet Table 13. Bipolar Output Range Possible Codes Straight Binary 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Decimal Code 7 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 −7 −8 Twos Complement 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 READBACK CONTROL REGISTER The readback control register operation provides the contents of the control register by setting the register address to 1100. Table 14 outlines the 24-bit shift register for this command, where the last 16 bits are don’t care bits. During the next command, the control register contents are shifted out of the SDO pin with the MSB shifted out first. Table 15 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out. Table 14. Readback Control Register, 24-Bit Shift Register to the SDI Pin MSB DB[23:21] DB20 XXX 1 0 1 LSB DB[19:16] Register address 1100 DB[15:0] Register data Don’t care X is don’t care. Table 15. Readback Control Register, 24-Bit Data Read from the SDO Pin MSB DB[23:21] DB20 XXX 1 0 1 DB[19:16] Register address 1100 DB[15:13] DB12 DB11 DB[10:9] XXX1 SC BO CV[1:0] DB8 DB7 Register data OVR B2C X is don’t care. Table 16. Readback Control Register Bit Descriptions Bit Name SC BO Description Short-circuit condition. The SC bit is reset at every control register write. 0: no short-circuit condition detected 1: short-circuit condition detected Brownout condition. The BO bit is reset at every control register write. 0: no brownout condition detected 1: brownout condition detected Rev. A | Page 30 of 35 DB6 DB5 DB[4:3] LSB DB[2:0] ETS IRO PV[1:0] RA[2:0] Data Sheet AD5761R/AD5721R UPDATE DAC REGISTER FROM INPUT REGISTER The update DAC register function loads the DAC register with the data saved in the input register and updates the DAC output voltage. This operation is equivalent to a software LDAC. Table 17 outlines how data is written to the DAC register. Table 17. Update DAC Register from Input Register MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 0010 DB16 DB[15:0] Register data Don’t care X is don’t care. READBACK DAC REGISTER The readback DAC register operation provides the contents of the DAC register by setting the register address to 1011. Table 18 outlines the 24-bit shift register for this command. During the next command, the DAC register contents are shifted out of the SDO pin with the MSB shifted out first. Table 19 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out. Table 18. Readback DAC Register, 24-Bit Shift Register to SDI Pin MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 1011 DB16 DB[15:0] Register data Don’t care X is don’t care. Table 19. Readback DAC Register, 24-Bit Data Read from SDO Pin MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 1011 DB16 DB[15:0] Register data Data read from DAC register X is don’t care. WRITE AND UPDATE DAC REGISTER The write and update DAC register (Register Address 0011) updates the input register and the DAC register with the entered data-word from the input shift register, irrespective of the state of LDAC. Setting the register address to 0001 writes the input register with the data from the input shift register, clocked in MSB first on the SDI pin. Table 20. Write and Update DAC Register MSB DB23 DB22 DB21 DB20 X1 X1 X1 X1 X1 X1 0 0 1 LSB DB19 DB18 DB17 Register address 0001 0011 X is don’t care. Rev. A | Page 31 of 35 DB16 DB[15:0] Register data Data loaded Data loaded AD5761R/AD5721R Data Sheet READBACK INPUT REGISTER The readback input register operation provides the contents of the input register by setting the register address to 1010. Table 21 outlines the 24-bit shift register for this command. During the next command, the input register contents are shifted out of the SDO pin with the MSB shifted out first. Table 22 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out. Table 21. Readback Input Register, 24-Bit Shift Register to the SDI Pin MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 1010 DB16 DB[15:0] Register data Don’t care X is don’t care. Table 22. Readback Input Register, 24-Bit Data Read from the SDO Pin MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 1010 DB16 DB[15:0] Register data Data read from input register X is don’t care. DISABLE DAISY-CHAIN FUNCTIONALITY The daisy-chain feature can be disabled to save the power consumed by the SDO buffer when this functionality is not required (see Table 23). When disabled, a readback request is not accepted because the SDO pin remains in tristate. Table 23. Disable Daisy-Chain Functionality Register MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 1001 DB16 DB[15:1] DB0 Register data Don’t care DDC X is don’t care. Table 24. Disable Daisy-Chain Bit Description Bit Name DDC Description DDC decides whether daisy-chain functionality is enabled or disabled for the device. By default, daisy-chain functionality is enabled. 0: daisy-chain functionality is enabled for the device. 1: daisy-chain functionality is disabled for the device. SOFTWARE DATA RESET The AD5761R/AD5721R can be reset via software to zero scale, midscale, or full scale (see Table 25). The value to which the device is reset is specified by the PV[1:0] bits, which are set in the write to control register command (see Table 11 and Table 12). Table 25. Software Data Reset Register MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 0111 X is don’t care. Rev. A | Page 32 of 35 DB16 DB[15:0] Register data Don’t care Data Sheet AD5761R/AD5721R SOFTWARE FULL RESET The device can also be reset completely via software (see Table 26). When the register address is set to 1111, the device behaves in a power-up state, where the output is clamped to AGND and the output buffer is powered down. The user must write to the control register to configure the device, remove the 1 kΩ resistor clamp to ground, and power up the output buffer. The software full reset command is also issued when the DAC output range is reconfigured during normal operation. Table 26. Software Full Reset Register MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 DB18 DB17 Register address 1111 DB16 DB[15:0] Register data Don’t care DB18 DB17 DB16 Register address 0000/0101/0110/1101/1110 DB[15:0] Register data Don’t care X is don’t care. NO OPERATION REGISTERS The no operation registers are ignored and do not vary the state of the device (see Table 27). Table 27. No Operation Registers MSB DB23 DB22 DB21 DB20 X1 X1 X1 0 1 LSB DB19 X is don’t care. Rev. A | Page 33 of 35 AD5761R/AD5721R Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT POWER SUPPLY CONSIDERATIONS Figure 76 shows the typical operating circuit for the AD5761R/ AD5721R. The only external components needed for this precision 16-/12-bit DAC are decoupling capacitors on the supply pins and supply voltage. Because the AD5761R/AD5721R incorporate a voltage reference and reference buffers, they eliminate the need for an external bipolar reference and associated buffers, resulting in overall savings in both cost and board space. The AD5761R/AD5721R must be powered by the following three supplies to provide any of the eight output voltage ranges available on the DAC: VDD = 21 V, VSS = −11 V, and DVCC = 5 V. AD5761R/ AD5721R ALERT 1 ALERT DGND 16 CLEAR 2 CLEAR DVCC 15 RESET 3 VREFIN 4 SCLK 14 RESET VREFIN/ 13 SYNC VREFOUT VOUT +15V 100nF 10µF 100nF 10µF 5 AGND 6 VSS 7 VOUT SDO 10 8 VDD DNC 100nF SDI 12 LDAC 11 + +23V SCLK ADP5070 SYNC +5V INPUT SDI LDAC +21V: VDD ADP7142 +5V: DVCC ADP7182 –11V: VSS LDO DC-TO-DC SWITCHING REGULATOR –13V LDO Figure 77. Postregulation by ADP7142 and ADP7182 SDO NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. ADP7142 LDO EVALUATION BOARD 9 Figure 76. Typical Operating Circuit DC-TO-DC SWITCHING REGULATOR 10µF +5V 12355-064 –15V ADP5070 +5V INPUT An evaluation board is available for the AD5761R to aid designers in evaluating the high performance of the device with minimum effort. The AD5761R evaluation kit includes a populated and tested AD5761R printed circuit board (PCB). The evaluation board interfaces to the USB port of a PC. Software is available with the evaluation board to allow the user to easily program the AD5761R. The EVAL-AD5761RSDZ user guide provides full details on the operation of the evaluation board. Rev. A | Page 34 of 35 12355-070 In Figure 76, VDD is connected to 15 V and VSS is connected to −15 V, but VDD and VSS can operate with supplies from 4.75 V to 30 V and from −16.5 V to 0 V, respectively. For applications requiring optimal high power efficiency and low noise performance, it is recommended to use the ADP5070 switching regulator to convert the 5 V input rail into two intermediate rails (+23 V and −13 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP7142 and ADP7182). Figure 77 shows the recommended method. Data Sheet AD5761R/AD5721R OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 78. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 8 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 08-16-2010-E PIN 1 INDICATOR 3.10 3.00 SQ 2.90 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 79. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5721RBRUZ AD5721RBRUZ-RL7 AD5721RBCPZ-RL7 AD5761RARUZ AD5761RARUZ-RL7 AD5761RBRUZ AD5761RBRUZ-RL7 AD5761RACPZ-RL7 AD5761RBCPZ-RL7 EVAL-AD5761RSDZ 1 Resolution (Bits) 12 12 12 16 16 16 16 16 16 Internal Reference (V) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12355-0-5/15(A) Rev. A | Page 35 of 35 INL (LSB) ±0.5 ±0.5 ±0.5 ±8 ±8 ±2 ±2 ±8 ±2 Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ Evaluation Board Package Option RU-16 RU-16 CP-16-22 RU-16 RU-16 RU-16 RU-16 CP-16-22 CP-16-22 Branding DHN DJ5 DJ6