ETC AB-053

APPLICATION BULLETIN
®
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Tel: (602) 746-1111 • Twx: 910-952-111 • Telex: 066-6491 • FAX (602) 889-1510 • Immediate Product Info: (800) 548-6132
IMPROVED NOISE PERFORMANCE OF THE
ACF2101 SWITCHED INTEGRATOR
By Bonnie C. Baker (602) 746-7984
The signal-to-noise ratio and bandwidth of the combination
of the ACF2101 dual, switched integrator and a low-level
input current is exceptional when compared to the performance of a classical transimpedance amplifier (Figure 1). To
further improve the ACF2101 signal-to-noise ratio, a resistor can be added in series with the input sensor.
Where:
VOUT = output voltage of op amp
CINT = integration capacitor
IIN = sensor current
The output of the ACF2101 switched integrator is a time
averaged representation of the input.
CINT
1/2 ACF2101
Reset
VOUT
Sensor
Hold
IIN
CINT
VOUT
Integrator Amplifier
Sensor
R2
VOUT
Sensor
IIN
Classical Transimpedance Amplifier
FIGURE 1. Typical Circuits Used to Convert Current Signals to Voltage.
The ACF2101 is a dual switched integrator, as shown in
Figure 2. The current from the sensor is integrated by the
capacitor (CINT) in the feedback loop of the amplifier. Since
the inverting input of the amplifier is kept at a virtual
ground, the output of the integrator changes in a negative
direction over time. The resulting transfer function of the
switched integrator is:
t
VOUT = –1 ∫O IIN dt
CINT
©
1993 Burr-Brown Corporation
FIGURE 2. The ACF2101 Switched Integrator Block Diagram.
Once the ACF2101 has integrated the input signal over a
predetermine period, the HOLD switch is opened, allowing
the user to read the output of the switched integrator at a held
voltage. The HOLD switch performs a sample/hold function
on the signal. Once the signal is read, the RESET switch is
closed in order to discharge the integration capacitor, CINT,
and bring the output back to the same potential as the
inverting input of the amplifier. Once the output returns to
ground, the RESET switch is opened. Shortly after the
RESET switch is opened, the HOLD switch closes to start
the integration cycle again.
Typically, a photodiode is used as the sensor for both
circuits shown in Figure 1. A photodiode can be modeled
using the sensor model shown in Figure 3. This model
includes a current source (IIN), parasitic resistor (R1), and
parasitic capacitor (C1). Typical values of R1 range from
100kΩ to 100GΩ. Typical values of C1 range from 20pF to
1000pF. C1 can be higher if the sensor is placed at a remote
location, and a cable, with parasitic capacitance to ground,
is used to transmit the signal to the input of the switched
integrator.
AB-053
Printed in U.S.A. May, 1993
R1
Ideal
Diode
The three dominate sources of noise at the output of the
switched integrator are the gained op amp noise, the charge
injection noise of the switches and the KT/C noise of the
integration capacitor. A bode plot of the op amp noise gain
of the switched integrator is shown in Figure 6. The lowfrequency pole of the noise gain is equal to:
C1
IIN
f
FIGURE 3. Photodiode Model Used in Noise Analysis.
fZ =
2 π( R | | R
1
1
RESET
) (C 1
+ C
INT
)
This zero is also usually found at very low frequencies. For
example, if R1 = 100MΩ, C1 = 50pF, RRESET = 1000GΩ, and
CINT = 100pF, fZ would equal 10.6Hz.
As a consequence, the op amp output noise of the switched
integrator is dominated by the high frequency op amp noise
multiplied by:
RRESET

C1
High frequency noise gain = 1 +

C

INT
CINT




The total rms noise can be estimated as equal to:
VOUT
C1
1
2 π R RESET C INT
The zero of the noise gain plot is equal to:
1/2 ACF2101
RHOLD
=
This pole is usually found at very low frequencies. For
example, if RRESET = 1000GΩ and CINT = 100pF, the pole
would occur at 0.00159Hz.
The noise model for the complete photodiode/switched
integrator application is shown in Figure 4. In most applications the switched integrator is in the integrate mode for
most of the total integration cycle. The model in Figure 4
represents the ACF2101 with the HOLD switch closed and
the RESET switch opened. The typical on-resistance of the
HOLD switch is 1.5kΩ, and the typical open-resistance of
the RESET switch is 1000GΩ.
Photodiode
P
R1
NOISE OP
AMP

C 
1 
= 10  1 +
 µVrms
C

INT 
The charge injection noise of the switches and the integration capacitor noise both have broad band noise equivalent
to 10µVrms. The total characterized noise of the ACF2101
switched integrator with various input capacitance and integration capacitance is shown in Figure 6.
FIGURE 4. ACF2101 Switched Integrator and Photodiode
Model Used for Noise Analysis.
Open Loop Gain
of Op Amp
|A|
dB
100
1+
C1
CINT
Total Output Noise (µVrms)
90
Noise Gain
80
CINT = 100pF
70
60
50
40
CINT = 200pF
30
CINT = 500pF
20
CINT = 1000pF
10
ƒP
ƒZ =
ƒP =
ƒZ
Log ƒ
0
0
1
100 200 300 400 500 600 700 800 900 1000
C1 (pF)
2π (R1 || RRESET) (C1 + CINT)
1
2π RRESET CINT
FIGURE 6. Total Output Noise of the ACF2101 Switched
Integrator vs Parasitic Photodiode Capacitance,
C1, and the ACF2101 Integration Capacitor,
CINT.
FIGURE 5. Noise Gain of the ACF2101, Switched Integrator.
2
An application example is shown in Figure 9. The photodiode is modeled with a parasitic capacitance of 1000pF and
parasitic resistance of 50MΩ. The integration capacitor used
in the feedback loop of the op amp in the ACF2101 is equal
to 100pF. The 20-bit, 40kHz ADC750 A/D converter block
diagram is shown in Figure 10. Extreme care should be
taken to properly guard the high impedance input pins of the
ACF2101 in order to reduce the possibility of coupled noise
into the signal.
To further improve the signal-to-noise ratio of the ACF2101
switched integrator, a resistor can be added in series with the
sensor, as shown in Figure 7. This additional resistor, RN, in
series with RHOLD, adds a pole/zero pair at higher frequencies. When RN equals 0Ω, the pole/zero pair generated by
HOLD switch on-resistance (RHOLD = 1.5kΩ) occurs at
frequencies close to the open loop gain of the amplifier. As
shown in the bode plot in Figure 8, RN plus RHOLD attenuates
high frequency noise.
The design trade-off for improved noise performance of the
switched integrator is a slight degradation in the linearity
performance of the photodetector. The current from the
sensing device will cause an IR drop across RN. This IR drop
will impress a voltage across the sensor, causing a small
degree of dark current to start to conduct. As shown in
Figure 8, the pole generated by the additional resistor, RN, is
equal to:
1/2 ACF2101
RRESET
Photodiode
RN
CINT
RHOLD
VOUT
Pole =
R1
C1
Op Amp Open
Loop Gain
30
Gain (dB)
RN = 10kΩ
(RN +
R
HOLD
)
C
1
RN = 3.1kΩ
Pole
10
0
1
The ACF2101 switched integrator is optimized for good
noise and bandwidth performance for low-level input currents. The addition of a resistor in series with the photodiode
further improves the noise performance without sacrificing
bandwidth.
40
ACF2101 Noise Gain
2π R
The pole is directly affected by the value of RN and C1
(photodetector parasitic capacitance). Higher values for C1
will reduce the noise without compromising the linearity
performance of the photodetector. The overall circuit performance is best optimized when the photodetector parasitic
capacitance, C1, is 200pF or greater.
FIGURE 7. The ACF2101 Switched Integrator with an
Additional Resistor, RN, Added in Series with
the Photodiode to Reduce Noise.
20
R N + R 1 + R HOLD
RN = 1kΩ
RN = 31kΩ
C1 = 1000pF
R1 = 50MΩ
RRESET = 1000GΩ
CINT = 100pF
RN = 100kΩ
–10
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 8. Noise Gain Plots of ACF2101 with an Additional Resistor, RN, in Series with the Photodiode.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
1/2 ACF2101
Reset
RN
50MΩ
Hold
100pF
1000pF
Digital
Out
ADC750
10µVrms (typ)
2.5ms
30µs
HOLD
5µs
RESET
WRITE
5µs
Timing Diagram
FIGURE 9. Circuit and Timing Diagram used to Test the Noise Performance of the ACF2101 with and without RN.
+
Analog
Inputs
•
•
•
8-Channel
Differential
Input
Multiplexer
Convert
Command
–
Automatic
Selectable-Gain
Amplifier
G = 1, 8, 64
Sample/Hold
Amplifier
Timing, Control and Autozero Logic
Autozero Select
Gain Select (Manual/Auto)
Channel Select
FIGURE 10. Block Diagram of ADC750 A/D Converter.
4
A/D
Converter
Mantissa
Data
Output
(16 Bits)
Exponent
Data (2 Bits)