DEM-ACF2101BP EVALUATION FIXTURE FEATURES DESCRIPTION ● PROGRAMMABLE TIMING GENERATOR The DEM-ACF2101BP is an evaluation fixture for the ACF2101BP dual, switched integrator. The board converts an input current to an output voltage using an ACF2101BP, with the switches of the ACF2101BP driven by a programmable timing generator. ● EXTERNAL INTEGRATION CAPACITOR OPTION ● FLEXIBLE INPUT FOR CURRENT OR VOLTAGE INPUTS ● OUTPUT BUFFER INCLUDED ● EXTERNAL OUTPUT HOLD CAPACITOR OPTION ● DUAL CHANNEL OPERATION International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1992 Burr-Brown Corporation As a complete circuit, the DEM-ACF2101BP makes it easy to do a quick evaluation of the ACF2101BP. The design and implementation of a programmable timing generator is included on the board as well as additional space for external capacitors and resistors. • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 LI-415A Printed in U.S.A. February, 1995 OVERVIEW The cycle time can be easily adjusted over a range of 50µs to 500ms by adjustment of the trigger frequency. An external capacitor can also be added to the board so that integration capacitor values larger than 100pF can be used if desired. The DEM-ACF2101BP is an evaluation board designed for simultaneous operation of both channels of the ACF2101. Figure 1 illustrates the design of the board with a simplified block diagram. The user provides a positive current input signal, ±15V and +5V DC supplies, and a trigger signal ranging up to 20kHz. The ACF2101 output voltage is buffered by a unity gain op amp circuit. The trigger input controls the basic operational rate of the programmable timing generator circuit. The on-board, user controlled, timing generator provides control signals for the HOLD, RESET, and SELECT switches of the ACF2101. The on-board switch matrix allows the user to control the timing of the ACF2101 RESET, HOLD, and output SELECT switches. This board is configured at the factory for a recommended reset time of tPULSE = 20µs. The table below shows selected values of input current, cycle time, and integration capacitance needed to provide an output of –10V. Both channels of the ACF2101 are configured at the factory with a 1ms cycle time using the ACF2101’s internal 100pF integration capacitor (CINT). This cycle time and integration capacitor will provide a –10V output signal with an input current of 1µA. Trigger In INPUT CURRENT CYCLE TIME INTEGRATION CAPACITANCE 0.01µA 0.1µA 1µA 10µA 10µA 100µA 100ms 10ms 1ms 100µs 1.1ms 110µs 100pF (internal) 100pF (internal) 100pF (internal) 100pF (internal) 1100pF (internal + external) 1100pF (internal + external) Programmable Timing Generator C2 (Installed by user) Side A of the ACF2101 In A 1/2 OPA2107 R3 (Installed by user) Out A 1/2 ACF2101BP C3 (Installed by user) C6 (Installed by user) C5 (Installed by user) Side B of the ACF2101 In B 1/2 OPA2107 R4 (Installed by user) 1/2 ACF2101BP C4 (Installed by user) C7 (Installed by user) FIGURE 1. Simplified Block Diagram. DEM-ACF2101BP 2 Out B ∆VOUT = –(iIN • ∆t)/(CINT + CEXT) TECHNICAL DESCRIPTION ∆VOUT = the maximum output voltage (in volts) The analog circuit (Figure 2) is designed for simultaneous two channel operation of the dual ACF2101. Both channels are configured at the factory for a 0 to 1µA input signal over a 1ms cycle time. This cycle time and input signal will provide a 0 to –10V output signal. A block diagram of 1/2 of the ACF2101 is shown in Figure 3. The transfer function of the ACF2101 can be calculated as: CINT = the integration capacitor on the chip (in farads) CEXT = the external capacitor, C2 and C5 (in farads) iIN = the input current (in amperes) ∆t = the cycle time (in seconds) see Figure 4 J5 Out B Note that CINT can be used alone or in parallel with CEXT. If an external integration capacitor is used it should have a low C9 2.2µF + 13 SW Out B Out B 12 15 14 SW COM B SEL B COM B GND B 11 Select Hold In B Reset C4 R4 J3 C3 R3 C5 10 16 RST B 9 CAP B 17 Hold B 18 V– SW In B In B 8 7 V+ SW In A 20 In A Hold A 19 6 5 22 21 RST A CAP A 4 In A J2 C2 3 GND A COM A SEL A SW COM A 23 2 SW Out A 1 Out A U5 ACF2101 24 +5 C8 0.01µF C10 + 2.2µF –15 C11 0.01µF C7 C6 –15 U6 OPA 2107 1 Out A +VS 2 –In A Out B 3 +In A –In B 4 –VS +In B 8 7 6 5 +15 J4 Out A ACF2101BP Analog Circuit Configuration FIGURE 2. Analog Portion of DEM-ACF2101BP Evaluation Fixture. 3 DEM-ACF2101BP Hold Reset voltage coefficient, temperature coefficient, memory, and leakage current. Suitable types include NPO ceramic, polycarbonate, polystyrene, and silver mica. Space for an external integration capacitor (C2 and C5) is also provided on the board. Select 100pF Cap Out CINT The SW OUT of both channels are connected to operational amplifiers configured as buffers (U6). A space for an output hold capacitor (C6 and C7) is provided on the board for each side of the dual ACF2101BP. An example of how C6 and C7 could be used with the help of the OPA2107 (U6) operational amplifier is shown in Figure 5. In Figure 5, the ACF2101BP is used as a programmable current to voltage converter. The output of the circuit, VOUT is a dc level for a constant current input. Refer to the ACF2101 data sheet (PDS-1078) for a detailed discussion of this application. In Reset Sw In Hold Sw Out Com Sw Com FIGURE 3. Block Diagram of 1/2 of the ACF2101BP. By changing R3 and R4 from zero ohm (factory configured) jumpers to resistors, a voltage source can be integrated instead of a current source as shown in the schematic in Figure 6. C3 and C4 must be added to the circuit in this application to prevent the voltage at SW IN A and SW IN B from exceeding +0.5V when the HOLD switch is off (or open). If the voltage at SW IN A or SW IN B exceeds +0.5V, the protection circuitry will begin to conduct. This will not damage the ACF2101BP, but performance specifications will not be met. Selection of C3 and C4 is dependent on the time that the ACF2101BP is in the hold mode and the magnitude of iIN. Cycle Time HOLD INTEGRATE HOLD RST HOLD INTEGRATE OUTPUT (V) 0 –10 OFF C3, C4 ≥ (tHOLD • iIN(max)) / 0.5V HOLD ON tHOLD = time that the ACF2101BP is in the hold mode (seconds) OFF iIN(MAX) = maximum expected input current (amperes) RESET ON C3, C4 = capacitance (farads) MODES OF OPERATION SWITCH Hold Switch Reset Switch MODE OF OPERATION INTEGRATE HOLD RESET On Off Off Off PROGRAMMABLE TIMING GENERATOR The timing generator (Figure 7) provides the RESET, SELECT, and HOLD control signals for the operation of the ACF2101. This generator is a programmable state machine that consist of a decade counter and a few flip-flops. Each ACF2101 control signal has its own edge-triggered flip-flop. On/Off On On: Switch shorted; Logic 0 input. Off: Switch open; Logic 1 input. FIGURE 4. Modes of Operation of the ACF2101. 100pF Reset ISENSOR Hold Sensor 1/2 OPA2107 1/2 ACF2101 VOUT Select C6 or C7 10nF CIN FIGURE 5. Block Diagram of a Programmable Current-to-Voltage Converter using the DEM-ACF2101BP Evaluation Fixture. DEM-ACF2101BP 4 Hold CF Cap LIN +VIN initiates a logic high on the SELECT pin, which opens the SELECT switches of the ACF2101BP. HOLD is controlled by columns G and F. A rising edge of G initiates a logic high on the HOLD pin, which opens the HOLD switches on both sides of the dual ACF2101BP. A rising edge of F initiates a logic low on the HOLD pin, which closes the HOLD switches of the ACF2101BP. The logic table is shown below. Select Out 100pF In R3 or R4 Reset Reset Sw In C3 or C4 Sw Out Hold VOUT SW1 Sw Com Com A B C D E F G H J K 1/2 ACF2101 FIGURE 6. Block Diagram of Using the ACF2101BP with a Voltage Input Instead of a Current Input. The outputs of the counter will change the state of the flipflops depending on the settings of the matrix switches. The RESET, SELECT, and HOLD control signals are the same for both sides of the dual ACF2101BP. This is not a requirement for ACF2101 operation. The RESET, SELECT and HOLD control lines were hard-wired on this board to make it easier to use. CLOCK LOGIC EDGE No Connect Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge Rising Edge No Connect No Connect No Connect ACF2101 SWITCH AFFECTED NEW ACF2101 SWITCH CONDITION RESET RESET SELECT SELECT HOLD HOLD OPEN CLOSED OPEN CLOSED CLOSED OPEN Examples of switching arrangements for the DEMACF2101BP are shown in Figure 9. FACTORY TIMING AND TEST CIRCUIT The block diagram of the analog portion of the DEMACF2101BP and timing configuration used to test the board is shown in Figure 10. The setting of column A on SW1 determines the clock cycle of the counter, U1. Column A is set to Row 0 to give the longest clock cycle and the most programming flexibility. The REF102 is a 10V reference chip. Two 10MΩ resistors are used to generates two 1µA current sources, which sink into SW IN A and SW IN B of the ACF2101BP. C3 and C4 are used during test to prevent the hold switch input from exceeding 0.5V. The timing circuit is adjusted to a 20µs pulse width. Operation of the clock and the ACF2101 is verified. The rising edge of the trigger initiates the clocking sequence shown in Figure 8. After a delay the switching signals (row 1 through row 10) that will ultimately control the RESET, SELECT, and HOLD control pins begin. Each row follows the preceding row with a rising edge delay of tPULSE. The pulse width, tPULSE, is changed by adjusting the value of RV1 potentiometer on the board. The nominal range of tPULSE is 6ns to 36µs. The trigger frequency ranges from 2Hz to 20kHz to give a range of cycle times from 500ms to 50µs. All of the signals from the counter, U1, are connected to the rows of the switch matrix, SW1. The signals on the rows of SW1 can be switched into the columns by toggling the switches on the matrix. RESET is controlled by columns B and C. The rising edge of C initiates a logic low on the RESET pin, which closes the RESET switches on both sides of the dual ACF2101BP (U5). The rising edge of B initiates a logic high on the RESET pin, which opens the RESET switches of the ACF2101BP. SELECT is controlled by columns E and D. The rising edge of E initiates a logic low on the SELECT pin, which closes the SELECT switches on both sides of the dual ACF2101BP. The rising edge of D LAYOUT CONSIDERATIONS Care was taken in the layout of this board to ensure the best performance of the ACF2101BP. The inputs of the ACF2101BP are carefully guarded to prevent excess currents from being capacitively coupled into the summing junction of the ACF2101 amplifier. Since this is a four-layer board, we found that the power planes were critical in this case and had to be removed from the area. 5 DEM-ACF2101BP FIGURE 7. Programmable Timing Generator Portion of the DEM-ACF2101BP Evaluation Fixture. DEM-ACF2101BP 6 +5 15 CLR 14 CLK 13 /CLKEN Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CO U1 74HC4017 3 2 4 7 10 1 5 6 9 11 12 1 2 3 4 5 6 7 8 9 0 A B C D E F G H J K SW1 AMP 436270-1 +5 +5 +5 1 2 4 5 9 10 12 13 /4Y /3Y /2Y & /1Y CLK Adj 74HCT132 U2 1A 1B 2A 2B 3A 3B 4A 4B 11 8 6 3 C1 2.2nF RV1 25kΩ R1 4.99kΩ Trigger In J1 R4 49.9Ω –15 +15 +5 –15V GND +15V +5V GND Spare P1 /Q2 Q2 10 S2 11 C2 12 D2 13 R2 4 S1 3 C1 2 D1 1 R1 /Q2 Q2 /Q1 Q1 U3 74HCT74 10 S2 11 C2 12 D2 13 R2 8 9 6 5 8 9 U4 74HCT74 4 5 S1 Q1 3 C1 2 D1 1 6 R1 /Q1 Test Point GND 6 5 4 3 2 1 HDR1 Hold Reset Select Hold Select Reset Cycle Time Trigger In 3.3(1) TPULSE Row 2 TPULSE(1) Row 3(2) Row 4(2) Row 5(2) Row 6(2) Row 7(2) Row 8(2) Row 9(2) NOTE: (1) TPULSE = 0.55 (R1 + RV1) C1 . (2) True for Column A set to row 0 (if Column A is set to Row 9, Row 9 will always be zero. If Column A is set to Row 8, Row 8 and Row 9 will always be zero, etc.) FIGURE 8. Timing Sequence of the Rows of SW1 on the DEM-ACF2101BP Evaluation Fixture. Trigger Row Column 3 G 6 F Procedure for Setting Timing of Switches Hold Time 1. Draw desired switching diagram for your application. 2. Select cycle time for your application. It must be greater than 50µs and less than 500ms. Cycle Time Select Time 3 E 3 D 5 C 5 B 3. Calculate the trigger frequency, fTRIGGER = 1/cycle time. 4. Apply power (±15, +5, ground) and the trigger signal to the DEM-ACF2101BP board. 5. Select desired pulse width. It must be greater than 6ns and less th an 36µs. Reset Time Pulse Time (TPULSE) Trigger Row Column 3 G 8 F Hold Time 6. Adjust desired pulse width by setting SW1, Row 2 to Column D and Row 2 to Column E. Look at Select signal on a scope and adjust signal width with RV1. 7. Set the Rows of SW1 to match desired columns to match switching diagram. 8. NOTE: The rise edge of the Reset switch should not coincide with the falling edge of the Hold switch. If it does, there is a chance that data wll be lost. Cycle Time Select Time 3 E 4 D 6 C 7 B Reset Time Pulse Time (TPULSE) FIGURE 9. Examples of Switch Settings and Procedure for Setting the Timing of the Switches for the DEM-ACF2101BP Evaluation Fixture. 7 DEM-ACF2101BP +15V 2 8 6 +10V 10M REF102 4 SW In 1/2 OPA2107 1/2 ACF2101BP 4.7µF 1µF FIGURE 10a. Factory Test Circuit for the DEM-ACF2101BP. Trigger = 1kHz Hold Time = 80µs Row Column 3 G 6 F Cycle Time = 1ms Select Time = 20µs Row Column 4 E 4 D Row Column 5 C 5 B Reset Time = 20µs TPULSE = 20µs FIGURE 10b. Timing Configuration for the Factory Test of DEM-ACF2101BP. DEM-ACF2101BP 8 Output FIGURE 11. Silk Screen. FIGURE 12. Solder Side. 9 DEM-ACF2101BP FIGURE 13. Power Plane. FIGURE 14. Component Side. DEM-ACF2101BP 10 FIGURE 15. Ground Plane. DEM-ACF2101BP PARTS LIST QTY REF DES MANUFACTURER 74HC4017 74HCT132 74HCT74 ACF2101BP OPA2107 824-AG31D 808-AG11D 4362701 U1 U2 U3, U4 U5 U6 (U5) (U6) SW1 Any Signetics Signetics Burr-Brown Burr-Brown Augat Augat Amp Resistors 1 1 2 1 RJ26FW253 RN55D4991F FRJ-50 RN55D49R9F RV1 R1 R2, R3 R4 Bourns Dale Philips Dale Capacitors 1 2 2 C320C222J1G5CA C320C103K2R5CA ECS-F1EE225K C1 C8, C9 C10, C11 Kemet Kemet Panasonic J1, J2, J3, J4, J5 P1 HDR1 GND N/A N/A N/A Kings Amp Samtec Mil Max Precision WW EF Johnson HMS 1 1 2 1 1 1 1 1 Mechanical 5 1 1 1 1 4 4 PART NO. KC-79-274-M06 102203-3 TWS-103-07-G-S 2308-2-00-01-00-00-07-0 678164 312-6473-032 DESCRIPTION CROSS P/N Decade Counter Quad Nand Schmitt Trigger Flip-Flop Dual Switched Integrator Dual FET Op Amp 24 Pin DIP 0.3 GLD/TIN 8 Pin DIP 0.3 GLD/TIN 10 X 10 Matrix SW N/A (1) N/A (1) Must match specs Must match specs N/A (1) 25k Trimmer 4.99k 1/4W 1% 0 Jumper Resistor 49.9 1/4W 1% RJRFW253 (2) N/A (1) N/A (1) N/A (1) 2200pF 50V-200V 5% 0.1" LS 0.1µF CERC RAD 0.1" LS 10% 2.2µF TANT 25V 10% Must match specs Must match specs N/A (1) PCB MNT BNC Pwr in Connector 3 Pin STRT HDR GLD/GLD Turret Terminal Input Pwr Cable 1" Standoffs 4-40 1/4-1/2" 4-40 Pan Hd Scws N/A (1) N/A (1) Must match specs N/A (1) N/A (1) 1450E (2) MFG Bourns Keystone NOTE: (1) All parts with N/A in cross P/N column are not to be crossed. (2) If a part number appears in cross P/N column part can only be crossed to that alternate. 11 DEM-ACF2101BP WORKSHEET Trigger Row Column Hold TIme Select Time Reset Time Pulse Time (TPULSE) DEM-ACF2101BP 12