ETC DAC1220E/2K5

®
DAC1220
DAC
122
0
For most current data sheet and other product
information, visit www.burr-brown.com
20-Bit Low Power
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● 20-BIT MONOTONICITY GUARANTEED
OVER –40°C to +85°C
● LOW POWER: 2.5mW
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● VOLTAGE OUTPUT
● SMART TRANSMITTERS
● SETTLING TIME: 2ms to 0.012%
● PORTABLE INSTRUMENTS
● CLOSED-LOOP SERVO-CONTROL
● MAX LINEARITY ERROR: ±0.0015%
● ON-CHIP CALIBRATION
DESCRIPTION
The DAC1220 features a synchronous serial interface.
In single-converter applications, the serial interface
can be accomplished with just two wires, allowing
low-cost isolation. For multiple converters, a CS signal
allows for selection of the appropriate D/A converter.
The DAC1220 is a 20-bit digital-to-analog (D/A)
converter offering 20-bit monotonic performance over
the specified temperature range. It utilizes delta-sigma
technology to achieve inherently linear performance
in a small package at very-low power. The resolution
of the device can be programmed to 20 bits for fullscale, settling to 0.003% within 15ms typical, or 16
bits for full-scale, settling to 0.012% within 2ms max.
The output range is two times the external reference
voltage. On-chip calibration circuitry dramatically reduces low offset and gain errors.
XOUT
XIN
The DAC1220 has been designed for closed-loop
control applications in the industrial process control
market and high-resolution applications in the test and
measurement market. It is also ideal for remote applications, battery-powered instruments, and isolated systems. The DAC1220 is available in a SSOP-16
package.
AVDD
VREF
AGND
Clock Generator
Microcontroller
Instruction Register
Command Register
Data Register
Offset Register
Full-Scale Register
SDIO
SCLK
Second-Order
∆∑
Modulator
Second-Order
Continuous
Time Post Filter
C1
VOUT
C2
Modulator Control
Serial
Interface
CS
First-Order
Switched
Capacitor Filter
DVDD
DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1998 Burr-Brown Corporation
SBAS082
PDS-1418B
1
Printed in U.S.A. April , 2000
SPECIFICATIONS
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 2.5MHz, VREF = +2.5V, and 16-bit mode, unless otherwise noted.
DAC1220E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
16
Bits
20-Bit Mode
20
Bits
ACCURACY
Monotonicity
Monotonicity
±1(1)
Linearity Error
Unipolar Offset Error(2)
±4
VOUT = 20mV
Unipolar Offset Error Drift(3)
Bipolar Zero Offset Error(2)
1
VOUT = VREF
Bipolar Zero Offset Drift(3)
±1
LSB
1
ppm/°C
±10
Power Supply Rejection Ratio
at DC, dB = –20log(∆VOUT/∆VDD)
LSB
ppm/°C
Gain Error(2)
Gain Error Drift(3)
LSB
LSB
2
ppm/°C
60
dB
ANALOG OUTPUT
Output Voltage(4)
0
2 • VREF
V
0.5
mA
Output Current
Capacitive Load
500
pF
Short-Circuit Current
±20
mA
Short-Circuit Duration
GND or V DD
Indefinite
DYNAMIC PERFORMANCE
Settling Time(5)
Output Noise Voltage
To ±0.012%
1.8
20-Bit Mode, to ±0.003%
15
ms
0.1Hz to 10Hz
1
µVrms
2
ms
REFERENCE INPUT
Input Voltage
2.25
Input Impedance
2.5
2.75
100
V
kΩ
DIGITAL INPUT/OUTPUT
Logic Family
TTL-Compatible CMOS
Logic Levels (all except XIN)
VIH
2.0
DVDD +0.3
VIL
–0.3
0.8
VOH
IOH = –0.8mA
VOL
IOL = 1.6mA
3.6
XIN Frequency Range (fXIN)
0.5
User Programmable
V
V
Input-Leakage Current
Data Format
V
0.4
V
±10
µA
2.5
MHz
5.25
V
Offset Two’s Complement
or Straight Binary
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
4.75
Supply Current
Analog Current
360
µA
Digital Current
140
µA
µA
Analog Current
20-Bit Mode
460
Digital Current
20-Bit Mode
140
Power Dissipation
2.5
µA
3.5
mW
20-Bit Mode
3.0
mW
Sleep Mode
0.45
mW
TEMPERATURE RANGE
Specified Performance
–40
+85
°C
NOTES: (1) Valid from AGND + 20mV to AVDD – 20mV, in the 16-bit mode. (2) Applies after calibration, in 16-bit mode. (3) Re-calibration can remove these errors.
(4) Ideal output voltage, does not take into account gain and offset error. (5) Valid from AGND +20mV to AVDD –20mV. Outside of this range, settling time may
be twice the value indicated. For 16-bit mode, C1 = 2.2nF, C2 = 0.22nF; for 20-bit mode, C1 = 10nF, C2 = 3.3nF.
®
DAC1220
2
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
SSOP
DVDD
1
16
SCLK
XOUT
2
15
SDIO
XIN
3
14
CS
DGND
4
13
AGND
DAC1220E
AVDD
5
12
VREF
DNC
6
11
VOUT
DNC
7
10
C2
DNC
8
9
C1
PIN
NAME
DESCRIPTION
1
DVDD
Digital Supply, +5V nominal
2
XOUT
System Clock Output (for Crystal)
3
XIN
4
DGND
5
AVDD
Analog Supply, +5V nominal
6
DNC
Do Not Connect
7
DNC
Do Not Connect
8
DNC
9
C1
Filter Capacitor, see text.
10
C2
Filter Capacitor, see text.
11
VOUT
Analog Output Voltage
12
VREF
Reference Input
13
AGND
14
CS
System Clock Input
Digital Ground
Do Not Connect
Analog Ground
Chip Select Input
15
SDIO
Serial Data Input/Output
16
SCLK
Clock Input for Serial Data Transfer
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
AVDD to DVDD ................................................................................... ±0.3V
AVDD to AGND ........................................................................ –0.3V to 6V
DVDD to DGND ....................................................................... –0.3V to 6V
AGND to DGND ............................................................................... ±0.3V
VREF Voltage to AGND .......................................................... 2.0V to 3.0V
Digital Input Voltage to DGND .............................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND ........................... –0.3V to DVDD + 0.3V
Package Power Dissipation ............................................. (TJMAX – TA)/θJA
Maximum Junction Temperature (TJMAX) ..................................... +150°C
Thermal Resistance, θJA
SSOP-16 ................................................................................ 200°C/W
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
LINEARITY
ERROR
(LSB)
DAC1220E
"
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
±1
SSOP-16
322
–40°C to +85°C
"
"
"
"
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DAC1220E
DAC1220E/2K5
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “DAC1220E/2K5” will get a single 2500-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DVDD = +5.0V, fXIN = 2.5MHz, VREF = 2.5V, C1 = 2.2nF and C2 = 0.22nF, calibrated mode, unless otherwise specified.
LARGE-SIGNAL SETTLING TIME
POWER SUPPLY REJECTION RATIO vs FREQUENCY
60
5.0
4.5
4.0
3.5
40
3.0
(V)
PSRR (dB)
50
30
2.5
2.0
20
1.5
400mVp-p Ripple
Mid-Range Output
10
1.0
0.5
0
0.0
10
100
1k
10k
0
1
Frequency (Hz)
2
3
4
Time (ms)
OUTPUT NOISE VOLTAGE vs FREQUENCY
LINEARITY ERROR vs CODE
10
10k
–40°C
8
Linearity Error (ppm)
Noise (nV/√Hz)
1k
100
10
+25°C
+85°C
6
4
2
0
–2
1
10
100
1k
10k
100k
0
1M
20000
30000
40000
Code
Frequency (Hz)
®
DAC1220
10000
4
50000
60000
70000
THEORY OF OPERATION
ANALOG OPERATION
The DAC1220 is a precision, high dynamic range, selfcalibrating, 20-bit, delta-sigma digital-to-analog converter.
It contains a second-order delta-sigma modulator, a firstorder switched-capacitor filter, a second-order continuoustime post filter, a microcontroller including the Instruction,
Command and Calibration registers, a serial interface, and a
clock generator circuit.
The system clock is divided down to provide the sample
clock for the modulator. The sample clock is used by the
modulator to convert the multi-bit digital input into a one-bit
digital output stream. The use of a 1-bit DAC provides
inherent linearity. The digital output stream is then converted into an analog signal via the 1-bit DAC and then
filtered by the 1st-order switched capacitor filter.
The design topology provides low system noise and good
power-supply rejection. The modulator frequency of the
delta-sigma D/A converter is controlled by the system clock.
The output of the switched-capacitor filter feeds into the
continuous time filter. The continuous time filter uses external capacitors connected between the C1, C2, VREF, and
VOUT pins to adjust the settling time. The connections for the
capacitors are shown in Figure 1 (C1 connects between the
VREF and C1 pins, and C2 connects between the VOUT and C2
pins).
The DAC1220 also includes complete onboard calibration
that can correct for internal offset and gain errors.
The calibration registers are fully readable and writable.
This feature allows for system calibration. The various
settings, modes, and registers of the DAC1220 are read or
written via a synchronous serial interface. This interface
operates as an externally clocked interface.
DEFINITION OF TERMS
Differential Nonlinearity Error—The differential
nonlinearity error is the difference between an actual step
width and the ideal value of 1 LSB. If the step width is
exactly 1 LSB, the differential nonlinearity error is zero.
A differential nonlinearity specification of less than 1 LSB
guarantees monotonicity.
DAC1220
VREF
12
VOUT
11
C2
10
C1
9
C2
C1
Drift—The drift is the change in a parameter over temperature.
Full-Scale Range (FSR)—This is the magnitude of the
typical analog output voltage range which is 2 • VREF.
For example, when the converter is configured with a 2.5V
reference, the full-scale range is 5.0V.
FIGURE 1. External Capacitor Connections.
CAPACITOR
Gain Error—This error represents the difference in the
slope between the actual and ideal transfer functions.
Linearity Error—The linearity error is the deviation of the
actual transfer function from an ideal straight line between
the data end points.
16-BIT MODE
20-BIT MODE
C1
2.2nF
10nF
C2
0.22nF
3.3nF
TABLE I. External Capacitor Values.
CALIBRATION
The DAC1220 offers a self-calibration mode which automatically calibrates the output offset and gain. The calibration is performed once and then normal operation is resumed. In general, calibration is recommended immediately
after power-on and whenever there is a “significant” change
in the operating environment. The amount of change which
should cause a re-calibration is dependent on the application. Where high accuracy is important, re-calibration should
be done on changes in temperature and power supply.
Least Significant Bit (LSB) Weight—This is the ideal
change in voltage that the analog output will change with a
change in the digital input code of 1 LSB.
Monotonicity—Monotonicity assures that the analog output will increase or stay the same for increasing digital input
codes.
Offset Error—The offset error is the difference between
the expected and actual output, when the output is zero. The
value is calculated from measurements made when
VOUT = 20mV.
After a calibration has been accomplished, the Offset Calibration Register (OCR) and the Full-Scale Calibration Register (FCR) contain the results of the calibration.
Note that the values in the calibration registers will vary
from configuration-to-configuration and from part to part.
Settling Time—The settling time is the time it takes the
output to settle to its new value after the digital code has
been changed.
fXIN—The frequency of the crystal oscillator or CMOScompatible input signal at the XIN input of the DAC1220.
®
5
Self-Calibration
Output Mode
A self-calibration is performed after the bits “01” have been
written to the Command Register Operation Mode bits
(MD1 through MD0) and a “1” has been written to the
Command Register sample-and-hold bit (SH). This initiates
a self-calibration on the next clock cycle. The offset correction code is determined by a repeated sequence of autozeroing the calibration comparator to the offset reference
and then comparing the DAC output to the offset reference
value. The end result is then averaged, Offset Two’s Complement adjusted, and placed in the OCR. The gain correction
is done in a similar fashion except the correction is done
against VREF to eliminate common-mode errors. The FCR
result represents the gain code and is not Offset Two’s
Complement adjusted.
The DAC1220 can operate in either 16-bit mode or 20-bit
mode. The mode is determined by setting (20-bit) or clearing
(16-bit) the RES bit in the CMR register.
The output of the DAC1220 can be synchronously reset. By
setting the CLR bit in the CMR, the data input register is
cleared to zero. This will result in an output of 0V when
DF = 1 or VREF when DF = 0, assuming no calibration errors.
The settling time is determined by the DISF, RES, and
ADPT bits of the command register. The default state of
DISF = 0 and ADPT = 0 enables fast settling, unless the
output step is small (≈ 40mV). However, the DAC1220 can
be forced to always use fast settling if the ADPT bit is
set to 1. If DISF is set to 1, all fast settling is disabled.
The SH bit of the CMR register determines if C2 is internally
connected to VREF. By clearing the SH bit, C2 is disconnected from VREF.
The CRST bit of the CMR register can be used to reset the
offset and calibration registers. By setting the CRST bit, the
contents of the calibration register are reset to 0.
The calibration function takes between 300ms and 500ms to
complete (for fXIN = 2.5MHz). Once calibration is initiated,
further writing of register bits is disabled until calibration
completes. The status of calibration can be verified by
reading the status of the Command Register Operation Mode
bits (MD1 through MD0). These bits will return to normal
mode “00” when calibration is complete.
REFERENCE INPUT
Self-calibration can be done with the output isolated or
connected. This is done by setting (output connected) or
clearing (output isolated) the CALPIN bit in the CMR
register.
The reference input voltage of 2.5V can be directly connected to VREF.
The recommended reference circuit for the DAC1220 is
shown in Figure 2.
+5V
+5V
0.10µF
7
100kΩ
2
6
1
10kΩ
3
+
REF1004-2.5
10µF
0.10µF
100Ω
To VREF Pin
OPA336
+
10µF
0.1µF
4
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DAC1220.
®
DAC1220
6
DIGITAL OPERATION
R/W (Read/Write) Bit—For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:
SYSTEM CONFIGURATION
The DAC1220 is controlled by 8-bit instruction codes (INSR)
and 16-bit command codes (CMR) via the serial interface,
which is externally clocked.
R/W
The DAC1220 Microcontroller (MC) consists of an ALU
and a register bank. The MC has three states: power-on reset,
calibration, and normal operation. In the power-on reset
state, the MC resets all the registers to their default states. In
the calibration state, the MC performs offset and gain selfcalibration. In the normal state, the MC performs D/A
conversions.
The DAC1220 has five internal registers, as shown in
Table II. Two of these, the Instruction Register (INSR) and
the Command Register (CMR), control the operation of the
converter. The Instruction register utilizes an 8-bit instruction code to control the serial interface to determine whether
the next operation is either a read or a write, to control the
word length and to select the appropriate register to
read/write. Communication with the DAC1220 is controlled
via the INSR. The INSR is written as the first part of each
serial communication. The instruction that is sent determines
what type of communication will occur next. It is not
possible to read the INSR. The Command register has a 16bit command code to set up the DAC1220 operation mode,
resolution mode, settling mode and data format. The Data
Input Register (DIR) contains the value for the next conversion. The Offset and Full-Scale Calibration Registers (OCR
and FCR) contain data used for correcting the internal
conversion value after it is placed into the DIR. The data in
these two registers may be the result of a calibration routine,
or they may be values which have been written directly via
the serial interface.
INSR
DIR
CMR
OCR
FCR
Instruction Register
Data Input Register
Command Register
Offset Calibration Register
Full-Scale Calibration Register
Read
MB1
MB0
0
0
1 Byte
0
1
2 Bytes
1
0
3 Bytes
A3 – A0 (Address) Bits—These four bits select the beginning register location that will be read from or written to, as
shown in Table III. Each subsequent byte will be read from
or written to the next higher location (increment address).
If the BD bit in the Command register is set, each subsequent byte will be read from or written to the next lower
location (decrement address). This bit does not affect INSR
register or the write operation for the CMR register. If the
next location is reserved in Table III, the results are unknown. Reading or writing continues until the number of
bytes specified by MB1 and MB0 have been transferred.
TABLE II. DAC1220 Registers.
Instruction Register (INSR)
Each serial communication starts with the 8 bits of the INSR
being sent to the DAC1220. The read/write bit, the number
of bytes n, and the starting register address are defined, as
shown in Table III. When the n bytes have been transferred,
the instruction is complete. A new communication cycle is
initiated by sending a new INSR (under restrictions outlined
in the Interfacing section).
R/W
Write
1
MB1, MB0 (Multiple Bytes) Bits—These two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:
8 Bits
24 Bits
16 Bits
24 Bits
24 Bits
MSB
0
A3
A2
A1
A0
0
0
0
0
Data Input Register Byte 2 MSB
0
0
0
1
Data Input Register Byte 1
0
0
1
0
Data Input Register Byte 0 LSB
0
0
1
1
Reserved
0
1
0
0
Command Register Byte 1 MSB
0
1
0
1
Command Register Byte 0 LSB
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Offset Cal Register Byte 2 MSB
1
0
0
1
Offset Cal Register Byte 1
1
0
1
0
Offset Cal Register Byte 0 LSB
1
0
1
1
Reserved
1
1
0
0
Full-Scale Cal Register Byte 2 MSB
1
1
0
1
Full-Scale Cal Register Byte 1
1
1
1
0
Full-Scale Cal Register Byte 0 LSB
1
1
1
1
Reserved
TABLE IV. A3 - A0 Addressing.
LSB
MB1
MB0
0
A3
A3
A1
A0
TABLE III. Instruction Register.
®
7
Command Register (CMR)
RES (Resolution) Bit—The Resolution bit selects either
16-bit or 20-bit resolution.
The CMR controls all of the functionality of the DAC1220.
The new configuration is latched in on the negative transition of SCLK for the last bit of the last byte of data being
written to the command register. The organization of the
CMR is comprised of 16 bits of information in 2 bytes of 8
bits each.
MSB
RES
0
1
CALPIN
SH
RES
CLR
DF
0
1
0
CRST
0
BD
MSB
MD1
MD0
Byte 0
LSB
DISF
Default
CLR (Clear) Bit—The CLR bit synchronously resets the
data input register to zero. The analog output will be based
on the DF bit—if 1, the output will be 0V; if 0, the output
will be VREF.
Byte 1
ADPT
16-Bit
20-Bit
CLR
NOTE: In order to obtain optimal performance, the default bit states for
the Command Register should be used (refer to Table VI). The only exception is the SH bit—the default bit state is 0, however, the bit should be
set to 1 for optimal performance.
0
1
Default
DF (Data Format) Bit—The DF bit controls the format of
the input data, shown in hexadecimal (either Offset Two’s
Complement or Straight Binary), as shown:
TABLE V. Command Register.
ADPT (Adaptive Filter Disable) Bit—The ADPT bit determines if the adaptive filter is enabled or disabled. When
the Adaptive Filter is enabled, the DAC1220 does fast
settling only when there is an output step of larger than
≈ 40mV. For small changes in the data, fast settling is not
necessary. When ADPT = 1, the Adaptive Filter is disabled
and the DAC1220 will not look at the size of a step to
determine the necessity of using fast settling. In either case,
fast settling can be defeated if DISF = 1.
Input Code
ADPT
0
1
OFF
ON
Offset Two's
Complement
DF = 0
(default)
Straight
Binary
DF = 1
VOUT
8000
0000
7FFF
0000
8000
FFFF
0
VREF
2 • VREF
DISF (Disable Fast Settling) Bit—The DISF bit disables
the fast settling option. If this bit is zero, the fast settling
performance is determined by the ADPT bit, the RES bit,
and the ADPT bit.
Enabled (default)
Disabled
CALPIN (Calibration Pin) Bit—The Calibration Pin bit
determines if the output is isolated or connected during
calibration.
DISF
0
1
Fast Settling (default)
Disable Fast Settling
CALPIN
0
Output Isolated
1
Output Connected
Default
BD (Byte Order) Bit—The BD bit controls the order in
which bytes of data are transferred (either most significant
byte first (MSBF) or least significant byte first (LSBF)), as
shown:
SH (Sample/Hold) Bit —The Sample-and-Hold bit determines if C2 is internally connected to VREF. For best performance, it is recommended to set this bit to 1.
BD bit:
0 (default)
register
1
0 (default)
read
1
write
SH
INSR
write only
write only
MSBF
MSBF
0
1
CMR
DIR
OCR
FCR
MSBF
MSBF
MSBF
MSBF
LSBF
LSBF
LSBF
LSBF
MSBF
MSBF
MSBF
MSBF
MSBF
LSBF
LSBF
LSBF
Disconnected
Connected
Default
Recommended
CRST (Calibration Reset) Bit—The CRST bit resets the
offset and full-scale calibration registers.
Care must be observed in reading the Command Register if
the state of the BD bit is unknown. If a two byte read is
started at address 0100 with BD = 0, it will read the contents
at address 0100, then 0101. However, if BD = 1, it will read
from 0100, then 0011. If the BD bit is unknown, all reads of
the command register are best performed as read commands
of one byte.
CRST
0
1
OFF
Reset
Default
®
DAC1220
8
MSB (Bit Order) Bit—The MSB bit controls the order in
which bits within a byte of data are read or written (either
most significant bit first or least significant bit first) as
follows:
Full-Scale Calibration Register (FCR)
The FCR is a 24-bit register which contains the full-scale
correction factor that is applied to the digital input before it
is transferred to the modulator. The contents of this register
will be the result of a self-calibration, or written to by the
user.
MSB
0
1
MSB-First
LSB-First
Default
The FCR is both readable and writable via the serial interface. For applications requiring an accurate system calibration, a system calibration can be performed, the results
averaged, and a more precise value written back to the FCR.
MD1 - MD0 (Operating Mode) Bits—The Operating Mode
bits control the calibration functions of the DAC1220. The
Normal mode is used to perform conversions. The SelfCalibration mode is a one-step calibration sequence that
calibrates both the offset and full scale.
MD1
MD0
0
0
1
1
0
1
0
1
The actual FCR value after calibration will change from part
to part and with configuration, temperature, and power
supply.
In addition, be aware that the contents of the FCR are not
used to directly correct the digital input. Rather, the correction is a function of the FCR value. This function is linear
and two known points can be used as a basis for interpolating intermediate values for the FCR. The contents of the
FCR are in unsigned binary format. This is not affected by
the DF bit in the Command register.
Normal Mode
Self-Cal
Sleep
X
Offset Calibration Register (OCR)
MSB
The OCR is a 24-bit register containing the offset correction
factor that is used to apply a correction to the digital input
before it is transferred to the modulator. The results of the
self-calibration process will be written to this register.
The OCR is both readable and writable via the serial interface. For applications requiring a more accurate calibration,
a calibration can be performed, the results averaged, and a
more precise offset calibration value written back to the
OCR.
FCR23
FCR15
FCR7
OCR21
OCR20
FCR14
FCR13
FCR6
FCR5
OCR18
OCR17
OCR14
OCR13
OCR12
OCR6
OCR5
OCR4
FCR16
FCR12
FCR11
FCR10
FCR9
FCR8
FCR4
FCR3
FCR2
FCR1
FCR0
LSB
OCR16
DIR23
Byte 2
DIR22
DIR21
DIR20
DIR19
DIR18
DIR17
DIR16
DIR11
DIR10
DIR9
DIR8
DIR3
DIR2
DIR1
DIR0
Byte 1
OCR11
OCR10
OCR9
Byte 0
OCR7
FCR17
The DIR is a 24-bit register which contains the digital input
value (see Table VIII). The register is latched on the falling
edge of the last bit of the last byte sent. The contents of the
DIR are then loaded into the modulator. This means that the
DIR register can be updated after sending 1, 2, or 3 bytes,
which is determined by the MB1 and MB0 bits in the
Instruction Register. The contents of the DIR can be Offset
Two’s Complement or Straight Binary.
Byte 1
OCR15
FCR18
Data Input Register (DIR)
MSB
OCR19
FCR19
TABLE VII. Full-Scale Calibration Register.
Byte 2
OCR22
FCR20
Byte 0
The results of calibration are averaged, Offset Two's Complement adjusted, and placed in the OCR.
MSB
FCR21
Byte 1
The actual OCR value after calibration will change from part
to part and with configuration, temperature, and power supply.
In addition, be aware that the contents of the OCR are not
used to directly correct the digital input. Rather, the correction is a function of the OCR value. This function is linear
and two known points can be used as a basis for interpolating intermediate values for the OCR.
OCR23
Byte 2
FCR22
OCR8
DIR15
DIR14
DIR13
DIR7
DIR6
DIR5
LSB
OCR3
OCR2
OCR1
DIR12
Byte 0
OCR0
TABLE VI. Offset Calibration Register.
DIR4
LSB
TABLE VIII. Data Input Register.
®
9
SLEEP MODE
Reset, Power-On Reset and Brown-Out
The Sleep Mode is entered after the bit combination 10 has
been written to the CMR Operation Mode bits (MD1 and
MD0). This mode ends when these bits are changed to a
value other than 10.
The DAC1220 contains an internal power-on reset circuit. If
the power supply ramp rate is greater than 50mV/ms, this
circuit will be adequate to ensure the device powers up
correctly. Due to oscillator settling considerations, communication to and from the DAC1220 should not occur for at
least 25ms after power is stable.
If this requirement cannot be met or if the circuit has brownout considerations, the timing diagram of Figure 3 can be
used to reset the DAC1220. This accomplishes the reset by
controlling the duty cycle of the SCLK input.
Communication with the DAC1220 can continue during
Sleep Mode. When a new mode (other than Sleep) has been
entered, the DAC1220 will execute a very brief internal
power-up sequence of the analog and digital circuitry. In
addition, the settling of the external VREF and other circuitry
must be taken into account to determine the amount of time
required to resume normal operation.
Sleep mode is the default state after power on or reset. The
output is high impedance during sleep mode.
I/O Recovery
The output is turned off in sleep mode.
If serial communication stops during an instruction or data
transfer for longer than 100ms (for fXIN = 2.5MHz), the
DAC1220 will reset its serial interface. This will not affect
the internal registers. The main controller must not continue
the transfer after this event, but must restart the transfer from
the beginning. This feature is very useful if the main controller can be reset at any point. After reset, simply wait 200ms
(for fXIN = 2.5MHz) before starting serial communication.
Isolation
SERIAL INTERFACE
The DAC1220 includes a flexible serial interface which can
be connected to microcontrollers and digital signal processors in a variety of ways. Along with this flexibility, there is
also a good deal of complexity. This section describes the
trade-offs between the different types of interfacing methods
in a top-down approach—starting with the overall flow and
control of serial data, moving to specific interface examples,
and then providing information on various issues related to
the serial interface.
The serial interface of the DAC1220 provides for simple
isolation methods. An example of an isolated two-wire
interface is shown in Figure 4.
t1: > 512 • tXIN
< 800 • tXIN
Reset On
Falling Edge
t2
t2: > 10 • tXIN
t2
t3: > 1024 • tXIN
< 1800 • tXIN
SCLK
t1
t3
t4
t4: ≥ 2048 • tXIN
< 2400 • tXIN
FIGURE 3. Resetting the DAC1220.
Isolated
Power
DVDD
DAC1220
C1
12pF
1
DVDD
SCLK
16
2
XOUT
SDIO
15
3
XIN
CS
14
4
DGND
AGND
13
5
AVDD
VREF
12
6
DNC
VOUT
11
7
DNC
C2
10
8
DNC
C1
9
XTAL
C2
12pF
AVDD
P1.1
Opto
Coupler
P1.0
VREF
8051
= Isolated
VOUT
C2
C1
= DGND
= AGND
FIGURE 4. Isolation for Two-Wire Interface
®
DAC1220
Opto
Coupler
10
Using CS
TIMING
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other. The CS
signal does not directly control the tri-state condition of the
SDIO output. These signals are normally in the tri-state
condition. They only become active when serial data is
being transmitted from the DAC1220. If the DAC1220 is in
the middle of a serial transfer and the SDIO is an output,
taking CS HIGH will not tri-state the output signal.
The maximum serial clock frequency cannot exceed the
DAC1220 XIN frequency divided by 10. Table IX and
Figures 5 through 9 define the basic digital timing characteristics of the DAC1220. Figure 5 and the associated timing
symbols apply to the XIN input signal. Figures 6 through 9
and associated timing symbols apply to the serial interface
signals (SCLK, SDIO, and CS). The serial interface is
discussed in detail in the Serial Interface section.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, the CS signal must be used. The CS
signal is then used to enable communication with the
DAC1220.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
fXIN
XIN Clock Frequency
1
NOM
2.5
MHz
tXIN
XIN Clock Period
400
1000
t1
XIN Clock High
0.4 • tXIN
ns
t2
XIN Clock LOW
0.4 • tXIN
ns
t3
SCLK HIGH
5 • tXIN
ns
t4
SCLK LOW
5 • tXIN
ns
t5
Data In Valid to SCLK Falling Edge (Setup)
40
ns
t6
SCLK Falling Edge to Data In Not Valid (Hold)
20
ns
t7
Data Out Valid After Rising Edge of SCLK (Hold)
0
t8
SCLK Rising Edge to New Data Out Valid (Delay)(1)
t9
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data
13 • tXIN
t10
Falling Edge of CS to Rising Edge of SCLK
11 • tXIN
t11
Falling Edge of Last SCLK for INSR to SDIO as Output
8 • tXIN
t12
SDIO as Output to Rising Edge of First SCLK for Register Data
t13
Falling Edge of Last SCLK for Register Data to SDIO Tri-State
4 • tXIN
t14
Falling Edge of Last SCLK for Register Data to Rising Edge
of First SCLK of next INSR (CS Tied LOW)
41 • tXIN
ns
t15
Rising Edge of CS to Falling Edge of CS (Using CS)
22 • tXIN
ns
ns
ns
50
ns
ns
ns
ns
10 • tXIN
4 • tXIN
ns
ns
6 • tXIN
ns
NOTE: (1) With 10pF load.
TABLE IX. Digital Timing Characteristics.
®
11
t3
t4
tXIN
t1
t5
SCLK
t2
t6
XIN
t7
SDIO
t8
FIGURE 5. XIN Clock Timing.
FIGURE 6. Serial Input/Output Timing.
t9
t14
SCLK
SDIO
IN7
IN1
IN0
INM
IN1
IN0
IN7
OUT1
OUT0
IN7
Write Register Data
SDIO
IN7
IN1
IN0
OUTM
Read Register Data
FIGURE 7. Serial Interface Timing (CS LOW).
t15
CS
t10
t10
t9
SCLK
IN7
SDIO
IN1
IN0
INM
IN1
IN0
IN7
OUTM
OUT1
OUT0
IN7
Write Register Data
IN7
SDIO
IN1
IN0
Read Register Data
FIGURE 8. Serial Interface Timing (using CS).
CS
t11
t10
SCLK
t12
t13
IN7
SDIO
IN0
OUT MSB
t9
SDIO is an input
SDIO is an output
FIGURE 9. SDIO Input to Output Transition Timing.
®
DAC1220
12
OUT0
From Read
flowchart
To Write
flowchart
Start
Writing
Start
Reading
CS taken HIGH
for t15 periods
minimum
(or CS tied LOW)
CS taken HIGH
for t15 periods
minimum
(or CS tied LOW)
CS
state
CS
state
HIGH
LOW
CS
state
External device
generates 8
serial clock cycles
and transmits
instruction register
data via SDIO
LOW
HIGH
No
End
CS
state
External device
generates 8 serial
clock cycles and
transmits instruction
register data
via SDIO
LOW
External device
generates n
serial clock cycles
and transmits
specified
register data
via SDIO
More
instructions?
HIGH
HIGH
LOW
SDIO input to
output transition
External device
generates n serial
clock cycles and
receives specified
register data via SDIO
Yes
Is next
instruction
a read?
No
SDIO transitions to
tri-state condition
Yes
To Read
flowchart
More
instructions?
No
End
Yes
Is next
instruction
a Write?
No
Yes
To Write
flowchart
FIGURE 10. Flowchart for Writing and Reading Register Data.
®
13
LAYOUT
GROUNDING
POWER SUPPLIES
The analog and digital sections of the design should be
carefully and cleanly partitioned. Each section should have
its own ground plane with no overlap between them. AGND
should be connected to the analog ground plane, as well as
all other analog grounds. DGND should be connected to the
digital ground plane, and all digital signals referenced to this
plane.
The DAC1220 requires the digital supply (DVDD) to be no
greater than the analog supply (AVDD) +0.3V. In the majority of systems, this means that the analog supply must come
up first, followed by the digital supply and VREF. Failure to
observe this condition could cause permanent damage to the
DAC1220.
The DAC1220 pinout is such that the converter is cleanly
separated into an analog and digital portion. This should
allow simple layout of the analog and digital sections of the
design.
Inputs to the DAC1220, such as SDIO or VREF, should not
be present before the analog and digital supplies are on.
Violating this condition could cause latch-up. If these signals are present before the supplies are on, series resistors
should be used to limit the input current.
For a single converter system, AGND and DGND of the
DAC1220 should be connected together, underneath the
converter. Do not join the ground planes. Instead, connect
the two with a moderate signal trace. For multiple converters, connect the two ground planes at one location, as central
to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect
the two planes together. The printed circuit board can be
designed to provide different analog/digital ground connections via short jumpers. The initial prototype can be used to
establish which connection works best.
The best scheme is to power the analog section of the design
and AVDD of the DAC1220 from one +5V supply, and the
digital section (and DVDD) from a separate +5V supply. The
analog supply should come up first. This will ensure that
SCLK, SDIO, CS and VREF do not exceed AVDD, that the
digital inputs are present only after AVDD has been established, and that they do not exceed DVDD.
The analog supply should be well regulated and low noise.
For designs requiring very high resolution from the DAC1220,
power supply rejection will be a concern. See the “PSRR vs
Frequency” curve in the Typical Performance Curves section of this data sheet for more information.
DECOUPLING
Good decoupling practices should be used for the DAC1220
and for all components in the design. All decoupling capacitors, and specifically the 0.1µF ceramic capacitors, should
be placed as close as possible to the pin being decoupled. A
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic
capacitor, should be used to decouple AVDD to AGND. At
a minimum, a 0.1µF ceramic capacitor should be used to
decouple DVDD to DGND, as well as for the digital supply
on each digital component.
The requirements for the digital supply are not as strict.
However, high frequency noise on DVDD can capacitively
couple into the analog portion of the DAC1220. This noise
can originate from switching power supplies, very fast
microprocessors, or digital signal processors.
If one supply must be used to power the DAC1220, the
AVDD supply should be used to power DVDD. This connection can be made via a 10Ω resistor which, along with the
decoupling capacitors, will provide some filtering between
DVDD and AVDD. In some systems, a direct connection can
be made. Experimentation may be the best way to determine
the appropriate connection between AVDD and DVDD.
®
DAC1220
14
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