GM71C4263C GM71CS4263CL LG Semicon Co.,Ltd. 262,144 WORDS x 16 BIT CMOS DYNAMIC RAM Description Features The GM71C(S)4263C/CL is the new generation dynamic RAM organized 262,144 x 16 bit. GM71C(S)4263C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)4263C/CL offers Extended Data Out(EDO) Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)4263C/CL to be packaged in standard 400 mil 40 pin plastic SOJ. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. * 262,144 Words x 16 Bit Organization * Extended Data Out (EDO) Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time (Unit: ns) Pin Configuration tRAC tCAC tRC tHPC GM71C(S)4263C/CL-60 GM71C(S)4263C/CL-70 GM71C(S)4263C/CL-80 60 70 80 17 20 20 104 124 144 25 30 35 * Low Power Active : 715/660/605 mW(MAX) Standby : 5.5mW (CMOS level : MAX) 1.1mW (L-version) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 512 Refresh Cycles/8§Â * 512 Refresh Cycles/128§Â (L-version) * Battery Back Up Operation (L-version) * 2 CAS byte Control * Self-Refresh Operation (L-version) 40 SOJ VCC 1 40 VSS I/O0 I/O1 I/O2 I/O3 2 39 3 38 4 37 5 36 I/O15 I/O14 I/O13 I/O12 VCC 6 35 VSS I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 7 34 8 33 VCC 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 20 21 VSS (Top View) 1 GM71C4263C GM71CS4263CL LG Semicon Pin Description Pin Function Pin Function A0-A8 Address Inputs WE Read/Write Enable A0-A8 Refresh Address Inputs OE Output Enable Data Input / Data Output VCC Power (+5V) Row Address Strobe VSS Ground Column Address Strobe NC No Connection I/O0-I/O15 RAS UCAS, LCAS Ordering Information 2 Type No. Access Time Package GM71C4263CJ-60 GM71C4263CJ-70 GM71C4263CJ-80 60ns 70§À 80§À 400 Mil 40 Pin Plastic SOJ GM71CS4263CLJ-60 GM71CS4263CLJ-70 GM71CS4263CLJ-80 60ns 70§À 80§À 400 Mil 40 Pin Plastic SOJ GM71C4263C GM71CS4263CL LG Semicon Absolute Maximum Ratings* Symbol Parameter Rating Unit 0 ~ 70 C TA Ambient Temperature under Bias TSTG Storage Temperature (Plastic) -55 ~ 125 C VIN/VOUT Voltage on any Pin Relative to VSS -1.0 ~ 7.0 V VCC Voltage on VCC Relative to VSS -1.0 ~ 7.0 V IOUT Short Circuit Output Current 50 mA PD Power Dissipation 1.0 W Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Recommended DC Operating Conditions* (TA = 0 ~ 70C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - 6.5 V VIL Input Low Voltage -1.0 - 0.8 V Note: All voltage referred to Vss Truth Table RAS LCAS UCAS WE OE I/O0-I/O7 I/O8-I/O15 Operation H H H H H High-Z High-Z Standby L H H H H High-Z High-Z Refresh L L H H L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care Lower Byte Write L H L L H Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z H to L L H - - High-Z High-Z H to L H L - - High-Z High-Z H to L L L - - High-Z High-Z CBR Refresh or Self Refresh 3 GM71C4263C GM71CS4263CL LG Semicon DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C) Symbol Parameter Min Max Unit Note VOH Output Level Output "H" Level Voltage (IOUT = -2mA) 2.4 VCC V VOL Output Level Output "L" Level Voltage (IOUT = 2mA) 0 0.4 V ICC1 Operating Current Average Power Supply Operating Current (RAS, LCAS or UCAS Cycling: tRC = tRC min) 60§À - 130 70§À - 120 80§À - 110 - 2 60§À - 130 70§À - 120 80§À - 110 60§À - 130 70§À - 120 80§À - 110 - ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 Standby Current (TTL) Power Supply Standby Current (RAS, LCAS, UCAS = VIH, DOUT = High-Z) RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (tRC = tRC min) EDO mode current Average Power Supply Current (tHPC = tHPC min) mA 1, 3 1 mA 4 - 200 uA 4,5 60§À - 130 70§À - 120 80§À - 110 Battery Back Up Current (Standby with CBR Refresh) ICC9 II(L) IO(L) Standby Current RAS = VIH LCAS or UCAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, LCAS, UCAS <=0.2V, DOUT = High-Z) Input Leakage Current Any Input (0V<=VIN<=6.5V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<=6.5V) mA 300 § Ë 4, 5 - 5 mA 1 - 200 uA 6 -10 10 uA -10 10 uA - Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while LCAS and UCAS = VIH. 4. VIH>=VCC-0.2V, 0<=VIL<=0.2V, Address can be changed once or less while RAS=VIL. 5. L-version. 6. Self-refresh series. (GM71CS4263CL) 4 mA 2 (tRC=125¥ìS , tRAS<=1¥ìS , WE, OE=VIH, LCAS, UCAS=VIL, DOUT=High-Z) ICC8 1, 2 mA Standby Current (CMOS) Power Supply Standby Current (RAS, LCAS, UCAS, WE, OE>=VCC-0.2V, DOUT=High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) mA GM71C4263C GM71CS4263CL LG Semicon Capacitance (VCC = 5V+/-10%, TA = 25C) Parameter Symbol Min Max Unit Note CI1 Input Capacitance (Address) - 5 §Ü 1 CI2 Input Capacitance (Clocks) - 7 §Ü 1 CI/O Output Capacitance (Data-In/Out) - 7 §Ü 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. OE= VIH to disable DOUT. AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 17, 18) Test Conditions Input rise and fall times : 2ns Input level : VIL = 0V , VIH = 3.0V Input timing reference level : 0.8V, 2.4V Output timing reference level : 0.8V, 2.0V Output load : 1TTL gate + CL (100pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80 Unit Note Min Max Min Max Min Max 124 - 144 - §À 50 - 60 - §À 13 - 15 - §À tRC Random Read or Write Cycle Time 104 tRP tCP RAS Precharge Time 40 CAS Precharge Time 10 tRAS RAS Pulse Width 60 10,000 70 10,000 80 10,000 §À tCAS CAS Pulse Width 12 13 10,000 15 10,000 §À tASR Row Address Set-up Time 0 - 0 - 0 - §À tRAH Row Address Hold Time 10 - 10 - 10 - §À tASC Column Address Set-up Time 0 - 0 - 0 - §À 19 tCAH Column Address Hold Time 10 13 - 15 - §À 19 tRCD RAS to CAS Delay Time 20 43 20 50 20 55 §À 8 tRAD RAS to Column Address Delay Time 15 30 15 35 15 40 §À 9 tRSH RAS Hold Time 15 - 18 - 20 - §À tCSH CAS Hold Time 48 - 58 - 68 - §À tCRP CAS to RAS Precharge Time 5 - 5 - 5 - §À 20 tODD OE to DIN Delay Time 15 - 18 - 20 - §À 24 tDZO OE Delay Time from DIN 0 - 0 - 0 - §À 25 tDZC CAS Setup Time from DIN 0 - 0 - 0 - §À 25 tT Transition Time (Rise and Fall) 2 50 2 50 2 50 §À 7 tREF Refresh Period - 8 - 8 - 8 §Â Refresh Period (L-version) - 128 - 128 - 128 §Â - 22 5 GM71C4263C GM71CS4263CL LG Semicon Read Cycle Symbol Parameter GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80 Min Max Min Max Min Max Unit Note tRAC Access Time from RAS - 60 - 70 - 80 §À 2, 3 tCAC Access Time from CAS - 17 - 20 - 20 §À 3, 4, 13 tAA Access Time from Address - 30 - 35 - 40 §À 3, 5, 13 tOAC Access Time from OE - 15 - 18 - 20 §À 3 tRCS Read Command Setup Time 0 - 0 - 0 - §À 19 tRCH Read Command Hold Time to CAS 0 - 0 - 0 - §À 16, 19 tRRH Read Command Hold Time to RAS 0 - 0 - 0 - §À 16 tRAL Column Address to RAS Lead Time 30 - 35 - 40 - §À tCAL Column Address to CAS Lead Time 30 - 35 - 40 - §À tCLZ CAS to Output in Low-Z 0 - 0 - 0 - §À tOH Output Data Hold Time 5 - 5 - 5 - §À tOHO Output Data Hold Time from OE 5 - 5 - 5 - §À tOFF Output Buffer Turn-off Time 0 15 0 20 0 20 §À 6 tOEZ Output Buffer Turn-off Time from OE 0 15 0 20 0 20 §À 6 tCDD CAS to DIN Delay Time 15 - 18 - 20 - §À 24 tOHR Output Data Hold Time from RAS 5 - 5 - 5 - §À tOFR Output Buffer Turn-off Time from RAS 0 15 0 15 0 15 §À 6 tWEZ Output Buffer Turn-off Time from WE 0 15 0 15 0 15 §À 6 tWDD WE to DIN Delay Time 15 - 18 - 20 - §À tRDD RAS to DIN Delay Time 15 - 18 - 20 - §À Write Cycle Symbol 6 Parameter GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80 Min Max Min Max Min Max Unit Note tWCS tWCH Write Command Setup Time 0 - 0 - 0 - §À 10, 19 Write Command Hold Time 10 - 13 - 15 - §À 19 tWP Write Command Pulse Width 10 - 10 - 10 - §À tRWL tCWL tDS Write Command to RAS Lead Time 10 - 13 - 15 - §À Write Command to CAS Lead Time 10 - 13 - 15 - §À 21 Data-in Setup Time 0 - 0 - 0 - §À 11, 21 tDH Data-in Hold Time 10 - 13 - 15 - §À 11, 21 GM71C4263C GM71CS4263CL LG Semicon Read- Modify-Write Cycle Symbol Parameter GM71C(S)4263 C/CL-60 GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80 Min Max Min Max Min Max Unit Note tRWC Read-Modify-Write Cycle Time 133 - 159 - 183 - §À tRWD RAS to WE Delay Time 77 - 90 - 102 - §À 10 tCWD CAS to WE Delay Time 32 - 38 - 42 - §À 10 tAWD Column Address to WE Delay Time 47 - 55 - 62 - §À 10 tOEH OE Hold Time from WE 15 - 18 - 20 - §À Refresh Cycle Symbol Parameter tCSR CAS Setup Time (CAS-before-RAS Refresh Cycle) tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) tRPC RAS Precharge to CAS Hold Time GM71C(S)4263 C/CL-60 Min Max GM71C(S)4263 C/CL-70 GM71C(S)4263 C/CL-80 Min Max Min Max Unit Note - 10 - 10 - §À 19 10 - 10 - 10 - §À 20 10 - 10 - 10 - §À 19 Unit Note 10 EDO Mode Cycle Symbol Parameter GM71C(S)4263 C/CL- 60 GM71C(S)4263 C/CL- 70 GM71C(S)4263 C/CL- 80 Min Max Min Max Min Max tHPC EDO Mode Cycle Time 25 - 30 - 35 - §À 26 tRASP EDO Mode RAS Pulse Width 60 100,000 70 100,000 80 100,000 §À 12 tACP Access Time from CAS Precharge - 35 - 40 - 45 §À 3, 13, 20 tRHCP RAS Hold Time from CAS Precharge 35 - 40 - 45 - §À tCPW EDO Mode Read-Modify-Write Cycle CAS Precharge to WE Delay Time 52 - 60 - 67 - §À tHPRWC EDO Mode Read-Modify-Write Cycle Time 66 - 75 - 85 - §À tCOL CAS hold time referred OE 10 - 13 - 15 - §À tCOP CAS to OE setup time Read command hold time from CAS Precharge 5 - 5 - 5 - §À 35 - 40 - 45 - §À 5 - 5 - 5 - §À tRCHP tDOH Output data hold time from CAS low 10,20 7 GM71C4263C GM71CS4263CL LG Semicon Self-Refresh Mode Symbol Parameter GM71CS4263 CL-60 GM71CS4263 CL-70 GM71CS4263 CL-80 Min Max Min Max Min Max Unit tRASS RAS Pulse Width (Self-Refresh) 100 - 100 - 100 - ns tRPS RAS Precharge Time (Self-Refresh) 110 - 130 - 150 - §À tCHS CAS Hold Time (Self-Refresh) -50 - -50 - -50 - §À Note 21 Notes: 1. AC Measurements assume tT = 2§À. 2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 100§Ü. 4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max). 5. Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max). 6. tOFF(max), tOEZ(max), tOFR(max), and tWEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 10. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only ; if tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read modify write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to UCAS and LCAS leading edge in early write cycle and to WE leading edge in a delayed write or a read modify write cycle. 12. tRASP defines RAS pulse width in EDO mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP. 14. An initial pause of 100¥ìS is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 8 LG Semicon GM71C4263C GM71CS4263CL 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH > tCWL , the I/O pin will remain open circuit (high impedance ); if tOEH > tCWL , invalid data will be out at each I/O. 16. Either tRCH or tRRH must be satisfied for a read cycle. 17. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 18. All the VCC and VSS pins shall be supplied with the same voltages. 19. tASC, tCAH, tRCS, tRCH, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. 20. tCRP, tCHR, tACP and tCPW are determined by the later rising edge of UCAS or LCAS. 21. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS. 22. tCP is determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 24. Either tODD or tCDD must be satisfied. 25. Either tDZO or tDZC must be satisfied. 26. tHPC (min) can be achieved during a series of EDO mode write cycles or EDO mode read cycles. If both write and read operation are mixed in a EDO mode RAS cycle (EDO mode mix cycle (1), (2)), minimum value of CAS cycle ( tCAS + tCP +2tT ) becomes greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO mode is shown in EDO mode mix cycle(1) and (2). 9 GM71C4263C GM71CS4263CL LG Semicon Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1) Each of the UCAS/LCAS should satisfy the timing specifications individually. 2) Different operation mode for upper/lower byte is not allowed; such as following. RAS UCAS Delay Write LCAS Early Write WE 3) Closely separated upper/lower byte control is not allowed. However when the condition(tCP<=tUL) is satisfied, EDO page mode can be performed. RAS UCAS LCAS tUL 4) Byte control operation by remaining LCAS or UCAS high is guaranteed. 10 GM71C4263C GM71CS4263CL LG Semicon Timing Waveforms tRC tRP tRAS RAS tCSH tCRP tRCD tRSH tCAS tT UCAS tOFR tOHR LCAS tRAD tRAL tCAL tASR ADDRESS tRAH tASC ROW tCAH tRDD COLUMN tRRH tRCHR tRCS tRCH tWEZ WE tDZC tWDD tCDD High-Z DIN tDZO tODD tOAC OE tOEZ tOHO tCAC tAA tOFF tOH tRAC tCLZ High-Z DOUT DOUT INVALID DOUT * : Don’t care FIGURE 1. READ CYCLE 11 GM71C4263C GM71CS4263CL LG Semicon tRC tRAS tRP RAS tRSH tT tRCD tCAS tCRP tCSH UCAS LCAS tASR ADDRESS tRAH tASC ROW tCAH COLUMN tWCS tWCH WE tDS DIN tDH DIN High-Z*** DOUT * : Don’t care ** OE : Don’t care > tWCS (min) *** tWCS = FIGURE 2. EARLY WRITE CYCLE 12 GM71C4263C GM71CS4263CL LG Semicon tRC tRAS tRP RAS tRSH tT tRCD tCAS tCRP tCSH UCAS LCAS tASR ADDRESS tRAH tCAH tASC ROW COLUMN tCWL tRCS tRWL tWP WE tDZC tDS High-Z DIN DIN tODD tDZO tDH tOEH OE tOEZ tCLZ DOUT High-Z INVALID DOUT * : Don’t care FIGURE 3. DELAYED WRITE CYCLE *Note : In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance); if tOEH<=tCWL, invalid data will be out at each I/O. 13 GM71C4263C GM71CS4263CL LG Semicon tRWC tRAS tRP RAS tT tRCD tCAS tCRP UCAS LCAS tRAD tASR ADDRESS tRAH tCAH tASC ROW COLUMN tCWL tRWL tWP tCWD tRCS tAWD tRWD WE tDZC tDS High-Z DIN DIN tODD tDZO tDH tOEH tOAC OE tCAC tAA tRAC tOEZ tOHO High-Z DOUT DOUT INVALID DOUT tCLZ * : Don’t care FIGURE 4. READ MODIFY WRITE CYCLE *Note : In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance); if tOEH<=tCWL, invalid data will be out at each I/O. 14 GM71C4263C GM71CS4263CL LG Semicon tRC tRAS tRP RAS tT tCRP tRPC tCRP UCAS LCAS tASR tRAH ADDRESS ROW tOFR tOFF DOUT INVALID DOUT High-Z * : Don’t care ** OE, WE : Don’t care FIGURE 5. RAS ONLY REFRESH CYCLE 15 GM71C4263C GM71CS4263CL LG Semicon tRC tRP tRAS tRC tRP tRAS tRP RAS tRPC tCP tT tCSR tRPC tCHR tCP tCRP tCSR tCHR UCAS LCAS ADDRESS tOFF DOUT INVALID DOUT tOFR High-Z * : Don’t care ** OE , WE : Don’t care FIGURE 6. CAS BEFORE RAS REFRESH CYCLE 16 GM71C4263C GM71CS4263CL LG Semicon tRC tRC tRAS tRP tRAS tRC tRP tRAS tRP RAS tT tRCD tRSH tCHR tCRP UCAS LCAS tRAD tASR ADDRESS tRAH tRAL tCAH tASC ROW COLUMN tRRH tRCS tRCH WE tWDD High-Z DIN tRDD tDZC tDZO tCDD tODD tOAC OE tOEZ tWEZ tCAC tAA tOFF tOH tRAC tCLZ tOHO High-Z DOUT DOUT INVALID DOUT tOHR * tOFR : Don’t care FIGURE 7. HIDDEN REFRESH CYCLE 17 GM71C4263C GM71CS4263CL LG Semicon tRASP tRP tRHCP RAS tT tHPC tCSH tRCD tCAS tCP tRSH tCAS tCP tCAS tCRP UCAS LCAS tRAD tASR ADDRESS tRAH ROW tCAL tASC tCAL tCAH tASC COLUMN 1 tCAH COLUMN 2 tRAL tASC tCAH COLUMN N tRCH tRCHP tRCS tRRH WE tCAL tACP tAA tCAC tOAC OE tACP tAA tCAC tRAC tAA tCAC tOEZ tOH tDOH DOUT High-Z DOUT 1 INVALID DOUT tWEZ tOHR tOFR tOFF INVALID DOUT tDOH DOUT 2 DOUT N INVALID DOUT * : Don’t care FIGURE 8. EXTENDED DATA OUT MODE READ CYCLE 18 GM71C4263C GM71CS4263CL LG Semicon tRP tRASP tRHCP RAS tT tHPC tCSH tCP LCAS tCP tCAS tRSH tCAS tCAS tRCHR tRCHP tRCH tRCS tCRP tHPC tCP tCAS UCAS tHPC tRRH tRCS tRCH WE tWDD tRAL tASC tCAH tASR ADDRESS tASC tASC tCAH tCAH tASC tRDD tCDD tCAH tRAH ROW COLUMN 1 COLUMN 2 tCAL COLUMN 3 tCAL COLUMN N tCAL tCAL tOFR tOFF tOHR tDZC tOH High-Z DIN tDZO tCOL tODD tCOP OE tACP tOAC tCAC tAA tRAC tWEZ DOUT High-Z DOUT 1 tAA tOEZ tACP tAA tCAC tCAC tOHO tOAC DOUT 2 tDOH DOUT 2 tACP tAA tOEZ tOHO DOUT 3 tOAC tOEZ tOHO tCAC DOUT N INVALID DOUT * : Don’t care FIGURE 9. EXTENDED DATA OUT MODE READ CYCLE (OE CONTROL) *Note : EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high during CAS high, the data will not come out until next CAS access. When WE goes low during CAS high, the data will not come out until next CAS access. 19 GM71C4263C GM71CS4263CL LG Semicon tRP tRASP RAS tT tHPC tCSH tCP tCP tCP tCRP tHPC tCAS tRSH tCAS tCAS LCAS tHPC tCAS UCAS tASR tASC tRAH tASC ADDRESS tASC tCAH COLUMN 1 ROW tDZC tRCS tCAH tCAH COLUMN 2 tCAH COLUMN 4 COLUMN 3 tRCHP tCAL tCAL tCAL tCAL tASC tRRH tRCH WE tWDD High - Z DIN tDZO tCAC tCAC tAA tDOH OE tRAC LDOUT High - Z tOAC tAA tACP High - Z tCOP tOEZ tOEZ tOHO DOUT 1 tODD tCAC tAA tOAC tOHO DOUT 2 INVALID DOUT UDOUT tCOL tOAC tACP DOUT 2 tAA tOEZ tOHO tOFF tOH tOFR DOUT 4 tCAC tOHR tACP DOUT 1 DOUT 3 DOUT 4 * : Don’t care FIGURE 10. EXTENDED DATA OUT MODE READ CYCLE (2CAS TYPE) 20 GM71C4263C GM71CS4263CL LG Semicon tRP tRASP RAS tT tCSH tHPC tRCD tCAS tCP tRSH tCAS tCRP tCP tCAS UCAS LCAS tASR tRAH ADDRESS tASC ROW tCAH COLUMN 1 tWCS tWCH tASC tASC tCAH COLUMN 2 tWCS tCAH COLUMN N tWCH tWCS tWCH WE tDS DIN tDH DIN 1 tDS tDH tDS DIN 2 tDH DIN N High-Z** DOUT * OE : Don’t care ** tWCS >=tWCS (min) *** : Don’t care FIGURE 11. EXTENDED DATA OUT MODE EARLY WRITE CYCLE 21 GM71C4263C GM71CS4263CL LG Semicon tRASP tRP RAS tCP tT tCP tCSH tCRP tHPC tRCD tCAS tRSH tCAS tCAS UCAS LCAS tRAD tASR tASC tRAH ADDRESS ROW tASC tCAH tASC tCAH tCAH COLUMN 1 COLUMN 2 tCWL tRCS COLUMN N tCWL tRCS tCWL tRWL tRCS WE tWP tDZC tDS tWP tDS tDZC tDH DIN tDH tDZO tODD tOEH tDH DIN 2 DIN 1 tDZO tWP tDS tDZC High-Z DIN N tDZO tODD tOEH tODD tOEH OE tCLZ tCLZ tCLZ tOEZ tOEZ tOEZ High-Z DOUT INVALID DOUT INVALID DOUT INVALID DOUT * : Don’t care FIGURE 12. EXTENDED DATA OUT MODE DELAYED WRITE CYCLE 22 GM71C4263C GM71CS4263CL LG Semicon tRP tRASP RAS tHPRWC tT tCRP tRSH tCP tRCD tCAS tCP tCAS tCAS UCAS tRAD LCAS tASR tRAH ADDRESS tASC tASC tCAH tRCS tCAH tCAH COLUMN 1 ROW tASC COLUMN 2 tRWD tAWD tCWD tCWL tRCS tCPW tAWD tCWD COLUMN N tRCS tCPW tAWD tCWD tDZC tDS tCWL tCWL tRWL WE tWP tDS tDZC tWP tDS tDZC tDH tDH DIN 1 DIN tWP tDH DIN N DIN 2 High-Z tDZO tDZO tDZO tODD tODD tODD tOEH tOEH tOEZ OE tOAC tCAC tAA tOEZ tOAC tCAC tAA tACP tCLZ tOEZ tOHO tOHO tRAC tOEH tOAC tCAC tACP tCLZ tOHO tAA tCLZ High-Z DOUT INVALID DOUT DOUT 1 INVALID DOUT DOUT 2 INVALID DOUT * DOUT N : Don’t care FIGURE 13. EXTENDED DATA OUT MODE READ MODIFY WRITE CYCLE 23 GM71C4263C GM71CS4263CL LG Semicon tRP tRASP RAS tT tRCD tCP tCAS UCAS LCAS tCRP tCP tCP tCAS tCAS tCAS tCSH tWCS tWCH tRCHP tRSH tWP tRCH tCPW WE tRAL tCAL tAWD tRAH tASC tCAH tASR ADDRESS COLUMN 1 ROW COLUMN 2 COLUMN 4 COLUMN 3 tDS tDH DIN 1 DIN tCAH tCAH tCAH tCAL tDS tASC tASC tASC tRDD tCDD tDH High - Z tRRH DIN 3 tWDD tODD OE tOHO tCAC tOAC tAA tACP High - Z DOUT tDOH tCAC tOEZ tCAC tAA tAA tOAC tACP tACP DOUT 2 DOUT 3 tOFR DOUT 4 * FIGURE 14. EXTENDED DATA OUT MODE MIX CYCLE (1) 24 tOFF tOH tOEZtWEZ tOHO : Don’t care GM71C4263C GM71CS4263CL LG Semicon tRP tRASP RAS tT tRCD tCSH tCP tCP tCAS UCAS LCAS tCAS tCAS tCAS tRCH tRCHR tRCS tWCH tRSH tWCS tWP tCPW WE tRAH tASC tCAH tASC tASR ADDRESS tCAH COLUMN 2 COLUMN 1 ROW tCRP tCP tASC tRAL tASC tCAH COLUMN 4 High - Z DIN 2 DIN tCAL tCAL tDS tDH tDS tCAH COLUMN 3 tCAL tCAL tRRH tRCH tDH tRDD tCDD DIN 3 tWDD tCOL tODD tODD OE tCAC tAA tCAC tAA tOEZ tOAC DOUT 1 tOEZ tACP tOAC tOHO tRAC DOUT tCOP High - Z tCAC tAA tOAC tACP DOUT 3 tOFF tOH tWEZ tOEZ tOHO tOFR DOUT 4 * : Don’t care FIGURE 15. EXTENDED DATA OUT MODE MIX CYCLE (2) *Note :tHPC(min) can be achieved during a series of EDO mode write cycles or EDO mode read cycles. If both write and read operation are mixed in a EDO mode RAS cycle(EDO mode mix cycle (1),(2) ) minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO mode is shown in EDO mode mix cycle (1) and (2). 25 GM71C4263C GM71CS4263CL LG Semicon tRP RAS tRPC tRASS tRPS tT tCHS tCSR tCP tCRP UCAS LCAS tOFR tOFF DOUT INVALID DOUT High-Z * : Don’t care ** Address, OE , WE : Don’t care The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1. Please do not tRASS timing, 10us<=tRASS<=100us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS>=100us, then RAS precharge time should use tRPS instead of tRP. 2. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6us interval should be executed within 8ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6us interval in normal read/write cycle, CBR refresh should be executed within 15.6us immediately after exiting from and before entering into the self refresh mode. 4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. FIGURE 16. SELF-REFRESH CYCLE 26 GM71C4263C GM71CS4263CL LG Semicon Package Dimension Unit: Inches (mm) 40 SOJ 0.025(0.64) 0.366(9.30) MIN 0.375(9.55) MAX 0.445(11.30) MAX 0.435(11.06) MIN 0.405(10.29) MAX 0.395(10.03) MIN MIN 0.083(2.10) 1.010(25.67) MIN MIN 1.021(25.93) MAX 0.128(3.25) MIN 0.148(3.75) MAX 0.026(0.66) MIN 0.050(1.27) 0.032(0.81) MAX TYP 0.015(0.38) MIN 0.020(0.50) MAX 27