GMM7658287CNTG-5/6
8,388,608WORDS x 64 BIT
CMOS EDO DYNAMIC RAM MODULE
Description
Features
* 144 pins Dual In-Line Package
- GMM7658287CNTG : Gold plating
* Extended Data Out(EDO)Mode Capability
* Single Power Supply
* Fast Access Time & Cycle Time
(Unit: ns)
The GMM7658287CNTG is an 8M x 64 bits
Dynamic RAM MODULE which is assembled 8
pieces of 4M x 16bit DRAMs in 50pin TSOP
package, one 2k EEPROM for SPD in 8-pin
TSSOP package mounted on a 144 pin printed
circuit board with decoupling capacitors.
The GMM7658287CNTG is optimized for
application to the systems which are required high
density and large capacity such as main memory
of the computers and an image memory systems,
and to the others which are requested compact
size. The GMM7658287CNTG provides common
data inputs and Extended Data Outputs.
tRAC tCAC tRC
Speed
tHPC
GMM7658287CNTG-5
50
13
84
20
GMM7658287CNTG-6
60
15
104
25
* Low Power
Active : 2,044/ 2,188 mW (MAX)
Standby : 8.64 mW (CMOS level : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/128ms
* Self Refresh Operation
* Battery Back-up Operation
GMM7658287CNTG(Both Side)
143
2
1
144
Pin Configuration (Top View)
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
Vss
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
Vcc
Vcc
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
Vss
Vss
/CE0
/CE4
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
/CE1
/CE5
Vcc
Vcc
A0
A3
A1
A4
A2
A5
Vss
Vss
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
Vcc
Vcc
DQ12
DQ44
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
Vss
Vss
RSVD
RSVD
RSVD
RSVD
RFU
RFU
Vcc
Vcc
RFU
RFU
/WE
RFU
/RE0
RFU
/RE1
RFU
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
/OE
RFU
Vss
Vss
RSVD
RSVD
RSVD
RSVD
Vcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
DQ20
DQ52
DQ21
DQ53
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ22
DQ54
DQ23
DQ55
Vcc
Vcc
A6
A7
A8
A11
Vss
Vss
A9
A12*
A10
A13*
Vcc
Vcc
/CE2
/CE6
/CE3
/CE7
Vss
Vss
Pin Symbol
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
Vcc
Vcc
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
Vss
Vss
SDA
SCL
Vcc
Vcc
Note : Pins Marked * are not used in this module.
* This Data Sheet is subject to change without notice.
1
GMM7658287CNTG-5/6
LG Semicon
Block Diagram
/RE0
/RE1
/WE
/OE
/RAS /WE /OE
/RAS /WE /OE
/CE4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CE5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D1
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D5
/CE6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CE7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CE1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CE2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CE3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6 D4
I/O7
/CE0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D2
D6
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/RAS /WE /OE
/LCAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
D7
/RAS /WE /OE
D3
/UCAS
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Serial PD
A0~A11
D0~D7
D8
SCL
VCC
VSS
0.22§ ÞCapacitor
under each DRAM
A0
A1
SDA
A2
To all DRAMS
2
GMM7658287CNTG-5/6
LG Semicon
Pin Description
Function
Pin
Pin
Function
Address Inputs
OE
Output Enable
Data Input/Output
VCC
Power (+3.3V)
Row Address Strobe
VSS
Ground
Column Address Strobe
NC
No Connection
WE
Read/Write Enable
RSVD
Reserved Use
SDA
Serial Address / Data I/O
SCL
Serial Clock
A0-A11
DQ0-DQ63
RE0,RE1
CE0-CE7
SA0-SA2
Address in EEPROM
RFU
Reserved for Future use
Serial Presence Detect Information
. SPD Interface Protocol : IIC
. Current sink capability of SDA driver £ ¼3 mA
. Maximum Clock Frequency : 100 KHz
Byte
Function described
0
Defines # bytes written into serial memory at module mfgr
1
Function supported
Total # bytes of SPD memory device
Hex Value
128 bytes
80h
256 bytes
08h
2
Fundamental memory type(FPM, EDO..) form appendix A
EDO
02h
3
# Row Address on this assembly
12
0Ch
4
# Column Address on this assembly
10
0Ah
5
# Module Banks on this assembly
2
02h
6
Data Width of this assembly
64bits
40h
7
Module Data Width continuation
8
Voltage interface standard of this assembly
N/A
00h
LVTTL
01h
9
RAS # Access time of this assembly
tRAC = 50 ns
32h
10
CAS # Access time of this assembly
tCAC = 13 ns
0Dh
11
DIMM Configuration type(Non-Parity,Parity,ECC)
Non-Parity
00h
12
Refresh Rate/Type
4096/128ms
83h
13
DRAM Width, Primary DRAM
x16
10h
14
Error checking DRAM data width
0
00h
15-31
Reserved for future offerings
00h
32
Superset memory type(may be used in future)
00h
* Above data are based on the SPD specification of JEDEC standard.
3
GMM7658287CNTG-5/6
LG Semicon
Byte
Function described
33-62
Superset memory specific features(may be used in future)
63
64
Function supported
00h
Checksum for bytes 0-62
B5h
Manufacturers JEDEC ID code per JEP-106E
LGS
E0h
00h
65-71
72
Manufacturing location
73
Manufacturer`s part number
74
Hex Value
Korea
52h
GMM7658287CNTG-50
47h(G)
4Dh(M)
=== Allowed characters include 0-9, A-Z and space ===
75
4Dh(M)
76
37h(7)
77
36h(6)
78
35h(5)
79
38h(8)
80
32h(2)
81
38h(8)
82
37h(7)
83
43h(C)
84
4Eh(N)
85
54h(T)
86
47h(G)
87
2Dh(-)
88
35h(5)
89
20h
90
20h
91-92
Revision Code
Rev0
00h
93
Date Code
WW
00h
YY
61h(97)
94
95-98
Assembly serial number
Binary incremental
00h
99-125
Manufacturer specific data
N/A
00h
126-127
Reserved
128-255
Open User Free-Form area $ not defined
00h
00h
* Above data are based on the SPD specification of JEDEC standard.
4
GMM7658287CNTG-5/6
LG Semicon
Absolute Maximum Ratings*
Symbol
Parameter
Rating
Unit
-55 to 125
C
-0.5 to Vcc +0.5
V
TSTG
Storage Temperature (Plastic)
VT
Voltage on any Pin Relative to VSS
VCC
Voltage on any Pin Relative to VSS
IOUT
Short Circuit Output Current
50
mA
PD
Power Dissipation
8
W
-0.5 to 4.6
V
*Note: 1. Stress greater than above Absolute Maximum Ratings may cause permanent damage to the device.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
Parameter
Min
Typ
Max
Unit
Note
VCC
Supply Voltage
3.0
3.3
3.6
V
1
VIH
Input High Voltage
2.0
-
Vcc+0.3
V
1
VIL
Input Low Voltage
-0.3
-
0.8
V
1
*Note: 1. All voltages referenced to VSS.
5
GMM7658287CNTG-5/6
LG Semicon
DC Electrical Characteristics (VCC = 3.3V +/- 10%, TA = 0 ~ 70C)
Symbol
VOH
VOL
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
ICC8
ICC9
II(L)
IO(L)
Parameter
Min
Max
Output Level
Output Level Voltage (IOUT = -2mA)
2.4
Vcc
Output Level
Output Level Voltage (IOUT = 2mA)
0
0.4
50ns
-
608
60ns
-
568
-
16
50ns
-
608
60ns
-
568
50ns
-
488
Operating Current
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH)
RAS Only Refresh Current
Average Power Supply Current
RAS Only Mode
(RAS Cycling, CAS = VIH, tRC = tRC min)
Extended Data Out Mode Current
Average Power Supply Current
EDO Page Mode
(tHPC = tHPC min)
60ns
Unit
Note
V
1, 2
V
mA
mA
mA
2
mA
1, 3
-
448
-
4
-
2.4
50ns
-
608
60ns
-
568
-
4,000
uA
40
mA
-
3,200
uA
Input Leakage Current
Any Input (0V<=VIN <=4.6V)
-5
5
uA
Output Leakage Current
(D OUT is Disabled, 0V<=VOUT <=4.6V)
-5
5
uA
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS>=VCC-0.2V)
Standby Current (L_Version)
CAS before RAS Refresh Current
(tRC = tRC min)
Battery Back Up Operating Current(Standby with CBR Ref.)
( tRC=31.25us, tRAS =300ns,Dout=High-Z)
Standby Current RAS = VIH
CAS = VIL
DOUT = Enable
Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT=High-Z, CMOS interface)
-
mA
mA
4
1
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Mwasured with one sequential address change per EDO cycle, tHPC.
4. VIH >=VCC-0.2V, 0V<=VIL<=0.2V
6
GMM7658287CNTG-5/6
LG Semicon
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C, f = 1MHz)
Symbol
Min
Max
Unit
CI1
Input Capacitance (A0~A11)
Parameter
-
50
pF
Note
1
CI2
Input Capacitance (WE0, OE0)
-
42
pF
1, 2
C13
Input Capacitance (RAS0,RAS1)
-
40
pF
1, 2
C14
Input Capacitance (CAS0~CAS7)
-
15
pF
1, 2
CI/O
I/O Capacitance (DQ0~DQ63)
-
23
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns
Input level : VIL/VIH = 0.0/3.0V
Input timing reference levels : VIL/V IH = 0.8/2.0V
Output timing reference levels : VOL/VOH = 0.8/2.0V
Output load : 1 TTL gate+CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GMM7658287CNTG-5 GMM7658287CNTG-6
Symbol
Parameter
Min
Max
Min
Max
Unit Notes
tRC
Random Read or Write Cycle Time
84
-
104
-
§ À
tRP
RAS Precharge Time
30
-
40
-
§ À
tCP
CAS Precharge Time
8
-
10
-
§ À
tRAS
RAS Pulse Width
50
10000
60
10000
§ À
tCAS
CAS Pulse Width
8
10000
10
10000
§ À
tASR
Row Address Set-up Time
0
-
0
-
§ À
tRAH
Row Address Hold Time
8
-
10
-
§ À
tASC
Column Address Set-up Time
0
-
0
-
§ À
tCAH
Column Address Hold Time
8
-
10
-
§ À
tRCD
RAS to CAS Delay Time
12
37
14
45
§ À
3
tRAD
RAS to Column Address Delay Time
10
25
12
30
§ À
4
tRSH
RAS Hold Time
13
-
15
-
§ À
tCSH
CAS Hold Time
35
-
40
-
§ À
tCRP
CAS to RAS Precharge Time
5
-
5
-
§ À
tODD
OE to DIN Delay Time
13
-
15
-
§ À
5
tDZO
OE Delay Time from DIN
0
-
0
-
§ À
6
tDZC
CAS Set-up Time from DIN
0
-
0
-
§ À
6
TransitionTime
(Rise and Fall)
2
50
2
50
§ À
7
Refresh Period ( 4096 Cycles)
-
128
-
128
ms
tT
tREF
7
GMM7658287CNTG-5/6
LG Semicon
Read Cycles
Symbol
Parameter
GMM7658287CNTG-5
GMM7658287CNTG-6
Unit
Min
Max
Min
Max
Notes
tRAC
Access Time from RAS
-
50
-
60
§ À
tCAC
Access Time from CAS
-
13
-
15
§ À9,10,17
tAA
Access Time from Column Address
-
25
-
30
§ À9,11,17
tOAC
Access Time from OE
-
13
-
15
§ À
tRCS
Read Command Set-up Time
0
-
0
-
§ À
tRCH
Read Command Hold Time to CAS
0
-
0
-
§ À
12
tRRH
Read Command Hold Time to RAS
0
-
0
-
§ À
12
tRAL
Column Address to RAS Lead TIme
25
-
30
-
§ À
tCAL
Column Address to CAS Lead Time
15
-
18
-
§ À
tOFF
Output Buffer Turn-off Delay Time from CAS
-
13
-
15
§ À 13,21
tOEZ
Output Buffer Turn-off Delay Time from OE
-
13
-
15
§ À
13
tCDD
CAS to DIN Delay Time
13
-
15
-
§ À
5
tRDD
RAS to DIN Delay Time
13
-
15
-
§ À
tWDD
WE to DIN Delay Time
13
-
15
-
§ À
tOFR
Output Buffer Turn-off Delay Time from RAS
-
13
-
15
§ À 13,21
tWEZ
Output Buffer Turn-off Delay Time from WE
-
13
-
15
§ À 13
tOH
Output Data Hold Time
3
-
3
-
§ À 21
tOHR
Output Data Hold Time from RAS
3
-
3
-
§ À
tRCHR
Read Command Hold Time from RAS
50
-
60
-
§ À
tOHO
Output data Hold Time from OE
3
tCLZ
CAS to Output in Low - Z
0
-
§ À
8,9
9
21
3
-
0
8
GMM7658287CNTG-5/6
LG Semicon
Wrtie Cycles
GMM7658287CNTG-5 GMM7658287CNTG-6
Symbol
Parameter
Min
Max
Min
Max
Unit Notes
tWCS
Write Command Set-up Time
0
-
0
-
§ À 14
tWCH
Write Command Hold Time
8
-
10
-
§ À 21
tWP
Write Command Pulse Width
8
-
10
-
§ À
tRWL
Write Command to RAS Lead Time
13
-
15
-
§ À
tCWL
Write Command to CAS Lead Time
8
-
10
-
§ À
tDS
Data-in Set-up Time
0
-
0
-
§ À 15
tDH
Data-in Hold Time
8
-
10
-
§ À 15
Read-Modify-Write Cycles
GMM7658287CNTG-5 GMM7658287CNTG-6
Symbol
Parameter
Min
Max
Min
Max
Unit Notes
tRWC
Read-Modify-Write Cycle Time
116
-
140
-
§ À
tRWD
RAS to WE Delay Time
67
-
79
-
§ À 14
tCWD
CAS to WE Delay Time
30
-
34
-
§ À 14
tAWD
Column Address to WE Delay Time
42
-
49
-
§ À 14
tOEH
OE Hold Time from WE
13
-
15
-
§ À
Cycles
Refresh Cycle
GMM7658287CNTG-5 GMM7658287CNTG-6
Symbol
Parameter
Min
Max
Min
Max
Unit Notes
tCSR
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
5
-
5
-
§ À
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
8
-
10
-
§ À
tWRP
WE setup Time
(CAS-before-RAS Refresh Cycle)
0
-
0
-
§ À
tWRH
WE hold Time
(CAS-before-RAS Refresh Cycle)
8
-
10
-
§ À
tRPC
RAS Precharge to CAS Hold Time
5
-
5
-
§ À
9
GMM7658287CNTG-5/6
LG Semicon
Extended Data Out Mode Cycles
GMM7658287CNTG-5
Symbol
GMM7658287CNTG-6
Parameter
Unit
Min
Max
Min
Max
Notes
tHPC
EDO Page Mode Cycle Time
20
-
25
-
§ À 20
tWPE
Write pulse width during CAS Precharge
8
-
10
-
§ À
tRASP
EDO Mode RAS Pulse Width
-
100000
-
tACP
Access Time from CAS Precharge
-
28
-
35
tRHCP
RAS Hold Time from CAS Precharge
28
-
35
-
§ À
tCOL
CAS Hold Time Referred OE
8
-
10
-
§ À
tCOP
CAS to OE set-up Time
5
-
5
-
§ À
tRCHP
Read Command Hold Time from CAS
Precharge
28
-
35
-
§ À
tDOH
Output Data Hold Time from CAS Low
3
-
3
-
§ À 9,22
tOEP
OE Precharge Time
8
-
10
-
§ À
100000 § À 16
§ À 9,17
EDO Page Mode Read-Modify-Write cycle
GMM7658287CNTG-5
tHPRWC
tCPW
GMM7658287CNTG-6
Parameter
Symbol
Unit
EDO Page Mode Read-Modify-Write Cycle Time
WE delay time from CAS precharge
Notes
Min
Max
Min
Max
57
-
68
-
§ À
45
-
54
-
§ À 14
Self Refresh Cycles
GMM7658287CNTG-5
Symbol
Parameter
GMM7658287CNTG-6
Min
Max
Min
Max
Unit
Notes
tRASS
RAS Pulse Width(Self-Refresh)
100
-
100
-
us
26
tRPS
tCHS
RAS Precharge Time(Self-Refresh)
90
-
110
-
us
26
CAS Hold Time(Self-Refresh)
-50
-
-50
-
us
10
LG Semicon
GMM7658287CNTG-5/6
Notes:
1.
2.
AC measurements assume tT = 2§ À.
AC initial pause of 200 § Áis required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh)
3.
Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by t CAC.
4.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by t AA.
5.
Either tOED or tCDD must be satisfied.
6.
Either tDZO or tDZC must be satisfied.
7.
V IH (min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
8.
Assumes that t RCD¡ ÂtRCD(max) and tRAD¡ ÂtRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9.
Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t RCD¡ Ã
tRCD(max) and t RCD + tCAC(max) ¡ Ã
tRAD + tAA(max).
11. Assumes that t RAD ¡ ÃtRAD (max) and t RCD + tCAC(max)¡ ÂtRAD + tAA(max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
14. tWCS, tRWD, tCWD, t AWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if tWCS ¡ Ã
tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD ¡ ÃtRWD(min), tCWD¡ Ã
tCWD(min), tAWD¡ ÃtAWD(min) and tCPW¡ ÃtCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. tDS and tDH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in extended data out mode cycles.
17. Access time is determined by the longest among t AA, tCAC and t CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V CC/VSS line noise, which causes to degrade VIH min/V IL max level.
11
LG Semicon
GMM7658287CNTG-5/6
20. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycls. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC(tCAS + t CP + 2t T) becomes greater than the
specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
t
22. DOH defines the time at which the output level go cross. V OL=0.8V, VOH=2.0V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
§ Âperiod on the condition a and b below.
a. Enter self refresh mode within 15.6 § Áafter either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6§ Á
after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
25. For L_version, it is avaliable to apply each 128 § Âand 31.2 § Áinstead of 64 § Âand 15.6§ Áat
note 23.
10§ .ÁIt is undefined
26. At t RASS£ ¾100 § Á, self refresh mode is activated, and not actived at t RASS £ ¼
within the range of 10 § Á£ ¼tRASS £ ¼100 § Á. for tRASS £ 1¾0 § Á, it is necessary to satisfy tRPS.
27. XXX: H or L ( H : VIH(min)¡ ÂVIN¡ ÂVIH(max), L: VIH(min)¡ ÂVIN¡ ÂVIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
12
GMM7658287CNTG-5/6
LG Semicon
Timing Waveforms
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tRAD
tASR
ADDRESS
tRAL
tRAH
tASC
ROW
tCAH
COLUMN
tRRH
tRCS
tRCH
WE
tCAC
tOFF
tAA
High-Z
DOUT
DOUT
tRAC
tOEZ
tDZC
tCDD
High-Z
DIN
tDZO
tOAC
tOED
OE
*
: Don`t care
FIGURE 1. READ CYCLE
13
GMM7658287CNTG-5/6
LG Semicon
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
ADDRESS
tRAH
tASC
ROW
tCAH
COLUMN
tWCS
tWCH
WE
tDS
DIN
tDH
DIN
High-Z
DOUT
*
**
: Don`t care
OE : Don`t care
> tWCS (min)
*** tWCS =
FIGURE 2. EARLY WRITE CYCLE
14
GMM7658287CNTG-5/6
LG Semicon
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
ADDRESS
tRAH
tCAH
tASC
ROW
COLUMN
tCWL
tRCS
tRWL
tWP
WE
tDZC
tDH
tDS
High-Z
DIN
DIN
tOED
tDZO
tOEH
OE
tOEZ
High-Z
DOUT
**
INVALID
OUTPUT
*
: Don`t care
** Invalid DOUT comes out,
when OE is low level.
FIGURE 3. DELAYED WRITE CYCLE
15
GMM7658287CNTG-5/6
LG Semicon
tRWC
tRAS
tRP
RAS
tT
tRCD
tCAS
tCRP
CAS
tRAD
tRAH
tASR
ADDRESS
tASC
ROW
tCAH
COLUMN
tCWL
tRWL
tWP
tCWD
tAWD
tRCS
tRWD
WE
tAA
tRAC
tDZC
High-Z
DIN
tDH
tDS
tCAC
DIN
tOED
tOEH
High-Z
DOUT
DOUT
tDZO
tOAC
tOEZ
OE
*
: Don`t care
FIGURE 4. READ MODIFY WRITE CYCLE
16
GMM7658287CNTG-5/6
LG Semicon
tRC
tRAS
tRP
RAS
tCRP
tT
tRPC
tCRP
CAS
tASR
ADDRESS
tRAH
ROW
High-Z
DOUT
* OE,WE : Don`t care
** Rrfresh address :
FIGURE 5. RAS ONLY REFRESH CYCLE
A0~A12 (AX0 ~ AX12)
tRC
tRP
tRAS
tRC
tRP
tRAS
tRP
RAS
tRPC
tCPN
tT
tCSR
tRPC
tCHR
tCPN
tCRP
tCSR
tCHR
CAS
ADDRESS
tOFF
DOUT
INVALID
DOUT
High-Z
: Don`t care
*
**
WE : VIH
FIGURE 6. CAS BEFORE RAS REFRESH CYCLE
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GMM7658287CNTG-5/6
LG Semicon
tRC
tRC
tRAS
tRP
(Read)
tRAS
tRC
tRP
tRAS
(Refresh)
tRP
(Refresh)
RAS
tT
tCHR
tRSH
tRCD
tCRP
tCAS
CAS
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
ROW
COLUMN
tRCH
tRCS
tRRH
WE
tCAC
tAA
tOFF
tRAC
DOUT
High-Z
DOUT
tDZC
tOEZ
High-Z
DIN
tCDD
tDZO
tOAC
tOED
OE
*
: Don`t care
FIGURE 7. HIDDEN REFRESH CYCLE
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GMM7658287CNTG-5/6
LG Semicon
tRASP
tRP
tRHCP
RAS
tT
tCSH
tRCD
tHPC
tCAS
tCP
tCAS
tRSH
tCP
tCAS
tCRP
CAS
tRAD
tRAL
tCSH
tASR
ADDRESS
tRAH
ROW
tASC
tCAH
tASC
COLUMN
tCAH
COLUMN
tASC
tCAH
COLUMNN
tRCH
tRCHA
tRCS
tRRH
tRCHC
WE
tOAC
OE
tRAC
tAA
tCAC
DOUT
tCPA
tAA
tCAC
High-Z
tWEZ
tOHR
tOFR
tOFF
tCPA
tAA
tCAC
tOEZ
tDOH
DOUT 1
tOH
tDOH
DOUT 2
DOUT N
*
: Don`t care
FIGURE 8. EXTENDED DATA OUT MODE READ CYCLE
19
GMM7658287CNTG-5/6
LG Semicon
tRASP
tRP
tCPRH
RAS
tT
tHPC
tCSH
tCP
tCP
tCAS
tRSH
tCAS
tCAS
tRCHR
tRCHC
tRCH
tRCS
tCRP
tHPC
tCP
tCAS
CAS
tHPC
tRRH
tRCS
tRCH
WE
tRAL
tASC
tASR
ADDRESS
ROW
tASC
tCAH
tASC
tCAH
tCAH
tASC
tCAH
tRAH
COLUMN 1
COLUMN 2
tCAL
COLUMN 3
tCAL
COLUMN N
tCAL
tCOL
tOFR
tOFF
tOHR
tOH
tCAL
tCOP
OE
tCPA
tOAC
tCAC
tAA
tRAC tWEZ
tAA
tOEZ
tCPA
tAA
tCAC
tCAC
tOAC
tCPA
tAA
tOEZ
tDOH
tOAC
tOEZ
tCAC
High-Z
DOUT
DOUT 1
DOUT 2
DOUT 2
DOUT 3
DOUT N
FIGURE 9. EXTENDED DATA OUT MODE READ CYCLE (OE CONTROL)*
*NOTE : EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high
during CAS high, the data will not come out until next CAS access. When WE goes low during
CAS high, the data will not come out until next CAS access.
20
GMM7658287CNTG-5/6
LG Semicon
tRP
tRASP
RAS
tT
tHPC
tCSH
tRCD
tCAS
tCP
tRSH
tCAS
tCRP
tCP
tCAS
CAS
tASR
tRAH
ADDRESS
tASC
ROW
tASC
tCAH
COLUMN 1
tWCS
tWCH
COLUMN 2
tWCS
tCAH
tASC
tCAH
COLUMN N
tWCH
tWCS
tWCH
WE
tDS
DIN
tDH
tDS
DIN 1
tDH
tDS
DIN 2
tDH
DIN N
High-Z
DOUT
* OE : Don`t care
** tWCS ¡ ÃtWCS (min)
***
: Don`t care
FIGURE 10. EXTENDED DATA OUT MODE EARLY WRITE CYCLE
21
GMM7658287CNTG-5/6
LG Semicon
tRP
tRASP
RAS
tCP
tT
tCP
tCSH
tCRP
tHPC
tRCD
tCAS
tRSH
tCAS
tCAS
CAS
tRAD
tASR
tASC
tRAH
ADDRESS
tASC
tCAH
ROW
tASC
tCAH
tCAH
COLUMN 1
COLUMN 2
COLUMN N
tCWL
tRCS
tCWL
tRCS
tCWL
tRWL
tRCS
WE
tWP
tDZC
tDS
tWP
tDS
tDZC
tDH
DIN
tDH
tDZO
tOED
tDH
DIN 2
DIN 1
tDZO
tWP
tDS
tDZC
DIN N
tDZO
tOED
tOEH
tOED
tOEH
tOEH
OE
tCLZ
High-Z
DOUT
tCLZ
tCLZ
tOEZ
INVALID
DOUT
tOEZ
tOEZ
INVALID
DOUT
INVALID
DOUT
*
: Don`t care
** tOEH=> tCWL
FIGURE 11. EXTENDED DATA OUT MODE DELAYED WRITE CYCLE
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GMM7658287CNTG-5/6
LG Semicon
tRP
tRASP
RAS
tHPRWC
tT
tCRP
tCP
tRCD
tCAS
tRSH
tCP
tCAS
tCAS
CAS
tRAD
tASR
tRAH
ADDRESS
tASC
tASC
tCAH
ROW
tCAH
tCAH
COLUMN 1
tRCS
tASC
COLUMN 2
tRWD
tAWD
tCWD
COLUMN N
tRCS
tCPW
tAWD
tCWD
tDZC
tDS
tCWL
tRCS
tCPW
tAWD
tCWD
tDZC
tDS
tCWL
tCWL
tRWL
WE
tWP
tDZC
tDS
tWP
tDH
DIN
tDH
tOED
tOEH
tOEZ
tOAC
tCAC
tAA
tRAC
tOEH
tOEZ
tOAC
tCAC
tAA
tCPA
tOEZ
tOAC
tCAC
tCPA
tCLZ
tCLZ
DOUT 1
High-Z
tOED
tOEH
OE
DIN N
tDZO
tDZO
tOED
tDH
DIN 2
DIN 1
tDZO
tWP
tAA
tCLZ
DOUT 2
DOUT N
DOUT
*
High-Z
: Don`t care
** tOEH => tCWL
FIGURE 12. EXTENDED DATA OUT MODE READ MODIFY WRITE CYCLE
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GMM7658287CNTG-5/6
LG Semicon
tRP
tRASP
RAS
tT
tCP
tCAS
tRCD
CAS
tCP
tCP
tCAS
tCRP
tCAS
tCAS
tCSH
tRCHC
tRSH
tWP
tWCS tWCH
tCPW
WE
tRRH tRCH
tRAL
tAWD
tRAH
tASC
ADDRESS
ROW
tASC
tASC
tCAH
tASR
COLUMN
1
COLUMN
2
tCAH
COLUMN
4
COLUMN
3
tRDD
tDS
tDH
tDS
tASC
tCAH
tCAH
tCDD
tDH
Din
DIN 1
High - Z
DIN 3
tWDD
tOED
OE
tCAC
tOAC
tAA
tCPA
Dout
High - Z
tDOH
tCAC
tOEZ
tAA
tCPA
DOUT 2
tCAC
tAA
tOAC
tOFR
tOFF
tOH
tCPA
DOUT 3
tWEZ
tOEZ
DOUT 4
: Don`t care
*
FIGURE 13. EXTENDED DATA OUT MODE MIX CYCLE (1)
*23
24
GMM7658287CNTG-5/6
LG Semicon
tRP
tRASP
RAS
tT
tCSH
tCRP
tCP
tCP
tCAS
tRCD
CAS
tCP
tCAS
tCAS
tCAS
tRCHR
tRCH tWCH
tWCS
tRCS
tASR
tRAH
tASC
tCAH
COLUMN
4
COLUMN
3
COLUMN
2
tCAL
tCAL
Din
tASC
tCAH
tCAH
COLUMN
1
ROW
tRAL
tASC
tASC
tCAH
tDS
High - Z
Dout
tOED
tCOL
tCAC
tAA
tOEZ
tCOP
tOEZ
tCPA
tOAC
DOUT 1
tRDD
tCDD
DIN 3
OE
tCAC
tAA
tOAC
tRAC
tCAL
tCAL
tDH
tDS
tDH
DIN 2
tOED
tRRH
tRCH
tCPW
WE
ADDRESS
tRSH
tWP
High - Z
tCAC
tAA
tOAC
tCPA
tOFF
tOH
tOFR
tWEZ
tOEZ
DOUT 4
DOUT 3
: Don`t care
*
FIGURE 14. EXTENDED DATA OUT MODE MIX CYCLE (2)
*23
25
GMM7658287CNTG-5/6
LG Semicon
Set Cycle***
Test Mode Cycle
Reset Cycle*
Normal Mode
~
~
RAS
~~
~~
CAS
~~
WE
*
CBR or RAS-only refresh
**
: Don`t care
***
Address, DIN , OE: Don`t care
FIGURE 15. TEST MODE CYCLE
tRC
tRP
tRAS
tRP
RAS
tRPC
tCSR
tCHR
tT
CAS
tCPN
tRPC
tCRP
tCPN
tWS
tWH
WE
ADDRESS
tOFF
High-Z
DOUT
INVALID DOUT
*
: Don`t care
FIGURE 16. TEST MODE SET CYCLE
26
GMM7658287CNTG-5/6
LG Semicon
tRC
tRAS
tRP
RAS
tT
tCSR
tCHR
tCPT
tRSH
tCRP
tCAS
CAS
tCAH
tASC
ADDRESS
COLUMN
tWS
tWH
tRRH
tRCH
tRCS
WE
tDZC
tCDD
High-Z
DIN
tOED
tDZO
OE
tOAC
tCAC
tOEP
tOEZ
tOFF
tAA
tRAC
High-Z
DOUT
DOUT
*
: Don`t care
FIGURE 16. CAS BEFORE RAS REFRESH COUNTER CHECK CYCLE (READ)
27
GMM7658287CNTG-5/6
LG Semicon
tRC
tRAS
tRP
RAS
tCSR
tCHR
tCPT
tRSH
tCRP
tCAS
tT
CAS
tASC
ADDRESS
tCAH
COLUMN
tWS
tWH
tWCS
tWCH
WE
tDS
DIN
tDH
DIN
OE
High-Z
DOUT
*
: Don`t care
FIGURE 17. CAS BEFORE RAS REFRESH COUNTER CHECK CYCLE (WRITE)
28
GMM7658287CNTG-5/6
LG Semicon
Units:mm
67.60
63.60
3.8 MAX.
2-R 3.0Min
COMPONENT AREA
4.0
20
0.1
4.0 Min
3.2 Min
6
1
143
B
2.00 MIN
3.30
4.60
32.80
23.20
1.*00 ¡ ¾0.10
A
24.50
38.60
29.00
3.70
4.60
32.80
23.20
2-¥ õ1.80
144
2
25.4
2-R FULL
SOLDER AREA
1.50 ¡ ¾0.10
0.6 ¡ ¾0.05
0.8 TYP
DETAIL A
(SCALE=1/3)
4.00 ¡¾0.10
2.55
0.25 Max.
2.5
DETAIL B
(SCALE=1/3)
NOTE : 1. Tolerances on all dimensions ¡ ¾0.15 unless otherwise specified.
2. Thickness(* Mark) includes Plating and / or Metallization.
29