GMM773322(3)80CNTG-5/6
32Mx72 Async. DRAM DIMM with ECC
Description
Features
* 168 pins Dual In-Line Package
- GMM773322(3)80CNTG : Gold plating
* Extended Data Ouput (EDO) Mode Capability
* Single 3.3V+/-0.3V Power Supply
* Fast Access Time & Cycle Time
(Unit: ns)
The GMM773322(3)80CNTG is an 32M x 72
bits Dynamic RAM MODULE which is
assembled 36 pieces of 16M x 4bit DRAMs in
32 pin TSOP-¥ ±package, two 16bit driver ICs
in 48pin TSSOP package mounted on a 168 pin
printed circuit board with decoupling capacitors.
The GMM773322(3)80CNTG is optimized for
application to the systems which are required
high density and large capacity such as main
memory of the computers and an image memory
systems, and to the others which are requested
compact size.
The GMM773322(3)80CNTG provides
common data inputs and Extended Data
Outputs.
tRAC tCAC tRC
Speed
tHPC
GMM773322(3)80CNTG-5
50
18
84
20
GMM773322(3)80CNTG-6
60
20
104
25
* Low Power
Active : 9310/8662mW (MAX)
Standby : 173mW (CMOS level : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* GMM77332280CNTG :4K Refresh / 64ms
GMM77332380CNTG: 8K Refresh / 64ms
GMM773322(3)80CNTG (Double Side)
Pin Configuration (Top View)
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
DQ16
DQ17
VSS
RSVD
RSVD
VCC
/WE0
/CAS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
RSVD
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
RFU
RFU
VSS
/OE2
/RAS2
/CAS4
RSVD
/WE2
VCC
RSVD
RSVD
DQ18
DQ19
VSS
DQ20
DQ21
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ22
DQ23
Vcc
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
VSS
PD1
PD3
PD5
PD7
ID 0
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
DQ36
DQ37
DQ38
DQ39
VCC
DQ40
DQ41
DQ42
DQ43
DQ44
VSS
DQ45
DQ46
DQ47
DQ48
DQ49
VCC
DQ50
DQ51
DQ52
DQ53
VSS
RSVD
RSVD
VCC
RFU
/CAS1
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
RSVD
/RAS1
RFU
VSS
A1
A3
A5
A7
A9
A11
A13*
VCC
RFU
B0
VSS
RFU
/RAS3
/CAS5
RSVD
/PDE
VCC
RSVD
RSVD
DQ54
DQ55
VSS
DQ56
DQ57
Pin Symbol
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ58
DQ59
VCC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
VSS
DQ64
DQ65
DQ66
DQ67
VCC
DQ68
DQ69
DQ70
DQ71
VSS
PD2
PD4
PD6
PD8
ID 1
VCC
Note : Pins Marked * are not used in this module.
A12(pin 39) is used for only GMM77332380CNTG(8K Ref.)
Rev 0.1 / Apr’01
* This Data Sheet is subject to change without notice.
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Block Diagram
OE0
OE2
WE0
WE2
RAS0
RAS1
RAS2
RAS3
CAS0
A0
A1-A11(A12*)
CAS1
CAS4
B0
A1-A11(A12*)
DQ 36
DQ 37
DQ 38
DQ 39
CAS5
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 8
DQ 9
DQ 10
DQ 11
DQ 0
DQ 1
DQ 2
DQ 3
DQ 12
DQ 13
DQ 14
DQ 15
DQ 0
DQ 1
DQ 2
DQ 3
DQ 16
DQ 17
DQ 18
DQ 19
DQ 0
DQ 1
DQ 2
DQ 3
DQ 20
DQ 21
DQ 22
DQ 23
DQ 0
DQ 1
DQ 2
DQ 3
DQ 24
DQ 25
DQ 26
DQ 27
DQ 0
DQ 1
DQ 2
DQ 3
DQ 28
DQ 29
DQ 30
DQ 31
DQ 0
DQ 1
DQ 2
DQ 3
DQ 32
DQ 33
DQ 34
DQ 35
DQ 0
DQ 1
DQ 2
DQ 3
A1~A11(A12*)
D0
D1
D2
D3
D4
D5
D6
D7
D8
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
D18
D19
D20
D21
D22
D23
D24
D25
D26
DRAMS: D0.~D35
A0
DRAMS: D0~D8, D18~D26
B0
DRAMS: D9~D17, D27~D35
* Note : A12 is used for only GMM77332380CNTG(8K Ref.)
Rev 0.1 / Apr’01
DQ 0
DQ 1
DQ 2
DQ 3
DQ 40
DQ 41
DQ 42
DQ 43
DQ 0
DQ 1
DQ 2
DQ 3
DQ 44
DQ 45
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
DQ 48
DQ 49
DQ 50
DQ 51
DQ 0
DQ 1
DQ 2
DQ 3
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQ 56
DQ 57
DQ 58
DQ 59
DQ 0
DQ 1
DQ 2
DQ 3
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 64
DQ 65
DQ 66
DQ 67
DQ 0
DQ 1
DQ 2
DQ 3
DQ 68
DQ 69
DQ 70
DQ 71
DQ 0
DQ 1
DQ 2
DQ 3
VCC
VSS
D9
D10
D11
D12
D13
D14
D15
D16
D17
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
D27
D28
D29
D30
D31
D32
D33
D34
D35
D0~D35, Buffer
0.1 or 0.22uF Capacitor
under each DRAM
D0~D35, Buffer
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Pin Description
Function
Pin
A0,B0 A1-A11/
A0,B0, A1-A12
Pin
Function
Address Inputs(4K Ref)/
Address Inputs(8K Ref)
PDE
Presence Detect Enable
Data Input/Output
VCC
Power (+3.3V)
RAS0~ RAS3
Row Address Strobe
VSS
Ground
CAS 0,1,4,5
Column Address Strobe
NC
No Connection
WE0, WE2
Read/Write Enable
DQ0-DQ71
PD 1-8
Presence Detect
ID 0-1
ID bit
Output Enable
OE0, OE2
RSVD
Reserved Use
RFU
Reserved for Future Use
Presence Detect Pins (Optional)
Pin
50ns
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID0
ID1
60ns
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
PD : 0 for Vol of Driver IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
Absolute Maximum Ratings*
Symbol
Parameter
Rating
Unit
0 ~ 70
C
TA
Ambient Temperature under Bias
TSTG
Storage Temperature (Plastic)
-55 ~ 125
C
VIN/VOUT
Voltage on any Pin Relative to VSS
-0.5 ~ 7.0
V
VCC
Power Supply Voltage
-0.5 ~ 7.0
V
IOUT
Short Circuit Output Current
50
mA
PD
Power Dissipation
23
W
*Note: 1. Stress greater than above Absolute Maximum Ratings may cause permanent damage to the device.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
Parameter
Min
Typ
Max
Unit
Note
VCC
Supply Voltage
3.0
3.3
3.6
V
1
VIH
Input High Voltage
2.4
-
Vcc+0.3
V
1
0
-
0.8
V
1
IL
Input LowtoVoltage
*Note: 1.VAll
voltages referenced
VSS.
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
DC Electrical Characteristics: (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C)
GMM77332280CNTG GMM77332380CNTG
Symbol
Parameter
Unit
Min
Max
Min
Max
VOH
Output Level
Output ``H`` Level Voltage (IOUT = -2mA)
2.4
Vcc
2.4
Vcc
V
VOL
Output Level
Output ``L`` Level Voltage (IOUT = 2mA)
0
0.4
0
0.4
V
-
2586
-
2226
ICC1
50ns
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)
60ns
ICC2
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
ICC3
RAS-Only Refresh Current
Average Power Supply Current
RAS-Only Refresh Mode
(RAS Cycling, CAS = VIH, tRC = tRC min)
ICC4
mA
-
2406
-
102
-
102
50ns
-
2586
-
2226
60ns
-
2406
-
2046
Extended Data Out Mode Current
Average Power Supply Current
Extended Data Out Mode
50ns
-
2046
-
2046
(RAS = VIL, CAS, Address
Cycling: tPC = tPC min)
60ns
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS>=VCC-0.2V, DOUT = High-Z)
ICC6
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
-
1866
-
1866
-
48
-
48
-
2586
-
2586
mA
mA
2
mA
1,3
mA
mA
60ns
RAS = VIH
CAS = VIL
DOUT = Enable
-
2406
-
2406
-
210
-
210
mA
ICC7
Standby Current
II(L)
Input Leakage Current, Any Input
(0V VIN Vcc)
-5
5
-5
5
uA
IO(L)
Output Leakage Current
(DOUT is Disabled, 0V VOUT
-5
5
-5
5
uA
Vcc)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
Rev 0.1 / Apr’01
1,2
2046
-
ICC5
Note
1
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C, f = 1MHz)
Symbol
Min
Max
Unit
Note
CI1
Input Capacitance (A1~A12, A0, B0)
Parameter
-
20
pF
1
CI2
Input Capacitance (WE0, WE2, OE0, OE2)
-
C13
Input Capacitance (RAS0~RAS3)
-
20
65
pF
pF
1, 2
1, 2
C14
Input Capacitance (CAS0,1/CAS4,5)
-
20
pF
1, 2
CI/O
I/O Capacitance (DQ0~DQ71)
-
20
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns
Input level : VIL/VIH = 0.0/3.0V
Input timing reference levels : VIL/VIH = 0.8/2.0V
Output timing reference levels : VOL/VOH = 0.8/2.0V
Output load : 1 TTL gate+CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GMM773322(3)80CNTG-5
Symbol
Parameter
GMM773322(3)80CNTG-6
Min
Max
Min
Max
Unit Notes
tRC
Random Read or Write Cycle Time
84
-
104
-
§ À
tRP
RAS Precharge Time
30
-
40
-
§ À
tCP
CAS Precharge Time
8
-
10
-
§ À
tRAS
RAS Pulse Width
50
10000
60
10000
§ À
tCAS
CAS Pulse Width
8
10000
10
10000
§ À
tASR
Row Address Set-up Time
5
-
5
-
§ À
tRAH
Row Address Hold Time
8
-
10
-
§ À
tASC
Column Address Set-up Time
0
-
0
-
§ À
tCAH
Column Address Hold Time
8
-
10
-
§ À
tRCD
RAS to CAS Delay Time
12
32
14
40
§ À
3
tRAD
RAS to Column Address Delay Time
10
20
12
25
§ À
4
tRSH
RAS Hold Time
18
-
20
-
§ À
tCSH
CAS Hold Time
35
-
40
-
§ À
tCRP
CAS to RAS Precharge Time
10
-
10
-
§ À
tODD
OE to DIN Delay Time
18
-
20
-
§ À
5
tDZO
OE Delay Time from DIN
0
-
0
-
§ À
6
tDZC
CAS Set-up Time from DIN
0
-
0
-
§ À
6
TransitionTime
(Rise and Fall)
2
50
2
50
§ À
7
Refresh Period ( 4096 Cycles)
-
64
-
64
ms
tT
tREF
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Read Cycles
GMM773322(3)80CNTG-5
GMM773322(3)80CNTG-6
Parameter
Symbol
Unit
Min
Max
Min
Max
Notes
tRAC
Access Time from RAS
-
50
-
60
§ À
tCAC
Access Time from CAS
-
18
-
20
§ À9,10,17
tAA
Access Time from Column Address
-
30
-
35
§ À9,11,17
tOAC
Access Time from OE
-
18
-
20
§ À
tRCS
Read Command Set-up Time
0
-
0
-
§ À
tRCH
Read Command Hold Time to CAS
0
-
0
-
§ À
12
tRRH
Read Command Hold Time to RAS
0
-
0
-
§ À
12
tRAL
Column Address to RAS Lead TIme
30
-
35
-
§ À
tCAL
Column Address to CAS Lead Time
15
-
18
-
§ À
tOFF
Output Buffer Turn-off Delay Time from CAS
-
18
-
20
§ À 13,21
tOEZ
Output Buffer Turn-off Delay Time from OE
-
18
-
20
§ À
13
tCDD
CAS to DIN Delay Time
18
-
20
-
§ À
5
tRDD
RAS to DIN Delay Time
13
-
15
-
§ À
tWDD
WE to DIN Delay Time
13
-
15
-
§ À
tOFR
Output Buffer Turn-off Delay Time from RAS
-
13
-
15
§ À 13,21
tWEZ
Output Buffer Turn-off Delay Time from WE
-
13
-
15
§ À
13
tOH
Output Data Hold Time
3
-
3
-
§ À
21
tOHR
Output Data Hold Time from RAS
3
-
3
-
§ À
21
tRCHR
Read Command Hold Time from RAS
50
-
60
-
§ À
tOHO
Output Data Hold Time from OE
3
-
3
-
§ À
tCLZ
CAS to Output in Low - Z
2
-
2
-
§ À
Rev 0.1 / Apr’01
8,9
9
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Wrtie Cycles
GMM773322(3)80CNTG-5
Symbol
GMM773322(3)80CNTG-6
Parameter
Min
Max
Min
Max
Unit Notes
tWCS
Write Command Set-up Time
0
-
0
-
§ À 14
tWCH
Write Command Hold Time
8
-
10
-
§ À 21
tWP
Write Command Pulse Width
8
-
10
-
§ À
tRWL
Write Command to RAS Lead Time
18
-
20
-
§ À
tCWL
Write Command to CAS Lead Time
8
-
10
-
§ À
tDS
Data-in Set-up Time
0
-
0
-
§ À 15
tDH
Data-in Hold Time
13
-
15
-
§ À 15
Read-Modify-Write Cycles
GMM77332(3)280CNTG-5
Symbol
GMM773322(3)80CNTG-6
Parameter
Min
Max
Min
Max
Unit Notes
tRWC
Read-Modify-Write Cycle Time
116
-
140
-
§ À
tRWD
RAS to WE Delay Time
72
-
84
-
§ À 14
tCWD
CAS to WE Delay Time
30
-
34
-
§ À 14
tAWD
Column Address to WE Delay Time
42
-
49
-
§ À 14
tOEH
OE Hold Time from WE
13
-
15
-
§ À
Cycles
Refresh Cycle
GMM773322(3)80CNTG-5
Symbol
Parameter
GMM773322(3)80CNTG-6
Min
Max
Min
Max
Unit Notes
tCSR
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
5
-
5
-
§ À
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
8
-
10
-
§ À
tWRP
WE setup Time
(CAS-before-RAS Refresh Cycle)
5
tWRH
WE Hold Time
(CAS-before-RAS Refresh Cycle)
8
-
10
-
§ À
tRPC
RAS Precharge to CAS Hold Time
5
-
5
-
§ À
Rev 0.1 / Apr’01
§ À
5
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Extended Data Out Mode Cycles
GMM773322(3)80CNTG-5
GMM773322(3)80CNTG-6
Parameter
Symbol
Unit
Min
Max
Min
Max
Notes
tHPC
EDO Page Mode Cycle Time
20
-
25
-
§ À 20
tWPE
Write pulse width during CAS Precharge
8
-
10
-
§ À
tRASP
EDO Mode RAS Pulse Width
-
100000
-
tACP
Access Time from CAS Precharge
-
28
-
35
tRHCP
RAS Hold Time from CAS Precharge
33
-
40
-
§ À
tCOL
CAS Hold Time Referred OE
8
-
10
-
§ À
tCOP
CAS to OE set-up Time
5
-
5
-
§ À
tRCHP
Read Command Hold Time from CAS
Precharge
28
-
35
-
§ À
tDOH
Output Data Hold Time from CAS Low
5
-
5
-
§ À 9,22
tOEP
OE Precharge Time
8
-
10
-
§ À
100000 § À 16
§ À 9,17
EDO Page Mode Read-Modify-Write cycle
GMM773322(3)80CNTG-5
tHPRWC
GMM773322(3)80CNTG-6
Parameter
Symbol
EDO Page Mode Read-Modify-Write Cycle Time
tCPW
WE delay time from CAS precharge
Notes
Unit
Min
Max
Min
Max
57
-
68
-
§ À
45
-
54
-
§ À 14
Present Detect Read cycle
GMM773322(3)80CNTG-5 GMM773322(3)80CNTG-6
Symbol
tPD
tPDOFF
Rev 0.1 / Apr’01
Parameter
Unit
Min
PDE to Valid PD bit
PDE to PD bit in active
Max
Min
10
2
7
2
Max
10
ns
7
§ À
Notes
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Notes:
AC measurements assume tT = 2§ .À
AC initial pause of 200 us is required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh)
3. Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if t RCD is greater than the specified t RCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the t RAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if t RAD is greater than the specified t RAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and V IL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
8. Assumes that t RCD<=tRCD(max) and t RAD<=tRAD(max). If t RCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >=tRAD + tAA(max).
11. Assumes that tRAD >=tRAD (max) and tRCD + tCAC(max)<=tRAD + tAA(max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
1.
2.
13. tOFF(max), tOEZ(max), t OFR(max) and t WEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
14. tWCS, t RWD, t CWD, t AWD, and t CPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if t WCS >=tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD >= tRWD(min), t CWD>=tCWD(min), t AWD>=tAWD(min) and t CPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. tDS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in extended data out mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
20. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC(tCAS + t CP + 2t T) becomes greater than the
specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in
EDO page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
22. tDOH defines the time at which the output level go cross. V OL=0.8V, VOH=2.0V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
§ Âperiod on the condition a and b below.
a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
25. For L_version, it is available to apply each 128 ms and 31.2 us instead of 64ms and 15.6us at
note 23.
10us. It is undefined
26. At t RASS£ ¾100 us , self refresh mode is activated, and not activated at tRASS£ ¼
within the range of 10 us £ t¼RASS £ 1¼00 us . for tRASS £ 1¾0 us , it is necessary to satisfy tRPS.
27. XXX: H or L ( H : VIH(min)<=VIN<=VIH(max), L: VIH(min)<=VIN<=VIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Timing Waveforms
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tRAD
tASR
ADDRESS
tRAL
tRAH
tASC
ROW
tCAH
COLUMN
tRRH
tRCS
tRCH
WE
tCAC
tOFF
tAA
High-Z
DOUT
DOUT
tRAC
tOEZ
tDZC
tCDD
High-Z
DIN
tDZO
tOAC
tOED
OE
*
FIGURE 1. READ CYCLE
Rev 0.1 / Apr’01
: Don`t care
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
ADDRESS
tRAH
tASC
ROW
tCAH
COLUMN
tWCS
tWCH
WE
tDS
DIN
tDH
DIN
High-Z
DOUT
*
**
: Don`t care
OE : Don`t care
> tWCS (min)
*** tWCS =
FIGURE 2. EARLY WRITE CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
ADDRESS
tRAH
tCAH
tASC
ROW
COLUMN
tCWL
tRCS
tRWL
tWP
WE
tDZC
tDH
tDS
High-Z
DIN
DIN
tOED
tDZO
tOEH
OE
tOEZ
High-Z
DOUT
**
INVALID
OUTPUT
*
: Don`t care
** Invalid DOUT comes out,
when OE is low level.
FIGURE 3. DELAYED WRITE CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRWC
tRAS
tRP
RAS
tT
tRCD
tCAS
tCRP
CAS
tRAD
tRAH
tASR
ADDRESS
tASC
ROW
tCAH
COLUMN
tCWL
tRWL
tWP
tCWD
tAWD
tRCS
tRWD
WE
tAA
tRAC
tDZC
High-Z
DIN
tDH
tDS
tCAC
DIN
tOED
tOEH
High-Z
DOUT
DOUT
tDZO
tOAC
tOEZ
OE
*
FIGURE 4. READ MODIFY WRITE CYCLE
Rev 0.1 / Apr’01
: Don`t care
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRC
tRAS
tRP
RAS
tCRP
tT
tRPC
tCRP
CAS
tASR
ADDRESS
tRAH
ROW
High-Z
DOUT
* OE,WE : Don`t care
** Rrfresh address :
FIGURE 5. RAS ONLY REFRESH CYCLE
A0~A12 (AX0 ~ AX12)
tRC
tRP
tRAS
tRC
tRP
tRAS
tRP
RAS
tRPC
tCPN
tT
tCSR
tRPC
tCHR
tCPN
tCRP
tCSR
tCHR
CAS
ADDRESS
tOFF
DOUT
INVALID
DOUT
High-Z
: Don`t care
*
**
WE : VIH
FIGURE 6. CAS BEFORE RAS REFRESH CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRC
tRC
tRAS
tRP
(Read)
tRAS
tRC
tRP
tRAS
(Refresh)
tRP
(Refresh)
RAS
tT
tCHR
tRSH
tRCD
tCRP
tCAS
CAS
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
ROW
COLUMN
tRCH
tRCS
tRRH
WE
tCAC
tAA
tOFF
tRAC
DOUT
High-Z
DOUT
tDZC
tOEZ
High-Z
DIN
tCDD
tDZO
tOAC
tOED
OE
*
FIGURE 7. HIDDEN REFRESH CYCLE
Rev 0.1 / Apr’01
: Don`t care
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRASP
tRP
tRHCP
RAS
tT
tCSH
tRCD
tHPC
tCAS
tCP
tCAS
tRSH
tCP
tCAS
tCRP
CAS
tRAD
tRAL
tCSH
tASR
ADDRESS
tRAH
ROW
tASC
tCAH
tASC
COLUMN
tCAH
COLUMN
tASC
tCAH
COLUMNN
tRCH
tRCHA
tRCS
tRRH
tRCHC
WE
tOAC
OE
tRAC
tAA
tCAC
DOUT
tCPA
tAA
tCAC
High-Z
tWEZ
tOHR
tOFR
tOFF
tCPA
tAA
tCAC
tOEZ
tDOH
DOUT 1
tOH
tDOH
DOUT 2
DOUT N
*
: Don`t care
FIGURE 8. EXTENDED DATA OUT MODE READ CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRASP
tRP
tCPRH
RAS
tT
tHPC
tCSH
tCP
tCP
tCAS
tRSH
tCAS
tCAS
tRCHR
tRCHC
tRCH
tRCS
tCRP
tHPC
tCP
tCAS
CAS
tHPC
tRRH
tRCS
tRCH
WE
tRAL
tASC
tASR
ADDRESS
ROW
tASC
tCAH
tASC
tCAH
tCAH
tASC
tCAH
tRAH
COLUMN 1
COLUMN 2
tCAL
COLUMN 3
tCAL
COLUMN N
tCAL
tCOL
tOFR
tOFF
tOHR
tOH
tCAL
tCOP
OE
tCPA
tOAC
tCAC
tAA
tRAC tWEZ
tAA
tOEZ
tCPA
tAA
tCAC
tCAC
tOAC
tCPA
tAA
tOEZ
tDOH
tOAC
tOEZ
tCAC
High-Z
DOUT 1
DOUT
DOUT 2
DOUT 2
DOUT 3
DOUT N
FIGURE 9. EXTENDED DATA OUT MODE READ CYCLE (OE CONTROL)*
*NOTE : EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high
during CAS high, the data will not come out until next CAS access. When WE goes low during
CAS high, the data will not come out until next CAS access.
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRP
tRASP
RAS
tT
tHPC
tCSH
tRCD
tCAS
tCP
tRSH
tCAS
tCRP
tCP
tCAS
CAS
tASR
tRAH
ADDRESS
tASC
ROW
tASC
tCAH
COLUMN 1
tWCS
tWCH
COLUMN 2
tWCS
tCAH
tASC
tCAH
COLUMN N
tWCH
tWCS
tWCH
WE
tDS
DIN
tDH
tDS
DIN 1
tDH
tDS
DIN 2
tDH
DIN N
High-Z
DOUT
* OE : Don`t care
** tWCS >=tWCS (min)
***
: Don`t care
FIGURE 10. EXTENDED DATA OUT MODE EARLY WRITE CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRP
tRASP
RAS
tCP
tT
tCP
tCSH
tCRP
tHPC
tRCD
tCAS
tRSH
tCAS
tCAS
CAS
tRAD
tASR
tASC
tRAH
ADDRESS
tASC
tCAH
ROW
tASC
tCAH
tCAH
COLUMN 1
COLUMN 2
COLUMN N
tCWL
tRCS
tCWL
tRCS
tCWL
tRWL
tRCS
WE
tWP
tDZC
tDS
tWP
tDS
tDZC
tDH
DIN
tDH
tDZO
tOED
tDH
DIN 2
DIN 1
tDZO
tWP
tDS
tDZC
DIN N
tDZO
tOED
tOEH
tOED
tOEH
tOEH
OE
tCLZ
High-Z
DOUT
tCLZ
tCLZ
tOEZ
INVALID
DOUT
tOEZ
tOEZ
INVALID
DOUT
INVALID
DOUT
*
: Don`t care
** tOEH=> tCWL
FIGURE 11. EXTENDED DATA OUT MODE DELAYED WRITE CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRP
tRASP
RAS
tHPRWC
tT
tCRP
tCP
tRCD
tCAS
tRSH
tCP
tCAS
tCAS
CAS
tRAD
tASR
tRAH
ADDRESS
tASC
tASC
tCAH
ROW
tCAH
tCAH
COLUMN 1
tRCS
tASC
COLUMN 2
tRWD
tAWD
tCWD
COLUMN N
tRCS
tCPW
tAWD
tCWD
tDZC
tDS
tCWL
tRCS
tCPW
tAWD
tCWD
tDZC
tDS
tCWL
tCWL
tRWL
WE
tWP
tDZC
tDS
tWP
tDH
DIN
tDH
tOED
tOEH
tOEZ
tOAC
tCAC
tAA
tRAC
tOEH
tOEZ
tOAC
tCAC
tAA
tCPA
tOEZ
tOAC
tCAC
tCPA
tCLZ
tCLZ
DOUT 1
High-Z
tOED
tOEH
OE
DIN N
tDZO
tDZO
tOED
tDH
DIN 2
DIN 1
tDZO
tWP
tAA
tCLZ
DOUT 2
DOUT N
DOUT
*
High-Z
: Don`t care
** tOEH => tCWL
FIGURE 12. EXTENDED DATA OUT MODE READ MODIFY WRITE CYCLE
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRP
tRASP
RAS
tT
tCP
tCAS
tRCD
CAS
tCP
tCP
tCAS
tCRP
tCAS
tCAS
tCSH
tRCHC
tRSH
tWP
tWCS tWCH
tCPW
WE
tRRH tRCH
tRAL
tAWD
tRAH
tASC
ADDRESS
ROW
tASC
tASC
tCAH
tASR
COLUMN
1
COLUMN
2
tCAH
COLUMN
4
COLUMN
3
tRDD
tDS
tDH
tDS
tASC
tCAH
tCAH
tCDD
tDH
Din
DIN 1
High - Z
DIN 3
tWDD
tOED
OE
tCAC
tOAC
tAA
tCPA
Dout
High - Z
tDOH
tCAC
tOEZ
tAA
tCPA
DOUT 2
tCAC
tAA
tOAC
tOFR
tOFF
tOH
tCPA
DOUT 3
DOUT 4
: Don`t care
*
FIGURE 13. EXTENDED DATA OUT MODE MIX CYCLE (1)
Rev 0.1 / Apr’01
*23
tWEZ
tOEZ
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRP
tRASP
RAS
tT
tCSH
tCRP
tCP
tCP
tCAS
tRCD
CAS
tCP
tCAS
tCAS
tCAS
tRCHR
tRCH tWCH
tWCS
tRCS
tASR
tRAH
tASC
tCAH
COLUMN
4
COLUMN
3
COLUMN
2
tCAL
tCAL
Din
tASC
tCAH
tCAH
COLUMN
1
ROW
tRAL
tASC
tASC
tCAH
tDS
High - Z
Dout
tOED
tCOL
tCAC
tAA
tOEZ
tCOP
tOEZ
tCPA
tOAC
DOUT 1
High - Z
tCAC
tAA
tOAC
tCPA
tOFF
tOH
tOFR
DOUT 4
DOUT 3
: Don`t care
*
FIGURE 14. EXTENDED DATA OUT MODE MIX CYCLE (2)
Rev 0.1 / Apr’01
tRDD
tCDD
DIN 3
OE
tCAC
tAA
tOAC
tRAC
tCAL
tCAL
tDH
tDS
tDH
DIN 2
tOED
tRRH
tRCH
tCPW
WE
ADDRESS
tRSH
tWP
*23
tWEZ
tOEZ
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Set Cycle***
Test Mode Cycle
Reset Cycle*
Normal Mode
~
~
RAS
~
~
~
~
CAS
~
~
WE
*
CBR or RAS-only refresh
**
: Don`t care
***
Address, DIN , OE: Don`t care
FIGURE 15. TEST MODE CYCLE
tRC
tRP
tRAS
tRP
RAS
tRPC
tCSR
tCHR
tT
CAS
tCPN
tRPC
tCRP
tCPN
tWS
tWH
WE
ADDRESS
tOFF
High-Z
DOUT
INVALID DOUT
*
FIGURE 16. TEST MODE SET CYCLE
Rev 0.1 / Apr’01
: Don`t care
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRC
tRAS
tRP
RAS
tT
tCSR
tCHR
tCPT
tRSH
tCRP
tCAS
CAS
tCAH
tASC
ADDRESS
COLUMN
tWS
tWH
tRRH
tRCH
tRCS
WE
tDZC
tCDD
High-Z
DIN
tOED
tDZO
OE
tOAC
tCAC
tOEP
tOEZ
tOFF
tAA
tRAC
High-Z
DOUT
DOUT
*
: Don`t care
FIGURE 16. CAS BEFORE RAS REFRESH COUNTER CHECK CYCLE (READ)
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
tRC
tRAS
tRP
RAS
tCSR
tCHR
tCPT
tRSH
tCRP
tCAS
tT
CAS
tASC
ADDRESS
tCAH
COLUMN
tWS
tWH
tWCS
tWCH
WE
tDS
DIN
tDH
DIN
OE
High-Z
DOUT
*
: Don`t care
FIGURE 17. CAS BEFORE RAS REFRESH COUNTER CHECK CYCLE (WRITE)
Rev 0.1 / Apr’01
GMM773322(3)80CNTG-5/6
32MX72 Async. DRAM DIMM with ECC
Unit: mil (mm)
* (1 mil = 1/1000 inches)
Package Dimension
700(17.78)
2000(50.8)
157.48(4.0)
5250(133.35)
1
450(11.43)
84
"C"1450(36.83)
"B"
2150(54.61)
"A"
250(6.35)
1700(43.18)
4550(115.57)
5013.78(127.35)
157.48(4.0) max.
157.48(4.0) min.
(Front Side)
168
85
(Rear Side)
50(1.27)
125(3.175)
R
50(1.27)
125(3.175)
39.37(1.0)
DETAIL "C"
78.74(2.0)
DETAIL "B"
100(2.54) min.
R
39.37(1.0)
39.37(1.0)
2(0.05)~10(0.25)
122.83(3.12)
78.74(2.0)
DETAIL "A"
NOTE : 1. Tolerances on all dimensions +/-5 (0.127) unless otherwise specified.
2. Thickness includes Plating and / or Metallization.
Rev 0.1 / Apr’01
21