ETC GMM27317230ATG-7J

16Mx72 bits
PC100 SDRAM Registered DIMM
based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
GMM27317230ATG
Description
Features
The GMM27317230ATG is a 16M x 72bits
Synchronous Dynamic RAM MODULE
which is assembled 9 pieces of 16M x 8bits
Synchronous DRAMs in 54 pin TSOP II
package, 2 pieces of 16 bits Register in 48 pin
TSSOP package, one clock distribution PLL
in 24 pin SOP and one 2048 bit EEPROM in 8
pin TSSOP package mounted on a 168 pin
printed circuit board with decoupling
capacitors. The GMM27317230ATG is
optimized for application to the systems which
are required high density and large capacity
such as main memory of the computers and an
image memory systems, and to the others
which are requested compact size.
The GMM27317230ATG provides common
data inputs and outputs.
GMM27317230ATG (Double Side)
* PC100/PC66 Compatible
-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)/-10K(PC66)
* 3.3V +/- 0.3V Power supply
* Maximum Clock frequency
100 / 125 MHz
* LVTTL Interface
* Burst read/write operation and burst read/
single write operation capability
* Programmable burst length ;
1, 2, 4, 8, Full page
* Programmable burst sequence
Sequential / Interleave
* Full Page burst length capability
Sequential burst
Burst stop capability
* Programmable CAS Latency ; 2, 3
* CKE power down mode
* Input / Output data masking
* 4096 Refresh Cycles / 64ms
* Auto refresh / Self refresh Capability
* Serial Presence Detect with EEPROM
Pin Name
(Top)
(Bottom)
CK0, 1, 2, 3
CKE0
S0, 2
RAS
CAS
WE
A0 ~ A11
BA0,1
REGE
DQ0 ~ 63
CB0 ~ 7
DQMB0 ~ 7
VCC
VSS
NC
VREF
SDA
SCL
SA0 ~ 2
WP
DU
Clock input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Bank Address input
Register Enable
Data input / output
Check Bits
Data input / output Mask
Power for internal circuit
Ground for internal circuit
No Connect
Power Supply for Reference
Serial Data input/ output
Serial Clock
Address in EEPROM
Write Protect for SPD
Don't Use
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Dec.99
© 1999 Hyundai MicroElectronics
GMM27317233ATG
Pin Configuration
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
VSS
29
DQMB1
57
DQ18
85
VSS
2
DQ0
30
S0
58
DQ19
86
3
DQ1
31
DU
59
VCC
4
DQ2
32
VSS
60
DQ20
5
DQ3
33
A0
61
NC
6
VCC
34
A2
62 *VREF, NC 90
7
DQ4
35
A4
63
*CKE1
8
DQ5
36
A6
64
VSS
9
DQ6
37
A8
65
10
DQ7
38
A10/AP
11
DQ8
39
12
VSS
40
13
DQ9
14
Pin
Symbol
Pin
Symbol
113 DQMB5 141
DQ50
DQ32
114
*S1
142
DQ51
87
DQ33
115
RAS
143
VCC
88
DQ34
116
VSS
144
DQ52
89
DQ35
117
A1
145
NC
VCC
118
A3
146 *VREF, NC
91
DQ36
119
A5
147
REGE
92
DQ37
120
A7
148
VSS
DQ21
93
DQ38
121
A9
149
DQ53
66
DQ22
94
DQ39
122
BA0
150
DQ54
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
VCC
68
VSS
96
VSS
124
VCC
152
VSS
41
VCC
69
DQ24
97
DQ41
125
CK1
153
DQ56
DQ10
42
CK0
70
DQ25
98
DQ42
126
*A12
154
DQ57
15
DQ11
43
VSS
71
DQ26
99
DQ43
127
VSS
155
DQ58
16
DQ12
44
DU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
S2
73
VCC
101
DQ45
129
*S3
157
VCC
18
VCC
46
DQMB2
74
DQ28
102
VCC
130 DQMB6 158
DQ60
19
DQ14
47
DQMB3
75
DQ29
103
DQ46
131 DQMB7 159
DQ61
20
DQ15
48
DU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
CB0
49
VCC
77
DQ31
105
CB4
133
VCC
161
DQ63
22
CB1
50
NC
78
VSS
106
CB5
134
NC
162
VSS
23
VSS
51
NC
79
CK2
107
VSS
135
NC
163
CK3
24
NC
52
CB2
80
NC
108
NC
136
CB6
164
NC
25
NC
53
CB3
81
WP
109
NC
137
CB7
165
SA0
26
VCC
54
VSS
82
SDA
110
VCC
138
VSS
166
SA1
27
WE
55
DQ16
83
SCL
111
CAS
139
DQ48
167
SA2
28
DQMB0
56
DQ17
84
VCC
112 DQMB4 140
DQ49
168
VCC
* These pins are not used in this module
Rev. 1.1/Dec.99
2
GMM27317233ATG
Block Diagram
S0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB0
DQMB1
CS
U0
CS
DQMB5
U1
CS
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ53
DQ 54
DQ 55
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQMB4
DQMB6
U2
CS
U5
CS
U6
CS
U7
S2
DQMB2
DQMB3
CS
DQMB7
U3
U8
CS
A0 ~ A11, BA0,1
U0 - U8
RAS
U0 - U8
U4
CAS
CK0
PLL
12pF
U0 - U8
WE
U0 - U8
S0,2
U0 - U8
PCK
REGE
Vcc
10kohm
CK1,2,3
12pF
SCL
VCC
VSS
Rev. 1.1/Dec.99
U0 - U8
Register
CKE0, DQMB0~7
10ohm
10ohm
CS
U0 ~ U8
Capacitor
two 0.0022uF and one 0.22uF per SDRAM
Serial PD
A0
A1
SDA
WP
A2
Vss
47kohm
U0 ~ U8
SA0 SA1 SA2
3
GMM27317233ATG
Pin Description
Pin Name
CK0, 1, 2, 3
(input pins)
CKE0
(input pin)
DESCRIPTION
CK is the master clock input to this pin. The other input signals are
referred at CK rising edge.
This pin determines whether or not the next CK is valid. If CKE is
High, the next CK rising edge is valid. If CKE is Low, the next CK
rising edge is invalid. This pin is used for power-down and clock
suspend modes.
S0, 2
(input pins)
When S is Low, the command input cycle becomes valid. When S is
high, all inputs are ignored. However, internal operations (bank active,
burst operations, etc.) are held.
RAS, CAS and WE
(input pins)
Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation
commands (read, write, etc.) depending on the combination of their
voltage levels. For details, refer to the command operation section.
A0 ~ A11
(input pins)
Row address (AX0 to AX11) is determined by A0 to A11 level at the
bank active command cycle CK rising edge. Column address is
determined by A0 to A9 level at the read or write command cycle CK
rising edge. And this column address becomes burst access start
address. A10 defines the precharge mode. When A10 = High at the
precharge command cycle, both banks are precharged. But when A10 =
Low at the precharge command cycle, only the bank that is selected by
BA0 is precharged.
BA0,1
(input pin)
BA0,1 are bank select signal. If BA0 is Low and BA1 is High, bank 0 is
selected. If BA0 is High and BA1 is Low, bank 1 is selected. If BA0 is
Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
DQ0 ~ DQ63
CB0 ~ CB7
(I/O pins)
Data is input and output from these pins. These pins are the same as
those of a conventional DRAMs. Data is not latched in the register.
DQMB0 ~ DQMB7
(input pins)
VCC
3.3 V is applied. (VCC is for the internal circuit)
VSS
Ground is connected. (VSS is for the internal circuit)
REGE
(register enable pin)
NC
Rev. 1.1/Dec.99
DQMB controls input/output buffers.
Read operation: If DQMB is High, The output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data
is not written). If DQMB is Low, the data is written.
If REGE input is high, permits the DIMM to operate in `registered mode`.
If REGE input is low, permits the DIMM to operate in `buffered mode`.
No Connection pins.
4
GMM27317233ATG
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
-0.5 to Vcc+0.5
(<= 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
-0.5 to +4.6
V
1
Short circuit output current
IOUT
50
mA
PT
1.0
W
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
-55 to +125
C
Power dissipation
Notes : 1. Respect to VSS
Recommended DC Operating Conditions (Ta = 0 to + 70C)
Parameter
Symbol
Min
Max
Unit
Note
VCC, VCCQ
3.0
3.6
V
1
VSS, VSSQ
0
0
V
Input high voltage
VIH
2.0
Vcc + 0.3
V
1, 2
Input low voltage
VIL
-0.3
0.8
V
1,3
Supply voltage
Notes : 1. All voltage referred to VSS.
2. VIH (max) = 5.6V for pulse width <= 3ns
3. VIL (min) = -2.0V for pulse width <= 3ns
Registered DIMM Operation
1. All control and address signals are registered on-DIMM register and hence delayed by one cycle in
arriving at the SDRAMs. But data is not registered in the register.
2. CAS latency defines the delay from when a READ command is registered on a rising clock edge to
when the data from that READ command becomes available at the outputs. Do not confuse DIMM
CAS latency with the SDRAM CAS latency which is one clock less.
Rev. 1.1/Dec.99
5
GMM27317233ATG
DC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ= 0 V)
Parameter
-8
- 7K
- 7J
- 10K
Max
Max
Max
Max
Symbol
Unit Test conditions Notes
Burst length= 1
tRC = min
CKE = VIL,
tCK = 12 ns
Operating
current
ICC1
Standby current in
power down
ICC2P
20
mA
ICC2PS
10
mA
CKE=VIL,
tCK= Infinity
6
ICC2N
140
mA
CKE,CS = VIH,
tCK = 12ns
4
ICC2NS
130
mA
CKE,CS = VIH,
tCK = Infinity
4
1,2,5
2,6
Standby current in
power down
(input signal stable)
Standby current in
non power down
(CAS Latency=2)
Standby current in
non power down
(input signal stable)
1100
1000
mA
1, 2, 3
5
ICC3P
50
mA
CKE = VIL,
tCK = 12 ns,
DQ = High-Z
Active standby current
in power down
ICC3PS
(input signal stable)
45
mA
CKE = VIL,
tCK = Infinity
1,2,4
2,8
Active standby current
in power down
ICC3N
280
mA
CKE,CS = VIH,
tCK = 12 ns,
DQ = High-Z
Active standby current
in non power down ICC3NS
(input signal stable)
260
mA
CKE,CS = VIH,
tCK = Infinity
tCK = min
Active standby current
in non power down
Burst
operating
current
( CL= 2 )
ICC4
1200
1200
900
900
mA
( CL= 3 )
ICC4
1300
1200
1200
1200
mA
Refresh current
ICC5
1900
1800
1800
1700
mA
tRC = min
3
Self refresh current
ICC6
mA
VIH >=VCC - 0.2
VIL <=0.2V
7
Rev. 1.1/Dec.99
20
BL = 4
1,2,3
6
GMM27317233ATG
- 8, - 7K, -7J, -10K
Parameter
Symbol
Unit Test conditions Notes
Min
Max
Input leakage current
ILI
-1
1
uA
0<=Vin<=VCC
Output leakage current
ILO
-1.5
1.5
uA
0<=Vout <=VCC
DQ = disable
Output high voltage
VOH
2.4
-
V
IOH = -2 mA
Output low voltage
VOL
-
0.4
V
IOL =2 mA
Notes : 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Addresses are changed once per one cycle.
4. Addresses are changed once per two cycles.
5. After Power down mode, CLK operating current.
6. After Power down mode, no CLK operating current.
7. After self refresh mode set, self refresh current.
8. Input signals are VIH or VIL fixed.
Capacitance (Ta = 25C, VCC, VCCQ = 3.3V +/- 0.3V)
Symbol
Parameter
Min
Max
Unit
Notes
CI1
Input capacitance (A0 ~ A11, BA0,1)
-
20
pF
1, 3
CI2
Input capacitance (RAS, CAS, WE, CKE)
-
20
pF
1, 3
CI3
Input capacitance (CK0~CK3)
-
40
pF
1, 3
CI4
Input capacitance (S0, S2)
-
20
pF
1, 3
CI5
Input capacitance (DQMB0 ~ DQMB7)
-
20
pF
1, 3
CI/O
I/O capacitance (DQ0 ~ 63)
-
20
pF
1, 2 ,3
Note :1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. DQMB = VIH to disable Dout.
3. This parameter is sampled and not 100% tested.
Rev. 1.1/Dec.99
7
GMM27317233ATG
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V)
-8
Parameter
System clock
cycle time
(CL=2)
(CL=3)
CLK high pulse width
CLK low pulse width
Access time
from CLK
(CL=2)
(CL=3)
Data-out hold time
CLK to Data-out low
impedance
CLK to Data-out
high impedance
( CL = 2,3 )
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for
power down exit
CKE hold time
Command (CS, RAS,
CAS, WE, DQM)
setup time
Command (CS, RAS,
CAS, WE, DQM)
hold time
Ref/Active to Ref/Active
command period
Active to Precharge
command period
Active command to
column command
(same bank)
Precharge to active
command period
Rev. 1.1/Dec.99
Symbol
- 7K
Min Max Min
- 7J
- 10K
Max Min Max
Min Max
Unit
Notes
ns
1
tCK
tCK
tCKH
tCKL
tAC
tAC
tOH
12
-
10
-
15
-
15
-
8
-
10
-
10
-
10
-
3
-
3
-
3
-
3
-
ns
1
3
-
3
-
3
-
3
-
ns
1
-
6
-
6
-
8
-
9
ns
1, 2
-
6
-
6
-
6
-
8
3
-
3
-
3
-
3
-
ns
1, 2
tLZ
2
-
2
-
2
-
2
-
ns
1, 2, 3
tHZ
-
6
-
6
-
6
-
7
ns
1, 4
tDS
tDH
tAS
tAH
tCES
2
-
2
-
2
-
2
-
ns
1
1
-
1
-
1
-
1
-
ns
1
2
-
2
-
2
-
2
-
ns
1
1
-
1
-
1
-
1
-
ns
1
2
-
2
-
2
-
2
-
ns
1, 5
tCESP
2
-
2
-
2
-
2
-
ns
1
tCEH
1
-
1
-
1
-
1
-
ns
1
tCS
2
-
2
-
2
-
2
-
ns
1
tCH
1
-
1
-
1
-
1
-
ns
1
tRC
68
-
70
-
70
-
90
-
ns
1
tRAS
48
120000
50
120000
50
120000
60
120000
ns
1
tRCD
20
-
20
-
20
-
30
-
ns
1
tRP
20
-
20
-
20
-
30
-
ns
1
8
GMM27317233ATG
AC Characteristics (Ta = 0 to 70C, VCC, VCCQ = 3.3 V +/- 0.3 V, VSS, VSSQ = 0 V)
(Continued)
-8
Parameter
Symbol
Write recovery or data-in
to precharge lead time
Active (a) to Active (b)
command period
Refresh period
PLL Stabilization time
- 7K
Min Max Min
- 7J
- 10K
Max Min Max
Min Max
Unit
Notes
tRWL
8
-
10
-
10
-
15
-
ns
1
tRRD
16
-
20
-
20
-
20
-
ns
1
tREF
tSTAB
-
64
-
64
-
64
-
64
ms
200
-
200
-
200
-
200
-
us
6
Notes : 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.40V.
If tT is longer than 1ns,transition time compensation should be considered.
2. Access time is measured at 1.40V. Load condition is CL = 50pF without termination.
3. tLZ (min)defines the time at which the outputs achieves the low impedance state.
4. tHZ (max)defines the time at which the outputs achieves the high impedance state.
5. tCES define CKE setup time to CKE rising edge except Power down exit command.
6. The on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before any
operation can be guaranteed.
Test Condition
• Input and output-timing reference levels: 1.4V
• Input waveform and output load: See following figures
I/O
2.4V
OPEN
80%
input
0.4V
20%
CL
tT
Rev. 1.1/Dec.99
tT
9
GMM27317233ATG
Relationship Between Frequency and Minimum Latency
-8
Parameter
frequency(MHz)
Symbol 125
DQM to data out
CKE to CLK disable
Register set to active command
CS to command disable
Power down exit to command
input
Rev. 1.1/Dec.99
-7J
-10K
Notes
83
100
100
100
66
100
66
8
12
10
10
10
15
10
15
lRCD
3
2
2
2
2
2
3
2
1
lRC
9
6
7
7
7
6
9
6
= [lRAS
+lRP], 1
lRAS
6
4
5
5
5
4
6
4
1
lRP
3
2
2
2
2
2
3
2
1
lRWL
1
1
1
1
1
1
1
1
1
lRRD
2
2
2
2
2
2
2
2
1
lSREX
1
2
1
1
1
2
2
2
lAPW
4
3
3
3
3
3
5
3
= [lRWL
+lRP], 1
lSEC
9
6
7
7
7
6
9
6
= [lRC]
lHZP
lHZP
-
2
2
2
-
2
-
2
3
3
3
3
3
3
3
3
lAPR
1
1
1
1
1
1
1
1
lEP
lEP
-
-1
-1
-1
-
-1
-
-1
-2
-2
-2
-2
-2
-2
-2
-2
lCCD
1
1
1
1
1
1
1
1
lWCD
0
0
0
0
0
0
0
0
lDID
lDOD
lCLE
lRSA
lCDD
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
lPEC
1
1
1
1
1
1
1
1
tCK (ns)
Active command to column
command (same bank)
Active command to active
command (same bank)
Active command to Precharge
command (same bank)
Precharge command to active
command (same bank)
Write recovery or last data-in to
Precharge command (same bank)
Active command to active
command (different bank)
Self refresh exit time
Last data in to active command
(Auto Precharge, same bank)
Self refresh exit to command
input
Precharge
(CL=2)
command to
(CL=3)
high impedance
Last data out to active
command
(auto Precharge) (same bank)
Last data out to
(CL=2)
Precharge
(CL=3)
(early Precharge)
Column command to column
command
Write command to data in
latency
DQM to data in
-7K
10
GMM27317233ATG
Relationship Between Frequency and Minimum Latency
-8
Parameter
frequency(MHz)
Symbol 125
tCK (ns)
Burst stop to
(CL=2)
output valid
(CL=3)
data hold
Burst stop to
(CL=2)
output high
(CL=3)
impedance
Burst stop to write data ignore
lBSR
lBSR
lBSH
lBSH
lBSW
- 7K
- 7J
- 10K
83
100
100
100
66
100
66
8
12
10
10
10
15
10
15
-
1
1
1
-
1
-
1
2
2
2
2
2
2
2
2
-
2
2
2
-
2
-
2
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
0
Notes
Notes : 1. lRCD to lRRD are recommended value.
Rev. 1.1/Dec.99
11
GMM27317233ATG
Unit: mil (mm)
* (1 mil = 1/1000 inches)
Package Dimension
700(17.78)
1500(38.10)
157.48(4.0)
5250(133.35)
1
84
"C"1450(36.83)
450(11.43)
"B"
2150(54.61)
"A"
250(6.35)
1700(43.18)
4550(115.57)
157.48(4.0) max.
5013.78(127.35)
157.48(4.0) min.
(Front Side)
168
85
(Rear Side)
39.37(1.0)
39.37(1.0)
R78.74
(2.0)
125(3.175)
50(1.27)
125(3.175)
39.37(1.0)
DETAIL "C"
78.74(2.0)
DETAIL "B"
100(2.54) min.
R78.74
(2.0)
5.9(0.15)
122.83(3.12)
78.74(2.0)
50(1.27)
DETAIL "A"
NOTE : 1. Tolerances on all dimensions +/-5 (0.127) unless otherwise specified.
2. Thickness includes Plating and / or Metallization.
Rev. 1.1/Dec.99
12
SDRAM Memory Module EEPROM Data Information
GMM27317230ATG-7J
Byte
Function described
0
Define # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type (FPM, EDO, SDRAM...) from appendix A
3
# Row addresses on this assembly
4
# Column addresses on this assembly
5
# Module banks on this assembly
6
Data width of this assembly...
7
...Data width continuation
8
Voltage interface standard of this assembly
9
SDRAM cycletime
10
SDRAM access from clock
11
DIMM configuration type (Non-parity, Parity, ECC)
12
Refresh rate/type
13
DRAM/SDRAM width, primary DRAM/SDRAM
14
Error checking SDRAM data width
15
Minimum clock delay, back to back random column address(tCCD)
16
Burst lengths supported
17
# Banks on each SDRAM device
18
CAS # latency
19
CS # latency
20
Write latency
21
SDRAM module attributes
22
SDRAM device attributes : General
23
Minimum clock cycle time at CL X-1
24
Maximum data access time from clock at CL X-1
25
Minimum clock cycle time at CL X-2
26
Maximum data access time from clock at CL X-2
27
Minimum row precharge time(tRP)
28
Minimum row active to row active delay(tRRD)
29
Minimum RAS to CAS delay(tRCD)
30
Minimum RAS pulse width(tRAS)
31
Module bank density
32
Command and address signal input setup time(tAS)
33
Command and address signal input hold time(tAH)
34
Data signal input setup time(tDS)
35
Data signal input hold time(tDH)
36-61
Superset information (may be used in future)
62
SPD revision
63
Checksum for bytes 0-62
64
Manufacturers JEDEC ID code per JEP-106F
65-71
….. Continuation Manufacturers JEDEC ID Code
72
Manufacturing location
73
Manufacturer's part number
74
=== Allowed characters include 0-9, A-Z and 'space' ===
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Revision Code
92
Revision Code
93
Date Code
94
95-98
Assembly serial number
99-125
Manufacturer specific data
126
Intel specification for frequency
127
Intel specfication details for 100Mhz Support
128-135
System integrator's ID
136-150
System integrator's P/N
151-152
System integrator's D/C
153-165
System integrator's S/N
166
Checksum for bytes 128-165
167-189
Top level system serial no.
190-221
Open
222
Checksum for bytes 167-221
223-253
Open
254
Checksum for Bytes 223-253
255
Checksum for bytes 0-128
Function support
128 Bytes
256 Bytes
SDRAM
12
10
1
72 bit
N/A
LVTTL
10.0 ns
6.0 ns
ECC
Normal(15.625us)
x8
x8
1 ns
Full Page Supported
4 banks
2&3
0
0
Register(w/ PLL)
Support All(VCC:10%)
15.0 ns
8.0 ns
N/A
N/A
20 ns
20 ns
20 ns
50 ns
128 MBytes
2.0 ns
1.0 ns
2.0 ns
1.0 ns
TBD
Rev 1.2
HME
Korea
GMM27317230ATG-7J
Rev 0
WW
YY
Binary incremental
N/A
CK0_CL3
HEX Code DEC Code
80
128
08
008
04
004
0C
012
0A
010
01
001
48
072
00
000
01
001
A0
160
60
096
02
002
80
128
08
008
08
008
01
001
8F
143
04
004
06
006
01
001
01
001
16
022
0F
015
F0
240
80
128
00
000
00
000
14
020
14
020
14
020
32
050
20
032
20
032
10
016
20
032
10
016
00
000
12
018
AF
175
E0
224
00
000
52
082
47
071
4D
077
4D
077
32
050
37
055
33
051
31
049
37
055
32
050
33
051
30
048
41
065
54
084
47
071
2D
045
37
055
4A
074
20
32
00
000
00
000
14
020
00
000
00
000
00
000
64
100
8D
141
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
BIN Code
10000000
00001000
00000100
00001100
00001010
00000001
01001000
00000000
00000001
10100000
01100000
00000010
10000000
00001000
00001000
00000001
10001111
00000100
00000110
00000001
00000001
00010110
00001111
11110000
10000000
00000000
00000000
00010100
00010100
00010100
00110010
00100000
00100000
00010000
00100000
00010000
00000000
00010010
10101111
11100000
00000000
01010010
01000111
01001101
01001101
00110010
00110111
00110011
00110001
00110111
00110010
00110011
00110000
01000001
01010100
01000111
00101101
00110111
01001010
00100000
00000000
00000000
00010100
00000000
00000000
00000000
01100100
10001101
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00.05.09
Note
1st Group
82d(free)
G
M
M
2
7
3
1
7
2
3
0
A
T
G
7
J
blank
20 ww
0 year
98byte start
Source : Intel Rev. 1.2B
SDRAM Memory Module EEPROM Data Information
GMM27317230ATG-7K
Byte
Function described
0
Define # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type (FPM, EDO, SDRAM...) from appendix A
3
# Row addresses on this assembly
4
# Column addresses on this assembly
5
# Module banks on this assembly
6
Data width of this assembly...
7
...Data width continuation
8
Voltage interface standard of this assembly
9
SDRAM cycletime
10
SDRAM access from clock
11
DIMM configuration type (Non-parity, Parity, ECC)
12
Refresh rate/type
13
DRAM/SDRAM width, primary DRAM/SDRAM
14
Error checking SDRAM data width
15
Minimum clock delay, back to back random column address(tCCD)
16
Burst lengths supported
17
# Banks on each SDRAM device
18
CAS # latency
19
CS # latency
20
Write latency
21
SDRAM module attributes
22
SDRAM device attributes : General
23
Minimum clock cycle time at CL X-1
24
Maximum data access time from clock at CL X-1
25
Minimum clock cycle time at CL X-2
26
Maximum data access time from clock at CL X-2
27
Minimum row precharge time(tRP)
28
Minimum row active to row active delay(tRRD)
29
Minimum RAS to CAS delay(tRCD)
30
Minimum RAS pulse width(tRAS)
31
Module bank density
32
Command and address signal input setup time(tAS)
33
Command and address signal input hold time(tAH)
34
Data signal input setup time(tDS)
35
Data signal input hold time(tDH)
36-61
Superset information (may be used in future)
62
SPD revision
63
Checksum for bytes 0-62
64
Manufacturers JEDEC ID code per JEP-106F
65-71
….. Continuation Manufacturers JEDEC ID Code
72
Manufacturing location
73
Manufacturer's part number
74
=== Allowed characters include 0-9, A-Z and 'space' ===
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Revision Code
92
Revision Code
93
Date Code
94
95-98
Assembly serial number
99-125
Manufacturer specific data
126
Intel specification for frequency
127
Intel specfication details for 100Mhz Support
128-135
System integrator's ID
136-150
System integrator's P/N
151-152
System integrator's D/C
153-165
System integrator's S/N
166
Checksum for bytes 128-165
167-189
Top level system serial no.
190-221
Open
222
Checksum for bytes 167-221
223-253
Open
254
Checksum for Bytes 223-253
255
Checksum for bytes 0-128
Function support
128 Bytes
256 Bytes
SDRAM
12
10
1
72 bit
N/A
LVTTL
10.0 ns
6.0 ns
ECC
Normal(15.625us)
x8
x8
1 ns
Full Page Supported
4 banks
2&3
0
0
Register(w/ PLL)
Support All(VCC:10%)
10.0 ns
6.0 ns
N/A
N/A
20 ns
20 ns
20 ns
50 ns
128 MBytes
2.0 ns
1.0 ns
2.0 ns
1.0 ns
TBD
Rev 1.2
HME
Korea
GMM27317230ATG-7K
Rev 0
WW
YY
Binary incremental
N/A
CK0_CL2
HEX Code DEC Code
80
128
08
008
04
004
0C
012
0A
010
01
001
48
072
00
000
01
001
A0
160
60
096
02
002
80
128
08
008
08
008
01
001
8F
143
04
004
06
006
01
001
01
001
16
022
0F
015
A0
160
60
096
00
000
00
000
14
020
14
020
14
020
32
050
20
032
20
032
10
016
20
032
10
016
00
000
12
018
3F
063
E0
224
00
000
52
082
47
071
4D
077
4D
077
32
050
37
055
33
051
31
049
37
055
32
050
33
051
30
048
41
065
54
084
47
071
2D
045
37
055
4B
075
20
32
00
000
00
000
14
020
00
000
00
000
00
000
64
100
8F
143
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
00
000
BIN Code
10000000
00001000
00000100
00001100
00001010
00000001
01001000
00000000
00000001
10100000
01100000
00000010
10000000
00001000
00001000
00000001
10001111
00000100
00000110
00000001
00000001
00010110
00001111
10100000
01100000
00000000
00000000
00010100
00010100
00010100
00110010
00100000
00100000
00010000
00100000
00010000
00000000
00010010
111111
11100000
00000000
01010010
01000111
01001101
01001101
00110010
00110111
00110011
00110001
00110111
00110010
00110011
00110000
01000001
01010100
01000111
00101101
00110111
01001011
00100000
00000000
00000000
00010100
00000000
00000000
00000000
01100100
10001111
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00.05.09
Note
1st Group
82d(free)
G
M
M
2
7
3
1
7
2
3
0
A
T
G
7
K
blank
20 ww
0 year
98byte start
Source : Intel Rev. 1.2B