GENLINX™ GS9010A Serial Digital Automatic Tuning Subsystem DATA SHEET FEATURES DEVICE DESCRIPTION • when used with the GS9005A or GS9015A and the GS9000B or GS9000S, the GS9010A: The GENLINX ™ GS9010A is a monolithic integrated circuit designed to be an Automatic Tuning Subsystem (ATS) when used with the GS9005A Receiver or the GS9015A Reclocker and the GS9000B or GS9000S Decoder. The GS9010A ATS eliminates the need to manually set or externally temperature compensate the Receiver or Reclocker VCO. The GS9010A can also determine whether the incoming data stream is 4ƒsc NTSC, 4ƒsc PAL or component 4:2:2. - constitutes an automatic 'tweakless' Serial Digital receiving system - eliminates the need for trim pots and external temperature compensation for bit rates to 370 Mb/s - automatically determines whether data is 4ƒsc or 4:2:2, and whether the 4ƒsc data is NTSC or PAL - acquires lock from a 'no signal' condition in typically 50 ms - holds lock during data interruptions for typically 2s - relocks from synchronous switching in less than 10 µs • 16 pin SOIC packaging • operates from a single +5 or -5 volt supply • typically consumes only 40 mW • immunity to spurious HSYNC inputs • defines minimum GS9005A VCO frequency after extended absence of input signal • matches GS9005A capture range APPLICATIONS • 4ƒsc, 4:2:2 & 360 Mb/s serial digital interfaces ORDERING INFORMATION Part Number Package Type Temperature Range GS9010ACKC 16 Pin Wide SOIC 0° to 70° C GS9010ACTC 16 Pin Wide SOIC Tape 0° to 70° C The GS9010A is an enhanced version of the GS9010. Pin compatible with the GS9010, the GS9010A offers improved noise immunity to spurious HSYNC signals. The GS9010A includes a ramp generator/oscillator which repeatedly sweeps the Receiver/Reclocker VCO frequency over a set range until the system is correctly locked. Once locked, an automatic fine tuning (AFT) loop maintains the VCO control voltage at its optimum centre point over variations in temperature. During normal operation, the GS9000B or GS9000S Decoder provides continuous HSYNC pulses which disable the ramp/oscillator of the GS9010A. This maintains the correct Receiver/Reclocker VCO frequency. When an interruption to the incoming data stream is detected by the Receiver/Reclocker, the Carrier Detect goes LOW and opens the AFT loop in order to maintain the correct VCO frequency for a period of typically 2 seconds. If the signal is re-established within this 2 seconds, the Receiver/Reclocker will rapidly relock. For periods longer than typically 2 seconds, the VCO slowly drifts towards a minimum frequency. Typically after 2 minutes, the serial clock output of the PLL settles to approximately 85 MHz when ƒ/2 is high or 170 MHz when ƒ/2 is low. The GS9010A is packaged in a 16 pin wide SOIC, operates from a single +5 or -5 volt supply and typically consumes 40 mW of power. + 1 PAL/NTSC 16 STANDARDS THRESHOLD ADJUST 2 OUT (to GS9005A) - FREQUENCY COMPENSATION 4 LOOP FILTER (from GS9005A) 5 VREF + 20k 3 CARRIER DETECT (from GS9005A) 14 13 OSCILLATOR OSCILLATOR 11 25kΩ 8 ƒ/2 (to GS9005A) DELAY Revision Date: August 1997 IN- 18k 6 10 ÷4 COMPOSITE / COMPONENT DETECTOR FUNCTIONAL BLOCK DIAGRAM 9 HSYNC ( (from GS9000B o orGS9000S) SWF (from GS9000B or GS9000S) FV CAP Document No. 521 - 01 - 05 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946 Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839 PIN CONNECTIONS GS9010A PIN DESCRIPTIONS P/N 1 16 STDT OUT 2 15 VCC1 IN - 3 COMP LF PIN SYMBOL TYPE No. 1 DESCRIPTION P/N O PAL/NTSC Output 2 OUT O Output to Receiver/Reclocker RVCO resistor 14 CD 3 IN- I Inverting input to internal amplifier 4 13 HSYNC 4 COMP I Frequency compensating Capacitor 5 12 GND 5 LF I Loop Filter input from Receiver/Reclocker 6 ƒ/2 O Divide by two output to Receiver/Reclocker 7 V CC 8 SWF I Sync Warning Flag Input from GS9000B 9 FV CAP I Capacitor for frequency to voltage converter GS9010A ƒ/2 6 11 OSC VCC2 7 10 DLY SWF 8 9 FV CAP or GS9000S ABSOLUTE MAXIMUM RATINGS Parameter Value/Units ±5.5 V Supply Voltage Input Voltage Range (any input) -VEE < VI < VCC DC Input Current (any one input) Operating Temperature Range Storage Temperature Range 10mA 0°C ≤ T A ≤ 70°C -65°C ≤ TS ≤150°C Lead Temperature (soldering, 10 seconds) 10 DLY I Capacitor for internal delay 11 OSC I RC time constant for internal oscillator 12 GND 13 HSYNC I HSYNC input from GS9000B or GS9000S Decoder 14 CD I Carrier Detect input from Receiver/Reclocker 15 V CC 16 STDT Most negative supply voltage Most positive supply voltage I Standards threshold adjust input from external potentiometer 260°C GS9010A DC ELECTRICAL CHARACTERISTICS PARAMETER Most positive supply voltage SYMBOL (V CC = 5 V, TA = 0° C to 70° C, unless otherwise specified) CONDITIONS MIN TYP MAX UNITS Supply Voltage VS 4.75 5.0 5.25 V Supply Current IS 5.5 8.0 10.0 mA OUT Voltage Maximum VOUT MAX VLF = 2.7 V 2.2 2.3 2.4 V LF Input Bias ILF VLF = 2.3 V -10 0 10 nA IN Input Bias I IN CD Low 0 5 70 nA STDT Input Bias I STDT VSTDT = 1.5 V -10 -0.5 0 µA STDT Input Voltage VSTDT 0 - 3 V CD Input Pull-Up Resistor RCD 13.5 18 22.5 kΩ P/N Low-Level Output Voltage VP/NL - - 0.2 V P/N Low-Level Output Current IP/NL -1 - - mA - 30 - kΩ IL = 0 P/N Output Pull-Up Resistor ƒ/2 High-Level Output Voltage Vƒ/2H IL = 0 4 4.6 - V ƒ/2 Low-Level Output Voltage Vƒ/2L IL = 0 - - 0.2 V ƒ/2 Output Current Iƒ/2 - ± 40 - µA SWF Input Bias ISWF 150 200 250 µA GS9010A AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL VSWF = 5 V ( V CC= 5 V, TA = 0° C to 70° C, unless otherwise specified) CONDITIONS MIN TYP MAX UNITS HSYNC Input Frequency for ƒ/2 High ƒCOMPOSITE VCC = 4.75 to 5.25 - 7.85 11.0 kHz HSYNC Input Frequency for ƒ/2 Low ƒCOMPONENT VCC = 4.75 to 5.25 11.0 15.7 - kHz HSYNC Input Rise / Fall Time trHSYNC CMOS Driving Levels - - 100 ns 521 - 01 - 05 2 SYSTEM DESCRIPTION The GS9005A Receiver or GS9015A Reclocker along with the GS9000B or GS9000S Decoder form a serial to parallel decoding system for Serial Digital Video signals. Use of the GS9010A eliminates the need to manually tune the VCO and externally temperature compensate for all data rates. Figure 1 shows a simplified block diagram of the Automatic Tuning Sub-System and Figure 2 shows the relevant waveforms. The active high CARRIER DETECT output of the Receiver/ Reclocker indicates the presence of serial data. If the CARRIER DETECT input to the GS9010A (pin 14) is HIGH (see Fig 2. [A]) and a Timing Reference Signal (TRS) is not being detected by the GS9000B or GS9000S Decoder, an oscillator in the GS9010A produces a s a w t o o t h r a m p s i g n a l a t t h e O U T p i n ( p i n 2 ) ( s e e Figure 2. [C]). This output is connected to the Receiver/Reclocker R VCO pin via a resistor which converts this voltage ramp into a current ramp. The frequency of the VCO is changed by varying the current drawn from the RVCO pin such that a lower sweep voltage at pin 2 of the GS9010A causes a higher VCO frequency. In order to avoid this, another circuit ensures that the MODULUS CONTROL is set HIGH (ƒ/2 ENABLED) for composite data rates and LOW (ƒ/2 OFF) for component data rates. This is accomplished through a Frequency Detector (Frequency to Voltage Convertor, FVC) which measures the frequency of HSYNC and compares it to a reference. If the frequency of HSYNC corresponds to composite video, the comparator output is high and the ÷ 4 (MODULUS CONTROL) is set HIGH. Conversely, when the frequency of HSYNC corresponds to component video, the MODULUS CONTROL is set LOW. If the FVC measurement results in any change to the MODULUS CONTROL, the PLL will immediately lose lock, the TRS will not be detected and the oscillator will begin to sweep the VCO frequency. Now the PLL will reacquire lock with the MODULUS CONTROL in the correct state before the ÷ 4 output changes state. In a noisy environment or at power-on, erratic TRS will cause the GS9000B or GS9000S to output an artificially low HSYNC frequency. This condition often subsides after input data stabilizes or in the case of power-up, once the supplies have settled. The GS9010A employs a technique to provide noise immunity within the COMPOSITE/COMPONENT DETECTOR (CCD) to protect against erroneous modulus settings. This technique is explained in the following paragraph. As the frequency sweeps, the PLL will lock to the incoming data stream and the GS9000B or GS9000S decoder will detect TRS. The TRS detect function is provided by the HSYNC output of the GS9000B or GS9000S. In this case, HSYNC is a digital signal which changes state whenever TRS is detected. This signal is connected to the HSYNC input (pin 13) of the GS9010A (see Figure 2 [B]). This signal will be at a rate equal to one half the horizontal scan rate for composite video and equal to the horizontal scan rate for component video since both EAV and SAV produce an HSYNC state change. The presence of detected TRS will shut off the GS9010A oscillator and disable the sweep. Even though the oscillator is off, the Automatic Fine Tuning (AFT) function provided by the buffer amplifier in the GS9010A remains in the control loop in order to centre the GS9005A or GS9015A loop filter voltage to VREF (approximately 2.3V). A delay is required for the FVC calculation within the CCD before the ÷ 4 is set/reset. In the GS9010A, the trigger threshold for this delay is controlled by the ƒ/2 and FVCAP output voltage. Because this threshold is modulated, the incoming HSYNC frequency must be compatible with the current ƒ/2 state before the delay is triggered. This threshold control prevents artificially low HSYNC frequencies from triggering the set/reset of the ÷ 4 thus preventing the wrong MODULUS CONTROL. If the serial digital signal is interrupted, CARRIER DETECT (pin 14) goes LOW and turns the internal oscillator off. The buffer from the LOOP FILTER input (pin 5) to the 20 kΩ integrator resistor is disabled and its output becomes high impedance, neither sinking nor sourcing current. In this state, the output voltage from the GS9010A will remain constant for a time period of typically 2 seconds. The VCO in the Receiver/ Reclocker will remain tuned to the correct frequency so that the PLL will relock quickly without frequency sweeping when the serial data returns. For longer periods of data interruption, the external integration capacitor between the OUT and IN pins will slowly discharge and the VCO will drift lower in frequency. The serial clock output frequency of the PLL will settle to approximately 170 MHz when ƒ/2 is high and 85 MHz when ƒ/2 is low. A limit has been set on the maximum OUT voltage to prevent Receiver/Reclocker VCO shutdown allowing faster relock time once data is reapplied. The VCO within the GS9005A or GS9015A has a dual modulus divider feature which optimises jitter performance for the lower data rates. This feature is enabled by a logic HIGH on the ƒ/2 pin. The MODULUS CONTROL output (pin 6) (see Figure 2. [D]) of the GS9010A controls this ƒ/2 function to set the VCO frequency to twice the normal rate. Under normal operation the VCO within the GS9005A or GS9015A, operates at twice the output clock frequency, which means that for 360 Mb/s data the VCO is operating at 720 MHz (2 x 360 MHz). For 177 Mb/s (PAL - 4fsc), with the ƒ/2 function enabled, the VCO operates at 708 MHz (2 x 2 x 177 MHz). In the case of component and composite NTSC, the VCO operates at 540 MHz (2 x 270 MHz) and 572 MHz (2 x 2 x 143 MHz) respectively. This means that the VCO is tuned to the same frequency range for 4:2:2 and the respective 4ƒsc signals. The MODULUS CONTROL itself is derived by dividing the GS9010A oscillator by four. It is possible that the PLL could lock with the MODULUS CONTROL in the wrong state (ƒ/2 OFF) for component data rates. 3 521 - 01 - 05 PAL/NTSC THRESHOLD ADJUST Capacitor values for the GS9010A should be used as indicated in Figure 3. These capacitors have been optimised to produce correct system operation. To adjust the P/N threshold using a potentiometer, monitor the OUT voltage at pin 2 of the GS9010A. Start with a composite NTSC source, and record the voltage at pin 2 as VNTSC. Now connect a PAL source to the input and record the voltage at pin 2 as VPAL. Adjust the reference voltage, VREF at pin 16 to a value approximately halfway between VPAL and VNTSC, i.e. VREF = (VNTSC + VPAL)/2. The P/N threshold will now be set. GS9010 REPLACEMENT NOTE: To ensure proper operation of the GS9010A, the resistor network connected between the GS9010A OUT (pin 2) and GS9005A RVCO3 (pin 17), and the value of FVCAP (pin 9) must be as per this data sheet (Figure 3). Replacing a GS9010 with a GS9010A will require modification to these component values. Gating of the HSYNC input is available on the SWF pin. This gating is used with the GS9010A to improve immunity to missing TRS detection during power-up or in noisy system applications. GS9000B/GS9000S GS9005A/GS9015A RE-TIMED DATA SERIAL DIGITAL PLL SERIAL DATA IN ƒ/2 DIGITAL VIDEO DECODER RECOVERED CLOCK RVCO CARRIER LOOP DETECT FILTER 1k2 1k2 +5V 120Ω 100nF THRESHOLD ADJUST HSYNC 16 + 1 PAL/NTSC VREF + 2 20k 5 - CINT 18k 14 13 OSCILLATOR 25kΩ 8 6 MODULUS CONTROL ÷4 COMPOSITE / COMPONENT DETECTOR GS9010A All resistors in ohms, all capacitors in microfarads unless otherwise stated. Fig. 1 Automatic Tuning Sub System Block Diagram 521 - 01 - 05 4 SWF 2 SECONDS (A) CARRIER DETECT (PIN 14) TRS 2 MINs TRS (B) HSYNC (PIN 13) LOOP LOCKED LOOP LOCKED (C) OUT (PIN 2) (D) ƒ/2 (PIN 6) COMPOSITE VIDEO COMPONENT VIDEO (NOT TO SCALE) Fig. 2 System Waveform Diagrams APPLICATIONS Correct operation of an autotuning receiver is determined by using a suitable EDH measurement tool or Digital to Analog Monitor to verify error free performance. Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed when a microstrip trace runs across a break in the ground plane. The correct operation of a locked autotuning receiver can be verified by referring to Figure 2. The HSYNC output from the GS9000B or GS9000S decoder will toggle on each occurrence of the Timing Reference Signal (TRS). The state of the HSYNC output is not significant, just the rate at which it toggles. The series resistors at the parallel data output of the GS9000B/S are used to slow down the fast rise/fall time of the GS9000B/S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins to minimize radiation from these pins. Figure 3 shows a typical application circuit using the GS9010A in an autotuning SDI receiver. Application Note - PCB Layout Special attention must be paid to component layout when designing high performance serial digital receivers. For background information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B Deserializer Evaluation Board” The use of a star grounding technique is required for the loop filter components of the GS9005A/15A. 5 521 - 01 - 05 SWF SSI DVCC +5V VCC +5V VCC 0.1µ 10µ + 100 3.3k 100 0.1µ + 0.1µ DGND 6 23 100 7 22 100 8 V SS1 21 CC SS0 20 390 9 390 10 VCC3 CD 19 VSS PARALLEL DATA BIT 8 25 100 24 100 23 100 22 100 21 100 20 100 PD1 19 100 PD7 PD6 SDI PD5 (4) SCI GS9000B PD4 or GS9000S PD3 SCI SS1 PD2 SS0 SST DVCC PARALLEL DATA BIT 9 28 27 26 PD8 1 PD9 VSS SDI 11 VCC 2 HSYNC 100 SCO RVCO3 EYEOUT RVCO2 RVCO1 VSS 24 3 SWF VCC4 SSI VEE2 A/D AGC VEE1 VCC1 5 12 13 14 15 16 17 18 5.6p (1) RVCO0 75 22n GS9005A 9 SDI 10 ƒ/2 VEE3 100 SCO VCC2 11 25 SDO 8 SDI 47p 390 SDO DDI 7 4 28 27 26 12 13 14 15 16 VDD 47p 1 DDI 6 LOOP 75 2 PDO 0.1µ 3 PCLK VCC 5 390 4 SYNC WARNING FLAG HSYNC OUTPUT DGND SWC DGND ECL DATA INPUT INPUT INPUT SELECTION 0.1µ SCE GND 100 DGND VCC VCC VDD 10µ VDD 10µ + 17 PARALLEL DATA BIT 7 PARALLEL DATA BIT 6 PARALLEL DATA BIT 5 PARALLEL DATA BIT 4 PARALLEL DATA BIT 3 PARALLEL DATA BIT 2 PARALLEL DATA BIT 1 DVCC PARALLEL DATA BIT 0 PARALLEL CLOCK OUT 18 SYNC CORRECTION ENABLE 0.1µ 113 (2) 910 0.1µ 0.1µF 100 100 DGND 10n DGND 1.2k DVCC VCC 1.2k (3) 0.1µ 68k 50k 22n VCC 120 STAR ROUTED DGND GS9010A 6.8µ + 1 (2) 6.8µ 2 + 3 4 3.3n 5 VCC P/N STDT OUT VCC INCOMP CD HSYNC LF GND 6 ƒ/2 OSC 7 VCC DLY 8 SWF FVCAP 16 0.1µ 15 14 13 VCC 12 11 10 STANDARD TRUTH TABLE 100k 9 82n (2) 0.68µ VCC 0.1µ 180n SWF ƒ/2 P/N STANDARD 0 0 4:2:2 - 270 0 1 4:2:2 - 360 1 0 4ƒsc - NTSC 1 1 4ƒsc - PAL All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated. (1) Typical value for input return loss matching (2) To reduce board space, the two anti-series 6.8 µF capacitors (connected across pins 2 and 3 of the GS9010A) may be replaced with a 1.0 µF non-polarized capacitor provided that: (a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a 0.33 µF capacitor and (b) the GS9005A /15A Loop Filter Capacitor is 10 nF. (3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A. (4) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to a maximum frequency of 300 Mbps. DOCUMENT IDENTIFICATION Fig. 3 Typical Application Circuit PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. REVISION NOTES Figures 1 and 3 updated PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. CAUTION ELECTROSTATIC DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright January 1994 Gennum Corporation. All rights reserved. Printed in Canada. 521 - 01 - 05 6