a FEATURES 35 MSPS Encode Rate 16 pF Input Capacitance 550 mW Power Dissipation Industry-Standard Pinouts MIL-STD-883 Compliant Versions Available APPLICATIONS Professional Video Systems Special Effects Generators Electro-Optics Digital Radio Electronic Warfare (ECM, ECCM, ESM) Monolithic 8-Bit Video A/D Converter AD9048 FUNCTIONAL BLOCK DIAGRAM NLINV 12 AD9048 NMINV 28 VIN 23 1 RT 18 R 2 E N C O D I N G R 127 R/2 RM 27 R/2 L O G I C 128 R L A T C H 254 1 D1 (MSB) 2 D2 3 D3 4 D3 13 D5 14 D6 15 D7 16 D8 (LSB) R GENERAL DESCRIPTION The AD9048 is an 8-bit, 35 MSPS flash converter, made on a high speed bipolar process, which is an alternate source for the TDC1048 unit, offers enhancements over its predecessor. Lower power dissipation makes the AD9048 attractive for a variety of system designs. Because of its wide bandwidth, it is an ideal choice for real-time conversion of video signals. Input bandwidth is flat with no missing codes. Clocked latching comparators, encoding logic and output buffer registers operating at minimum rates of 35 MSPS preclude a need for a sample-and-hold (S/H) or track-and-hold (T/H) in most system designs using the AD9048. All digital control inputs and outputs are TTL compatible. Devices operating over two ambient temperature ranges and with two grades of linearity are available. Linearities of either 0.5 LSB or 0.75 LSB can be ordered for a commercial range of 0°C to +70°C or extended case temperatures of –55°C to +125°C. 255 RB 26 CONVERT 17 6 10 VCC 7 8 VEE 9 5 11 DGND 19 25 AGND Commercial versions are packaged in 28-lead DIPs; extended temperature versions are available in ceramic DIP and ceramic LCC packages. Both commercial units and MIL-STD-883 units are standard products. The AD9048 A/D converter is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9048/883B data sheet for detailed specifications. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9048–SPECIFICATIONS (typical with nominal supplies unless otherwise noted) ABSOLUTE MAXIMUM RATINGS 1 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . 1.0 sec5 Operating Temperature Range (Ambient) AD9048JJ/KJ/JQ/KQ . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD9048SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C Maximum Junction Temperature (Plastic) . . . . . . . . +150°C6 Maximum Junction Temperature (Hermetic) . . . . . . +175°C6 Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C VCC to DGND . . . . . . . . . . . . . . . . . . . –0.5 V dc to +7.0 V dc AGND to DGND . . . . . . . . . . . . . . . . –0.5 V dc to +0.5 V dc VEE to AGND . . . . . . . . . . . . . . . . . . . +0.5 V dc to –7.0 V dc VIN, VRT or VRB to AGND . . . . . . . . . . . . . . . . . +0.5 V to VEE VRT to VRB . . . . . . . . . . . . . . . . . . . . . . –2.2 V dc to +2.2 V dc CONV, NMINV or NLINV to DGND –0.5 V dc to +5.5 V dc Applied Output Voltage to DGND . . . –0.5 V dc to +5.5 V dc2 Applied Output Current, Externally Forced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 mA to +6.0 mA3, 4 ELECTRICAL CHARACTERISTICS (V CC Parameter (Conditions) Temp Test Level RESOLUTION DC ACCURACY Differential Nonlinearity +25°C Full +25°C Full Full I VI I VI VI +25°C Full +25°C Full Full I VI I VI V Full V +25°C Full +25°C Full +25°C +25°C I VI I VI IV IV REFERENCE INPUT Positive Reference Voltage9 Negative Reference Voltage9 Differential Reference Voltage Reference Ladder Resistance Ladder Temperature Coefficient Reference Ladder Current Reference Input Bandwidth Full Full Full Full Full Full +25°C V V V VI V VI V DYNAMIC PERFORMANCE10 Conversion Rate Aperture Delay Aperture Uncertainty (Jitter) Output Delay (tPD) Output Hold Time (tOH)11 Transient Response12 Overvoltage Recovery Time13 Rise Time Fall Time Output Time Skew14 +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C I IV IV I I IV V I I I NMINV and NLINV INPUTS +0.4 V Input Current +2.4 V Input Current +5.5 V Input Current Full Full Full VI VI VI CONVERT INPUT Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Convert Pulsewidth (LOW) Convert Pulsewidth (HIGH) Full Full Full Full +25°C +25°C +25°C VI VI VI VI IV I I Integral Nonlinearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Voltage Range 7 Input Bias Current Input Resistance Input Capacitance Full Power Bandwidth8 = +5.0 V; VEE = –5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted) AD9048JJ/JQ Min Typ Max AD9048KJ/KQ Min Typ Max AD9048SE/SQ Min Typ Max AD9048TE/TQ Min Typ Max Units 8 8 8 8 Bits 0.4 0.75 1.0 0.6 0.75 1.0 GUARANTEED 5 4 200 40 10 30 35 5 0.3 0.5 0.75 0.4 0.5 0.75 GUARANTEED 12 12 8 8 5 4 0.4 0.75 1.0 0.6 0.75 1.0 GUARANTEED 12 12 8 8 5 4 0.3 0.5 0.75 0.4 0.5 0.75 GUARANTEED 12 12 8 8 5 4 12 12 8 8 20 20 20 20 –2.1; +0.1 36 60 100 300 –2.1; +0.1 36 60 100 300 –2.1; +0.1 36 60 100 300 –2.1; +0.1 36 60 100 300 16 15 0.0 –2.0 2.0 60 0.22 23 10 38 2.4 25 13 8 6 8 4.5 200 40 20 10 125 30 40 35 5 50 15 5 20 9 14 7 16 15 4.5 200 150 150 2.0 20 10 0.0 –2.0 2.0 60 125 0.22 23 40 10 38 2.4 25 9 8 6 8 35 5 50 15 5 20 9 14 7 2.0 4 0.0 –2.0 2.0 60 0.22 23 10 38 2.4 25 9 8 6 8 4.5 200 40 20 10 125 30 40 35 5 50 15 5 20 9 14 7 16 15 0.8 150 500 6 38 2.4 25 9 8 6 8 9 14 7 MHz ns ps ns ns ns ns ns ns ns 200 150 150 µA µA µA 4.5 0.8 150 500 6 4 18 10 V µA µA kΩ kΩ pF MHz V V V Ω Ω/°C mA MHz 5 50 15 20 2.0 4 18 10 20 mV mV mV mV µV/°C 0.0 –2.0 2.0 60 125 0.22 23 40 10 200 150 150 2.0 4 18 10 –2– 30 16 15 200 150 150 0.8 150 500 6 18 10 200 40 LSB LSB LSB LSB 0.8 150 500 6 V V µA µA pF ns ns REV. C AD9048 Parameter (Conditions) AC LINEARITY In-Band Harmonics dc to 2.438 MHz15 dc to 9.35 MHz16 Signal-to-Noise Ratio (SNR)15 1.248 MHz Input Frequency17 2.438 MHz Input Frequency17 1.248 MHz Input Frequency18 2.438 MHz Input Frequency18 Signal-to-Noise Ratio (SNR)16 1.248 MHz Input Frequency17 9.35 MHz Input Frequency17 Noise Power Ratio (NPR)19 Differential Phase 20 Differential Gain 20 DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Short Circuit Current5 POWER SUPPLY Positive Supply Current Negative Supply Current Nominal Power Dissipation Reference Ladder Dissipation Temp Test Level AD9048JJ/JQ Min Typ Max AD9048KJ/KQ Min Typ Max AD9048SE/SQ Min Typ Max AD9048TE/TQ Min Typ Max +25°C +25°C I V 47 50 48 49 55 48 47 50 48 49 55 48 dBc dBc +25°C +25°C +25°C +25°C I I I I 43.5 43 52.5 52 44 44 53 53 45 44 54 53 46 46 55 55 43.5 43 52.5 52 44 44 53 53 45 44 54 53 46 46 55 55 dB dB dB dB +25°C +25°C +25°C +25°C +25°C I V IV IV IV 43.5 44 40.5 36.5 39 45 46 40.5 39 43.5 44 40.5 39 45 Full Full Full VI VI VI 2.4 +25°C Full +25°C Full +25°C +25°C I VI I VI V V 36.5 1 2 36.5 1 2 2.4 90 34 90 550 45 56 58 110 120 550 45 1 2 dB dB dB Degree % 0.5 30 V V mA 2.4 0.5 30 56 58 110 120 NOTES 1 Maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the device may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 Applied voltage must be current-limited to specified range. 3 Forcing voltage must be limited to specified range. 4 Current is specified as negative when flowing into the device. 5 Output High; one pin to ground; one second duration. 6 Typical thermal impedances (no air flow) are as follows: Ceramic DIP: θJA = 49°C/W; θJC = 15°C/W LCC: θJA = 69°C/W; θJC = 21°C/W JLCC: θ JA = 59°C/W; θJC = 19°C/W To calculate junction temperature (T J ), use power dissipation (PD) and thermal impedance: TJ = PD (θ JA) + TAMBIENT = PD (θJC) = + T CASE. 7 Measured with VIN = 0 V and CONVERT low (sampling mode). 8 Determined by beat frequency testing for no missing codes. 9 VRT ≥ VRB under all circumstances. 1 2 2.4 0.5 30 34 46 40.5 36.5 39 0.5 30 34 90 550 45 56 58 110 120 34 90 550 45 Units 56 58 110 120 mA mA mA mA mW mW Outputs terminated with 40 pF and eight 10 Ω pull-up resistors. Interval from 50% point of leading edge CONVERT pulse to change in output data. 12 For full-scale step input, 8-bit accuracy attained in specified time. 13 Recovers to 8-bit accuracy in specified time after –3 V input overvoltage. 14 Output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. 15 Measured at 20 MHz encode rate with analog input 1 dB below full scale. 16 Measured at 35 MHz encode rate with analog input 1 dB below full scale. 17 RMS signal to rms noise. 18 Peak signal to rms noise. 19 DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading; 20 MHz encode. 20 Clock frequency = 4 × NTSC = 14.32 MHz. Measured with 40-IRE modulated ramp. Specifications subject to change without notice. 10 11 EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. Test Level II – 100% production tested at +25°C and sample tested at specific temperatures. Test Level III – Sample tested only. Test Level IV – Parameter is guaranteed by design and characterization testing. REV. C Test Level V – Parameter is a typical value only. Test Level VI – All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for military temperature devices; sample tested at temperature extremes for commercial/industrial devices. –3– AD9048 ORDERING GUIDE PIN DESIGNATIONS Model Linearity Temperature Package Option1 AD9048JJ AD9048KJ AD9048JQ AD9048KQ AD9048SE2 AD9048TE2 AD9048SQ2 AD9048TQ2 0.75 LSB 0.5 LSB 0.75 LSB 0.5 LSB 0.75 LSB 0.5 LSB 0.75 LSB 0.5 LSB 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C J-28A J-28A Q-28 Q-28 E-28A E-28A Q-28 Q-28 DIP (Q Package) (MSB) D1 1 28 NMINV D2 2 27 RM D3 3 26 RB D4 4 25 AGND DGND 5 23 VIN TOP VIEW (Not to Scale) VEE 7 NOTES 1 E = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; Q = Cerdip. 2 For temperature designation only. MIL-STD-883 and Standard Military Drawing available. 24 NC AD9048 VCC 6 22 NC VEE 8 21 NC VEE 9 20 NC VCC 10 19 AGND DGND 11 18 RT NLINV 12 17 CONVERT D5 13 16 D8 (LSB) D6 14 15 D7 AIN 28 27 26 RB 1 25 AGND VCC 6 24 NC VEE 7 23 VIN 22 NC 21 NC VCC 10 20 NC DGND 11 19 AGND AD9048 VEE 8 AGND 2 DGND 5 TOP VIEW (Not to Scale) VEE 9 AGND NMINV 3 RM 4 D2 LCC (E Package) D1 (MSB) Die Dimensions . . . . . . . . . . . . . . . . 140 × 137 × 21 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . . . . . . . . . 1 mil Gold; Gold Ball Bonding D4 NC = NO CONNECT D3 MECHANICAL INFORMATION RT (LSB) D8 D7 NC = NO CONNECT CONV 25 24 23 22 D4 D5 NC RB 26 18 RT 17 CONVERT NMINV 28 16 D8 (LSB) 15 D7 14 D6 D3 3 13 D5 D4 4 12 NLINV AD9048 TOP TOP VIEW VIEW VCC VCC DGND Bonding Diagram 5 6 7 8 VEE VEE VEE VEE VCC VEE DGND VCC 9 10 11 DGND (Not (Not to to Scale) Scale) D2 2 VCC 19 RM 27 (MSB) D1 1 DGND 20 VEE DGND 21 VCC NLINV AGND D6 NC D3 NC D7 VIN D8 D2 NC J-Leaded Ceramic (J Package) MSB AGND NMINV CONVERT RMID D6 RTOP D5 NLINV 12 13 14 15 16 17 18 RLOW NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9048 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. C AD9048 PIN FUNCTION DESCRIPTIONS Pin Description Pin Description D1–D8 Eight digital outputs. D1 (MSB) is the most significant bit of the digital output word; D8 (LSB) is the least significant bit. RB Most negative reference voltage for internal reference ladder. RM Midpoint tap on internal reference ladder. AGND One of two analog ground returns. Both grounds should be connected together and to low impedance ground plane near the AD9048. RT Most positive reference voltage for internal reference ladder. DGND One of two digital ground returns. Both grounds should be connected together and to low impedance ground plane near the AD9048. VCC Positive supply terminals; nominally +5.0 V. VEE Negative supply terminals; nominally –5.2 V. CONVERT Input for conversion signal; sample of analog input signal taken on rising edge of this pulse. VIN Analog input signal pin. NMINV “Not Most Significant Bit Invert.” In normal operation, this pin floats high; logic LOW at NMINV inverts most significant bit of digital output word [D1 (MSB)]. NLINV “Not Least Significant Bit Invert.” In normal operation, this pin floats high; logic LOW at NLINV inverts the seven least significant bits of the digital output word. Burn-In Diagram REV. C –5– AD9048 System timing, which provides details on delays through the AD9048 as well as the relationships of various timing events, is shown in Figure 2. THEORY OF OPERATION Refer to the Functional Block Diagram of the AD9048. The AD9048 comprises three functional sections: a comparator array, encoding logic and output latches. Dynamic performance of the AD9048, i.e., typical signal-tonoise ratio, is illustrated in Figures 3 and 4. Within the array, the analog input signal to be digitized is compared with 255 reference voltages. The outputs of all comparators whose references are below the input signal level will be high; outputs whose references are above that level will be low. The n-of-255 code that results from this comparison is applied to the encoding logic where it is converted into binary coding. When it is inverted with dc signals applied to the NLINV and/or NMINV pins, it becomes twos complement. After encoding, the signal is applied to the output latch circuits where it is held constant between updates controlled by the application of CONVERT pulses. The AD9048 uses strobed latching comparators in which comparator outputs are either high or low, as dictated by the analog input level. Data appearing at the output pins have a pipeline delay of one encode cycle. Input signal levels between the references applied to RT (Pin 18) and RB (Pin 26) will appear at the output as binary numbers between 0 and 255, inclusive. Signals outside that range will show up as either full-scale positive or full-scale negative outputs. No damage will occur to the AD9048 as long as the input is within the voltage range of VEE to +0.5 V. The significantly reduced input capacitance of the AD9048 lowers the drive requirements of the input buffer/amplifier and also induces much smaller phase shift in the analog input signal. Applications that depend on controlled phase shift at the converter input can benefit from using the AD9048 because of its inherently lower phase shift. The CONVERT, analog input and digital output circuits are shown in Figure 1. Figure 1. Input/Output Circuits Figure 2. Timing Diagram –6– REV. C AD9048 Ceramic 0.1 µF decoupling capacitors should be placed as closely as possible to the supply pins of the AD9048. For decoupling low frequency signals, use 10 µF tantalum capacitors, also connected as closely as practical to voltage supply pins. Within the AD9048, reference currents may vary because of coupling between the clock and input signals. As a result, it is important that the ends of the reference ladder, RT (Pin 18) and RB (Pin 28), be connected to low impedances (as measured from ground). If the AD9048 is being used in a circuit in which the reference is not varied, a bypass capacitor to ground is strongly recommended. In applications that use varying references, they must be driven from a low impedance source. Figure 3. Dynamic Performance (20 MHz Encode Rate) Figure 4. Dynamic Performance (35 MHz Encode Rate) LAYOUT SUGGESTIONS Designs that use the AD9048 or any other high speed device must follow some basic layout rules to ensure optimum performance. The first requirement is to have a large, low impedance ground plane under and around the converter. If the system uses separate analog and digital grounds, both should be solidly connected together, and to the ground plane, as closely to the AD9048 as practical to avoid ground loop currents. REV. C Figure 5. Typical Connections –7– AD9048 True Inverted Offset Twos Complement True Inverted NMINV = 1 NLINV = 1 00000000 00000001 • • • 01111111 10000000 10000001 • • • 11111110 11111111 0 0 11111111 11111110 • • • 10000000 01111111 01111110 • • • 00000001 00000000 0 1 10000000 10000001 • • • 11111111 00000000 00000001 • • • 01111110 01111111 Binary Step Range 000 001 • • • 127 128 129 • • • 254 255 –2.000 V FS 7.8431 mV Step 0.0000 V –0.0078 V • • • –0.9961 V –1.0039 V –1.0118 V • • • –1.9921 V –2.0000 V –2.0480 V FS 8.000 mV Step 0.0000 V –0.0080 V • • • –1.0160 V –1.0240 V –1.0320 V • • • –2.0320 V –2.0400 V 1 0 01111111 01111110 • • • 00000000 11111111 11111110 • • • 10000001 10000000 C1212a–0–1/99 Table I. Truth Table OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Ceramic Side-Brazed DIP 0.100 (2.54) 1 0.064 (1.63) 15 0.055 (1.40) 0.045 (1.14) 0.610 (15.24) 0.500 (14.43) 14 1.418 (36.02) 1.38 (35.06) 0.12 (3.05) 0.06 (1.53) 0.225 (5.72) MAX 0.065 (1.66) 0.038 (0.965) 0.458 (11.63) 0.442 (11.23) SQ 0.050 ±0.005 (1.27 ±0.13) 0.015 (0.305) 0.008 (0.203) 0.175 (4.45) 0.125 (3.18) 0.023 (0.508) 0.014 (0.381) SEATING 0.105 (2.67) PLANE 0.095 (2.42) 26 25 18 19 PIN 1 1 0.075 (1.91) REF 28 1 NO 1 PIN INDEX BOTTOM VIEW 11 12 0.040 (1.02) x 45° REF 3 PLCS 0.620 (15.4) 0.590 (14.74) 0.028 (0.71) 0.022 (0.56) 5 4 0.020 (0.51) x 45° REF 1 PLC NOTES 1 THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS 2 APPLIES TO ALL FOUR SIDES ALL TERMINALS ARE GOLD PLATED LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE GOLD PLATED (50 MICROINCHES MIN) KOVAR OR ALLOY 42 28-Lead J-Lead Package 25 0.450 ±0.006 (11.43 ±0.152) SQ 0.171 (4.34) MAX 26 BOTTOM VIEW 0.039 ±0.005 (0.991 ±0.127) 19 PRINTED IN U.S.A. 28 28-Terminal Leadless Chip Carrier 18 0.050 (1.27) BSC 0.028 ±0.002 (0.711 ±0.051) PIN 1 0.300 (7.62) TYP TOP VIEW (PINS DOWN) 0.420 ±0.010 (10.668 ±0.254) 0.019 ±0.002 (0.483 ±0.051) 12 4 5 0.022 ±0.003 (0.559 ±0.076) 0.488 ±0.010 SQ (11.43 ±0.254) –8– 11 0.102 ±0.010 (1.448 ±0.254) 0.006 ±0.0006 (0.152 ±0.015) REV. C