. IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Features • Programmable Wrap: Sequential or Interleave • High Performance: -68 -75A, -260, -360, Units CL=3 CL=3 CL=2 CL=3 fCK Clock Frequency 150 133 100 100 MHz tCK Clock Cycle 6.67 7.5 10 10 ns tAC Clock Access Time1 6 — — — ns tAC Clock Access Time2 — 5.4 6 6 ns 1. Terminated load. See AC Characteristics on page 40. 2. Unterminated load. See AC Characteristics on page 40. • Multiple Burst Read with Single Write Option • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (x4, x8) • Dual Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • Standard or Low Power operation • 4096 refresh cycles/64ms • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Edge • Four Banks controlled by A12/A13 (Bank Select) • Programmable CAS Latency: 2, 3 • Random Column Address every CLK (1-N Rule) • Single 3.3V ± 0.3V Power Supply • LVTTL compatible • Package: 54-pin 400 mil TSOP-Type II • Programmable Burst Length: 1, 2, 4, 8, full-page Description The IBMN364404, IBMN364804, and IBMN364164 are four-bank Synchronous DRAMs organized as 4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 150MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with IBM’s advanced 64Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CLK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus 19L3265.E35856B 1/01 accepts address data in the conventional RAS/CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (A12, A13) are strobed with RAS. Ten column addresses (A0-A9) plus bank select addresses and A10 are strobed with CAS. Column address A9 is dropped on the x8 device and column addresses A8 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A9 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 150MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR), Self Refresh, and Low Power operation are supported. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Pin Assignments for Planar Components (Top View) VDD VDD V DD 1 54 V SS VSS V SS DQ0 VDDQ DQ1 DQ0 VDDQ NC NC VDDQ NC 2 3 4 53 52 51 NC V SSQ NC DQ7 VSSQ NC DQ15 V SSQ DQ14 DQ2 DQ1 DQ0 5 50 DQ3 DQ6 DQ13 VSSQ DQ3 DQ4 VDDQ DQ5 VSSQ NC DQ2 VDDQ NC VSSQ NC NC VDDQ NC 6 7 8 9 10 49 48 47 46 45 V DDQ NC NC V SSQ NC VDDQ NC DQ5 VSSQ NC V DDQ DQ12 DQ11 V SSQ DQ10 DQ6 DQ3 DQ1 11 44 DQ2 DQ4 DQ9 VSSQ VSSQ VSSQ 12 43 V DDQ VDDQ V DDQ DQ7 VDD NC V DD NC V DD LDQM WE NC WE NC WE 13 14 15 16 42 41 40 39 NC V SS NC DQM NC VSS NC DQM DQ8 V SS NC UDQM CAS CAS RAS RAS CS CS A13/BS0 A13/BS0 CAS RAS CS A13/BS0 17 18 19 20 38 37 36 35 CLK CKE NC A11 CLK CKE NC A11 CLK CKE NC A11 A12/BS1 A12/BS1 A10/AP A10/AP A0 A0 A12/BS1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A9 A8 A7 A9 A8 A7 A1 A2 A1 A2 A1 A2 24 25 31 30 A6 A5 A6 A5 A6 A5 A3 VDD A3 VDD A3 V DD 26 27 29 28 A4 VSS A4 VSS A4 V SS 54-pin Plastic TSOP(II) 400 mil 4Mbit x 4 I/O x 4 Bank IBMN364404 2Mbit x 8 I/O x 4 Bank IBMN364804 1Mbit x 16 I/O x 4 Bank IBMN364164 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Pin Description CLK Clock Input DQ0-DQ15 Data Input/Output CKE Clock Enable DQM, LDQM, UDQM Data Mask CS (CS0, CS1) Chip Select V DD Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQs (+3.3V) WE Write Enable V SSQ Ground for DQs BS1, BS0 (A12, A13) Bank Select NC No Connection A0 - A11 Address Inputs — — Input/Output Functional Description Symbol Type Polarity Function CLK Input Positive Edge CKE Input Active High CS Input CS enables the command decoder when low and disables the command decoder when high. Active Low When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Active Low BS1, BS0 (A12, A13) Input — Selects which bank is to be active. The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. A0 - A11 Input — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. DQ0 - DQ15 InputOutput — Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. DQM LDQM UDQM Input Active High VDD , V SS Supply — Power and ground for the input buffers and the core logic. VDDQ V SSQ Supply — Isolated power supply and ground for the output buffers to provide improved noise immunity. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Ordering Information - Planar Devices (Single CS Pin) Part Number CAS Latencies IBMN364404CT3C-75A 3 Power Supply IBMN364404CT3C-260 Clock Cycle Package Power Org. 400mil Type II TSOP-54 SP x4 400mil Type II TSOP-54 SP x8 400mil Type II TSOP-54 SP x16 7.5ns 3.3V 2, 3 10ns IBMN364404CT3C-360 IBMN364804CT3C-75A IBMN364804CT3C-260 3 7.5ns 3.3V 2, 3 10ns IBMN364804CT3C-360 IBMN364164CT3C-68 IBMN364164CT3C-75A IBMN364164CT3C-260 6.67ns 3 3.3V 2, 3 7.5ns 10ns IBMN364164CT3C-360 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Planar Block Diagram Column Decoder CKE Buffer Row Decoder Row Decoder CLK Cell Array Memory Bank 0 Column Decoder Cell Array Memory Bank 1 CLK Buffer Sense Amplifiers Sense Amplifiers Column Address Counter Refresh Counter Mode Register Data Control Circuitry Control Signal Generator Address Buffers (14) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 (BS1) A13 (BS0) A10 Data Input/Output Buffers CKE Command Decoder WE Cell Array Memory Bank 2 Sense Amplifiers Column Decoder Row Decoder CAS Row Decoder CS DQX DQM Column Decoder RAS DQ0 Cell Array Memory Bank 3 Sense Amplifiers Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15). 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Mode Register Operation (Address Input For Mode Set) A13 A12 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 CAS Latency A3 A2 BT A1 A0 Address Bus (Ax) Mode Register(Mx) Burst Length Burst Type M3 Type 0 Sequential 1 Interleave Operation Mode M13 M12 M11 M10 M9 M8 M7 Burst Length Mode Length 0 0 0 0 0 0 0 Normal 0 0 0 0 1 0 0 Multiple Burst with Single Write M1 M0 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 Sequential Interleave CAS Latency 19L3265.E35856B 1/01 M2 M6 M5 M4 Latency 1 0 0 Reserved Reserved 0 0 0 Reserved 1 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 Full Page 0 0 1 Reserved 1 0 1 0 2 1 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Reserved ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A13. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organization: x4, x8, or x16). Full page burst operation is only possible using the sequential burst type. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected. Burst Length and Sequence Burst Length 2 4 8 Full Page (Note) Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) xx0 0, 1 0, 1 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 nnn Cn, Cn+1, Cn+2, ...... Not Supported Note: Page length is a function of I/O organization and column addressing. x4 organization (CA0-CA9); Page Length = 1024 bits x8 organization (CA0-CA8); Page Length = 512 bits x16 organization (CA0-CA7); Page Length = 256 bits ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank select address A12 - A13 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max). Bank Activate Command Cycle (CAS Latency = 3, tRCD = 3) T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CLK .......... Bank A Col. Addr. Bank A Row Addr. ADDRESS .......... RAS-CAS delay ( tRCD) Bank A Activate COMMAND NOP Bank B Row Addr. Bank A Row Addr. RAS - RAS delay time (tRRD) Write A with Auto Precharge NOP .......... Bank B Activate NOP Bank A Activate NOP : “H” or “L” RAS Cycle time (tRC) Bank Select The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation. Bank Selection Bits BS0 BS1 Bank 0 0 Bank 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 150 MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. If the burst length is full page, data is repeatedly read out or written until a Burst Stop or Precharge Command is issued. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs NOP NOP NOP NOP DOUT A0 DOUT A 1 DOUT A 2 DOUT A 3 DOUT A 0 DOUT A 1 DOUT A 2 NOP NOP NOP DOUT A3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQs NOP NOP NOP NOP DOUT A 0 DOUT B 0 DOUT B 1 DOUT B 2 DOUT B 3 DOUT A 0 DOUT B 0 DOUT B 1 DOUT B 2 DOUT B3 DOUT A 0 DOUT B 0 DOUT B 1 DOUT B 2 CAS latency = 3 tCK3, DQs NOP NOP NOP CAS latency = 4 tCK4, DQs ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 71 DOUT B3 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus. Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM high for CAS latency = 2 only. Required to mask first bit of READ data. DQM COMMAND CAS latency = 2 tCK2, DQs NOP READ A WRITE A NOP NOP NOP DIN A 0 DIN A1 DIN A2 DIN A 3 DIN A 0 DIN A1 DIN A2 DIN A 3 NOP NOP NOP CAS latency = 3 tCK3, DQs : “H” or “L” 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND READ A NOP WRITE A NOP NOP NOP NOP NOP NOP CL = 2: DQM needed to mask first, second bit of READ data. CAS latency = 2 tCK2, DQs DIN A 0 DIN A1 DIN A2 DIN A 3 CL = 3: DQM needed to mask first bit of READ data. CAS latency = 3 tCK3, DQs DIN A 0 DIN A1 DIN A2 DIN A 3 : DQM high for CAS latency = 2 : DQM high for CAS latency = 3 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Write Command The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK NOP COMMAND WRITE A DIN A0 DQs NOP NOP NOP DIN A 1 DIN A 2 DIN A 3 The first data element and the Write are registered on the same clock edge. NOP NOP NOP Extra data is masked. NOP : “H” or “L” Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 WRITE A WRITE B T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP NOP NOP DIN B 1 DIN B 2 DIN B 3 NOP NOP NOP 1 Clk Interval DQs 19L3265.E35856B 1/01 DIN A0 DIN B 0 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory. Minimum Write to Read Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs WRITE A READ B NOP DIN A0 NOP NOP NOP DOUT B0 DOUT B 1 DOUT B 2 DOUT B 3 DOUT B0 DOUT B1 DOUT B2 DIN A0 Input data for the Write is masked. : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 71 NOP NOP NOP DOUT B 3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Non-Minimum Write to Read Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs WRITE A NOP DIN A0 DIN A1 DIN A0 DIN A1 READ B NOP Input data for the Write is masked. NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B 3 DOUT B 0 DOUT B 1 DOUT B 2 NOP DOUT B3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. : “H” or “L” 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Stop Command Once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation or using a Precharge Command to interrupt a burst cycle and close the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. Termination of a Burst Read Operation (Burst Length = Full Page, CAS Latency = 2, 3) CLK COMMAND T0 READ A T1 NOP T2 T3 NOP NOP T4 T5 Burst Stop NOP T6 NOP T7 NOP T8 NOP The burst ends after a delay equal to the CAS latency. CAS latency = 2 DOUT A0 tCK2, DQs CAS latency = 3 tCK3, DQs DOUT A1 DOUT A2 DOUT A 3 DOUT A0 DOUT A1 DOUT A 2 DOUT A 3 If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Termination of a Burst Write Operation (Burst Length = Full Page, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2,3 DQs NOP WRITE A DIN A 0 NOP NOP DIN A1 DIN A2 Burst Stop NOP NOP NOP NOP : “H” or “L” Input data for the Write is masked. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. It should be noted that the device will not respond to the Auto-Precharge command if the device is programmed for full page burst read or write cycles, or full page burst read cycles with single write operation. When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended. Burst Read with Auto-Precharge (Burst Length = 1, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto-Precharge CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs Begin Auto-precharge 19L3265.E35856B 1/01 NOP NOP NOP NOP NOP NOP NOP NOP * tRP‡ DOUT A 0 * tRP ‡ DOUT A 0 *‡ Bank can be reactivated at completion of tRP. t RP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Read with Auto-Precharge (Burst Length = 2, CAS Latency = 2, 3) CLK COMMAND T0 T1 READ A Auto-Precharge NOP T2 T3 NOP T4 NOP tCK2, DQs DOUT A 0 NOP NOP NOP T7 T8 NOP NOP DOUT A1 * tRP‡ CAS latency = 3 tCK3, DQs T6 * tRP‡ CAS latency = 2 T5 DOUT A 0 DOUT A 1 Begin Auto-precharge *‡ Bank can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. Burst Read with Auto-Precharge (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto-Precharge NOP NOP NOP NOP DOUT A 0 DOUT A 1 DOUT A 2 Begin Auto-precharge ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 71 NOP * * tRP‡ DOUT A 0 NOP DOUT A 3 CAS latency = 3 tCK3, DQs NOP tRP‡ CAS latency = 2 tCK2, DQs NOP DOUT A 1 DOUT A 2 *‡ DOUT A3 Bank can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before autoprecharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP. Burst Read with Auto-Precharge Interrupted by Read (Burst Length = 4, CAS Latency = 2, 3) CLK COMMAND T0 READ A Auto-Precharge T1 NOP T2 READ B T3 T4 NOP NOP tCK2, DQs DOUT A 0 DOUT A 1 DOUT B 0 tCK3, DQs T7 NOP NOP NOP DOUT B 1 DOUT B2 DOUT B 3 DOUT B1 DOUT B2 T8 NOP * tRP‡ CAS latency = 3 T6 * tRP‡ CAS latency = 2 T5 DOUT A 0 DOUT A 1 *‡ DOUT B 0 DOUT B 3 Bank can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention. Burst Read with Auto-Precharge Interrupted by Write (Burst Length = 8, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto-Precharge NOP NOP NOP WRITE B tRP‡ CAS latency = 2 tCK2, DQs NOP DOUT A 0 DOUT B0 DOUT B 1 NOP NOP NOP * DOUT B 2 DOUT B3 DOUT B 4 DQM *‡ 19L3265.E35856B 1/01 Bank can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied. Burst Write with Auto-Precharge T0 T1 T2 T3 (Burst Length = 2, CAS Latency = 2, 3) T5 T6 T7 T8 T4 CLK COMMAND WRITE A Auto-Precharge NOP NOP DIN A 0 NOP NOP * tDAL‡ DIN A0 NOP NOP DIN A 1 CAS latency = 3 tCK3, DQs NOP * tDAL ‡ CAS latency = 2 tCK2, DQs NOP DIN A 1 *‡ Bank can be reactivated at completion of tDAL. Number of clocks required depends on clock cycle time and speed sort. See the Clock Frequency and Latency table. Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The precharge function will be initiated by the new command. After the Data-in to Active, delay, tDAL, is satisfied the bank may be reactivated. Burst Write with Auto-Precharge Interrupted by Write T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 3) T6 T7 T8 CLK COMMAND WRITE A Auto-Precharge NOP WRITE B NOP NOP DIN A 0 DIN A1 DIN B 0 DIN B 1 NOP NOP NOP * tDAL‡ CAS latency = 3 tCK3, DQs NOP DIN B 2 DIN B 3 *‡ Bank can be reactivated at completion of tDAL. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 71 Number of clocks required depends on clock cycle time and speed sort. See the Clock Frequency and Latency table. 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Write with Auto-Precharge Interrupted by Read T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 3) T6 T7 T8 CLK COMMAND WRITE A Auto-Precharge NOP NOP READ B DIN A0 DIN A1 NOP NOP NOP * tDAL‡ CAS latency = 3 tCK3, DQs NOP NOP DIN A 2 DOUT B0 *‡ DOUT B1 DOUT B2 Bank A can be reactivated at completion of tDAL. Number of clocks required depends on clock cycle time and speed sort. See the Clock Frequency and Latency table. Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, A12, and A13, are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 Bank Select Precharged Bank(s) LOW BS0, BS1 Single bank defined by BS0, BS1 HIGH DON’T CARE All Banks For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst Read Followed by the Precharge Command (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP NOP Precharge A NOP tRP NOP NOP * CAS latency = 2 DOUT Ax0 tCK2, DQs DOUT Ax1 DOUT Ax2 * DOUT Ax3 Bank A can be reactivated at completion of tRP. Burst Write Followed by the Precharge Command (Burst Length = 2, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP Activate Bank Ax NOP WRITE Ax0 NOP NOP tDPL‡ Precharge A NOP tRP‡ NOP * CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 *‡ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 71 Bank can be reactivated at completion of tRP. tDPL and tRP are functions of clock cycle and speed sort. See the Clock Frequency and Latency table. 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Precharge Termination The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency. Burst Read Interrupted by Precharge (Burst Length = 8, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP Precharge A NOP NOP NOP NOP * tRP‡ CAS latency = 2 tCK2, DQs DOUT Ax0 DOUT Ax1 DOUT Ax2 DOUT Ax3 * tRP‡ CAS latency = 3 tCK3, DQs DOUT Ax0 DOUT Ax1 DOUT Ax2 DOUT Ax3 * Bank A can be reactivated at completion of tRP. ‡ tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 25 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL. Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP WRITE Ax0 NOP NOP NOP Precharge A NOP NOP DQM tDPL ‡ CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL‡ CAS latency = 3 tCK3, DQs DIN Ax0 DIN Ax1 DIN Ax2 ‡ tDPL is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 26 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Automatic Refresh Command (CAS before RAS Refresh) When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC). Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 27 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge. Power Down Mode Exit Timing Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8 COMMAND NOP NOP NOP NOP NOP CLK tCK CKE tCES(min) COMMAND NOP : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 28 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency. Data Mask Activated during a Read Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP READ A DQs NOP NOP DOUT A0 NOP NOP DOUT A1 NOP NOP NOP A two-clock delay before the DQs become Hi-Z : “H” or “L” No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 29 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Clock Suspend Mode During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a oneclock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. Clock Suspend during a Read Cycle T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 2) T6 T7 T8 CLK CKE A one clock delay to exit the Suspend command A one clock delay before suspend operation starts NOP COMMAND READ A NOP NOP DQs NOP DOUT A0 DOUT A 2 DOUT A1 : “H” or “L” NOP DOUT element at the DQs when the suspend operation starts is held valid If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited. Clock Suspend during a Write Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CKE A one clock delay to exit the Suspend command A one clock delay before suspend operation starts COMMAND DQs NOP WRITE A DIN A0 NOP NOP NOP DIN A 1 DIN A 2 DIN A3 : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 30 of 71 NOP DIN is masked during the Clock Suspend Period 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Command Truth Table (See note 1) CKE Function Device State Previous Cycle Current Cycle CS RAS CAS WE DQM A12, A13 A10 A11, A9Notes A0 Mode Register Set Idle H X L L L L X Auto (CBR) Refresh Idle H H L L L H X X X X Entry Self Refresh Idle H L X X X X X X X X L L L H H X X X L H H H OP Code Exit Self Refresh Idle (SelfRefresh) L H Single Bank Precharge See Current State Table H X L L H L X BS L X Precharge all Banks See Current State Table H X L L H L X X H X Bank Activate Idle H X L L H H X BS Write Row Address 2 2 Active H X L H L L X BS L Column 2 Write with Auto-Precharge Active H X L H L L X BS H Column 2 Read Active H X L H L H X BS L Column 2 Read with Auto-Precharge Active H X L H L H X BS H Column 2 Burst Termination H X L H H L X X X X 3, 8 Active No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Clock Suspend Mode Entry Active H L X X X X X X X X Clock Suspend Mode Exit Active L H X X X X X X X X Data Write/Output Enable 4 Active H X X X X X L X X X Data Mask/Output Disable Active H X X X X X H X X X Power Down Mode Entry Idle/Active H L X X X X 6, 7 Power Down Mode Exit Any (Power Down) L H X X X X 6, 7 H X X X L H H H H X X X L H H H 5 1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table. 2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 0,1 selects bank 1; BS0, BS1 = 1,0 selects bank 2; BS0, BS1 = 1,1 selects bank 3. 3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. 8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 31 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Clock Enable (CKE) Truth Table CKE Current State Self Refresh Power Down All Banks Idle Any State other than listed above Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID 1 L H H X X X X X Power Down mode exit, all banks idle 2 L H L X X X X X ILLEGAL 2 L L X X X X X X Maintain Power Down Mode H H H X X X H H L H X X H H L L H X H H L L L H H H L L L L H L H X X X H L L H X X H L L L H X H L L L L H H L L L L L L X X X X X A12,A13 A11 - A0 3 Refer to the Idle State section of the Current State Truth Table 3 3 X X OP Code CBR Refresh Mode Register Set 4 3 Refer to the Idle State section of the Current State Truth Table 3 3 X X OP Code X Entry Self Refresh 4 Mode Register Set X Power Down 4 H H X X X X X X Refer to operations in the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend 5 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high (see page 28). 3. The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 32 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Current State Truth Table Current State Idle Row Active Read (Part 1 of 4)(See note 1) Command A11 - A0 CS RAS CAS WE A12,A13 OP Code Action Description L L L L L L L H X L L L L H H L H BS BS L H L L BS Column Write w/o Precharge ILLEGAL 4 L H L H BS Column Read w/o Precharge ILLEGAL 4 L L H H H H L H X X X X Burst Termination No Operation No Operation No Operation H X X X X X Device Deselect No Operation or Power Down L L L L L L L H OP Code X X X Mode Register Set Notes X Precharge Row Address Bank Activate X Set the Mode Register 2 Auto or Self Refresh Start Auto or Self Refresh 2, 3 No Operation Activate the specified bank and row 5 Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL L L H L BS L L H H BS Precharge Precharge L H L L BS Column Write Start Write; Determine if Auto Precharge 7, 8 L H L H BS Column Read Start Read; Determine if Auto Precharge 7, 8 L L H L L L H H X L L L H H X L L H L H X L H L X X X Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge L L H H BS L H L L BS Column Write Terminate Burst; Start the Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start a new Read cycle 8, 9 L L H H H X H H X L H X X X X X X X Burst Termination No Operation Device Deselect Terminate the Burst Continue the Burst Continue the Burst Row Address Bank Activate X X X OP Code X X BS X Row Address Bank Activate 6 ILLEGAL 4 ILLEGAL 4 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD ) is not satisfied. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 33 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Current State Truth Table Current State Write Read with Auto Precharge Write with Auto Precharge Precharging (Part 2 of 4)(See note 1) Command A11 - A0 CS RAS CAS WE A12,A13 L L L L OP Code L L L H X X L L H L BS X Action Description Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge Terminate Burst; Start the Precharge Row Address Bank Activate L L H H BS L H L L BS Column Write Terminate Burst; Start a new Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start the Read cycle 8, 9 L L H L L H H X L L H H X L L L H X L H X X X Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL L L H L BS Precharge ILLEGAL 4 L L H H BS ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L L H L L H H X L L H H X L L L H X L H X X X Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL L L H L BS L L H H BS L H L L BS Column L H L H BS Column L L H L L H H X L L H H X L L L H X L H X X X L L H L BS L L H H BS ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H L X X Burst Termination No Operation; Bank(s) idle after tRP L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X X Device Deselect No Operation; Bank(s) idle after tRP X X X OP Code X X X Row Address Bank Activate X X X OP Code X X X Precharge X 4 ILLEGAL 4 ILLEGAL 4 Write ILLEGAL 4 Read ILLEGAL 4 Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP Row Address Bank Activate X X X OP Code X X ILLEGAL Notes Precharge Row Address Bank Activate 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD ) is not satisfied. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 34 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Current State Truth Table Current State Row Activating Write Recovering Write Recovering with Auto Precharge (Part 3 of 4)(See note 1) Command A11 - A0 CS RAS CAS WE A12,A13 L L L L OP Code L L L H X X X Description Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge Action Notes L L H L BS ILLEGAL L L H H BS 4 ILLEGAL 4, 10 L H L L BS Column L H L H BS Column Write ILLEGAL 4 Read ILLEGAL Burst Termination No Operation; Row Active after tRCD 4 Row Address Bank Activate L H H L X X L H H H X X No Operation No Operation; Row Active after tRCD H X X X X X Device Deselect No Operation; Row Active after tRCD L L L L L L L H X OP Code X L L H L BS L L H H BS L H L L BS Column L H L H BS Column L H H L X L H H H H X X L L L L L L L L H L BS L L H H BS L H L L BS Column L H L H BS Column L H H L X L H H H X H X X ILLEGAL 4 ILLEGAL 4 Write Start Write; Determine if Auto Precharge 9 Read Start Read; Determine if Auto Precharge 9 X Burst Termination No Operation; Row Active after tDPL X X No Operation No Operation; Row Active after tDPL X X X Device Deselect No Operation; Row Active after tDPL L H OP Code X X X X X Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge Row Address Bank Activate X Mode Register Set ILLEGAL Auto or Self Refresh ILLEGAL Precharge ILLEGAL 4 ILLEGAL 4 Write ILLEGAL 4, 9 Read ILLEGAL 4, 9 X Burst Termination No Operation; Precharge after tDPL X No Operation No Operation; Precharge after tDPL Device Deselect No Operation; Precharge after tDPL Row Address Bank Activate X 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD ) is not satisfied. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 35 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Current State Truth Table Current State Refreshing Mode Register Accessing (Part 4 of 4)(See note 1) Command A11 - A0 CS RAS CAS WE A12,A13 L L L L OP Code L L L H X X L L H L BS X L L H H BS Row Address L H L L BS Column L H L H BS Column Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Notes ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC L H H L X X L H H H X X No Operation No Operation; Idle after tRC H X X X X X Device Deselect No Operation; Idle after tRC L L L L L L L L H L L L L H H H H X L L H H L L H H X L H L H L H L H X X BS BS BS BS X X X Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles OP Code X X Row Address Column Column X X X Burst Termination Action 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD ) is not satisfied. Absolute Maximum Ratings Symbol VDD VDDQ VIN VOUT TA TSTG PD IOUT Parameter Rating Units Notes Power Supply Voltage -0.3 to +4.6 V 1 Power Supply Voltage for Output -0.3 to +4.6 V 1 Input Voltage -0.3 to VDD +0.3 V 1 Output Voltage -0.3 to VDD +0.3 V 1 0 to +70 °C 1 -55 to +125 °C 1 Power Dissipation 1.0 W 1 Short Circuit Output Current 50 mA 1 Operating Temperature (ambient) Storage Temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 36 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Recommended DC Operating Conditions (TA = 0 to 70°C) Rating Symbol Parameter Units Notes 3.6 V 1 3.3 3.6 V 1 2.0 — VDD + 0.3 V 1, 2 -0.3 — 0.8 V 1, 3 Min. Typ. Max. Supply Voltage 3.0 3.3 Supply Voltage for Output 3.0 VIH Input High Voltage VIL Input Low Voltage VDD VDDQ 1. All voltages referenced to V SS and V SSQ. 2. VIH (max) = VDD/V DDQ + 1.2V for pulse width ≤ 5ns. 3. VIL (min) = VSS/VSSQ - 1.2V for pulse width ≤ 5ns. Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ±0.3V) Symbol CI CO Parameter Min. Typ Max. Units Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) 2.5 3.0 3.8 pF Input Capacitance (CLK) 2.5 2.8 3.5 pF Output Capacitance (DQ0 - DQ15) 4.0 4.5 6.5 pF 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 37 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C DC Electrical Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V) Symbol Parameter Min. Max. Units II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ V DD), All Other Pins Not Under Test = 0V -1 +1 µA IO(L) Output Leakage Current (D OUT is disabled, 0.0V ≤ V OUT ≤ V DDQ) -1 +1 µA VOH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) 2.4 — V VOL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) — 0.4 V DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 38 of 71 870Ω 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ±0.3V) Parameter Symbol Speed Test Condition -68 -75A -260 -360 Units Notes ICC1 1 bank operation tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 75 75 70 70 mA 1, 2 ICC2P CKE ≤ VIL(max), tCK = min, CS = VIH(min) 1 1 1 1 mA 7 ICC2PS CKE ≤ VIL(max), tCK = Infinity, CS = VIH(min) 1 1 1 1 mA 7 ICC2N CKE ≥ VIH (min), tCK = min, CS = VIH (min) 40 35 25 25 mA 4 ICC2NS CKE ≥ VIH (min), tCK = Infinity, 6 6 6 6 mA 6 ICC3N CKE ≥ VIH (min), tCK = min, CS = VIH (min) 45 40 30 30 mA 4 ICC3P CKE ≤ VIL(max), tCK = min, 3 3 3 3 mA 5, 7 Operating Current (Burst Mode) ICC4 tCK = min, Read/ Write command cycling, Multiple banks active, gapless data, BL = 4 135 120 90 90 mA 2, 3 Auto (CBR) Refresh Current ICC5 150 145 140 140 mA 7 ICC6 SP 1 1 1 1 mA Self Refresh Current LP 400 400 400 400 µA Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) tCK = min, tRC = tRC (min) CBR command cycling CKE ≤ 0.2V 7 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 2. The specified values are obtained with the output open. 3. Input signals are changed once during tCK (min). 4. Input signals are changed once during three clock cycles. 5. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 6. Input signals are stable. 7. SP: Standard power; LP: Low power. 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 39 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V) 1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT = 1.2ns. . AC Output Diagrams tT tCKL Clock tSETUP Vtt = 1.4V VIH 1.4V VIL tCKH 50Ω Output Zo = 50Ω 50pF AC Output Load Circuit (A) tHOLD 1.4V Input Output tAC Zo = 50Ω tOH 50pF tLZ AC Output Load Circuit (B) 1.4V Output Clock and Clock Enable Parameters Symbol Parameter -68 -75A -260 -360 Min. Max. Min. Max. Min. Max. Min. Max. Units Notes tCK3 Clock Cycle Time, CAS Latency = 3 6.67 1000 7.5 1000 10 1000 10 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 — — — — 10 1000 15 1000 ns tAC3 (A) Clock Access Time, CAS Latency = 3 — 6 — — — — — — ns 1 tAC2 (A) Clock Access Time, CAS Latency = 2 — — — — — — — — ns 1 tAC3 (B) Clock Access Time, CAS Latency = 3 — — — 5.4 — 6 — 6 ns 2 tAC2 (B) Clock Access Time, CAS Latency = 2 — — — — — 6 — 9 ns 2 tCKH Clock High Pulse Width 3 — 2.5 — 3 — 3 — ns tCKL Clock Low Pulse Width 3 — 2.5 — 3 — 3 — ns tCES Clock Enable Set-up Time 2 — 1.5 — 2 — 2 — ns tCEH Clock Enable Hold Time 1 — 0.8 — 1 — 1 — ns Power down mode Entry Time 0 6.67 0 7.5 0 10 0 10 ns Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 0.5 10 ns tSB tT 1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 40 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Common Parameters -68 Symbol -75A -260 -360 Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. Notes tCS Command Setup Time 2 — 1.5 — 2 — 2 — ns tCH Command Hold Time 1 — 0.8 — 1 — 1 — ns tAS Address and Bank Select Set-up Time 2 — 1.5 — 2 — 2 — ns tAH Address and Bank Select Hold Time 1 — 0.8 — 1 — 1 — ns RAS to CAS Delay 20 — 20 — 20 — 20 — ns 1 tRCD tRC Bank Cycle Time 66.7 — 67.5 — 70 — 70 — ns 1 tRAS Active Command Period 46.7 100K 45 100K 50 100K 50 100K ns 1 tRP Precharge Time 20 — 20 — 20 — 20 — ns 1 1 tRRD Bank to Bank Delay Time 13.3 — 15 — 20 — 20 — ns tCCD CAS to CAS Delay Time 1 — 1 — 1 — 1 — CLK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle -68 Symbol tRSC -75A -260 -360 Parameter Mode Register Set Cycle Time Min. Max. Min. Max. Min. Max. Min. Max. 2 — 2 — 2 — 2 — Units Notes CLK 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 41 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Read Cycle -68 Symbol tOH -75A -260 -360 Parameter Units Notes — ns 1 3 — ns 2, 4 Min. Max. Min. Max. Min. Max. Min. Max. 2.5 — — — 2.5 — 2.5 — — 2.7 — 3 — Data Out Hold Time tLZ Data Out to Low Impedance Time 0 — 0 — 0 — 0 — ns tHZ3 Data Out to High Impedance Time 3 6 3 5.4 3 6 3 6 ns 3 tHZ2 Data Out to High Impedance Time 3 6 — — 3 6 3 8 ns 3 tDQZ DQM Data Out Disable Latency 2 — 2 — 2 — 2 — CLK 1. 2. 3. 4. AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-75A). Refresh Cycle -68 Symbol tREF tSREX -75A -260 -360 Parameter Min. Max. Min. Max. Min. Max. Min. Max. Refresh Period — 64 — 64 — 64 — 64 Self Refresh Exit Time 10 10 10 Units Notes ms 1 10 ns 1. 4096 auto refresh cycles. Write Cycle -68 Symbol -75A -260 -360 Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. tDS Data In Set-up Time 2 — 1.5 — 2 — 2 — ns tDH Data In Hold Time 1 — 0.8 — 1 — 1 — ns tDPL Data input to Precharge 13.3 — 15 — 15 — 15 — ns tDAL3 Data In to Active Delay CAS Latency = 3 5 — 5 — 5 — 5 — CLK tDAL2 Data In to Active Delay CAS Latency = 2 — — — — 4 — 3 — CLK tDQW DQM Write Mask Latency 0 — 0 — 0 — 0 — CLK ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 42 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Clock Frequency and Latency Symbol Parameter -68 -75A -260 -360 Units fCK Clock Frequency 150 133 100 100 100 66 MHz tCK Clock Cycle Time 6.67 7.5 10 10 10 15 ns tAA CAS Latency 3 3 3 2 3 2 CLK tRP Precharge Time 3 3 2 2 2 2 CLK tRCD RAS to CAS Delay 3 3 2 2 2 2 CLK tRC Bank Cycle Time 10 9 7 7 7 6 CLK tRAS Minimum Bank Active Time 7 6 5 5 5 4 CLK tDPL Data In to Precharge 2 2 2 2 2 1 CLK tDAL Data In to Active/Refresh 5 5 5 4 5 3 CLK tRRD Bank to Bank Delay Time 2 2 2 2 2 2 CLK tCCD CAS to CAS Delay Time 1 1 1 1 1 1 CLK tWL Write Latency 0 0 0 0 0 0 CLK tDQW DQM Write Mask Latency 0 0 0 0 0 0 CLK tDQZ DQM Data Disable Latency 2 2 2 2 2 2 CLK tCSL Clock Suspend Latency 1 1 1 1 1 1 CLK 19L3265.E35856B 1/01 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 43 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Timing Diagrams Page AC Parameters for Write Timing ............................................................................................................... 45 AC Parameters for Read Timing (3/3/3), BL=4 ......................................................................................... 46 AC Parameters for Read Timing (2/2/2), BL=2 ......................................................................................... 47 AC Parameters for Read Timing (3/2/2), BL=2 ......................................................................................... 48 AC Parameters for Read Timing (3/3/3), BL=2 ......................................................................................... 49 Mode Register Set .................................................................................................................................... 50 Power on Sequence and Auto Refresh (CBR).......................................................................................... 51 Clock Suspension / DQM During Burst Read .......................................................................................... 52 Clock Suspension / DQM During Burst Write .......................................................................................... 53 Power Down Mode and Clock Suspend ................................................................................................... 54 Auto Refresh (CBR) .................................................................................................................................. 55 Self Refresh (Entry and Exit) .................................................................................................................... 56 Random Row Read (Interleaving Banks) with Precharge, BL=8 .............................................................. 57 Random Row Read (Interleaving Banks) with Auto-precharge, BL=8 ...................................................... 58 Random Row Write (Interleaving Banks) with Auto-Precharge, BL=8...................................................... 59 Random Row Write (Interleaving Banks) with Precharge, BL=8 .............................................................. 60 Read/Write Cycle ................................................................................................................................ 61 Interleaved Column Read Cycle ............................................................................................................... 62 Auto Precharge after a Read Burst, BL=4 ................................................................................................ 63 Auto Precharge after a Write Burst, BL=4 ................................................................................................ 64 Burst Read and Single Write Operation.................................................................................................... 65 Full Page Burst Read and Single Write Operation.................................................................................... 66 CS Function (Only CS signal needs to be asserted at minimum rate)...................................................... 67 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 44 of 71 19L3265.E35856B 1/01 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCKH CKE tCK2 tCKL tCS tCES tCEH tCH CS RAS AC Parameters for Write Timing \ 19L3265.E35856B 1/01 (Burst length = 4, CAS latency = 2) CAS WE * BS1 tAH RAx RBx RAy RAz RBy RAz RBy tAS A0-A9,A11 RAx CAx RBx CBx RAy CAy DQM tRCD tDAL‡ DQ tDPL‡ tDS tRC tDH tRP tRRD Hi-Z *BS0 = ”L” Bank2,3 = Idle Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank 0 Command Bank 1 Command Bank 0 Bank 1 Bx2 Bx3 Ay0 Activate Command Bank 0 Write Command Bank 0 Ay1 Ay2 Ay3 ‡ tDPL and tDAL depend on clock cycle time and speed sort. See the Clock Frequency and Latency Table. Precharge Command Bank 0 Activate Command Bank 0 Activate Command Bank 1 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 45 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T12 T11 T13 CLK tCK3 Begin Auto Precharge Bank 0 CKE Begin Auto Precharge Bank 1 CS RAS CAS WE * BS1 A10 RAx A0-A9,A11 RBx RAx CAx tRRD DQM RAy CBx RBx tRAS RAy tRP tRC tAC3 tOH tRCD 19L3265.E35856B 1/01 DQ Hi-Z * BS0 = ”L” Bank2,3 = Idle Ax0 Activate Command Bank 0 Read with Auto Precharge Command Bank 0 Activate Command Bank 1 Ax1 Ax2 Read with Auto Precharge Command Bank 1 Ax3 Bx0 Activate Command Bank 0 Bx1 Bx2 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 AC Parameters for Read Timing (3/3/3) \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 46 of 71 (Burst length = 4, CAS latency = 3; tRCD, tRP = 3) T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T12 T11 CLK tCK2 tCKH tCKL CKE Begin Auto Precharge Bank 0 tCS tCES tCH Begin Auto Precharge Bank 1 tCEH CS RAS CAS T13 AC Parameters for Read Timing (2/2/2) \ 19L3265.E35856B 1/01 (Burst length = 2, CAS latency = 2; tRCD, tRP = 2) WE * BS1 A10 RBx RAx RAy tAS A0-A9,A11 RAx RBx CAx tRRD tRAS (min) DQM Note: Must satisfy tRAS(min) For -260: extend tRCD1 clock DQ tRCD * BS0 = ”L” Bank2,3 = Idle tOH Ax0 Activate Command Bank 0 Read with Auto Precharge Command Bank 0 tRP tHZ tLZ Hi-Z RAy tRP tRC tAC2 CBx Activate Command Bank 1 Ax1 Read with Auto Precharge Command Bank 1 tHZ Bx0 Bx1 Activate Command Bank 0 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 47 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. tAH T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T12 T11 CLK tCK3 tCKH tCKL CKE tCS tCES Begin Auto Precharge Bank 0 tCH Begin Auto Precharge Bank 1 tCEH CS RAS CAS WE * BS1 tAH A10 RAx RBx RAy tAS A0-A9,A11 RAx CAx RBx CBx RAy tRRD tRAS DQM Note: Must satisfy tRAS(min). Extended tRCD 1 clock. Not required for BL ≥ 4. 19L3265.E35856B 1/01 DQ tAC3 tRCD Bank2,3=Idle tOH tHZ tLZ Hi-Z * BS0=” L” tRP tRC Ax0 Activate Command Bank 0 Read with Activate Auto Precharge Command Command Bank 1 Bank 0 Ax1 Read with Auto Precharge Command Bank 1 tRP tHZ Bx0 Bx1 Activate Command Bank 0 T13 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 AC Parameters for Read Timing (3/2/2) \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 48 of 71 (Burst length = 2, CAS latency = 3; tRCD, tRP = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T11 T13 T14 CLK tCK3 Begin Auto Precharge Bank 0 CKE Begin Auto Precharge Bank 1 tCEH CS RAS CAS AC Parameters for Read Timing (3/3/3) \ 19L3265.E35856B 1/01 (Burst length = 2, CAS latency = 3; tRCD, tRP = 3) WE * BS1 RAx A0-A9, A11 RAx RBx CAx RAy RBx CBx RAy tRRD tRAS (mIn) DQM tRP tRC tAC3 tOH tRP tRCD DQ Hi-Z Ax0 Bank 2,3=Idle *BS0=” L” Activate Command Bank 0 Note: Must satisfy Read with tRAS(min). Auto Precharge Extended tRCD not required Command for BL≥4. Bank 0 Activate Command Bank 1 Bx0 Ax1 Read with Auto Precharge Command Bank 1 Activate Command Bank 0 Bx1 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 49 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Mode Register Set T22 T21 T20 T19 Mode Register Set Command tRP ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 50 of 71 DQ DQM A0-A9, A11 A10 BS0,BS1 WE CAS RAS CS CKE CLK Hi-Z T0 T1 tCK2 Precharge Command All Banks T2 T3 T4 Address Key tRSC T5 T6 Any Command T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 (CAS latency = 2) \ 19L3265.E35856B 1/01 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CLK tCK High level is required CKE 2 Clock min. Minimum of 8 Refresh Cycles are required CS RAS CAS WE BS T20 T21 T22 Power-On Sequence and Auto Refresh (CBR) \ 19L3265.E35856B 1/01 T0 Address Key A0-A9, A11 DQM DQ tRP Hi-Z Precharge 1st Auto Refresh Command Command All Banks Inputs must be stable for 200µ s tRC 8th Auto Refresh Command Mode Register Set Command Any Command IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 51 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCES tCK3 tCEH CKE CS RAS CAS WE * BS1 A10 RAx A0-A9, A11 RAx CAx DQM tHZ DQ Hi-Z 19L3265.E35856B 1/01 * BS0=” L” Bank2,3=Idle Ax0 Activate Command Bank 0 Read Command Bank 0 Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Ax4 Ax6 Ax7 T22 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Clock Suspension / DQM During Burst Read \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 52 of 71 (Burst length = 8, CAS latency = 3; tRCD = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 CLK tCK3 CKE CS RAS CAS WE * BS1 T21 T22 RAx A0-A9, A11 RAx CAx DQM DQ T20 Hi-Z * BS0=” L” Bank2,3=Idle DAx0 Activate Command Bank 0 DAx1 Clock Suspend 1 Cycle Write Command Bank 0 DAx3 DAx2 Clock Suspend 2 Cycles Clock Suspend 3 Cycles DAx5 DAx6 DAx7 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 53 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T19 Clock Suspension / DQM During Burst Write \ 19L3265.E35856B 1/01 (Burst length = 8, CAS latency = 3; tRCD = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCES tCK2 tCES tCES tSB CKE VALID CS RAS CAS WE * BS1 A10 RAx A0 -A9, A11 RAx CAx DQM DQ 19L3265.E35856B 1/01 * BS0=” L” Bank2,3=Idle tHZ tSB Hi-Z Ax0 Activate Command Bank 0 Ax1 Clock Suspension Start ACTIVE STANDBY NOP Read Command Bank 0 Ax2 Clock Suspension End Ax3 Precharge Command Bank 0 PRECHARGE STANDBY NOP Any Command IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Power Down Mode and Clock Suspend \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 54 of 71 (Burst length = 4, CAS latency = 2) IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Auto Refresh (CBR) T22 T21 T20 T19 19L3265.E35856B 1/01 Precharge Command All Banks DQ DQM A0-A9, A11 A10 BS WE CAS RAS CS CKE CLK Hi-Z T0 T1 tCK2 tRP T2 T3 Auto Refresh Command T4 T5 T6 tRC T7 T8 T9 T10 Auto Refresh Command T11 T12 T13 tRC T14 T15 T16 T17 T18 (CAS latency = 2) \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 55 of 71 T1 T2 T3 T4 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 Tm+10 Tm+11 Tm+12 Tm+13 Tm+14 Tm+15 tCES tCES CKE CS RAS CAS WE BS A10 A0-A9, A11 DQM DQ Hi-Z tSB 19L3265.E35856B 1/01 All Banks must be idle Self Refresh Entry Power Down Entry tSREX Self Refresh Exit Power Down Exit tRC Any Command IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 CLK Self Refresh (Entry and Exit) \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 56 of 71 (Note: The CLK signal must be reestablished prior to CKE returning high.) T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCK3 CKE High CS RAS CAS WE A10 RBx A0-A9, A11 RBx CBx RBy RAx CAx CBy RBy tAC3 tRCD DQM DQ RAx Hi-Z Bx0 Activate Command Bank 1 * BS0=” L” Bank2,3=Idle Read Command Bank 1 Bx1 Activate Command Bank 0 Bx2 Bx3 Bx4 Read Command Bank 0 Bx5 Bx6 Precharge Command Bank 1 Ax0 Ax1 Ax4 Activate Command Bank 1 Ax5 Read Command Bank 1 Ax6 Ax7 By0 Precharge Command Bank 0 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 57 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. * BS1 T22 Random Row Read (Interleaving Banks) with Precharge \ 19L3265.E35856B 1/01 (Burst length = 8, CAS latency = 3; tRCD, tRP = 3) T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High Start Auto Precharge Bank 1 Start Auto Precharge Bank 0 CS RAS CAS WE * BS1 A10 A0-A9,A11 tRCD RBy RAx RAx CBx RBx DQM DQ RAx RAx RBx CAx CBy RBy tAC3 Hi-Z Bx0 19L3265.E35856B 1/01 Activate Command Bank 1 * BS0=” L” Bank2,3=Idle Read with Auto Precharge Command Bank 1 Bx1 Bx2 Activate Command Bank 0 Bx3 Bx4 Bx5 Bx6 Read with Auto Precharge Command Bank 0 Bx7 Ax0 Ax4 Ax1 Activate Command Bank 1 Ax5 Ax6 Read with Auto Precharge Command Bank 1 Ax7 By0 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Random Row Read (Interleaving Banks) with Auto-Precharge \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 58 of 71 (Burst length = 8,CAS latency = 3; tRCD, tRP = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T11 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS RAS CAS WE * BS1 RAx A0-A9,A11 RAx CAX RAy RBx RAy CBx CAy tDAL‡ tRCD DQM DQ RBx tDAL‡ Hi-Z DAx0 Activate Command Bank 0 * BS0=” L” Bank2,3=Idle DAx1 Write with Auto Precharge Command Bank 0 DAx4 DAx5 DAx6 Activate Command Bank 1 DAx7 DBx0 DBx1 Write with Auto Precharge Command Bank 1 ‡ DBx2 DBx3 DBx4 DBx5 DBx6 Activate Command Bank 0 DBx7 DAy0 Write with Auto Precharge Command Bank 0 Number of clocks depends on clock cycle time and speed sort. See the Clock Frequency and Latency table. Bank may be reactivated at the completion of tDAL. DAy1 DAy2 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 59 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 Random Row Write (Interleaving Banks) with Auto-Precharge \ 19L3265.E35856B 1/01 (Burst length = 8, CAS latency = 3; tRCD, tRP = 3) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS RAS CAS WE * BS1 A10 RAx A0-A9, A11 RAx CAX RAy RBx RAy CBx tRCD DQM 19L3265.E35856B 1/01 DQ RBx CAy tDPL tRP Hi-Z Activate Command * BS0=” L” Bank 0 Bank2,3=Idle DAx0 DAx1 Write Command Bank 0 DAx4 DAx5 DAx6 Activate Command Bank 1 DAx7 DBx0 DBx1 Write Command Bank 1 DBx2 DBx3 Precharge Command Bank 0 DBx4 DBx5 Activate Command Bank 0 DBx6 DBx7 DAy0 DAy1 DAy2 Write Command Bank 0 Precharge Command Bank 1 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Random Row Write (Interleaving Banks) with Precharge \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 60 of 71 (Burst length = 8,CAS latency = 3; tRCD, tRP = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 CLK tCK3 CKE T19 T20 T21 T22 Read / Write Cycle \ 19L3265.E35856B 1/01 (Burst length = 8, CAS latency = 3; tRCD, tRP = 3) CS RAS CAS WE * BS1 RAx A0-A9, A11 RAx CAx CAy DQM DQ Hi-Z * BS0=” L” Bank2,3=Idle Ax0 Activate Command Bank0 Read Command Bank 0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 The Read Data Write The Write Data is Masked with a Command is Masked with a Two Clock Bank 0 Zero Clock Latency Latency DAy4 Precharge Command Bank 0 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 61 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T17 T16 T18 T19 T20 CLK tCK3 CKE Start Auto Precharge Bank 0 CS RAS CAS WE * BS1 A10 RAx A0-A9, A11 RAx CAx RBx tRCD DQM DQ RBx 19L3265.E35856B 1/01 Bank2,3=Idle Ax0 Activate Command Bank 0 CBy CBz CAy tAC3 Hi-Z * BS0=” L” CBx Read Command Bank 0 Activate Command Bank 1 Ax1 Read Command Bank 1 Ax2 Ax3 Read Command Bank 1 Bx0 Bx1 By0 By1 Bz0 Bz1 Read with Read Precharge Command Auto Precharge Command Command Bank 1 Bank 1 Bank 0 Ay0 Ay1 Ay2 Ay3 T21 T22 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Interleaved Column Read Cycle \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 62 of 71 (Burst length = 4, CAS latency = 3; tRCD, tRP = 3) T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T12 T11 T13 T14 T15 T17 T16 T18 T19 T20 T21 CLK tCK3 CKE High CS RAS T22 Auto Precharge after Read Burst \ 19L3265.E35856B 1/01 (Burst length = 4, CAS latency = 3; tRCD, tRP = 3) CAS WE * BS1 RAx A0-A9, A11 RAx RBx CAx RBy RBx CBx CAy Start Auto Precharge Bank 1 DQM DQ RBy CBy Start Auto Precharge Bank 0 Start Auto Precharge Bank 1 Hi-Z Activate Command * BS0=” L” Bank 0 Bank2,3=Idle Ax0 Activate Command Bank 1 Read Command Bank 0 Ax1 Ax2 Read with Auto Precharge Command Bank 1 Ax3 Bx0 Bx1 Bx2 Read with Auto Precharge Command Bank 0 Bx3 Ay0 Activate Command Bank 1 Ay1 Ay2 Ay3 Read with Auto Precharge Command Bank 1 By0 By1 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 63 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS RAS CAS WE * BS1 A10 RBx RAx A0-A9, A11 RAx CAx RBy CBx RBx CAy RBy CBy tDAL‡ DQM DQ RAz CAz RAz tDAL‡ tDAL‡ Hi-Z DAx0 19L3265.E35856B 1/01 Activate Command Bank 0 * BS0=” L” Bank2,3=Idle DAx1 Write Command Bank 0 DAx2 DAx3 DBx0 DBx1 Write with Activate Command Auto Precharge Command Bank 1 Bank 1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 Write with Write with Write with Activate Activate Auto Precharge Command Auto Precharge Command Auto Precharge Command Command Command Bank 1 Bank 0 Bank 0 Bank 1 Bank 0 ‡ Number of clocks depends on clock cycle and speed sort. See the Clock Frequency and Latency table. Bank may be reactivated at the completion of tDAL. DAz2 DAz3 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Auto Precharge after Write Burst \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 64 of 71 (Burst length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS RAS CAS WE Burst Read and Single Write Operation \ 19L3265.E35856B 1/01 (Burst length = 4, CAS latency = 2) * BS1 RAv A0-A9,A11 RAv CAv CAw CAx CAy CAz LDQM UDQM DQ0 - DQ7 DQ8 - DQ15 Hi-Z Hi-Z * BS0=” L” Bank2,3=Idle Activate Command Bank 0 Read Command Bank 0 Av0 Av1 Av2 Av3 DAw0 Av0 Av1 Av2 Av3 DAw0 Single Write Command Bank 0 Ay0 DAx0 Single Write Command Bank 0 Ay1 Ay0 Lower Byte Read is masked Command Upper Byte Bank 0 is masked Ay2 Ay3 DAz0 Ay3 DAz0 Single Write Command Bank 0 Lower Byte is masked IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 65 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS RAS CAS WE * BS1 A10 RAv A0-A9, A11 RAv CAv CAw CAx CAy LDQM UDQM DQ0-DQ7 19L3265.E35856B 1/01 DQ8-DQ15 Hi-Z Av0 Av1 Av2 Av3 DAw0 DAx0 Ay0 Ay1 Ay2 Ay3 Av0 Av1 Av2 Av3 DAw0 DAx0 Ay0 Ay1 Ay2 Ay3 Hi-Z *BS0=” L” Bank2,3=Idle Activate Command Bank 0 Read Command Bank 0 Burst Stop Command Single Write Command Bank 0 Single Write Command Bank 0 Read Command Bank 0 Burst Stop Command IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C T0 Full Page Burst Read and Single Write Operation \ ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 66 of 71 (Burst length = Full page, CAS latency = t3; RCD, tRP = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 CLK tCK3 CKE CS RAS CAS WE A10 RAx A0 - A9 RAx DQM CAx CAy Low tDPL tRCD DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 DAy0 DAy1 Write Command Bank A DAy2 DAy3 Precharge Command Bank A T20 T21 T22 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Page 67 of 71 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A11(BS) T19 CS Function (Only CS signal needs to be asserted at minimum rate) \ 19L3265.E35856B 1/01 (at 100MHz Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3) IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Package Dimensions (400mil; 54 lead; Thin Small Outline Package) 22.22 ± 0.13 Detail A 10.16 ± 0.13 11.76 ± 0.20 Lead #1 Seating Plane 0.10 0.80 Basic 0.35 + 0.10 - 0.05 0.805REF 1.20 Max Detail A Gage Plane 0.25 Basic 0.5 ± 0.1 0.05 Min ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 68 of 71 19L3265.E35856B 1/01 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Revision Log Revision 11/21/97 4/17/98 Contents of Modification Initial release. page 1 Change PN designations: -322 -> -360, -222 -> -260. Also, page 19-page 23, page 25, page 39page 42. page 1 Add 2 high stack (x4). Also, page 9, page 27, page 31, page 37-page 39. page 28 Clarify Power Down Mode. page 39 Add low power current specification. Also, page 1. Modify sorts/timing information: 1) separate -80 sort added and/or page 40-page 2) 322 (360) and 222 (260) sorts modified (tCK3, tSB, tRAS, tRRD , tRSC, tDPL3 (tCK3 changed from 8ns to 42 10ns); tHZ ). Also, page 1, page 4, page 10, page 39. page 1 Add -68; changed CL = 3 timings (-260, -360) and CL = 2 timings (-260) to encompass JEDEC 125 MHz requirements. Also, page 40-page 42. page 22 Add note for -68 tDPL (2 clocks) / update wording. Also, page 26, page 60. page 39 Update currents based on timing changes. page 43 Add -68; update -260, -360 (125MHz), remove -10 CL = 1. page 46 Correct CKE. Also, page 50, page 52. page 49 Add note: tRAS(min). 5/14/98 page 37 Include minimum capacitance specification, update maximum for CLK. 5/29/98 page 19 Clarify Read with auto-precharge description. page 1 Change -260, -360 timings. 5/1/98 Remove x4, -68. Add x8, x16, -260, LP. Change clock cycle for -260, -360. pages 22 to 23, and 59 and 64 Update of notes, description, regarding Auto Precharge. Change in implementation of auto-precharge for Write with Auto-Precharge command and for interruption of Auto Precharge. page 23 Clarify wording for timing of precharge (Read). pages 24, 26, t DPL or t DAL updated. 42, 43, and 45 12/14/98 2/3/99 19L3265.E35856B 1/01 page 28 Correct Power Down Mode Exit requirements (NOP required on clock following CKE transition). Remove note (buffer enable) in diagram. page 31 Change WE in Self Refresh Exit Command from “X” to “H” (NOP). Also, in Power Down Mode Entry/Exit. Note edited: NOP or Device Deselect required. page 32 Correct note regarding CKE low to high transition. page 39 Update currents to reflect -260, -360 timing changes (scale for tCK(min)). Drop LP requirements for ICC3P, ICC2P, ICC2PS, ICC5. page 40 Correct tCKH , tCKL in diagram. Remove note 4 (tCKH, tCKL measurement). Update -260, -360 timings. Also page 41-page 43. Revise method of specifying tRSC (clk versus ns). page 42 Clarify tOH / load conditions across speed sorts. page 48 Correct Read (322) timing: Auto-precharge start, extend tRCD . page 49 Clarify note about tRAS(min). page 58 Correct timing (last activate/read commands). page 1 Change timings, delete -68, add -75A. page 4 Remove -68, add -75A, change clock cycle for -260, -360. page 37 Update Capacitance Table (max values), add typical values. page 39 Update currents to reflect -260, -360 timing changes, added sort. page 40 Update sorts, timings. Also, page 41 - page 43. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 69 of 71 IBMN364164 IBMN364804 IBMN364404 64Mb Synchronous DRAM - Die Revision C Revision Log Revision Contents of Modification 3/21/99 page 41 Change tRP, tRCD for -75A (22.5 to 20ns) 4/22/99 page 39 Update ICC2NS (5 to 6mA) 5/14/99 page 50 Corrected addessing in timing diagram - Mode Register Set. 7/2/99 page 1,page 4, page 38-47 Add x16, -68 10/20/99 01/00 Removed Preliminary. page 4 Updated Ordering information. 8/9/00 Updated entire docuement removing all stacked information and -10 speed sort. 1/30/01 Updated ordering information to add -75A and -260 speed sorts to x16 parts. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 70 of 71 19L3265.E35856B 1/01 â Copyright and Disclaimer ã Copyright International Business Machines Corporation 1997- 2001 All Rights Reserved Printed in the United States of America January 2001 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com 19L3265.E35856B 1/01