INFINEON HYB39S16400BT-10

HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
16 MBit Synchronous DRAM
Advanced Information
•
High Performance:
-8
-10
Units
fCK(max.)
125
100
MHz
tCK3
8
10
ns
tAC3
6
7
ns
tCK2
10
13.3
ns
tAC2
6
8
ns
•
Fully Synchronous to Positive Clock Edge
•
0 to 70 °C operating temperature
•
Dual Banks controlled by A11 ( Bank Select)
•
Programmable CAS Latency : 2, 3
•
Programmable Wrap Sequence : Sequential
or Interleave
•
Programmable Burst Length: 1, 2, 4, 8
•
full page(optional) for sequencial wrap
around
•
Multiple Burst Read with Single Write
Operation
•
Automatic
Command
•
Data Mask for Read / Write control (x4, x8)
•
Dual Data Mask for byte control ( x16)
•
Auto Refresh (CBR) and Self Refresh
•
Suspend Mode and Power Down Mode
•
4096 refresh cycles / 64 ms
•
Random Column Address every CLK
( 1-N Rule)
•
Single 3.3V +/- 0.3V Power Supply
•
LVTTL Interface
•
Plastic Packages:
P-TSOPI-44 400mil width ( x4, x8 )
P-TSOPII -50 400 mil width ( x 16 )
•
-8 version for PC100 applications
and
Controlled
Precharge
The HYB39S16400/800/160BT are dual bank Synchronous DRAM’s based on the die revisions “D“,
& “E” and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS’advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
4.98
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Ordering Information
Type
Ordering Code
Package
Description
HYB 39S16400BT-8
P-TSOPII-44 (400mil)
125MHz 2B x 2M x 4 SDRAM
HYB 39S16400BT-10
P-TSOPII-44-(400mil)
100MHz 2B x 2M x 4 SDRAM
HYB 39S16800BT-8
P-TSOPII-44-(400mil)
125MHz 2B x 1M x 8 SDRAM
HYB 39S16800BT-10
P-TSOPII-44 (400mil)
100MHz 2B x 1M x 8 SDRAM
HYB 39S16160BT-8
P-TSOPII-50 (400mil)
125MHz 2B x 512k x 16 SDRAM
HYB 39S16160BT-10
P-TSOPII-50-(400mil)
100MHz 2B x 512k x 16 SDRAM
LVTTL-version:
Pin Description and Pinouts:
CLK
Clock Input
DQ
Data Input /Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS
Chip Select
Vdd
Power (+3.3V)
RAS
Row Address Strobe
Vss
Ground
CAS
Column Address Strobe
Vddq
Power for DQ’s (+ 3.3V)
WE
Write Enable
Vssq
Ground for DQ’s
A0-A10
Address Inputs
NC
not connected
A11 (BS)
Bank Select
Semiconductor Group
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Vdd
NC
Vssq
DQ0
Vddq
NC
Vssq
DQ1
Vddq
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vdd
DQ0
Vssq
DQ1
Vddq
DQ2
Vssq
DQ3
Vddq
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
Vss
NC
Vssq
DQ3
Vddq
NC
Vssq
DQ2
Vddq
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
HYB39S16400BT
2 Bank x 2MBit x 4
TSOPII-44
( 400 mil x 725 mil)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vss
DQ7
Vssq
DQ6
Vddq
DQ5
Vssq
DQ4
Vddq
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
HYB39S16800BT
2 Bank x 1MBit x 8
TSOPII-44
( 400 mil x 725 mil )
Vdd
DQ0
DQ1
Vssq
DQ2
DQ3
Vddq
DQ4
DQ5
Vssq
DQ6
DQ7
Vddq
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
Vssq
DQ13
DQ12
Vddq
DQ11
DQ10
Vssq
DQ9
DQ8
Vddq
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
HYB39S16160BT
2 Bank x 512kbit x 16
TSOPII-50
( 400 mil x 825 mil )
Semiconductor Group
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Signal Pin Description
Pin
Type
Signal Polarity
Function
CLK
Input
Pulse
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby inititiates either the Power Down mode, Suspend mode or the
Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
RAS,
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
Positive The system clock input. All of the SDRAM inputs are sampled on the rising
Edge edge of the clock.
During a Bank Activate command cycle, A0-A10 defines the row address
(RA0-RA10) when sampled at the rising clock edge.
A0 A10
Input
Level
—
During a Read or Write command cycle, A0-A9 defines the column
address (CA0-CAn) when sampled at the rising clock edge.CAn depends
from the SDRAM organisation.
4M x 4 SDRAM CAn = CA9
2M x 8 SDRAM CAn = CA8
1M x 16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If A10 is high,
autoprecharge is selected and A11 defines the bank to be precharged
(low=bank A, high=bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with A11
to control which bank(s) to precharge. If A10 is high, both bank A and bank
B will be precharged regardless of the state of A11. If A10 is low, then A11
is used to define which bank to precharge.
A11
(BS)
Input
Level
—
Selects which bank is to be active. A11 low selects bank A and A11 high
selects bank B.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write
mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the write operation if
DQM is high.
DQM
LDQM
UDQM
Input
VDD,
VSS
Supply
VDDQ
VSSQ
Supply
Pulse
Power and ground for the input buffers and the core logic.
—
Semiconductor Group
—
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
4
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Row Decoder
CKE
CKE Buffer
2048
2048 x 1024
Memory Bank A
Self
Refresh Clock
1024
Row
Address
Counter
CLK
Sense Amplifiers
Bank A
Row/Column
Select
CLK Buffer
Column Decoder and DQ Gate
4
8
3
WE
WE Buffer
DQM
Sequential
Control
Bank B
Data Latches
Predecode B
8
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Sense Amplifiers
1024
CAS Buffer
Command Decoder
RAS Buffer
Mode Register
11
CS Buffer
CAS
Data Latches
8
12
11
RAS
Sequential
Control
Bank A
2048
DQM Buffer
2048
Memory Bank B
2048 x 1024
Block Diagram for HYB39S16400BT (2 banks x 4M x 4 SDRAM)
Semiconductor Group
5
Data Input/Output Buffers
3
12
Row Decoder
CS
Address Buffers (12)
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
8
Predecode A
DQ0
DQ1
DQ2
DQ3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Row Decoder
Row Decoder
CKE
CKE Buffer
2048 x 512
Memory Bank A
2048
Self
Refresh Clock
8
Sense Amplifiers
Sense Amplifiers
Bank A
Row/Column
Select
CLK Buffer
Column Decoder and DQ Gate
Column Decoder and DQ Gate
8
CS
Address Buffers (12)
11 Predecode A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Sequential
Control
Bank A
3
12
8
8
12
Mode Register
11
8
CS Buffer
3
Sequential
Control
Bank B
8
Data Latches
WE Buffer
DQM
8
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Sense Amplifiers
8
DQM Buffer
512
WE
8
Row Decoder
Row Decoder
CAS Buffer
Command Decoder
RAS Buffer
CAS
8
Data Latches
Data Latches
11 Predecode B
RAS
8
8
2048
Memory Bank B
Memory
2048Bank
x 512B
2048 x 1024
Block Diagram for HYB39S16800BT (2 banks x 1M x 8 SDRAM)
Semiconductor Group
6
Data Input/Output Buffers
CLK
512
1024
Row
Address
Counter
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Row Decoder
Row Decoder
Row Decoder
Row Decoder
CKE Buffer
2048
Sense Amplifiers
Sense Amplifiers
Sense Amplifiers
Column Decoder
Sense
and
Amplifiers
DQ Gate
Column Decoder and DQ Gate
Column Decoder and DQ Gate
Column Decoder and DQ Gate
16
Bank A
Row/Column
Select
CLK Buffer
8
16
CS
Address Buffers (12)
3
12
Sequential
Control
Bank A
8
8
8
Data Latches
Data Latches
Data Latches
Data Latches
11 Predecode A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
256
CLK
1024
Row
Address
Counter
16
512
1024
Self
Refresh Clock
16
8
11 Mode Register
12
8
CS Buffer
3
Sequential
Control
Bank B
16
Data Latches
Data Latches
CAS
CAS Buffer
WE
WE Buffer
UDQM
DQM Buffer
LDQM
DQM Buffer
16
Bank B
Row/Column
Select
Column Decoder and DQ Gate
Column Decoder and DQ Gate
Sense Amplifiers
Sense Amplifiers
16
256
RAS Buffer
8
Row Decoder
Row Decoder
Row Decoder
Row Decoder
RAS
Command Decoder
11 Predecode B
2048
Memory Bank B
Memory
Bank
B
2048
x 256
Memory
Bank
B
2048
x 1024
Memory
Bank
B
2048 x 512
2048 x 1024
Block Diagram for HYB39S16160BT (2 banks x 512k x 16 SDRAM)
Semiconductor Group
7
Data Input/Output Buffers
CKE
2048 x 512
Memory Bank A
2048 x 256
Memory Bank A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Operation
CS
RAS
CAS
WE
(L/U)DQM
Standby, Ignore RAS, CAS, WE and Address
H
X
X
X
X
Row Address Strobe and Activating a Bank
L
L
H
H
X
Column Address Strobe and Read Command
L
H
L
H
X
Column Address Strobe and Write Command
L
H
L
L
X
Precharge Command
L
L
H
L
X
Burst Stop Command
L
H
H
L
X
Self Refresh Entry
L
L
L
H
X
Mode Register Set Command
L
L
L
L
X
Write Enable/Output Enable
X
X
X
X
L
Write Inhibit/Output Disable
X
X
X
X
H
No Operation (NOP)
L
H
H
H
X
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be
programmed in the SDRAM mode register. The mode set operation must be done before any
activate command after the initial power up. Any content of the mode register can be altered by reexecuting the mode set command. Both banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the following table.
Semiconductor Group
8
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Address Input for Mode Set (Mode Register Operation)
BS A10 A9
A8
A7
A6
Operation Mode
A5
A4
A3
A2
CAS Latency
BT
Burst Length
Operation Mode
A1
A0
Address Bus (Ax)
Mode Register (Mx)
Burst Type
M11 M10 M9 M8 M7
Mode
M3
Type
0
0
0
0
0
Normal
0
Sequential
Interleave
X
1
0
0
Multiple Burst
with Single
Write
1
X
Burst Length
CAS Latency
M6
M5
M4
Latency
0
0
0
Reserve
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserve
1
0
1
Reserve
1
1
0
Reserve
1
1
1
Reserve
M2
M1
M0
0
0
0
0
Length
Sequential
Interleave
0
1
1
0
1
2
2
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Full Page*)
Sequential Burst Addressing
Interleave Burst Addressing
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
Semiconductor Group
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
9
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Reserve
*) optional
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define
either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full
page is an optional feature in this device. Column addresses are segmented by the burst length and
serial data accesses are done within this boundary. The first column address to be accessed is
supplied at the CAS timing and the subsequent addresses are generated automatically by the
programmed burst length and its sequence. For example, in a burst length of 8 with interleave
sequence, if the first address is 2’
‘ , then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5 .
Full page burst operation is only possible using the sequential burst type and page length is
a function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycles is
supported. When the previous burst is interrupted, the remaining addresses are overridden by the
new address with the full burst length. An interrupt which accompanies with an operation change
from a read to a write is possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two
banks can realize fast serial data access modes among many different pages. Once two banks are
activated, column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS before RAS (CBR) automatic refresh and a self refresh.
All of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the self refresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals
including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh
exit operation. After the exit command, at least one tRC delay is required prior to any access
command.
Semiconductor Group
10
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high
at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency t DQZ). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t DQW = zero
clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes
the internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t CSL ).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE
low enters the power down mode and all of receiver circuits are gated. All banks must be
precharged before entering this mode. One clock delay is required for mode entry and exit. The
Power Down mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. The SDRAM automatically enters the precharge operation one clock after the
Read Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3.
If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is
initiated. The SDRAM automatically enters the precharge operation one clock delay form the last
data-in for CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced
as tDPL .
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require
a time tDPL from the last burst data to apply the precharge command.
Bank Selection by Address Bits
A10
Semiconductor Group
A11
Bank A Only
Low
Low
Bank B Only
Low
High
Both A and B
High
Don’t Care
11
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Power Up Procedure
All Vdd and Vddq must reach the specified voltage no later than any of input signal voltages. An
initial pause of 200 µsec is required after power on. All banks have to be precharged and a minimum
of 2 auto-refresh cycles are required prior to the mode register set operation.
Semiconductor Group
12
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range...................................................................................... – 55 to + 150 °C
Input/output voltage .............................................................................. – 0.5 to min(Vcc+0.5, 4.6) V
Power supply voltage VDD / VDDQ.......................................................................... – 1.0 to + 4.6 V
Power Dissipation............................................. ................................................................ ..........1 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings ” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operation and Characteristics for LV-TTL versions:
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
Input high voltage
VIH
2.0
Vcc+0.3
V
1, 2, 3
Input low voltage
VIL
– 0.3
0.8
V
1, 2, 3
Output high voltage ( IOUT = – 2.0 mA)
VOH
2.4
–
V
3
Output low voltage ( IOUT = 2.0 mA)
VOL
–
0.4
V
3
Input leakage current, any input
(0 V < VIN < Vddq, all other inputs = 0 V)
II(L)
– 10
10
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
– 10
10
µA
Notes:
1. All voltages are referenced to VSS.
2. Vih may overshoot to Vcc + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to
-2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak
to DC reference.
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Values
Unit
min.
max.
Input capacitance (CLK)
CI1
2.5
4.0
pF
Input capacitance
CI2
2.5
5.0
pF
CIO
4.0
6.5
pF
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
Input / Output capacitance (DQ)
Semiconductor Group
13
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, VCC = 3.3V ± 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test Condition
CAS
Latency
max. max.
mA
mA
mA
CKE<=VIL(max),
tck>=tck(min.)
3
3
mA
Icc2PS CKE<=VIL(max),
2
2
mA
20
20
mA CS=
Precharge
Standby Current
in Power Down
Mode
Icc2P
Active Standby
Current in Power
Down Mode
Note
65
90
100
Icc1
Precharge
Standby Current
in Non-power
down Mode
-10
80
115
125
Operating Current
Burst Length = 4
trc>=trc (min.)
tck>=tck(min.), Io = 0mA
2 bank interleave operation
1
2
3
-8
1, 2
tCK=infinite
Icc2N
CKE>=VIH(min),
tck>=tck(min.) input signals
changed once in 3 cycles
High
Icc2NS CKE>=VIH(min),
10
10
mA
CKE<=VIL(max),
tck>=tck(min.)
3
3
mA
Icc3PS CKE<=VIL(max),
2
2
mA
25
25
mA CS=
tCK=infinite, input signals
are stable
Icc3P
tCK=infinite, inpit signals
are stable
Active Standby
Current in Nonpower Down
Mode
Icc3N
CKE>=VIH(min),
tck>=tck(min.),
changed once in 3 cycles
High,
1
Icc3NS CKE>=VIH(min),
15
15
mA
tCK=infinite, input signals
are stable
Burst Operating
Current
Icc4
Burst Length = full page
trc = infinite
tck >= tck (min.), IO = 0 mA
2 banks activated
1
2
3
50
80
120
40
65
95
mA
1, 2
Auto (CBR)
Refresh Current
Icc5
trc>=trc(min)
1
2
3
75
95
115
60
75
90
mA
mA
mA
1, 2
Self Refresh
Icc6
CKE=<0,2V
11
1
mA
1, 2
Notes:
1. The specified values are valid when addresses are changed no more than three times during trc(min.) and
when No Operation commands are registered on every rising clock edge during tRC(min).
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
Semiconductor Group
14
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
AC Characteristics 1)2)3)
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Limit Values
Symbol
-8
min
Unit
-10
max
min
max
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3 tCK
CAS Latency = 2
8
10
–
–
10
12
–
–
CAS Latency = 3 tCK
CAS Latency = 2
–
–
125
100
–
–
100
75
s
ns
ns
Clock Frequency
MHz
MHz
Access Time from Clock
CAS Latency = 3 tAC
CAS Latency = 2
–
–
6
6
–
–
7
8
ns
ns
Clock High Pulse Width
tCH
3
–
3
–
ns
Clock Low Pulse Width
tCL
3
–
3
–
ns
Transition time
tT
0.5
10
0.5
10
ns
Input Setup Time
tIS
2
–
3
–
ns
5
Input Hold Time
tIH
1
–
1
–
ns
5
CKE Setup Time
tCKS
2
–
3
–
ns
5
CKE Hold Time
tCKH
1
–
1
–
ns
5
Mode Register Set-up time
tRSC
16
–
20
–
ns
Power Down Mode Entry Time
tSB
0
8
0
10
ns
Row to Column Delay Time
tRCD
20
–
24
–
ns
6
Row Active Time
tRAS
45
100k
60
100k
ns
6
Row to Column Delay Time
tRCD
20
–
24
–
ns
6
Row Precharge Time
tRP
20
–
24
–
ns
6
Row Cycle Time
tRC
70
–
90
–
ns
6
Activate(a) to Activate(b) Command
period
tRRD
16
–
20
–
ns
6
2, 4
Setup and Hold Times
Common Parameters
Semiconductor Group
15
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Parameter
Limit Values
Symbol
-8
Unit
-10
min
max
min
max
tCCD
1
–
1
–
CLK
Refresh Period
(4096 cycles)
tREF
–
64
–
64
ms
Self Refresh Exit Time
tSREX
10
Data Out Hold Time
tOH
3
–
3
–
ns
Data Out to Low Impedance Time
tLZ
0
–
0
–
ns
Data Out to High Impedance Time
tHZ
3
8
3
10
ns
DQM Data Out Disable Latency
tDQZ
2
–
2
–
CLK
Write Recovery Time
tWR
8
–
10
–
ns
DQM Write Mask Latency
tDQW
0
–
0
–
CLK
Write Latency
tWL
0
–
0
–
CLK
CAS(a) to CAS(b) Command period
Refresh Cycle
10
ns
Read Cycle
2
8
Write Cycle
Frequency vs. AC Parameter Relationship Table:
-8 -parts
CL
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tWL
tWR
125 MHz
3
9
6
3
2
3
1
0
1
100 MHz
2
7
5
2
2
2
1
0
1
CL
tRC
tRAS
tRP
tRRD
tRCD
tCCD
WL
tWR
100 MHz
3
8
6
3
2
3
1
0
1
75 MHz
2
7
5
2
2
2
1
0
1
-10 -parts:
Semiconductor Group
16
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns
with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 50 pF only,
without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.
tCH
2.4 V
+ 1.4 V
CLOCK
0.4 V
tCL
tSETUP
50 Ohm
tT
tHOLD
Z=50 Ohm
I/O
1.4V
INPUT
50 pF
I/O
tAC
tAC
tLZ
50 pF
tOH
1.4V
OUTPUT
Measurement conditions for
tac and toh
fig.1
tHZ
3. If clock rising time is longer than 1 ns, a time (t T/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (t T -1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
Semiconductor Group
17
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Package Outlines:
Plastic Package P-TSOPII-44 ( 400mil, 0.8mm lead pitch)
Thin small outline package, SMD
GLX05862
TSOP-44 (400).WMF
0.8
3
0.15 +0.06
-0.0
1.2 max
0.1 +0.05
1+0.05
-
Plastic Package P-TSOPII-50 ( 400mil, 0.8mm lead pitch)
Thin small outline package, SMD
10.16 +0.13
-
0.5+0.1
-
0.4 +0.05
-0.1
0.2
M
0.1
50x
50
11.76 +0.2
-
26
1
25
20.95 +0.13 1)
-
Index marking
1) Does not include plastic or metal protusion of 0.25 max. per side
Semiconductor Group
18
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Read & Write with Auto-Precharge
7.1 Burst Write with Auto Precharge
7.2 Burst Read with Auto Precharge
8. Burst Termination
8.1 Termination of a Burst Read Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst ReadCAS Latency = 1
12. 2 Clock Suspension During Burst ReadCAS Latency = 2
12. 3 Clock Suspension During Burst ReadCAS Latency = 3
12. 4 Clock Suspension During Burst Write CAS Latency = 1
12. 5 Clock Suspension During Burst Write CAS Latency = 2
12. 6 Clock Suspension During Burst Write CAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Auto Refresh (CBR)
15. Self Refresh ( Entry and Exit)
16. Random Column Read ( Page within same Bank)
16.1 CAS Latency = 1
16.2 CAS Latency = 2
16.3 CAS Latency = 3
17. Random Column Write ( Page within same Bank)
17.1 CAS Latency = 1
17.2 CAS Latency = 2
17.3 CAS Latency = 3
Semiconductor Group
19
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Timing Diagrams (cont’d)
18. Random Row Read ( Interleaving Banks)
18.1 CAS Latency = 1
18.2 CAS Latency = 2
18.3 CAS Latency = 3
19. Random Row Write ( Interleaving Banks)
19.1 CAS Latency = 1
19.2 CAS Latency = 2
19.3 CAS Latency = 3
20. Full Page Read Cycle (optional feature)
20.1 CAS Latency = 1
20.2 CAS Latency = 2
20.3 CAS Latency = 3
21. Full Page Write Cycle (optional feature)
21.1 CAS Latency = 1
21.2 CAS Latency = 2
21.3 CAS Latency = 3
22. Precharge Termination of a Burst
22.1 CAS Latency = 1
22.2 CAS Latency = 2
22.3 CAS Latency = 3
Semiconductor Group
20
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
..........
ADDRESS
Bank A
Col. Addr.
Bank A
Row Addr.
..........
tRCD
COMMAND
Bank A
Activate
NOP
Bank A
Row Addr.
Bank B
Row Addr.
tRRD
NOP
Write A
with Auto
Precharge
..........
Bank B
Activate
NOP
Bank A
Activate
: “H” or “L”
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
CAS latency = 1
tCK1, DQ’s
CAS latency = 2
tCK2, DQ’s
NOP
NOP
NOP
NOP
NOP
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
NOP
CAS latency = 3
tCK3, DQ’s
Semiconductor Group
21
DOUT A 3
NOP
NOP
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
READ A
READ B
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 1
DOUT A 0
tCK1, DQ’s
CAS latency = 2
tCK2, DQ’s
NOP
NOP
NOP
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
DOUT A 0
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
DOUT A0
DOUT B 0
DOUT B 1
DOUT B 2
NOP
NOP
NOP
NOP
CAS latency = 3
tCK3, DQ’s
DOUT B 3
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
NOP
DQ’s
WRITE B
DIN B0
DOUT A 0
Must be Hi-Z before
the Write Command
: “H” or “L”
Semiconductor Group
NOP
22
NOP
NOP
DIN B1
DIN B2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
4 2. Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
NOP
COMMAND
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
CAS latency = 1
tCK1, DQ’s
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
DIN A0
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS latency = 2
tCK2, DQ’s
: “H” or “L”
4. 3. Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
DIN B0
DIN B1
DIN B2
DOUT A 1
DIN B0
DIN B1
DIN B2
DOUT A 0
DIN B0
DIN B1
DIN B2
CLK
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
CAS latency = 1
tCK1, DQ’s
CAS latency = 2
DOUT A 0
DOUT A1
DOUT A 2
Must be Hi-Z before
the Write Command
DOUT A 0
tCK2, DQ’s
CAS latency = 3
tCK3, DQ’s
: “H” or “L”
Semiconductor Group
23
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
5. Burst Write Operation
(Burst Length = 4, CAS latency = 1, 2, or 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
DQ’s
WRITE A
DIN A0
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the same clock edge.
NOP
NOP
NOP
NOP
don’t care
Extra data is ignored after
termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 1, 2, or 3)
T0
T1
T2
WRITE A
WRITE B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
1 Clk Interval
DQ’s
Semiconductor Group
DIN A0
DIN B0
24
NOP
NOP
NOP
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
WRITE A
READ B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 1
DIN A0
tCK1, DQ’s
CAS latency = 2
tCK2, DQ’s
CAS latency = 3
tCK3, DQ’s
DIN A0
don’t care
DIN A0
don’t care
NOP
NOP
NOP
DOUT B 0
DOUT B 1
DOUT B2
DOUT B 3
DOUT B 0
DOUT B 1
DOUT B 2
DOUT B 3
DOUT B0
DOUT B 1
DOUT B 2
don’t care
NOP
NOP
NOP
DOUT B 3
Input data must be removed from the DQ’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
Input data for the Write is ignored.
7.1 Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
BANK A
ACTIVE
NOP
NOP
WRITE A
Auto-Precharge
NOP
NOP
tDPL
CAS latency = 1
DQ’s
DIN A0
DIN A1
tDPL
NOP
NOP
tRP
*
tRP
CAS latency = 2
DQ’s
DIN A0
DIN A1
tRP
tDPL
CAS latency = 3
DQ’s
*
DIN A0
DIN A1
*
*
Begin Autoprecharge
Bank can be reactivated after trp
Semiconductor Group
25
NOP
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
7.2 Burst Read with Auto-Precharge
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
with AP
NOP
*
CAS latency = 1
*
CAS latency = 2
tCK2, DQ’s
NOP
NOP
NOP
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 1
DOUT A 2
NOP
NOP
NOP
tRP
DOUT A 0
tCK1, DQ’s
NOP
tRP
DOUT A 0
*
CAS latency = 3
tCK3, DQ’s
tRP
DOUT A 0
DOUT A 3
*
Begin Autoprecharge
Bank can be reactivated after trp
8.1 Termination of a Burst Read Operation
(CAS latency = 1, 2, 3 / Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
CAS latency = 1
tCK1, DQ’s
CAS latency = 2
tCK2, DQ’s
NOP
NOP
NOP
Burst
Stop
DOUT A0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
NOP
NOP
Semiconductor Group
NOP
The burst ends after a delay equal to theCAS latency.
CAS latency = 3
tCK3, DQ’s
NOP
26
DOUT A 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
8.2 Termination of a Burst Write Operation
(CAS Laency = 1, 2, 3, Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 1,2,3
DQ’s
WRITE A
DIN A0
NOP
NOP
DIN A1
DIN A2
Burst
Stop
NOP
don’t care
Input data for the Write is masked.
Semiconductor Group
27
NOP
NOP
NOP
Semiconductor Group
28
DQ
DQM
Addr
AP
BA
WE
CAS
RAS
CS
CKE
CLK
Hi-Z
tCH
tAS
tCKS
T0
tRCD
tAH
T3
T4
Ax0
CAx
tCK2
tCH
tCS
T2
Ax1
T5
Ax2
tRC
RBx
RBx
T6
Ax3
T7
T9
T10
Bx0
CBx
Bx1
Bx2
RAy
RAy
Bx3
tDS
Begin Auto Precharge
Bank A
T8
Activate
Write with
Activate
Write with
Activate
Command Auto Precharge Command Auto Precharge Command
Bank A
Command
Bank B
Command
Bank A
Bank A
Bank B
RAx
RAx
tCL
T1
9.1 AC Parameters for Write Timing
T13
T14
Write
Command
Bank A
Ay0
Ay1
tDH
Ay2
T16
Precharge
Command
Bank A
tDPL
T15
Ay3
Begin Auto Precharge
Bank B
T12
RAy
T11
tRP
tCKH
T20
Activate
Command
Bank B
RBy
RBy
T19
tRRD
T18
Activate
Command
Bank A
RAz
RAz
T17
T21
T22
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
29
DQ
DQM
Addr
AP
BA
WE
CAS
RAS
CS
CKE
CLK
Hi-Z
tCKS
tCH tCL
T0
tAS
RAx
RAx
tCS
tRCD
tAH
tCH
tCK2
T2
Activate
Command
Bank A
T1
9.2 AC Parameters for Read Timing
tRRD
CAx
T4
Read
Command
Bank A
T3
tLZ
tAC2
tAC2
Ax0
tOH
tRAS
RBx
RBx
T6
Activate
Command
Bank B
T5
RBx
T8
Read with
Auto Precharge
Command
Bank B
Ax1
tHZ
tRC
T7
T10
Precharge
Command
Bank A
Bx0
Begin Auto
Precharge
Bank B
T9
tHZ
Bx1
tRP
tCKH
RAy
RAy
T12
Activate
Command
Bank A
T11
T13
Burst Length = 2, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
30
Addr
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
Precharge
Command
All Banks
T1
10. Mode Register Set
T5
Mode Register
Set Command
T6
Any
Command
2 Clock min.
T4
Address Key
T3
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
31
DQ
DQM
Addr
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T
T
T
Precharge 1st Auto Refresh
Command
Command
All Banks
tRP
High level
is required
T
Inputs must be
stable for 200µs
Hi-Z
T0
T
T
T
T
T1
T
T
T
2nd Auto Refresh
Command
Minimum of 2 Refresh Cycles are required
T
11. Power on Sequence and Auto Refresh (CBR)
tRC
T
T
T
Mode Register
Set Command
T
Any
Command
2 Clock min.
T
Address Key
T
T
T
T
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
32
Hi-Z
DQ
T3
Read
Command
Bank A
CAx
T2
Activate
Command
Bank A
RAx
Addr
DQM
RAx
tCK1
T1
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
Ax0
Ax1
T5
T6
Clock Suspend
1 Cycle
T4
Ax2
T8
Clock Suspend
2 Cycles
T7
T9
Ax3
T11
tHZ
T12
Clock Suspend
3 Cycles
T10
12.1 Clock Suspension During Burst Read (Using CKE) (1 of 3)
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
33
DQ
Activate
Command
Bank A
RAx
Addr
Hi-Z
RAx
DQM
T1
tCK2
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
CAx
T3
Read
Command
Bank A
T2
T4
Ax0
Ax1
T6
T7
Clock Suspend
1 Cycle
T5
Ax2
T9
Clock Suspend
2 Cycles
T8
T10
Ax3
T12
tHZ
T13
Clock Suspend
3 Cycles
T11
12.2 Clock Suspension During Burst Read (Using CKE) (2 of 3)
T14
T15
T16
T17
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
34
DQ
Activate
Command
Bank A
RAx
Addr
Hi-Z
RAx
DQM
T1
tCK3
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
CAx
T4
Read
Command
Bank A
T3
T5
T6
Ax0
Ax1
T8
T9
Clock Suspend
1 Cycle
T7
T11
Clock Suspend
2 Cycles
Ax2
T10
12.3 Clock Suspension During Burst Read (Using CKE) (3 of 3)
T12
Ax3
T14
tHZ
T15
Clock Suspend
3 Cycles
T13
T16
T17
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
35
Hi-Z
DQ
T3
DAx1
T4
Write
Command
Bank A
Clock Suspend
1 Cycle
DAx0
CAx
T2
Activate
Command
Bank A
RAx
Addr
DQM
RAx
tCK1
T1
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T6
T8
DAx2
T7
Clock Suspend
2 Cycles
T5
T10
Clock Suspend
3 Cycles
T9
T12
DAx3
T11
12.4 Clock Suspension During Burst Write (Using CKE) (1 of 3)
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
36
DQ
Activate
Command
Bank A
RAx
Addr
Hi-Z
RAx
DQM
T1
tCK2
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T3
T4
Write
Command
Bank A
T6
T7
Clock Suspend
2 Cycles
T5
DAx1
Clock Suspend
1 Cycle
DAx0
CAx
T2
DAx2
T8
T10
Clock Suspend
3 Cycles
T9
T12
DAx3
T11
12.5 Clock Suspension During Burst Write (Using CKE) (2 of 3)
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
37
Hi-Z
DQ
tCK3
T1
Activate
Command
Bank A
RAx
Addr
DQM
RAx
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
CAx
T4
Write
Command
Bank A
T7
T8
Clock Suspend
2 Cycles
T6
DAx1
T5
Clock Suspend
1 Cycle
DAx0
T3
DAx2
T9
T11
Clock Suspend
3 Cycles
T10
T13
DAx3
T12
12.6 Clock Suspension During Burst Write (Using CKE) (3 of 3)
T14
T15
T16
T17
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
38
DQ
T2
T3
tCKSP
Clock Suspend
Mode Entry
Activate
Command
Bank A
RAx
Addr
Hi-Z
RAx
DQM
T1
tCK2
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
CAx
T6
Read
Command
Bank A
T5
Clock Suspend
Mode Exit
T4
13. Power Down Mode and Clock Suspend
T7
Ax1
T9
Clock Mask
Start
Ax0
T8
T10
T12
Clock Mask
End
Ax2
T11
tHZ
T13
T15
Precharge
Command
Bank A
Ax3
T14
T16
T18
Power Down
Mode Entry
T17
tCKSP
T19
T21
T22
Any
Command
Power Down
Mode Exit
T20
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
39
Hi-Z
Precharge
Command
All Banks
T4
T5
tRC
T6
T7
T9
Auto Refresh
Command
T8
T10
T12
tRC
T11
T13
T14
T15
DQ
DQM
Auto Refresh
Command
(Minimum Interval)
Activate
Command
Bank A
RAx
T3
Addr
T2
RAx
tRP
tCK2
T1
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
14. Auto Refresh (CBR)
T17
Read
Command
Bank A
CAx
T16
T18
Ax0
T19
Ax1
T20
Ax2
T21
Ax3
T22
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
40
DQ
DQM
A0 - A9
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
All Banks
must be idle
Hi-Z
T0
T1
T3
Self Refresh
Entry
T2
T4
15. Self Refresh (Entry and Exit)
T5
T6
T8
T10
tRC
T11
Begin Self Refresh
Exit Command
tSREX
tCKSR
T9
Self Refresh Exit
Command issued
T7
T
Self Refresh
Exit
T
T
T
T
T
T
T
T
T
T
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
41
DQ
CAw
T2
Activate
Command
Bank A
Read
Command
Bank A
RAw
Addr
Hi-Z
RAw
DQM
T1
tCK1
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
Aw0
T3
Aw1
T4
Aw3
CAx
T6
Read
Command
Bank A
Aw2
T5
Ax1
CAy
T8
Read
Command
Bank A
Ax0
T7
Ay0
T9
Ay1
T10
Ay3
T12
RAz
RAz
T14
CAz
T13
T15
Az0
Precharge
Read
Command
Command
Bank A
Bank A
Activate
Command
Bank A
Ay2
T11
16.1 Random Column Read (Page within same Bank) (1 of 3)
Az1
T16
Az2
T17
Az3
T18
T19
T20
T21
T22
Burst Length = 4, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
42
DQ
Activate
Command
Bank A
RAw
Addr
Hi-Z
RAw
DQM
T1
tCK2
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
CAw
T3
Read
Command
Bank A
T2
T4
Aw0
T5
Aw2
CAx
T7
Read
Command
Bank A
Aw1
T6
Ax0
CAy
T9
Read
Command
Bank A
Aw3
T8
Ax1
Ay2
T13
Precharge
Command
Bank A
T12
Ay1
T11
Ay0
T10
16.2 Random Column Read (Page within same Bank) (2 of 3)
Ay3
RAz
RAz
T15
Activate
Command
Bank A
T14
T17
Read
Command
Bank A
CAz
T16
T18
Az0
T19
Az1
T20
Az2
T21
Az3
T22
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
43
DQ
Activate
Command
Bank A
RAw
Addr
Hi-Z
RAw
DQM
T1
tCK3
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
CAw
T4
Read
Command
Bank A
T3
T5
T6
Aw1
CAx
T8
Read
Command
Bank A
Aw0
T7
Aw3
CAy
T12
Ax1
T11
Ax0
T10
Read
Command
Bank A
Aw2
T9
16.3 Random Column Read (Page within same Bank) (3 of 3)
Ay0
T13
Ay1
Precharge
Command
Bank A
T16
Ay3
T15
Ay2
T14
T18
Activate
Command
Bank A
RAz
RAz
T17
T19
T21
Read
Command
Bank A
CAz
T20
T22
Burst Length = 4, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
44
DQ
T3
T4
T5
CBx
T6
T7
CBy
T8
T9
T10
T11
Write
Command
Bank B
Write
Command
Bank B
T12
RBz
RBz
T13
Precharge
Command
Bank B
Activate
Command
Bank B
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
CBw
T2
Activate
Command
Bank B
Write
Command
Bank B
RBw
Addr
Hi-Z
RBw
DQM
T1
tCK1
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
17.1 Random Column Write (Page within same Bank) (1 of 3)
T14
T15
T16
T18
T19
T20
T21
Write
Command
Bank B
DBz0 DBz1 DBz2 DBz3
CBz
T17
T22
Burst Length = 4, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
45
DQ
Bx0
tRCD tAC1
CBx
tCK1
T1
Activate
Command
Bank B
Read
Command
Bank B
Hi-Z
RBx
A0 - A9
DQM
RBx
High
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
T0
Bx1
T2
Bx2
T3
T4
Bx3
Bx4
T5
T6
Bx5
Bx6
RAx
RAx
T8
Bx7
CAx
T9
Ax0
Ax1
tRP
RBy
RBy
T10
Ax2
T11
Activate
Precharge
Command
Command
Bank A
Bank B
Activate
Read
Command
Command
BankB
Bank A
T7
18.1 Random Row Read (Interleaving Banks) (1 of 3)
Ax3
T12
Ax4
T13
Ax5
T14
Ax6
T15
Ax7
T16
T17
By0
T19
Read
Command
Bank B
CBy
T18
T22
By2
T21
Precharge
Command
Bank A
By1
T20
Burst Length = 8, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
46
DQ
tRCD
Activate
Command
Bank B
Hi-Z
RBx
A0 - A9
DQM
RBx
High
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
T0
T2
Read
Command
Bank B
CBx
tCK2
T1
tAC2
T3
Bx0
T4
Bx1
T5
Bx2
T6
Bx4
RAx
RAx
T8
Activate
Command
Bank A
Bx3
T7
Bx6
CAx
Ax1
RBy
RBy
T13
Activate
Command
Bank B
T12
Ax0
tRP
T11
Bx7
T10
Precharge
Command
Bank B
Read
Command
Bank A
Bx5
T9
18.2 Random Row Read (Interleaving Banks) (2 of 3)
Ax2
T14
Ax3
Ax6
T17
Ax5
T16
Ax4
T15
T19
Read
Command
Bank B
Ax7
CBy
T18
By0
T20
By1
T21
T22
Burst Length = 8, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
47
DQ
Activate
Command
Bank B
Hi-Z
RBx
A0 - A9
DQM
RBx
High
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
T0
tRCD
tCK3
T1
CBx
T3
Read
Command
Bank B
T2
T4
tAC3
T5
Bx0
T6
Bx2
RAx
RAx
T8
Activate
Command
Bank A
Bx1
T7
Bx3
T9
18. 3 Random Row Read (Interleaving Banks) (3 of 3)
Bx4
Bx7
tRP
RBy
RBy
Activate
Command
Bank B
Ax3
T16
Ax2
T15
Ax1
T14
Ax0
T13
Precharge
Command
Bank B
T12
Bx6
T11
Read
Command
Bank A
Bx5
CAx
T10
Ax4
T17
Ax6
T19
Read
Command
Bank B
Ax5
CBy
T18
By0
T21
Precharge
Command
Bank A
Ax7
T20
T22
Burst Length = 8, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
48
DQ
T1
tCK1
CAx
T2
T3
T4
T5
T6
T7
RBx
RBx
T8
CBx
T9
T10
T11
T12
tRP
T13
RAy
RAy
T14
T15
tDPL
T16
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
T17
T19
T20
T21
T22
Write
Command
Bank A
DAy0 DAy1 DAy2 DAy3
CAy
T18
Burst Length = 8, CAS Latency = 1
Precharge
Command
Bank B
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7
tRCD
Activate
Command
Bank A
Hi-Z
RAx
A0 - A9
DQM
RAx
High
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
T0
19.1 Random Row Write (Interleaving Banks) (1 of 3)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
49
DQ
Activate
Command
Bank A
Hi-Z
RAx
A0 - A9
DQM
RAx
High
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
T0
T3
T4
T5
T6
T7
RBx
RBx
T8
CBx
tDPL
T9
T10
T12
tRP
T11
RAy
RAy
T13
T14
T15
T16
tDPL
CAy
T17
T18
T19
T20
T21
T22
Burst Length = 8, CAS Latency = 2
Activate
Command
Bank B
Precharge
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
T2
Write
Command
Bank A
tRCD
CAy
CAX
tCK2
T1
19.2 Random Row Write (Interleaving Banks) (2 of 3)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
50
DQ
Activate
Command
Bank A
Hi-Z
RAx
A0 - A9
DQM
RAx
High
A10
A11(BS)
WE
CAS
RAS
CS
CKE
CLK
T0
tRCD
tCK3
T1
CAX
T3
T4
T5
T6
T7
RBx
RBx
T8
T9
T11
tDPL
CBx
T10
T12
T13
tRP
T14
T15
RAy
RAy
T16
T17
T19
tDPL
CAy
T18
T20
T21
T22
Burst Length = 8, CAS Latency = 3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
T2
19.3 Random Row Write (Interleaving Banks) (3 of 3)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Semiconductor Group
51
DQ
Activate
Command
Bank B
RBz
Addr
Hi-Z
RBz
DQM
T1
tCK2
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
CBz
T3
T4
T5
T6
CBx
T7
T8
CBy
T9
T10
T11
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
T13
Precharge
Command
Bank B
T12
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
T2
17.2 Random Column Write (Page within same Bank) (2 of 3)
T15
Activate
Command
Bank B
RAw
RBz
RAw
RBz
T14
T17
T18
T19
T20
Write
Command
Bank B
DBz0 DBz1 DBz2 DBz3
CAx
CBz
T16
T21
T22
Burst Length = 4, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
52
DQ
Activate
Command
Bank B
RBz
Addr
Hi-Z
RBz
DQM
T1
tCK3
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
CBz
T4
T5
T6
T7
CBx
T8
T9
CBy
T10
T11
T12
T13
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
T3
17.3 Random Column Write (Page within same Bank) (3 of 3)
T15
Precharge
Command
Bank B
T14
T16
T18
Activate
Command
Bank B
RBz
RBz
T17
T19
T21
T22
Write
Command
Bank B
DBz0 DBz1
CBz
T20
Burst Length = 4, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
53
DQ
tRRD
CAx
Ax
RBx
RBx
tCK1
T1
T3
T4
Ax-2
T
Ax-1
T
Ax
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Ax+1 Ax+2
T2
Activate
Activate
Command
Command
Bank B
Bank A
Read
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
20.1 Full Page Read Cycle (1 of 3)
Ax+1
CBx
T
Read
Command
Bank B
T
Bx+1 Bx+2
T
T
Bx+3
T
T
Bx+4 Bx+5
T
Bx+6
T
Bx+7
tRP
T
RBy
RBy
T
Activate
Command
Bank B
Precharge
Command
Bank B
T
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues Burst Stop
bursting beginning with the starting address. Command
Bx
T
T
T
T
T
Burst Length = Full Page, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
54
DQ
Activate
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
Read
Command
Bank A
CAx
tCK2
T1
Ax
RBx
RBx
Ax+1
T4
Activate
Command
Bank B
T3
20.2 Full Page Read Cycle (2 of 3)
T
Ax-1
T
Ax
CBx
T
T
Bx
T
Bx+1
T
Bx+2
T
T
Bx+3 Bx+4
T
T
Bx+6
T
Burst Stop
Command
Precharge
Command
Bank B
Bx+5
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Ax+1
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Ax-2
T6
Ax+2
T5
tRP
RBy
RBy
T
Activate
Command
Bank B
T
T
T
T
Burst Length = Full Page, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
55
DQ
Activate
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
tCK3
T1
CAx
T3
Read
Command
Bank A
T2
RBx
RBx
T5
Activate
Command
Bank B
T4
20.3 Full Page Read Cycle (3 of 3)
Ax
T8
T
Ax-1
CBx
T
Ax
T
Ax+1
T
Bx
T
Bx+1
T
Bx+2
T
T
Bx+3 Bx+4
T
Read
Command
Bank B
tRRD
T
Bx+5
Full Page burst operation does not
terminate when the length is
Precharge
satisfied; the burst counter
Command
increments and continues
Bank B
The burst counter wraps bursting beginning with
from the highest order
the starting address.
page address back to zero
Burst Stop
during this time interval.
Command
Ax+2 Ax-2
T7
Ax+1
T6
RBy
RBy
T
Activate
Command
Bank B
T
T
T
Burst Length = Full Page, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
56
DQ
RBx
T2
T3
T4
T
T
T
CBx
T
T
T
T
T
T
T
T
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Write
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
T
RBy
RBy
T
Activate
Command
Bank B
Precharge
Command
Bank B
T
T
T
T
Page Length:
2Mb x 4I/O x 2 Banks = 1024
1Mb x 8I/O x 2 Banks = 512
512kb x 16I/O x 2 Banks = 256
T
Burst Length = Full Page, CAS Latency = 1
Burst Stop
Command
Data is ignored.
DAx DAx+1 DAx+2 DAx+2 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7
CAx
RBx
tCK1
T1
Activate
Command
Activate
Bank B
Command
Bank A
Write
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
21.1 Full Page Write Cycle (1 of 3)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
57
DQ
Activate
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
T3
RBx
RBx
T4
T5
T
T
T
CBx
T
T
T
T
T
T
T
Write
Command
Bank A
T
T
RBy
RBy
T
Activate
Command
Bank B
T
T
T
T
Burst Length = Full Page, CAS Latency = 2
Activate
Write
Command
Precharge
Command
Data is ignored.
Command
Bank B
Bank B
Bank B
The burst counter wraps
Full Page burst operation does not
from the highest order
terminate when the burst length is satisfied;
page address back to zero
Burst Stop
the burst counter increments and continues
during this time interval.
bursting beginning with the starting address.
Command
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
CAx
tCK2
T1
21.2 Full Page Write Cycle (2 of 3)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
58
DQ
Activate
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
tCK3
T1
CAx
T3
T4
RBx
RBx
T5
T6
T
T
T
CBx
T
T
T
T
T
T
Write
Command
Bank A
T
T
RBy
RBy
T
Activate
Command
Bank B
T
Data is ignored.
T
T
T
Burst Length = Full Page, CAS Latency = 3
Activate
Write
Command
Precharge
Command Full Page burst operation does not
Command
Bank B
Bank B terminate when the length is
Bank B
satisfied;
the
burst
counter
The burst counter wraps
increments and continues
from the highest order
bursting beginning with
page address back to zero
Burst Stop
the starting address.
during this time interval.
Command
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
T2
21.3 Full Page Write Cycle (3 of 3)
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
59
Hi-Z
DQ
CAx
T3
T4
T5
T6
T7
Write
Command
Bank A
tRP
T8
RAy
RAy
T9
CAy
T10
Read
Precharge
Command
Command
Bank A
Bank A
Precharge Termination
Activate
of a Write Burst.
Command
Write data is masked.
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4
T2
Activate
Command
Bank A
RAx
Addr
DQM
RAx
tCK1
T1
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
22.1 Precharge Termination of a Burst (1 of 3)
Ay0
T11
Ay2
tRP
T13
RAz
RAz
CAz
T15
T16
T17
T18
T19
T20
T21
T22
Write
Command
Bank A
DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7
Precharge
Termination of
a Read Burst.
T14
Activate
Command
Bank A
Precharge
Command
Bank A
Ay1
T12
Burst Length = Full Page, CAS Latency = 1
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
60
DQ
Activate
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
T2
T3
T4
T5
T6
Write
Precharge
Command
Command
Bank A
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
DAx0 DAx1 DAx2 DAx3
CAx
tCK2
T1
tRP
RAy
RAy
T8
Activate
Command
Bank A
T7
22.2 Precharge Termination of a Burst (2 of 3)
CAy
T10
Read
Command
Bank A
T9
T11
Ay1
T13
Precharge
Command
Bank A
Ay0
T12
RAz
RAz
T15
Activate
Command
Bank A
Ay2
tRP
T14
T17
T18
Az1
T21
Az2
tRP
T20
Precharge
Command
Bank A
Az0
T19
Precharge Termination
of a Read Burst.
Read
Command
Bank A
CAz
T16
T22
Burst Length = 8 or Full Page, CAS Latency = 2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
Semiconductor Group
61
DQ
Activate
Command
Bank A
Hi-Z
RAx
Addr
DQM
RAx
High
AP
BA
WE
CAS
RAS
CS
CKE
CLK
T0
CAx
T3
Write
Command
Bank A
DAx0
T2
Write Data
is masked
tCK3
T1
T5
tRP
T6
RAy
RAy
T8
Activate
Command
Bank A
T7
Precharge Termination
of a Write Burst.
Precharge
Command
Bank A
T4
22.3 Precharge Termination of a Burst (3 of 3)
T9
T11
Read
Command
Bank A
CAy
T10
T12
T13
Ay1
T15
Precharge
Command
Bank A
Ay0
T14
Ay2
tRP
T16
T18
T19
T20
T21
Precharge Termination
of a Read Burst.
Activate
Command
Bank A
RAz
RAz
T17
T22
Burst Length = 4,8 or Full Page, CAS Latency = 3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
\
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Complete List of Operation Commands
SDRAM FUNCTION TRUTH TABLE
CURRENT
STATE 1
CS
RAS
CAS
WE
BS
Addr
ACTION
Idle
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
L
H
H
L
L
X
H
L
X
H
L
H
L
X
X
BS
BS
BS
BS
X
Op-
X
X
X
X
RA
AP
X
Code
NOP or Power Down
NOP
ILLEGAL2
ILLEGAL2
Row (&Bank) Active; Latch Row Address
NOP4
Auto-Refresh or Self-Refresh5
Mode reg. Access5
Row Active
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
L
L
H
H
L
X
X
H
L
H
L
X
X
X
BS
BS
BS
BS
X
X
X
CA,AP
CA,AP
X
AP
X
NOP
NOP
Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP
ILLEGAL2
Precharge
ILLEGAL
Read
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, New Read, DetermineAP3
Term Burst, Start Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge
ILLEGAL
Write
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, Start Read, DetermineAP3
Term Burst, New Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge3
ILLEGAL
Read
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Semiconductor Group
62
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
SDRAM FUNCTION TRUTH TABLE(continued)
CURRENT
STATE 1
CS
RAS
CAS
WE
BS
Addr
ACTION
Write
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Precharging H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Idle after tRP
NOP;> Idle after tRP
ILLEGAL2
ILLEGAL2
ILLEGAL2
NOP4
ILLEGAL
Row
Activating
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Row Active after tRCD
NOP;> Row Active after tRCD
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Write
Recovering
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP
NOP
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Refreshing
H
L
L
L
L
X
H
H
L
L
X
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP;> Idle after tRC
NOP;> Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
Accessing
Semiconductor Group
63
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
CLOCK ENABLE (CKE) TRUTH TABLE:
STATE(n)
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Addr
ACTION
SelfRefresh6
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Self-Refresh, Idle after tRC
EXIT Self-Refresh, Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Power-Down, > Idle.
EXIT Power-Down, > Idle.
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle7
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
X
H
H
H
L
L
L
X
X
X
H
H
L
H
L
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Enter Power- Down
Enter Power- Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
Any State
other than
listed above
H
H
L
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Begin Clock Suspend next cycle8
Exit Clock Suspend next cycle8.
Maintain Clock Suspend.
ABBREVIATIONS:
RA = Row Address
CA = Column Address
BS = Bank Address
AP = Auto Precharge
Notes for SDRAM function truth table :
1. Current State is state of the bank determined by BS. All entries assume that CKE was active
cycle.
(HIGH) during the preced
ing clock
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).
5. Illegal if any bank is not Idle.
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before
any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
Semiconductor Group
64