ICs for Communications Quad ISDN 4B3T Echocanceller Digital Front End DFE-T V2.1 PEF 24901 Version 2.1 Preliminary Data Sheet 06.99 DS 1 • PEF 24901 Revision History: Current Version: 06.99 Previous Version: Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com • ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. Edition 06.99 Published by Infineon Technologies AG i. Gr., SC, Balanstraße 73, 81541 München © Infineon Technologies AG i.Gr. 1999. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PEF 24901 Preface This document describes the interfaces, functions and behavior of the QUAD ISDN 4B3T Echocanceller Digital Front End (DFE-T V2.1). The PEF 24901 is the digital part of a twochip solution featuring four times ISDN basic rate access at 144kbit/s. DFE-T V2.1 supersedes the existing versions, DFE-T V1.1 and DFE-T V1.2. The corresponding Analog Front End, the AFE V2.1 (PEF 24902) is described in detail in the Data Sheet V1.1, the Delta Sheet V1.2 and the Delta Sheet V2.1. Organization of this Document This Preliminary Data Sheet is divided into 9 chapters. It is organized as follows: • Chapter 1, Introduction Gives a general description of the product and its family, lists the key features, and presents some typical applications. • Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. • Chapter 3, Functional IC Description Gives a functional overview of the device, shows a block diagram, specifies the various interfaces and describes the provided U-transceiver functions. • Chapter 4, Operational Description Describes the reset and power-down behavior, illustrates the activation and deactivation procedures, shows how the device is tested and how maintenance data can be retrieved. • Chapter 5, Monitor Commands Lists all available Monitor Commands that can be applied. • Chapter 6, Register Description Lists all register functions that are addressable by the new MON-12 protocol which behaves like a serial microprocessor interface. • Chapter 7, Electrical Characteristics Denotes the operating conditions and gives the exact interface timing. • Chapter 8, Package Outlines • Chapter 9, Appendix A: Standards and Specifications Preliminary Data Sheet iii 06.99 PEF 24901 • Chapter 10, Glossary • Chapter 11, Index Related Documentation • • • • • DFE-T V2.1 Product Overview 04.99 DFE-T V2.1 Delta Sheet 03.98 AFE V1.1 Data Sheet 05.96 AFE V1.2 Delta Sheet 06.97 AFE V2.1 Delta Sheet 09.98 Your Comments We welcome your comments on this document as we are continuously aiming at improving our documentation. Please send your remarks and suggestions by e-mail to [email protected] Please provide in the subject of your e-mail: device name (DFE-T V2.1), device number (PEF 24901), device version (Version 2.1), and in the body of your e-mail: document type (Preliminary Data Sheet), issue date (06.99) and document revision number (DS 1). Preliminary Data Sheet -iv 06.99 PEF 24901 Table of Contents Page Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii 1 1.1 1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 2 2.1 2.2 2.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pinning Changes from DFE-T V1.2 to DFE-T V2.1 . . . . . . . . . . . . . . . . . . 2-8 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.6.7 3.6.8 3.6.9 3.6.10 3.6.11 3.6.12 3.6.12.1 3.6.12.2 3.6.12.3 3.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 IOM®-2 Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 IOM®-2 Command/ Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 IOM®-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 MON-12 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 U-Transceiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 4B3T Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Exchanging Transparent Messages . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Coding from Binary to Ternary Data . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Decoding from Ternary to Binary Data . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Scrambler / Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Awake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 LT Mode State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 State Machine Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 State Machine Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 4 4.1 4.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Preliminary Data Sheet v 06.99 PEF 24901 Table of Contents Page 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.4 4.4.1 4.4.1.1 4.4.1.2 4.4.1.3 4.4.2 4.4.3 4.4.4 4.4.4.1 4.4.4.2 4.4.4.3 4.4.4.4 4.4.4.5 4.4.4.6 4.4.4.7 4.4.4.8 4.4.5 4.4.5.1 4.4.6 Layer 1 Activation/ Deactivation Procedures . . . . . . . . . . . . . . . . . . . . . . . 4-3 Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . 4-4 Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Complete Activation Initiated by Exchange with Repeater . . . . . . . . . . 4-6 Complete Activation Initiated by Terminal with Repeater . . . . . . . . . . . 4-7 Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Activation of Loop#1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Activation of Loop#1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Activation of Loop#2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Maintenance and Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Analog Loopback (No.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Available Loopbacks by Register Map . . . . . . . . . . . . . . . . . . . . . . . 4-14 Block Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Bit Error Rate Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 System Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Send Single Pulses Test Mode (SSP) . . . . . . . . . . . . . . . . . . . . . . . 4-17 Data Through Mode (DT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Master Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Pulse Mask Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Power Spectral-Density Measurement . . . . . . . . . . . . . . . . . . . . . . 4-18 Return-Loss Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Quiet Mode Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Insertion Loss Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Retrieving DSP Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Reading/Writing Coefficient Values . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 5 Monitor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 LP_SEL - Line Port Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 MRD - M-Bit Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 MWR - M-Bit Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 TEST - Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 LOOP - Loopback Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 RDS - Block Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 BERC - Bit Error Rate Counter Register . . . . . . . . . . . . . . . . . . . . . . . 6-11 DSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Preliminary Data Sheet vi 06.99 PEF 24901 Table of Contents Page 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.6 7.6.1 7.6.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 9 Appendix A: Standards and Specifications . . . . . . . . . . . . . . . . . . . . . 9-1 10 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 11 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Preliminary Data Sheet vii 06.99 PEF 24901 List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 6-1 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Page DFE-T/ AFE 2nd Generation Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 16-Line Card Application with DELPHI Solution . . . . . . . . . . . . . . . . . 1-5 16-Line Card Application with ELIC®/ IDEC® Solution . . . . . . . . . . . . 1-6 Connecting Two AFE/DFE-T Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Recommended Clocking Scheme for More Than Two DFE-T/AFE Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Pin Configuration (60 of 64 used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Data Flow Diagram (DFE-T V2.1 + AFE). . . . . . . . . . . . . . . . . . . . . . . 3-1 DFE-T V2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Clock Supply and Data Exchange between Master and Slave . . . . . . 3-3 Multiplexed Frame Structure of the IOM®-2 Interface . . . . . . . . . . . . . 3-5 Handshake Protocol with a 2-Byte Monitor Message/Response . . . . . 3-7 Abortion of Monitor Channel Transmission . . . . . . . . . . . . . . . . . . . . . 3-9 Monitor Access with MTO Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Frame Structure on SDX/SDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 M-Bit Access via MRD, MWR Register Pair. . . . . . . . . . . . . . . . . . . . 3-22 M-Bit Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Awake Procedure initiated by the LT . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 Awake Procedure initiated by the NT. . . . . . . . . . . . . . . . . . . . . . . . . 3-30 State Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 LT State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 Maximum Tolerable Input Jitter of the 15.36MHz Clock . . . . . . . . . . 3-44 Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Activation with Repeater Initiated by LT. . . . . . . . . . . . . . . . . . . . . . . . 4-6 Activation with Repeater Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . 4-7 Deactivation (Always Initiated by the Exchange) . . . . . . . . . . . . . . . . . 4-8 Activation of Loop#1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Activation of Loop#1A (Repeater) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Activation of Loop#2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 4-15 DSP Data Transfer Synchronization by Handshake Signals . . . . . . . 4-19 Provided DSP Registers for Access to Coefficient Data . . . . . . . . . . 4-21 DFE-T V2.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 IOM®-2 Interface Timing (Double Clock Mode) . . . . . . . . . . . . . . . . . . 7-4 Dynamic Input and Output Requirements at the Analog Interface. . . . 7-6 Preliminary Data Sheet viii 06.99 PEF 24901 Figure 7-5 Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Preliminary Data Sheet -ix 06.99 PEF 24901 List of Tables Table 2-1 Table 2-2 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 4-1 Table 4-2 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 6-1 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Page Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pinning Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 IOM®-2 Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Assignments of IOM® Channels to Time-Slots No. on SDX/SDR and Line Ports No. 3-14 Coding of the 4B3T Data Pulse (AOUT/BOUT) . . . . . . . . . . . . . . . . 3-15 Frame Structure for Downstream Transmission LT to NT . . . . . . . . 3-18 Frame Structure for Upstream Transmission NT to LT . . . . . . . . . . 3-19 MMS 43 Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 4B3T Decoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Coding of the 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . 3-27 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Command / Indicate Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Differences to LT-SM of DFE-T V1.2 . . . . . . . . . . . . . . . . . . . . . . . . 3-36 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 Boundary Scan Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 TAP Controller Instructions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 MON-8 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 MON-8 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 MON-0 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 MON-0 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Register Map Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 IOM®-2 Dynamic Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7-4 IOM®-2 Dynamic Output Characteristics . . . . . . . . . . . . . . . . . . . . . . 7-5 Dynamic Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Dynamic Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Boundary Scan Dynamic Timing Requirements . . . . . . . . . . . . . . . . 7-7 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Preliminary Data Sheet x 06.99 PEF 24901 Introduction 1 Introduction The Quad ISDN 4B3T Echocanceller Digital Front End (DFE-T) is the digital part of an optimized two-chip solution featuring 4x ISDN basic rate access at 144kbit/s. The PEF 24901 is designed to provide in conjunction with the Quad ISDN Echocanceller Analog Front End (PEF 24902 V2.1) full duplex data transmission at the U-reference point according to FTZ Guideline 1TR 220, ETSI TS 102 080 and ITU-T I.430 standards. The DFE-T 2nd generation has been completely reengineered to guarantee the availability of the well proved DFE-T/AFE solution over the year 2000. PEF 24901 V2.1 is downwards pin compatible and functionally equivalent to the DFE-T V1.x. Thus, line card manufacturers can make use of the most advanced process technology without the need to change their current design (besides the changeover to 3.3V power supply). No software changes are required if the DFE-T V2.1 is deployed in existing DFE-T V1.x solutions. Some new features are provided such as transparent message exchange and enhanced monitoring and test functions. The data rate is programmable from 1Mbit/s to 4Mbit/s. • 15.36MHz +\EULG [8 +\EULG +\EULG $)(9 ')(79 3() ,20 3() +\EULG 5HOD\'ULYHU 3RZHU&RQWUROOHU chipset.emf Figure 1-1 DFE-T/ AFE 2nd Generation Chip Set The output and input pins are throughout 5V TTL compatible although the PEF 24901 is processed in advanced 3.3V CMOS technology. A power down state with very low power consumption is featured. The PEF 24901 comes in a P-MQFP-64 package. Preliminary Data Sheet 1-1 06.99 Quad ISDN 4B3T Echocanceller Digital Front End DFE-T V2.1 Version 2.1 1.1 PEF 24901 CMOS Features U-Interface • Digital part of a two-chip solution featuring full duplex data transmission and reception over twowire metallic subscriber loops providing 4x ISDN basic rate access at 144 kbit/s • Conforms to: P-MQFP-64 – FTZ 1TR 220 (1991) – ETSI TS 102 080 V1.3.1 (1998) – ITU-T I.430 (1995) • 4B3T-block code at 120-kHz symbol rate • Subscriber loop length without repeater: – up to 4.2 km on 0.4 mm wire – up to 8.0 km on 0.6 mm wire • LT mode • 1 kbit/s maintenance channel for transmission of data loopback commands, detected transmission errors and transparent messages • Activation/ deactivation controller • Adaptive echo cancellation and equalization • Automatic gain control and polarity adaption • Clock recovery (frame and bit synchronization) • Transmission error counters for line monitoring • Remote and local control of test loops System Interface • IOM®-2 interface with programmable data rates (1 Mbit/s to 4 Mbit/s) • 4 relay driver pins per port addressable by Monitor command • 2 status pins per port accessible via Monitor channel Type Package PEF 24901 P-MQFP-64 Preliminary Data Sheet 1-2 06.99 PEF 24901 Introduction Other Features • • • • • • • • • Software compatible to the PEF 24901 V1.2 Inputs and outputs 5V TTL compatible DOUT (open drain) accepts pull-up to 3.3V or 5V Advanced low power CMOS technology (digital: 0.35µ process) Sophisticated power management for restricted power mode +3.3V ±0.3V Power Supply Extended temperature range (– 40...to 85°C) available Boundary-Scan, JTAG IEEE 1149.1 Add-On Features and Differences with Respect to DFE-T V1.2 • +3.3V instead of +5V power supply • Exchange of transparent messages via Maintenance channel by use of MON-0 commands • LT-RP mode is not supported • DOUT configurable either as open drain or push-pull (tristate) output • Monitor Time-Out (MTO) procedure • Bit Error Rate measurement per port • Additional digital local loops • C/I codes ’LTD’ and ’HI’ are no more supported • C/I code mnemonics adapted to 2B1Q notation for consistency reasons - coding has been retained unchanged • State machine notation is aligned to that of 2B1Q for consistency reasons • New MON-12 class features internal register access • Coefficients retrievable by MON-12 commands instead of MON-8 commands • The Boundary-Scan instructions ’CLAMP’ and HIGHZ are supported in version 2.1 (’SSP’ is omitted since for this function a dedicated pin is reserved) • JTAG Boundary-Scan with dedicated reset line TRST (replaces power-on reset functionality) Preliminary Data Sheet 1-3 06.99 PEF 24901 Introduction 1.2 Logic Symbol • %RXQGDU\6FDQ 7', 7'2 7567 73 )6& 6'; '&/ 6'5 ',1 4 '287 3'0 6/27 072 4 '$'%'&'' 4 &/ '$'%'&'' &/6 2 6767 &/6 &/6 2 6767 9'' &/6 966 4 9 Figure 1-2 383 &ORFNV 5HOD\'ULYHU6WDWXV3LQV ')(79 ,20 0RGH3LQV 6/27 ,20 ,QWHUIDFH $)(')(,QWHUIDFH 706 7&. 7HVW3LQ '7 663 5(6 4 0RGH6HWWLQJV 9 logsym.vsd Logic Symbol Preliminary Data Sheet 1-4 06.99 PEF 24901 Introduction 1.3 System Integration This paragraph shows how the DFE-T V2.1 may be integrated in systems using other Infineon ISDN devices. The PEF 24901 V2.1 is optimized for use in the following applications: – Digital Line Cards for Central Office – Digital Line Cards for Access Networks (LT mode only) – PBX applications (LT mode only) Figure 1-3 and Figure 1-4 illustrate line card solutions with various Infineon line card controllers. The DELPHI (PEB 20570) supersedes the ELIC® (PEB 20550) and will feature up to 32 HDLC controllers on-chip. • 7HVW8QLW $)( 9 ')(7 9 3() 3() 3&0+: ,20 '(/3+,/& 3(% 6LJQDOOLQJ 4,+3& 5$0 & 3(% lc_delphi.emf Figure 1-3 16-Line Card Application with DELPHI Solution Preliminary Data Sheet 1-5 06.99 PEF 24901 Introduction • 7HVW8QLW 3&0 +LJKZD\ (/,& $)( ')(7 9 9 3() 3() ,20 3(% 6LJQDOOLQJ ,'(& &%XV 3(% 4,+3& 3(% & & lc_elic.emf Figure 1-4 16-Line Card Application with ELIC®/ IDEC® Solution Figure 1-5 shows how a 8 channel line card application is realized by use of two AFE/ DFE-T chip sets: One AFE PLL generates the synchronized 15.36MHz clock and provides the master clock at pin CL15 for the other 3 devices. The internal PLL of the first AFE synchronizes the 15.36 MHz master clock onto a PTT reference clock of either 8 kHz or 2048 kHz. The PLL of the second AFE is deactivated. The 15.36 MHz master clock is applied at pin CL15. CL15 is configured as input if XIN is clamped either to VDD or to VSS. Pin XOUT has to be left open and CLOCK shall be tied to GND. Preliminary Data Sheet 1-6 06.99 PEF 24901 Introduction • 15.36MHz +\EULG +\EULG [8 ;,1 ;287 8/ 2048kHz PTT Reference Cock &/2&. ,20 3'0 6'5 $)(9 3() +\EULG +\EULG &/ )6& ')(79 3() 6'; 0+] +\EULG [8 &/ +\EULG '287 0%LWV &/ 6'; $)(9 3() +\EULG ',1 &/ 0+] +\EULG '&/ 6'5 ')(79 3() 3'0 ;,1 ;287 &/2&. 9'' 1& 966 966 clkchain1.emf Figure 1-5 Connecting Two AFE/DFE-T Chip Sets The DFE-T devices are supplied by the first AFE at pin CL15 with the synchronized 15.36MHz clock. The IOM®-2 channels the DFE-T devices are assigned to can be programmed by the two slot pins. Starting from channel no. 0/4/8/12 always four subsequent channels are occupied. Alternatively the clocking scheme as shown in Figure 1-6 may be applied if more than 3 devices are to be clocked (e.g. in a 16-channel line card application). Instead to supply the 2nd AFE with the master clock at pin CL15, here the 15.36MHz master clock is input at pin XIN. Thereby pin CL15 is configured as output and passes the 15.36MHz clock on to the attached DFE-T. If the clock chain is extended in the same way by another two AFE/DFE-T chip sets a 16-channel line card application can be realized with just one single crystal. Note that the 15.36MHz clock is inverted once by the AFE if it is input at XIN and output at CL15. This way the duty cycle is recovered again. Preliminary Data Sheet 1-7 06.99 PEF 24901 Introduction • 15.36MHz +\EULG +\EULG [8 ;,1 ;287 8/ 2048kHz PTT Reference Cock &/2&. ,20 3'0 6'5 $)(9 3() +\EULG +\EULG &/ 6'; 0+] )6& ')(79 3() '&/ ',1 '287 &/ 0+] +\EULG +\EULG [8 ;,1 1& 966 ;287 &/2&. 0%LWV 3'0 6'5 $)(9 3() +\EULG +\EULG &/ 6'; 0+] ')(79 3() &/ 0+] +\EULG +\EULG [8 +\EULG +\EULG ;,1 1& 966 ;287 &/2&. $)(9 3() &/ clkchain2.emf Figure 1-6 Recommended Clocking Scheme for More Than Two DFE-T/AFE Chip Sets Preliminary Data Sheet 1-8 06.99 PEF 24901 Introduction 1.4 Operational Overview The DFE-T V2.1 operates always in LT mode. System Interface Configurations The following parameters of the system interface are configurable: • Open Drain/ Push-Pull Mode Configured as open drain the output pin DOUT is floating and a pull-up resistor is required. In push-pull mode the output pin is high impedance outside the active time slots. • IOM®-2 Channel Assignment IOM®-2 channels are always assigned in blocks of four. SLOT1 Assigned IOM®-2 Channels SLOT0 0 0 0 .. 3 0 1 4 .. 7 1 0 8 .. 11 1 1 12 .. 15 • IOM®-2 Data Rates DCL Frequency [kHz] Data Rate [kBit/s] IOM®-2 Channels 2048 1024 4 3072 1536 6 4096 2048 8 6144 3072 12 8192 4096 16 Preliminary Data Sheet 1-9 Remarks LT Burst Mode 06.99 PEF 24901 Introduction Send Single Pulses Test Mode In test mode ’Send Single Pulses’ +1 pulses spaced by 1ms are transmitted on all U lines. The test mode is activated by pin SSP= set to ’1’. The SSP test function can be as well stimulated by C/I= SSP besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line. Data Through Mode In test mode ’Data Through’ the U-transceiver is forced to enter the ’Transparent’ state and to issue U4 independent of the wake-up protocol. The DT test mode is activated by pin DT= set to ’1’. The DT test function can be as well stimulated by C/I= DT besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line. Preliminary Data Sheet 1-10 06.99 PEF 24901 Pin Descriptions 2 Pin Descriptions 2.1 Pin Diagram (top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 52 29 53 28 54 27 55 26 56 25 304)3 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 2-1 ',1 '287 072 7', 7'2 &/ 6'5 9'' 3'0 3'0 966 3'0 3'0 '&/ )6& 49 50 51 706 73 '' '' &/6 1& 9'' 6/27 663 966 1& 1& 5(6 &/6 '7 7567 7&. 9'' '% 1& '% '$ '$ '' '' '& 6/27 '& '& '& 966 '% '% • 383 '$ '$ &/6 67 67 67 966 67 67 9'' 67 &/6 67 67 6'; pinning.vsd Pin Configuration (60 of 64 used) Preliminary Data Sheet 2-1 06.99 PEF 24901 Pin Descriptions 2.2 Pin Definitions and Functions • Table 2-1 Pin No. Pin Definitions and Functions Symbol Input (I) Output (O) Function IOM®-2 Interface 13 FSC I Frame Synchronization Clock (8kHz) the start of the first B1-channel in time-slot 0 is marked, FSC is expected to be ’1’ for at least two DCL periods. 12 DCL I Data Clock clock rate ranges from 2048 to 8192kHz (1024 to 4096kBit/s) 14 DIN I Data In input of IOM®-2 data synchronous to DCL clock 15 DOUT O (OD/ PuP) Data Out output of IOM®-2 data synchronous to DCL clock Mode Selection Pins 60 RES I Reset triggers asynchronous HW reset, Schmitt trigger input ’1’= inactive ’0’= active 55 SLOT0 I IOM®-2 Channel Slot Selection 0 assigns IOM®-2 channels in blocks of 4 SLOT1, 0: ’00’= IOM®-2 channels 0 to 3 ’01’= IOM®-2 channels 4 to 7 ’10’= IOM®-2 channels 8 to 11 ’11’= IOM®-2 channels 12 to 15 45 SLOT1 Preliminary Data Sheet I (PD) IOM®-2 Channel Slot Selection 1 assigns IOM®-2 channels in blocks of 4, internal pulldown resistor (160kΩ) 2-2 06.99 PEF 24901 Pin Descriptions Table 2-1 Pin No. 16 Pin Definitions and Functions Symbol Input (I) Output (O) Function MTO I (PD) Monitor Channel Time-Out if activated the Monitor channel is reset every 12ms, internal pulldown resistor (160kΩ) ’1’= enables 12ms time-out ’0’= disables the 12ms time-out 32 PUP I (PD) Push Pull Mode in push pull mode ’0’ and ’1’ is actively driven during an occupied time slot (as soon as 1.FSC was received after reset), outside the active time slots DOUT is high impedance (tristate), internal pulldown resistor (160kΩ) ’1’= configures DOUT as push/pull output ’0’= configures DOUT as open drain output 56 SSP I Send Single Pulses (SSP) Test Mode ’1’= +1 pulses are issued at all line ports in 1ms intervals ’0’= deactivated, clamp to GND if not used Note: This pin function corresponds to the SW selection by C/I= SSP besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line 62 DT I Data Through (DT) Test Mode enables/disables DT test mode ’1’= DT test mode enabled, the U-transceiver is forced on all line ports to enter the ’Transparent’ state ’0’= DT test mode disabled Note: This pin function corresponds to the SW selection by C/I= DT besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line Preliminary Data Sheet 2-3 06.99 PEF 24901 Pin Descriptions Table 2-1 Pin No. Pin Definitions and Functions Symbol Input (I) Output (O) Function Interface to the Analog Front End 4 CL15 I 15.36MHz Master Clock Input 11 PDM0 I Pulse Density Modulated Receive Data of Line Port 0 pulse density modulated bit stream from the PEB 24902 Quad AFE that is output from the second-order sigma-delta ADC 10 PDM1 I Pulse Density Modulated Receive Data of Line Port 1 pulse density modulated bit stream from the PEB 24902 Quad AFE that is output from the second-order sigma-delta ADC 8 PDM2 I Pulse Density Modulated Receive Data of Line Port 2 pulse density modulated bit stream from the PEB 24902 Quad AFE that is output from the second-order sigma-delta ADC 7 PDM3 I Pulse Density Modulated Receive Data of Line Port 3 pulse density modulated bit stream from the PEB 24902 Quad AFE that is output from the second-order sigma-delta ADC 5 SDR I Serial Data Receive Line interface signal from the PEB24902 Quad AFE that transports level detect information for the wake-up recognition of all 4 lines by use of TDM Preliminary Data Sheet 2-4 06.99 PEF 24901 Pin Descriptions Table 2-1 Pin No. 17 Pin Definitions and Functions Symbol Input (I) Output (O) Function SDX O Serial Data Transmit Line interface to the PEB24902 Quad AFE for the transmit and control data. Transmission is based on clock CL15 (15.36 Mbit/s). For each line port the following bits are exchanged: TD0, TD1: Transmit data RANGE: Range select LOOP: Analog loopback switch PDOW: Power down/power up Synchronization information Relay Driver/ Status Pins 30, 35, 42, 47 D0A D0B D0C D0D O Relay Driver Pins of Line Port 0 addressable via MON-8 command in IOM®-2 channel 0/4/8/12. The logic values of the bit positions A,B,C, D of the MON-8 command ’SETD’ determine the output setting. Default value after pin-reset is low. C/I-code reset does not affect the current status. 31, 37, 43, 48 D1A D1B D1C D1D O Relay Driver Pins of Line Port 1 addressable via MON-8 command in IOM®-2 channel 1/5/9/13. The logic values of the bit positions A,B,C, D of the MON-8 command ’SETD’ determine the output setting. Default value after pin-reset is low. C/I-code reset does not affect the current status. 33, 39, 44, 50 D2A D2B D2C D2D O Relay Driver Pins of Line Port 2 addressable via MON-8 command in IOM®-2 channel 2/6/10/14. The logic values of the bit positions A,B,C, D of the MON-8 command ’SETD’ determine the output setting. Default value after pin-reset is low. C/I-code reset does not affect the current status. Preliminary Data Sheet 2-5 06.99 PEF 24901 Pin Descriptions Table 2-1 Pin No. Pin Definitions and Functions Symbol Input (I) Output (O) Function 34, 40, 46, 51 D3A D3B D3C D3D O Relay Driver Pins of Line Port 3 addressable via MON-8 command in IOM®-2 channel 3/7/11/15. The logic values of the bit positions A,B,C, D of the MON-8 command ’SETD’ determine the output setting. Default value after pin-reset is low. C/I-code reset does not affect the current status. 28, 27 ST00 ST01 I Status Pin of Line Port 0 change of status is passed to IOM®-2 channel 0/4/8/12 via the MON-8 message ’AST’ at bit positions S0, S1. Connect to either VDD or VSS if not used. 26, 24 ST10 ST11 I Status Pin of Line Port 1 change of status is passed to IOM®-2 channel 1/5/9/13 via the MON-8 message ’AST’ at bit positions S0, S1. Connect to either VDD or VSS if not used. 23, 21 ST20 ST21 I Status Pin of Line Port 2 change of status is passed to IOM®-2 channel 2/6/10/14 via the MON-8 message ’AST’ at bit positions S0, S1. Connect to either VDD or VSS if not used. 19, 18 ST30 ST31 I Status Pin of Line Port3 change of status is passed to IOM®-2 channel 3/7/11/15 via the MON-8 message ’AST’ at bit positions S0, S1. Connect to either VDD or VSS if not used. 29 CLS0 O 120kHz Transmit Baud Clock of Port 0 can be used for monitoring and test purposes 20 CLS1 O 120kHz Transmit Baud Clock of Port 1 can be used for monitoring and test purposes 52 CLS2 O 120kHz Transmit Baud Clock of Port 2 can be used for monitoring and test purposes Test Pins Preliminary Data Sheet 2-6 06.99 PEF 24901 Pin Descriptions Table 2-1 Pin No. Pin Definitions and Functions Symbol Input (I) Output (O) Function 61 CLS3 O 120kHz Transmit Baud Clock of Port 3 can be used for monitoring and test purposes 49 TP1 I Test Pin 1 Not available to user. Connect to GND. JTAG Boundary Scan 64 TCK I Test Clock 1 TMS I (PU) Test Mode Select internal pullup resistor (160kΩ) 2 TDI I (PU) Test Data Input internal pullup resistor (160kΩ) 3 TDO O Test Data Output 63 TRST I (PU) JTAG Boundary Scan Disable resets the TAP controller state machine (asynchronous reset), active low internal pullup (160kΩ) ’1’= reset inactive ’0’= reset active Power Supply Pins 6, 22, 38, 54 VDD 3.3V ±0.3V supply voltage 9, 25, 41, 57 VSS 0V ground OD: PuP: PD: PU: Open Drain Push Pull Internal Pull Down Internal Pull Up Preliminary Data Sheet 2-7 06.99 PEF 24901 Pin Descriptions 2.3 Pinning Changes from DFE-T V1.2 to DFE-T V2.1 • Table 2-2 Pin No. Pinning Changes V2.1 V1.2 Comment 16 MTO N.C. activates the Monitor Time-Out procedure as provided in IEC-Q 32 PUP SLOT2 additional push-pull mode eases interface adaption, SLOT2 was not used in V1.2 49 TP1 TP3 renamed 53 N.C. LT as in V1.x LT-RP mode is neither supported in V2.1 56 SSP TSP dedicated pin for ’Send Single Pulses’ test mode 62 DT TP dedicated pin for ’Data Through’ test mode 63 TRST TP1 power-on-reset is replaced by a dedicated reset line Preliminary Data Sheet 2-8 06.99 PEF 24901 Functional Description 3 Functional Description 3.1 Functional Overview A functional overview of the DFE-T V2.1 is given in Figure 3-1. Besides the signal processing and frame formatting blocks the PEF 24901 features an on-chip activation/ deactivation controller and programmable general purpose I/O pins for the control of test relays and power feeding circuits. An application specific DSP core services all four lines and cuts chip size to a minimum. $)( ')(79 /,8 83URWRFRO3URFHVVLQJ8QLW '63 0 '$& [8 GUL E\ + 8 %7 6FUDPEOHU (QFRGHU 6,8 8 )UDPLQJ )UDPLQJ ; (FKR &DQFHOOHU 6\VWHP 6\QF:RUG ,20 ,QWHUIDFH SD $'& $ 3'0 )LOWHU * 0 (TXDOL]HU & 8QLW 8 ; %7 'H 8'H 'HFRGHU 6FUDPEOHU )UDPLQJ 7LPLQJ /HYHO'HWHFWLRQ 5HFRYHU\ $FWLYDWLRQ'HDFWLYDWLRQ &RQWUROOHU IRU:DNH8S %DQGJDS %LDV5HIHU &ORFN*HQHUDWLRQ 0RGH6HWWLQJ ,2&RQWURO &ORFNV 0RGH3LQV *HQHUDO 3XUSRVH,2V dataflow.vsd Figure 3-1 Data Flow Diagram (DFE-T V2.1 + AFE) Preliminary Data Sheet 3-1 06.99 PEF 24901 Functional Description 3.2 Block Diagram • 9 3RZHU6XSSO\ '63 0HPRU\ $)( &RQWUROOHU 0HPRU\ ,20 ,QWHUIDFH $)( ,QWHUIDFH ,20 '63&RUH &ORFNV &ORFN *HQHUDWLRQ 'H 6FUDPEOHU %7'H &RGLQJ -7$* /D\HU &RQWUROOHU %6&$1 0RGH3LQV 0RQLWRU &KDQQHO 3URFHVVRU ,2V 5HOD\V 3RZHU&RQWUROOHU block_ds.emf Figure 3-2 DFE-T V2.1 Block Diagram Preliminary Data Sheet 3-2 06.99 PEF 24901 Functional Description 3.3 IOM®-2 Interface The IOM®-2 interface is a four-wire serial interface providing a symmetrical full-duplex communication link to layer-1 and layer-2 backplane devices. It transports user data, control/programming and status information via dedicated time multiplexed channels. The structure used follows the 2B + 1 D-channel structure of ISDN. The ISDN-user data rate of 144 kbit/s (B1 + B2 + D) on the U-interface is transmitted transparently in both directions (U <=> IOM®) over the interface. • FSC ,20 6ODYH DCL ,20 0DVWHU DU DD DCL FSC DU DD n. Bit of Frame 1. Bit of Frame 2. Bit of Frame 3. Bit of Frame iomif.emf Figure 3-3 Clock Supply and Data Exchange between Master and Slave The Frame Sync Signal FSC is a 8 kHz signal delimiting the frames. This signal is used to determine the start of a frame. The data is clocked by a Data Clock (DCL) which operates at twice the data rate. The data clock is a square wave signal with a duty cycle ratio of typically 1:1. Incoming data is sampled on the falling edge of the DCL-clock. Data is carried over Data Upstream (DD) and Data Downstream (DU) signals. The upstream and downstream directions are always defined with respect to the exchange: Downstream refers to information flowing from the exchange to the subscriber, upstream is defined vice versa. The output line is operating either as open drain or push-pull output. Both modes are selected by signal “PUP”. In open drain mode an external pull-up resistor is required. The absence of a pull-up resistor is not automatically recognized (i.e. no push-pull detection). Preliminary Data Sheet 3-3 06.99 PEF 24901 Functional Description Within one FSC-period, 128 to 512 bit are transmitted, corresponding to DCLfrequencies ranging from 2048 kHz up to 8192 kHz. The following table shows possible operating frequencies of the IOM®-2-interface. IOM®-2 Data Rates Table 3-1 DCL Frequency [kHz] Data Rate [kBit/s] IOM®-2 Channels 2048 1024 4 3072 1536 6 4096 2048 8 6144 3072 12 8192 4096 16 3.3.1 Remarks LT Burst Mode IOM®-2 Interface Frame Structure The typical IOM®-2 line card application comprises a DCL-frequency of 4096 kHz with a nominal bit rate of 2048 kbit/s. Therefore eight channels are available, each consisting of the basic frame with a nominal data rate of 256 kbit/s. The downstream data (DD) is transferred on signal DIN, the upstream data (DU) on signal DOUT. The IOM®-2 channel assignment is programmable by pin strapping (SLOT1,0). The basic IOM®-2 frame and clocking structure consists of: channel bits B1 B2 Monitor D Command / Indicate MR MX 8 8 8 2 4 1 1 • Two 64-kbit/s channels B1 and B2 • The monitor channel for transferring maintenance information between layer-1 and layer-2 devices • Two bits for the 16-kbit/s D-channel • Four command / indication (C/I) bits for controlling of layer-1 functions (activation/ deactivation and additional control functions) by the layer-2 controller • Two bits MR and MX for handling the monitor channel Preliminary Data Sheet 3-4 06.99 PEF 24901 Functional Description • Figure 3-4 3.3.2 Multiplexed Frame Structure of the IOM®-2 Interface IOM®-2 Command/ Indicate Channel The Command/Indication (C/I) channel carries real-time control and status information between the DFE-T V2.1 and a layer-1 control device. A new C/I code must be detected in two consecutive IOM®-2 frames to be considered valid (double last look criterion). An indication is issued permanently by the DFE-T V2.1 on DOUT until a new indication needs to be forwarded. The C/I code is 4 bit wide and located at bit positions 27–30 in each time-slot. A listing and explanation of the U-transceiver C/I codes can be found on page 3-32. 3.3.3 IOM®-2 Monitor Channel The Monitor channel represents a second method of initiating and reading U-transceiver specific information. Features of the monitor channel are supplementary to the command/indicate channel. Unlike the command/indicate channel with an emphasis on status control, the monitor channel provides access to internal bits (maintenance, overhead) and test functions (local loop-backs, block error counter and self-test). Besides the known MON-8 commands two new MON classes, MON-0 and MON-12 are introduced in the DFE-T V2.1: • New MON-0 Class Like in the 2B1Q version MON-0 messages allow the user to transfer transparent Preliminary Data Sheet 3-5 06.99 PEF 24901 Functional Description messages across the U-interface. • New MON-12 Class By use of MON-12 commands the DFE-T V2.1 provides the ability to address parts of the device internal register map and thus to address functions that have been added with version 2.1. MON-12 commands are always prioritized and processed first if other Monitor commands are outstanding. See Chapter 3.3.4 for the details. This means that Monitor commands are split into three categories. Each category derives its name from the first nibble (4 bits) of the two byte long message. These are: • MON-12 • MON-0 • MON-8 (Internal Register Map) (Transparent Channel) (Local Functions) The order of the list above corresponds to the priority attributed to each category. MON12 commands are always processed first. MON-0 messages will be transmitted before MON-8 messages in case several messages are initiated simultaneously. The various MON-0 and MON-8-commands are discussed in detail in chapter "Monitor Commands" on page 5-1. Structure The structure of the Monitor channel is 8 bit wide, located at bit position 17 – 24 in every time-slot. Monitor commands/messages sent to/from the U-transceiver are always 2 bytes long. Transmission of multiple monitor bytes is specified by IOM®-2 (see next section “Handshake Procedure” for details). For handshake control in multiple byte transfers, bit 31, monitor read “MR”, and bit 32, monitor transmit “MX”, of every time-slot are used. Verification A double last-look criterion is implemented for the monitor channel. If the monitor message that was received consecutively after a change has been detected is not identical to the message that was received before the message will be aborted. Handshake Procedure IOM®-2 provides a sophisticated handshake procedure for the transfer of monitor messages. For handshake control two bits, MX and MR, are assigned to each IOM®-2 frame (on DIN and DOUT). The monitor transmit bit (MX) indicates when a new byte has been issued in the monitor channel (active low). The transmitter postpones transmitting the next information until the correct reception has been confirmed. A correct reception will be confirmed by setting the monitor read bit (MR) to low. Preliminary Data Sheet 3-6 06.99 PEF 24901 Functional Description The monitor channel is full duplex and operates on a pseudo-asynchronous base, i.e. while data transfer on the bus takes place synchronized to frame synchronization, the flow of monitor data is controlled by the MR- and MX-bits. Monitor data will be transmitted repeatedly until its reception is acknowledged. Figure 3-5 illustrates a monitor transfer at maximum speed. The transmission of a 2-byte monitor command followed by a 2-byte response requires a minimum of 15 IOM ®-2 frames (reception 7 frames + transmission 8 frames = 1.875 ms). In case the controller is able to confirm the receipt of first response byte in the frame immediately following the MX-transition on DOUT from high to low (i.e. in frame No. 9), 1 byte may be saved (7 frames + 7 frames). Transmission and reception of monitor messages can be performed simultaneously by the U-transceiver. In the procedure depicted in Figure 3-5 it would be possible for the Utransceiver to transmit monitor data in frames 1–5 (excluding EOM-indication) and receive monitor data from frame 8 onwards. M 1/2: R 1/2: Monitor message 1. and 2. byte Monitor response 1. and 2. byte • Figure 3-5 Handshake Protocol with a 2-Byte Monitor Message/Response Idle State After the bits MR and MX have been held inactive (i.e. high) for two or more successive IOM®-frames, the channel is considered idle in this direction. Preliminary Data Sheet 3-7 06.99 PEF 24901 Functional Description Standard Transmission Procedure 1. The first byte of monitor data is placed by the external controller on the DIN line of the DFE-T V2.1 and MX is activated (low; frame No. 1). 2. The DFE-T V2.1 reads the data of the monitor channel and acknowledges by setting the MR-bit of DOUT active if the transmitted bytes are identical in two received frames (frame No. 2 because data are already read and compared while the MX-bit is not activated). 3. The second byte of monitor data is placed by the controller on DIN and the MX-bit is set inactive for one single IOM®-frame. This is performed at a time convenient to the controller. 4. The DFE-T V2.1 reads the new data byte in the monitor channel after the rising edge of MX has been detected. In the frame immediately following the MX-transition activeto-inactive, the MR-bit of DOUT is set inactive. The MR-transition inactive-to-active exactly one IOM®-frame later is regarded as acknowledgment by the external controller (frame No. 4–5). The acknowledgment by the DFE-T V2.1 will always be sent two IOM®-frames after the activation of a new data byte. 5. After both monitor data bytes have been transferred to the DFE-T V2.1, the controller transmits “End Of Message” (EOM) by setting the MX-bit inactive for two or more IOM®-frames (frame No. 5–6). 6. In the frame following the transition of the MX-bit from active to inactive, the DFE-T V2.1 sets the MR-bit inactive (as was the case in step 4). As it detects EOM, it keeps the MR-bit inactive (frame No. 6). The transmission of the monitor command by the controller is complete. 7. If the DFE-T V2.1 is requested to return an answer it will commence with the response as soon as possible. In case the “monitor time out” function is enabled it may have to postpone the answer until after the internal reset (see section Monitor Procedure Time-out for details). Figure 3-5 illustrates the case where the response can be sent immediately. The procedure for the response is similar to that described in points 1 – 6 except for the transmission direction. It is assumed that the controller does not latch monitor data. For this reason one additional frame will be required for acknowledgment. Transmission of the 2nd monitor byte will be started by the DFE-T V2.1 in the frame immediately following the acknowledgment of the first byte. The U-transceiver does not delay the monitor transfer. Preliminary Data Sheet 3-8 06.99 PEF 24901 Functional Description Transmission Abortion If no EOM is detected after the first two monitor bytes, or received bytes are not identical in the first two received frames, transmission will be aborted through receiver by setting the MR-bit inactive for two or more IOM®-2-frames. The controller reacts with EOM. This situation is illustrated in Figure 3-6. Figure 3-6 Abortion of Monitor Channel Transmission MONITOR Procedure Time-Out (MTO) The DFE-T V2.1 offers an internal reset (monitor procedure “Time-out”) for the monitor routine. This reset function transfers the monitor channel into the idle state (MR and MX set to high) thereby resolving possible lock-up situations. It therefore is to be used in all systems where no microprocessor is capable of detecting and solving hang-up situations in the monitor procedure. The reset procedure is started in 12 ms intervals. In order to avoid the loss of transmitted or received data the DFE-T V2.1 commences a monitor transfer only when enough time is available before the next reset will be initiated. If this is not the case transmission is postponed until after the reset. Once a message has been issued on IOM®-2, its transfer needs to be completed before the next reset. If this is not accomplished, the message can be lost without notice. For this reason the control software should be able to transfer monitor messages as quickly as possible. Signal “MTO” set to ’1’ enables the MTO-function, signal “MTO” set to ’0’ disables it. Preliminary Data Sheet 3-9 06.99 PEF 24901 Functional Description With the MTO-function enabled, the monitor routine is reset every 12ms. Every reset sets both handshake bits of DOUT to the idle state (MR and MX set to high) thereby preventing lock-up situations. The MX and MR are reset synchronously. With the MTO-function disabled no internal resets are performed. In this case an external controller must prevent lock-up situations in the monitor channel. • PV PV PV 1R6WDUW PV RI1HZ 7UDQVIHU 7UDQVIHU +:5HVHW [,20 0725HVHW 0725HVHW [,20 )UDPHV Figure 3-7 1R6WDUW RI1HZ )UDPHV mto.vsd Monitor Access with MTO Enabled Note that there is no relationship of the reset timing to the U-frame, since no superframe exists as for the 2B1Q line code. DFE-T V2.1 operates as Transmitter with MTO Enabled The transmitter is reset in 12ms intervals as shown in the figure above. In case the transmission of a monitor message has not been completed before the transmitter is reset, the complete message will be lost. A message that has been lost due to the interruption of a monitor reset will not be retransmitted. To prevent this loss of monitor messages, the DFE-T V2.1 will only commence a monitor transmission if more than 16 IOM®-2 frames will be available for transmission before the next reset occurs. To ensure correct transmission the receiver must not delay the receive procedure for more than the following value: 2-byte transmission: max. speed = 8 frames => max. controller (receive) delay = 8 frames DFE-T V2.1 operates as Receiver with MTO Enabled The receiver is reset in 12ms intervals as shown in the figure above. In case the reception of a monitor message has not been completed before the receiver is reset, the complete message can be lost because the generation of an abort request can not be guaranteed. Preliminary Data Sheet 3-10 06.99 PEF 24901 Functional Description To prevent this loss of monitor messages the DFE-T V2.1 will only commence a monitor reception (i.e. acknowledge the 1st received byte) if more than 16 IOM®-2 frames will be available for reception before the next reset occurs. Reception thus does not start if there is less than 2ms (=16x IOM®-2 frames) time left. To ensure correct reception, the transmitter must not delay the receive procedure for more than the following value: 2-byte reception: max. speed = 7 frames => max. controller (transmit) delay = 9 frames 3.3.4 MON-12 Protocol MON-12 commands feature direct access to the device internal register map via the Monitor channel. This means that although the DFE-T V2.1 features no microcontroller interface internal register functions can be directly addressed by use of MON-12 commands. A MON-12 read request command must be first acknowledged by the DFE-T V2.1 before a subsequent read request can be triggered. In case of a failure condition the DFE-T V2.1 repeats the last outstanding MON-12 answer. MON-12 commands are prioritized over the other MON classes. If U-interface functions are addressed then the value of register LP_SEL determines the register bank of the channel that is referred to. As a result the desired line port number must be programmed first in register LP_SEL before any U-interface register can be accessed. For this reason MON-12 commands may not be issued simultaneously on different IOM®-2 channels, but must be issued consecutively if they address U-interface functions. For registers that are addressable by MON-12 commands please refer to the register map in Chapter 6.2 on page 6-4. MON-12 commands are of the following format: • A MON-12 write command comprises 3 bytes, the first byte contains the MON-12 header, the second byte the register address, the third byte the register value. 1. Byte 1100 w=1 0 0 0 MON-12 2. Byte AAAA 3. Byte AAAA Register Address DDDD DDDD Register Value • A MON-12 read request command comprises 2 bytes, the first byte contains the MON-12 header, the second byte the register address of the data that is requested. Preliminary Data Sheet 3-11 06.99 PEF 24901 Functional Description 1. Byte 1100 r=0 0 0 0 MON-12 2. Byte AAAA AAAA Register Address • After a read request the DFE-T V2.1 reacts with a 3-byte message. A MON-12 read answer comprises 3 bytes, the first byte contains the MON-12 header, the second byte the register address, the third byte the register value. 1. Byte 1100 r=0 0 0 0 MON-12 Preliminary Data Sheet 2. Byte AAAA 3. Byte AAAA Register Address 3-12 DDDD DDDD Register Value 06.99 PEF 24901 Functional Description 3.4 Interface to the Analog Front End The interface to the PEF 24902 AFE V2.1 is a 6-wire interface (see Figure 3-8). On SDX and SDR transmit and receive data is exchanged as well as control information for the start-up procedure by means of time division multiplexing. On SDX transmit data, power-up/down information, range function and analog loopback requests are transferred. On SDR level status information is received for all line ports. On PDM0..PDM3 the ADC output data from the AFE is transferred to the DFE-T V2.1. The timing of all signals is based on the 15.36MHz master clock which is provided by the AFE. • 6'; 6'5 $)(9 3() 3'0 3'0 3'0 3'0 ')(79 3() dfe_afe_if.emf Figure 3-8 Interface to the Analog Front End The 128 available bits (related to the 15.36 MHz clock) on SDR/SDX during a 120 kHz period are divided into 9 time-slots. 8 time-slots are 13 bits long and are reserved for data transmission, 1 time-slot is 24 bits long and used for synchronization purposes. The DFE-T V2.1 uses four of them, time-slots no. 1, 3, 5 and 7. Table 3-2 shows the assignment of the IOM®-2 channels to the time-slots on SDX/SDR and the assignment of the time-slots to the line ports. Preliminary Data Sheet 3-13 06.99 PEF 24901 Functional Description • Assignments of IOM ® Channels to Time-Slots No. on SDX/SDR and Line Ports No. Table 3-2 IOM®-2 Channel No. Time-Slot No. Line Port No. 0/4/8/12 1 0 1/5/9/13 3 1 2/6/10/14 5 2 3/7/11/15 7 3 The status on SDR is synchronized to SDX. Each time-slot on SDR carries the corresponding LD bit during the last 12 bits of the slot. • Figure 3-9 Frame Structure on SDX/SDR The data on SDX is interpreted as follows: NOP: The no-operation-bit is set to ’0’ if none of the control bits (PDOW, RANGE and LOOP) shall be changed. The values of the control bits of the assigned line port is latched. The states of the control bits on SDX are ignored, they should be set to ’0’ to reduce any digital cross-talk to the analog signals. The NOPQ bit is set to ’1’ if at least one of the control bits shall be changed. In this case all control bits are transmitted with their current values. PDOW: If the PDOW bit is set to ’1’, the assigned line port is switched to power-down. Otherwise it is switched to power-up. RANGE: RANGE = ’1’ activates the range function, otherwise the range function is deactivated. "Range function activated" refers to high input levels. Preliminary Data Sheet 3-14 06.99 PEF 24901 Functional Description LOOP: LOOP = ’1’ activates the loop function, i.e. the loop is closed. Otherwise the line port is in normal operation. SY: First bit of the time-slots with transmission data. For synchronization and bit allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR. "0": Reserved bit. Reserved bits are currently not defined and shall be set to ’0’. Some of these bits may be used for test purposes or can be assigned a function in later versions. The 4B3T data is coded with the bits TD1, TD0: • Table 3-3 Coding of the 4B3T Data Pulse (AOUT/BOUT) 4B3T Data Pulse TD1 TD0 0 0 0 +1 1 0 –1 1 1 The data on SDR is interpreted as follows: LD: The level detect information is communicated to the DFE-T V2.1 on SDR. If the signal amplitude reaches the wake-up level, the LD bit toggles with the signal frequency. If the input signal at the U-interface is below the wake-up level, the LD bit is tied to either low or high. SY: First bit of the time-slots with transmission data. For synchronization and bit allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR. Preliminary Data Sheet 3-15 06.99 PEF 24901 Functional Description 3.5 General Purpose I/Os The DFE-T V2.1 features 6 general purpose I/O pins per line port. This way transparent control of test relays and power feeding circuits is possible via the IOM®-2 Monitor channel. Four of the six pins are outputs, two are inputs. Setting Relay Driver Pins Four relay driver output pins Dij (where i = 0, 1, 2, 3 denotes the line port no. and j = A, B, C, D specifies the pin) are available per line port. The logic state of the four relay driver outputs which are assigned to the same line port can be set by a single MON-8 command, called ’SETD’. The value is latched as long as no other SETD command with different relay driver settings is received. The state of the relay driver pins is not affected by any software reset (C/I= RES). The state of all relay driver pins after hardware reset is „low“. Reading Status Pins Each line port owns two status pins ST ij (where i = 0,1, 2, 3 denotes the line port no. and j = 0, 1 specifies the pin) whose logical value is reported in the associated Monitor channel. Any signal change at one of the status pins ST1..4 causes automatically the issue of a two-byte MON-8 message ’AST’ whose two least significant bits reflect the status of pin STij. However, this automatic mechanism is only enabled again, if the previous status pin message has been transferred and acknowledged correctly according to the Monitor channel handshake protocol. It takes The DFE-Q V1.2 at least 8x IOM®-2 frames (1ms) to transmit the 2-byte MON-8 message. Thus, repeated changes within periods shorter than 8x IOM®-2 frames will overwrite the status pin register information. For this reason only the value of the last recent status change will be reported. Note that the MON-8 transfer time depends also on the reaction time (acknowledge by MR-bit) of the DFE-Q counterpart. Besides this automatic report the DFE-T V2.1 will issue the status pin Monitor message ’AST’ upon the MON-8 request ’RST’ . The STij pins have to be tied to either VDD or GND, if they are not used. Preliminary Data Sheet 3-16 06.99 PEF 24901 Functional Description 3.6 U-Transceiver Functions The 4B3T U-interface performs full duplex data transmission and reception at the Ureference point according to ETSI ETR 080 and FTZ 1TR 220. It applies the 4B3T block code together with adaptive echo cancelling and equalization. Transmission performance shall be such that it meets all ETSI and FTZ test loops with margin. The U-interface is designed for data transmission on twisted pair wires in local telephone loops with ISDN basic rate access and a user bit rate of 144 kbit/s. The following information is transmitted over the twisted pair: • Bidirectional: – B1, B2, D data channels – 120 kHz Symbol clock, 160 kbit/s Transmission rate – 1 kHz Frame and 40 kHz block clock – Activation • From LT to NT side: – Power feeding – Deactivation – Remote control of test loops • From NT to LT side: – Indication of monitored code violations On the U-interface transmission ranges 4.2 km on wires of 0.4 mm diameter and 8 km on 0.6 mm wires are achieved without additional signal regeneration in the loop. The transmission ranges can be doubled by inserting a repeater for signal regeneration. 3.6.1 4B3T Frame Structure 1 ms frames are transmitted across the U-interface, each consisting of: • 108 symbols: 144 bit scrambled and coded B1 + B2 + D data • 11 symbols: Barker code for both symbol and frame synchronization (not scrambled) • 1 symbol: Ternary maintenance symbol (not scrambled) The 108 user data symbols are split into four equally structured groups. Each group (27 ternary symbols, resp. 36 bits) contains the user data of two IOM®-2 frames in the same order (8B + 8B + 2D + 8B + 8B + 2D). Different syncwords are used for each direction: • Downstream from LT to NT+ + + – – – + – – + – • Upstream from NT to LT– + – – + – – – + + + On the NT side the transmitted Barker code begins 60 symbols after the received Barker code and vice versa. After successful synchronization, resynchronization will occur if the syncword is not detected at the expected position in 64 consecutive frames. Preliminary Data Sheet 3-17 06.99 PEF 24901 Functional Description The U-transceiver is synchronized, if it detects the syncword four times consecutively within a period of 1 ms. • Table 3-4 1 Frame Structure for Downstream Transmission LT to NT 2 D1 D1 13 14 D1/2 25 D1/2 26 D2 37 D2 38 D3 49 D3 50 D4 61 D4 62 D5 73 D5 74 D6 85 D6 86 0 97 3 D7 98 D7/8 4 D1 15 D1/2 27 D2 39 D3 51 D4 63 D5 75 D6 87 D7 99 5 D1 16 D2 28 D3 40 D3/4 52 D4 64 D5 76 D6 88 6 D1 17 D2 29 D3 41 D3/4 53 D4 65 D5 77 D6 89 7 D1 D1 18 19 D2 D2 30 31 D3 D3 42 43 D3/4 54 D4 55 D4 66 D5 78 D5 67 D5/6 79 D6 90 8 D6 91 9 D1 20 D2 32 D3 44 D4 56 D5 68 D5/6 80 D6 92 10 D1 21 D2 33 D3 45 D4 57 D5 69 D5/6 81 D6 93 D1 22 D2 34 D3 46 D4 58 D5 70 D6 82 D7 94 11 D1 23 D2 35 D3 47 D4 59 D5 71 D6 83 D7 95 D7/8 12 D1 24 D2 36 D3 48 D4 60 D5 72 D6 84 D7 96 D7 D7 D7 D7 D7 D7 D7 D7/8 100 101 102 103 104 105 106 107 108 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 109 110 111 112 113 114 115 116 117 118 119 120 D8 ± ± ± ± ± ± D1 ... D8 M +, – Ternary 2B + D data of IOM-2 frames 1 ... 8 Maintenance symbol Syncword Preliminary Data Sheet 3-18 06.99 PEF 24901 Functional Description • Table 3-5 1 Frame Structure for Upstream Transmission NT to LT 2 U1 13 U1 14 U1/2 25 U1/2 26 0 37 U2 38 U3 49 U3 50 ± U4 61 62 U4 73 U4 74 U5 85 U5 86 U6 97 3 U6 98 4 U1 15 U1/2 27 U2 39 U3 51 5 U1 16 U2 28 U2 40 U3 52 63 U4 75 U5 87 U6 99 ± 64 U4 76 U5 88 6 U1 17 U2 29 U3 41 U3/4 53 ± 65 U4 77 U5 89 7 U1 18 U2 30 U3 42 U3/4 54 8 U1 19 U2 31 U3 43 U3/4 55 66 U4 78 U5 90 ± 67 U5 79 U5/6 91 9 U1 20 U2 32 U3 44 U4 56 ± 68 U5 80 U5/6 92 10 U1 21 U2 33 U3 45 U4 57 ± 69 U5 81 U5/6 93 U1 22 U2 34 U3 46 U4 58 70 U5 82 U6 94 11 U1 23 U2 35 U3 47 U4 59 71 U5 83 U6 95 12 U1 24 U2 36 U3 48 U4 60 72 U5 84 U6 96 U6 U6 U6 U6 U6 U6 U7 U7 U7 100 101 102 103 104 105 106 107 108 U7 U7 U7 U7 U7 U7 U7 U7 U7 109 110 111 112 113 114 115 116 117 118 119 120 U8 U8 U8 U8 U8 U8 U8 U8 U8 U8 U8 U8 U1 ... U8 Ternary 2B + D data of IOM-2 frames 1... 8 M Maintenance symbol +, - Syncword Preliminary Data Sheet 3-19 U7/8 U7/8 U7/8 06.99 PEF 24901 Functional Description 3.6.2 Maintenance Channel The 4B3T frame structure provides a 1kbit/s M(aintenance)-channel for the transfer of remote loopback commands, error indications and transparent messages. Loopback Commands The LT station uses the M-channel to request remote loopbacks. Loopback commands are coded with a series of ’0’ and ’+’ symbols. • A continuous series of ’+0’ requests for loopback 1A activation in the repeater • A continuous series of ’+’ requests for loopback 2 activation in the NT • A continuous series of ’0’ requests for deactivation of any loopback The NT station reacts as soon as the pattern has been detected in 8 consecutive symbols. Error Indications The NT U-transceiver reports line code violations via the M-channel to the exchange by setting one M-Bit to ’+’ polarity. Transparent Messages In either direction it is possible to transmit transparent messages via the M-channel. Transparent messages have priority and may override loopback commands and line code violations. So the user has to make sure that during an activation the NT is able to recognize a loopback command and that there is no conflict by simultaneous use of the transparent channel. ’-’ polarity represents a logic ’0’, ’+’ and ’0’ polarity represents a logic ’1’. The interpretation of the M-Bit symbols depending on the direction (up-, downstream) is summarized below: • LT -> NT Loopback Commands the symbol sequence given below shall be received at least 8 times before the loopback command is approved valid ’+0..’= ’++..’= ’00..’= loopback 1A activation (in regenerator) loopback 2 activation (in NT) loopback deactivation Transparent Channel Messages ’0’= ’+’= ’-’= logic ’1’ and no loop request logic ’1’ and loop request logic ’0’ Preliminary Data Sheet 3-20 06.99 PEF 24901 Functional Description NT -> LT Transmission Error Detection and Report ’+’= ’0’= code violation detected by the NT idle code Transparent Channel Message ’0’= ’+’= ’-’= logic ’1’ and no code violation logic ’1’ and a detected code violation logic ’0’ Preliminary Data Sheet 3-21 06.99 PEF 24901 Functional Description 3.6.3 Exchanging Transparent Messages The 4B3T U-transceiver provides via its register pair MRD and MWR direct access to the transparent channel. Access to the MRD and MWR registers is provided in turn via the Monitor channel of the IOM®-2 interface. Therefore two MON-0 messages were defined, MON-0 ’MRD’ and MON-0 ’MWR’. Register MRD contains the last eight received M-bits, register MWR stores the M-bit data that is serialized and sent with the next eight outgoing U-frames (see Figure 3-10). • %ORFN(UURU &RXQWHU 8 8)UDPH1 8)UDPH 18)UDPH 0 ,20 1 18)UDPH 18)UDPH 18)UDPH 18)UDPH 18)UDPH 0 0 0 0 0 0 0 0 0:5 0 0 0 0 0 0 0 0 05' 2302'( 075$16 0RQLWRU&KDQQHO &RQWUROOHU 8)UDPH 0 1 8)UDPH1 0210HVVDJH([FKDQJH 6WDWH 0DFKLQH &,&RGH Mbit_acs.emf Figure 3-10 M-Bit Access via MRD, MWR Register Pair Transparent channel mode is enabled by bit MTRANS set to ’1’ in the OPMODE register using the MON-12 protocol. As soon as OPMODE.MTRANS has been set to ’1’ the Utransceiver starts with the next incoming U-frame to shift M-bit data into the MRD register. Simultaneously - starting with the MSB value- the content of the MWR register is inserted at the M-bit positions of the next outgoing U-frame. In case the MWR register was not preloaded before, zero or plus polarity is sent by default. The same applies if the MWR register is not reloaded in time again. Preliminary Data Sheet 3-22 06.99 PEF 24901 Functional Description Once eight M-bits have been stacked by MRD (every 8ms) or the content of MWR has been shifted out, a MON-0 message is sent. That is every 8ms an autonomous MON-0 message will be issued which contains the last eight received M-bit data. The periodic transmission of MON-0 messages allows to align MON-0 write commands in the transmit direction. See Figure 3-11 for the access timing (MON TX= Monitor channel transmit register, MON RX= Monitor channel receive register). • 8LQWHUIDFH 5; 87UDQVFHLYHU 7; 0217; ,20 /D\HU 0215; :5 0 021 [ 0 0:5 [ [ [ D W D ' 0 (QDEOH 0 0 0 ' 5 0 D W D ' 0 0 0215; 2302'( 1ms 16 75$ '(0 302 2 021 0215; 05' 0:5 :5 0 021 0215; 05' 0 0:5 5 : 0 05' 0 0 0 ' 5 0 0215; 021 0 5' 0217; 0:5 0215; 05' 0 :5 0 021 0:5 0215; : 0 0 0 D W D ' 0 0 0217; 0:5 05' 0215; 0217; 0:5 0215; 05' 0 :5 0 021 0:5 0215; 5 0 : 0 05' D W D ' ' 5 0 0 0 0 D W D ' 0 5 0 : 0 021 0 5' 8ms 05' 0 ' 5 0 0 05' 5 D W D ' D W D ' 0 8ms D W D ' 0217; 0:5 0217; 0:5 0215; 021 0 5' 0217; 0215; MBit_timg.emf Figure 3-11 M-Bit Access Timing Preliminary Data Sheet 3-23 06.99 PEF 24901 Functional Description 3.6.4 Coding from Binary to Ternary Data Each 4 bit block of binary data is encoded into 3 ternary symbols using the MMS 43 block code according to Table 3-6. The number of the next column to be used, is given at the right hand side of each block. The left hand signal elements in the table (both ternary and binary) are transmitted first. • Table 3-6 MMS 43 Coding Table t→ 6 6 6 6 t→ t→ t→ t→ 0 0 0 1 0 – + 1 0 – + 2 0 – + 3 0 – + 4 0 1 1 1 – 0 + 1 – 0 + 2 – 0 + 3 – 0 + 4 0 1 0 0 – + 0 1 – + 0 2 – + 0 3 – + 0 4 0 0 1 0 + – 0 1 + – 0 2 + – 0 3 + – 0 4 1 0 1 1 + 0 – 1 + 0 – 2 + 0 – 3 + 0 – 4 1 1 1 0 0 + – 1 0 + – 2 0 + – 3 0 + – 4 1 0 0 1 + – + 2 + – + 3 + – + 4 – – – 1 0 0 1 1 0 0 + 2 0 0 + 3 0 0 + 4 – – 0 2 1 1 0 1 0 + 0 2 0 + 0 3 0 + 0 4 – 0 – 2 1 0 0 0 + 0 0 2 + 0 0 3 + 0 0 4 0 – – 2 0 1 1 0 – + + 2 – + + 3 – – + 2 – – + 3 1 0 1 0 + + – 2 + + – 3 + – – 2 + – – 3 1 1 1 1 + + 0 3 0 0 – 1 0 0 – 2 0 0 – 3 0 0 0 0 + 0 + 3 0 – 0 1 0 – 0 2 0 – 0 3 0 1 0 1 0 + + 3 – 0 0 1 – 0 0 2 – 0 0 3 1 1 0 0 + + + 4 – + – 1 – + – 2 – + – 3 Preliminary Data Sheet 3-24 06.99 PEF 24901 Functional Description 3.6.5 Decoding from Ternary to Binary Data Decoding is done in the reverse manner of coding. The received blocks of 3 ternary symbols are converted into blocks of 4 bits. The decoding algorithm is given in Table 3-7. As in the encoding table the left hand symbol of each block (both binary and ternary) is the first bit and the right hand is the last. If a ternary block "0 0 0" is received, it is decoded to binary "0 0 0 0". This pattern usually occurs only during deactivation. Table 3-7 4B3T Decoding Table 7HUQDU\%ORFN 0 0 0, 0 0 0 0 0 – + 0 0 0 1 + – 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 +, + 0 +, %LQDU\%ORFN 0 – 0 – – 0 – + 0 0 + +, – 0 0 0 1 0 1 – + +, – – + 0 1 1 0 0 1 1 1 – 0 + + 0 0, 0 – – 1 0 0 0 + – +, – – – 1 0 0 1 + + –, + – – 1 0 1 0 1 0 1 1 + 0 – + + +, – + – 1 1 0 0 0 + 0, – 0 – 1 1 0 1 1 1 1 0 1 1 1 1 0 + – + + 0, 3.6.6 0 0 – Monitoring of Code Violations The running digital sum monitor (RDSM) computes the running digital sum from the received ternary symbols by adding the polarity of the received user data (+ 1, 0, –1). At the end of each block, the running digital sum is supposed to reflect the number of the next column in Table 3-6 "MMS 43 Coding Table" on page 3-24. Preliminary Data Sheet 3-25 06.99 PEF 24901 Functional Description A code violation has occurred if the running digital sum is less than one or more than four at the end of a ternary block, or if the ternary block 0 0 0 (three user symbols with zero polarity) is found in the received data. If at the end of a ternary block no error was found, the running digital sum retains its current value. If the counter value is greater than 4, it is set to 3 at the beginning of the next ternary block, if its value is 0 or less, it is set to one. So after a code violation has been detected, the RDSM synchronizes itself within a period depending on the received data pattern. Note there are some transmission errors which do not cause a code violation. 3.6.7 Scrambler / Descrambler Scrambler The binary transmit data from the IOM®-2 interface is scrambled with a polynomial of 23 bits, before it is sent to the 4B3T coder. The scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are transmitted. – The scrambler polynomial in LT mode and NT mode with the analog loop closed is: z – 23 +z –5 +1 – The scrambler polynomial in NT mode with open analog loop is: z – 23 +z – 18 +1 Descrambler The received data (after decoding from ternary to binary) is multiplied with a polynomial of 23 bits in order to recover the original data before it is forwarded to the IOM®-2 interface. The descrambler itself is synchronized after 23 symbols. – The descrambler polynomial in LT mode with open analog loop is: z – 23 +z – 18 +1 – The descrambler polynomial in NT mode or in LT with the analog loop closed is: z Preliminary Data Sheet – 23 +z –5 +1 3-26 06.99 PEF 24901 Functional Description 3.6.8 4B3T Signal Elements For control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by TS 102 080 and FTZ 1 TR 220. Encoding Scheme The table below describes the characteristics of the defined 4B3T signal elements. • Table 3-8 Coding of the 4B3T Signal Elements 8SVWUHDPIURP17WR/7 'RZQVWUHDPIURP/7WR17 U1W: 16 times ternary + + + + + + + + – – – – – – – – A tone of: Frequency: 7.5 kHz Period: 2.13 ms U2W 16 times ternary + + + + + + + + – – – – – – – – A tone of: Frequency: 7.5 kHz Period: 2.13 ms U1A: Binary continuous "0" before scrambling. No frame, ternary "0" instead of Barker code U2A: Binary continuous "0" before scrambling. No frame, ternary "0" instead of Barker code U1: Binary continuous "0" before scrambling. Frame (Transmitting Barker code) U2: Binary continuous "0" before scrambling. Frame (Transmitting Barker code) U3: Binary continuous "1" before scrambling. Frame (Transmitting Barker code) U4H: Binary continuous "1" before scrambling with duration of 1 ms. Frame (Transmitting Barker code) U5: Binary data from the digital interface. Frame (Transmitting Barker code) U4: Binary data from the digital interface. Frame (Transmitting Barker code) U0: Ternary continuous "0" No frame, no signal level U0: Ternary continuous "0" No frame, no signal level Preliminary Data Sheet 3-27 06.99 PEF 24901 Functional Description Detection of U0, U1, U2, U3 and U4H • The DFE-T V2.1 detects an U1 or U3 signal element if the continuous binary data is found on the descrambler output after 8 subsequent U-frames. Thus these signal elements are detected valid after 8 to 9 ms. • U4H is recognized if the NT finds 16 subsequent binary 1s in the data stream. • U0 is recognized if the LT finds one complete frame with continuous zero level. The significance of the U0 signal element is given in Table 3-9. Significance of the 4B3T Signal Elements Table 3-9 lists the defined 4B3T signal elements that are exchanged across the Ureference point in the course of an activation or deactivation process. • Table 3-9 4B3T Signal Elements U0 No signal or deactivation signal that is used in both directions. Downstream, it requests the NT to deactivate. Upstream, the NT acknowledges by U0 that it is deactivated. U1W Awake or awake acknowledge signal XSVWUHDP (7.5kHz) used in the awake procedure of the U-interface. U2W Awake or awake acknowledge signal GRZQVWUHDP (7.5kHz) used in the awake procedure of the U-interface. U2 The LT sends U2 to enable the own echo canceller to adapt the coefficients. By the Barker code the NT at the other end is enabled to synchronize. The detection of U2 is used by the NT as a criterion for synchronization. The M-channel on U may be used to transfer loop commands. U1A U1A is similar to U1 but without framing information. While the NT synchronizes on the received signal, it sends out U1A to enable its echo canceller to adapt its coefficients, but sends no Barker code to prevent the LT from synchronizing on the still asynchronous signal. Due to proceeding synchronization, the U-frame may jump from time to time. U1A can not be detected by the far-end LT. Preliminary Data Sheet 3-28 06.99 PEF 24901 Functional Description Table 3-9 U1 4B3T Signal Elements When synchronized, the NT sends the Barker code and the LT may synchronize itself. U1 indicates additionally that a terminal equipment has not yet activated. Upon receiving U1 the LT indicates the synchronized state by C/I ’UAI’ to layer-2. Usually during activation, no U1 signal is detected in the LT because the TE is activated first and U1 changes to U3 before being detected. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. U3 U3 indicates that the whole link to the TE is synchronous in both directions. On detecting U3 the LT requests the NT by U4H to establish a fully transparent connection. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. U4H U4H requires the NT to go to the ’Transparent’ state. On detecting U4H the NT stops sending signal U3 and informs the S-transceiver or a layer-2 device via the IOM®-2 interface. The M-channel on U may be used to transfer loop commands and 1 kbit/s transparent data. U4 U4 transports operational data on B and D channels. The M-channel on U may be used to transfer loop commands and 1 kbit/s transparent data. U5 U4 transports operational data on B and D channels. The M-channel on U may be used to transfer code error indications and 1 kbit/s transparent data. SP The DFE-T V2.1 sends periodically single pulses spaced by 1 ms on the U-interface. The test mode can be used for pulse mask measurements. Preliminary Data Sheet 3-29 06.99 PEF 24901 Functional Description 3.6.9 Awake Protocol For the awake process two signals are defined ’U1W’ and ’U2W’. Depending on the call direction (up-, downstream) U1W and U2W are interpreted as awake or acknowledge signals (see figures below). • Figure 3-12 Awake Procedure initiated by the LT • 6 ms 7 ms LT INFO U2W INFO U2(A) 2.133 ms 13 ms NT INFO U1W INFO U1A ITD06386 2.133 ms Figure 3-13 Awake Procedure initiated by the NT Preliminary Data Sheet 3-30 06.99 PEF 24901 Functional Description Acting as Calling Station After sending the awake signal, the awaking device waits for the acknowledge. After 12 ms the awake signal is repeated, if no acknowledge has been recognized. If an acknowledge signal has been recognized, the DFE-T V2.1 waits for its possible repetition (in case of previous coincidence of two awake signals). If no repetition was detected, the DFE-T V2.1 starts transmitting U2 with a delay of 7 ms. If such a repetition is detected, the DFE-T V2.1 interprets it as an awake signal and behaves like a device awoken by the far-end. Acknowledging a Wake-Up Call If the DFE-T V2.1 detects an awake signal on U, an acknowledge signal is sent out. Afterwards the DFE-T V2.1 waits for a possible repetition of the awake signal (in case the acknowledge signal has not been recognized). If no repetition is found, the awoken DFE-T V2.1 starts sending U2 after 7 ms from detecting the awake signal. If a repeated awake signal is found, the procedure in the awoken DFE-T V2.1 starts again. Preliminary Data Sheet 3-31 06.99 PEF 24901 Functional Description 3.6.10 C/I Codes The Control/Indicate (C/I) channel is used to control the operational status of the DFE-T V2.1 and to issue corresponding indications. Table 3-10 presents all defined C/I codes (former C/I code names of the DFE-T V1.2 are given in brackets). A new command or indication will be recognized valid after it has been detected in two successive IOM® frames (double last-look criterion). Indications are strictly state orientated. Refer to the state diagram in the following section for commands and indications applicable in various states. Table 3-10 Command / Indicate Codes Code LT-Mode DIN DOUT 0000 DR – 0001 – DEAC(DA) 0010 – – 0011 – (LTD) – (HI) 0100 – RSY (RSYU) 0101 SSP – 0110 DT(TEST) – 0111 – UAI(RDS) 1000 AR(ARN) AR(ARU) 1001 ARL – 1010 ARL2(AR2) – 1011 ARL1A(AR4) – 1100 – AI(AIU) 1101 RES – 1110 – – 1111 DC(DID) DI(DIU) • AI Activation Indication DI Deactivation Indication. AR Activation Request DR Deactivation Request ARL Activation Request Local Loop RES Reset ARL2 Activation Request Loop 2 RSY Resynchronization Indication ARL1A Activation Request Loop 1A SSP Send-Single-Pulses Preliminary Data Sheet 3-32 06.99 PEF 24901 Functional Description DC Deactivation Confirmation DEAC Deactivation Accepted Preliminary Data Sheet DT Data Through Mode UAI U Activation Indication 3-33 06.99 PEF 24901 Functional Description 3.6.11 State Machine Notation The following state diagram describes all the actions/reactions resulting from any command or detected signal and resulting from the various operating modes. The states with its inputs and outputs are interpreted as shown below: ,1 7UDQVPLWWHG86LJQDO 6WDWH1DPH &,&KDQQHO,QGLFDWLRQ '287 287 SM_expl.vsd Figure 3-14 State Diagram Example Each state has one or more transitions to other states. These transitions depend on certain conditions which are noted next to the transition lines. These conditions are the only possibility to leave a state. If more conditions have to be fulfilled together, they are put into parentheses with an AND operator (&). If more than one condition leads to the same transition, they are put into parentheses with an OR operator (|). The meaning of a condition may be inverted by the NOT operator (/). Only the described states and transitions exist. At some transitions, an internal timer is started. The start of a timer is indicated by TxS (’x’ is the timer number). Transitions that are caused if a timer has expired are labelled by TxE. Some conditions lead to the same target state. To reduce the number of lines and the complexity of the figures, a state named “ANY STATE” acts on behalf of all state. The state machine is designed to cope with all ISDN devices with IOM®-2 standard interfaces. Undefined situations are excluded. In any case the involved devices will enter defined conditions as soon as the line is deactivated. Preliminary Data Sheet 3-34 06.99 PEF 24901 Functional Description 3.6.12 LT Mode State Diagram $5$5/ $5/$5/$ 8 8 7(8 'HDFWLYDWHG 3HQG'HDFWLYDWLRQ ', '($& 76 '& $5/ 8 '5 3RZHU'RZQ $:5 ', $5$5/ $5/$5/$ 76 8: 76 76 $OHUWLQJ '5 $5 76 $:7 76 7($5/ 8 7($5/ 8: '5 '5 :DLWIRU8: $FNQRZOHGJH8: $5 $5 $:5$5/ 76 $:7 76 $:5 8 $ZDNH '5 $5 7( 8 '5 6\QFKURQL]LQJ 8 '5 8 /LQH$FWLYH 8$,56< $5 8 8_$5/ 76 8+ 3HQG7UDQVSDUHQW 76 '5 $5/ 8$,56< '5 7( 8 5HVHW '($& 76 8 $5/ :DLWPV '5 '5 63 7HVW '($& 8$,56< 7( 6633LQ663 8 '5 '73LQ'7 7UDQVSDUHQW $1<67$7( 5(63LQ5(6 $,56< LT_SM_cust.emf Figure 3-15 LT State Diagram Preliminary Data Sheet 3-35 06.99 PEF 24901 Functional Description • Table 3-11 Differences to LT-SM of DFE-T V1.2 No. V1.2 State/ Signal Change in V2.1 Comment 1. ’Maintenance’ State split into two states - Reset State - Test State simplifies SM implementation 2. State ’Deactivating’ renamed to state ’Pending Deactivation’ for consistency reasons to 2B1Q and to TS 102 080 3. State ’Deac. Acknowledge’ renamed to state ’Deactivated’ 4. State renamed to state ’Start Awak. U’ ’Alerting’ 5. State renamed to state ’Awake Signal ’Wait for U1W’ Sent’ 6. State ’Sending Awake Ack.’ renamed to state ’Acknowledge U1W’ 7. State ’Ack. Sent/ Received’ renamed to state ’Awake’ 8. State ’U Synch. no TE?’ renamed to state ’Line Active’ 9. State ’Link to TE Synch.’ renamed to state ’Pend. Transparent’ 10. State ’Data Transmission’ renamed to state ’Transparent’ 11. Any State transition condition PFOFF& no support of the IEC type power /ARL or LTD doesn’t exist controller interface any more Preliminary Data Sheet 3-36 06.99 PEF 24901 Functional Description Table 3-11 Differences to LT-SM of DFE-T V1.2 No. V1.2 State/ Signal Change in V2.1 Comment 12. Renamed C/I codes old ARN AR2 AR4 AIU DA DID DIU RSYU TEST consistency to 2B1Q coding 13. C/I codes LTD and HI C/I codes ’LTD’ and ’HI’ were function corresponds to that of C/I omitted and are no more ’RES’ available 14. Timer variables introduced Name T05 T1 T7 T12 Preliminary Data Sheet -> -> -> -> -> -> -> -> -> -> new AR ARL2 ARL1A AI DEAC DC DI RSY DT Duration 0.5ms 1.0ms 7.0ms 12.0ms 3-37 06.99 PEF 24901 Functional Description 3.6.12.1 State Machine Inputs C/I-Commands AR Activation Request The U-transceiver is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal U2W. ARL Activation Request Local Loop-back The U-Transceiver gets reset and is requested to operate an analog loopback. An activation procedure is started. Any other C/I-channel input, low on pin RES or high on pin SSP causes the analog loop to be opened and the Msymbol to be set to zero. ARL2 Activation Request Loop 2 in the NT The U-Transceiver is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal U2W. The loop 2 request is signalled via the Maintenance channel by a continuous plus polarity in the M-symbol. ARL1A Activation Request Loop 1A in the Repeater The U-Transceiver is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal U2W. The loop 1A request is signalled via the Maintenance channel by a series of alternating plus and zero polarity in the M-symbol. DR Deactivation Request The U-transceiver is requested to start a deactivation procedure. DC Deactivation Confirmation DC informs the U-transceiver that the upstream unit is also deactivated. The U-transceiver is now ready to receive awake signals. Upon DC the Utransceiver enters power-down mode. RES Reset Unconditional command which resets any stored settings of the U-transceiver; no line signal will be sent out. SSP Send Single Pulses Unconditional command which requests the transmission of single pulses with a period of 1ms. DT Data Through Test Mode Unconditional command which causes the U-transceiver to transit to the transparent state and to issue U4 independent of the wake-up protocol. A farend transceiver needs not to be connected. In case a far-end transceiver is present it is assumed to be in the same condition. Preliminary Data Sheet 3-38 06.99 PEF 24901 Functional Description Pins RES Pin-Reset Corresponds to C/I code ’RES’ besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line. C/I-message DEAC will be issued. SSP Pin-Send Single Pulses Corresponds to C/I code ’SSP’ besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line. C/I-message DEAC will be issued. U-Interface Events U0 U0 detected U0 is recognized after one complete frame with continuous zero level. U1 U1 detected The U-transceiver detects U1 if continuous binary data is found on the descrambler output after 8 subsequent U-frames. U1 is detected after 8 to 9 ms. U3 U3 detected See description of U1. AWR Awake signal (U1W) detected AWT Awake signal (U2W) has been sent out TxE Timer ended, the started timer has expired Timers The start of timers is indicated by TxS, the expiry by TxE. The following table shows which timers are used. • Table 3-12 Timers Timer Duration (ms) Function State T05 0.5 C/I code recognition Deactivated T1 1.0 Defines duration of U4H Pend. Transparent T7 7.0 Supervises U1W repetition Awake T12 12.0 Supervises U2W repetition Alerting, Wait for U1W Preliminary Data Sheet 3-39 06.99 PEF 24901 Functional Description 3.6.12.2 State Machine Outputs Below the signals and indications are summarized that are issued on IOM®-2 (C/Iindications) and on the U-interface (predefined U-signals). C/I Indications AR Activation Request The AR code indicates that an awake signal has been received and that a start-up procedure is in progress. UAI U-Activation Indication The U-transceiver has detected U1 or U3 indicating that the transmission line between the two U-interface stations is now synchronized. At this point of time the block error counter (RDS) is enabled. AI Activation Indication As soon as U3 has been detected the U-transceiver issues ’AI’ and transits to the ’Transparent’ state. ’AI’ indicates that the whole transmission line is now synchronized from the LT to the TE. DEAC Deactivation Accepted DEAC is issued in response to a DR-code and informs the upstream unit that the U-transceiver is deactivating the transmission line downstream. DI Deactivation Indication DI informs the upstream unit that the U-transmission line is deactivated. On receiving ’DC’ the U-transceiver enters the power-down state. The transmitter is disabled, but awake signals may be detected. RSY Resynchronization Indication RSY informs that the U-transceiver is not synchronous. RSY is issued if the Utransceiver was in the fully activated state and has lost synchronization afterwards (transmission of U4 will not be interrupted). Signals on U-Interface The signals U0, U2W, U2A, U2, U4H, U4 are transmitted on the U-interface in the course of an activation/ deactivation. They are defined in detail in Table 3-9 "4B3T Signal Elements" on page 3-28. SP Single Pulses The U-transceiver sends periodically single pulses spaced by 1 ms e.g. for pulse mask measurements. Preliminary Data Sheet 3-40 06.99 PEF 24901 Functional Description 3.6.12.3 State Description In this section each LT state is described with its inputs, outputs and its function. The C/I-channel output and the transmitted signal elements on U are already specified by the state diagram. Below they are only referred to, if within a state there are more than one of them specified. In this case, the C/I-channel output and the transmitted signal element depend on the given inputs. Acknowledge U1W On the receipt of the awake signal U1W the U-transceiver responds with the transmission of U2W. The user data (2B + D) on pin DOUT is clamped to high. Alerting On the receipt of AR, ARL, ARL2 or ARL1A in the C/I-channel the U-transceiver has powered up and is sending the awake signal U2W. The user data (2B + D) on pin DOUT is clamped to high. Awake If awaking the U-transceiver has received the acknowledge signal. If being awoken the U-transceiver has sent the acknowledge. In both cases the U-transceiver waits for a possible repetition or time-out. The user data (2B + D) on pin DOUT is clamped to high to prevent that wrong data is transmit in the D-channel during activation. Deactivated In the Deactivated state no signal is transmitted on the U-interface. The U-transceiver is ready to enter the power-down state. The user data (B + B + D) on pin DOUT is clamped to high. Line Active After the recognition of U1 the U-interface is synchronized in both directions. That is 1.152 subsequent bits have been transferred and received without any bit error. The Utransceiver transits to the ’Transparent’ state as soon as a TE signals its presence by signal U3. In case of an analog loop the U-transceiver leaves this state again immediately. If in 64 subsequent U-frames the Barker-code can not be detected at the expected position, the U-transceiver issues RSY on the C/I-channel until it has resynchronized. The criteria for resynchronization is that the Barker-code has been detected at the same position in 4 subsequent frames. The block error counter (RDS) and the coefficient adaptation are enabled until deactivation is performed. Preliminary Data Sheet 3-41 06.99 PEF 24901 Functional Description Pending Deactivation The U-transceiver deactivates the U-interface sending U0 and waits in turn for signal U0 to enter the ’Deactivated’ state. Timer T05 ensures that the C/I code DEAC is recognized by the exchange. The user data (2B + D) on pin DOUT is clamped to high. Pending Transparent The whole transmission system from the LT to the TE is now synchronized in both directions of transmission. Signal U4H is sent until the expiry of timer T1. U4H requires the NT to establish a transparent link to the TE. If synchronization has been lost the U-transceiver issues RSY on the C/I-channel until it has resynchronized again. Power Down On the receipt of ’DC’ in the C/I channel the U-transceiver enters the power-down state. In power-down mode all power consuming parts of the device which are not required for the wake-up detection are switched off. The U-transceiver waits either for an activation request (AR, ARL, ARL2, ARL1A) from the exchange or for a wake-up signal U1W from the NT. Reset The Reset state is entered by the unconditional command RES or pin-RES. All stored coefficients are erased. The U-transceiver leaves the Reset state if pin-RES is set inactive (’1’) and the C/I code DR or ARL is applied. The U-transceiver does not react on the receipt of a wake-up signal. The user data (B + B + D) on pin DOUT is clamped to high. Synchronizing After successful awake procedure, the U-transceiver looks for the signals U1 or U3 to synchronize its receiver. The user data (2B + D) on pin DOUT is clamped to high. Test Test mode is entered by the unconditional command SSP or pin-SSP. The Test state is left if pin SSP is set inactive (’0’) and the C/I code DR or ARL is applied. Single pulses spaced by 1ms are sent on the U-line. The U-transceiver does not react on the receipt of a wake-up signal. The user data (B + B + D) on pin DOUT is clamped to high. Preliminary Data Sheet 3-42 06.99 PEF 24901 Functional Description Transparent The transmission line is fully activated. User data can be exchanged by U4/U5. Transparent state may also be entered in the case of a loop-back 2. The exchange is informed by C/I code AI that the transparent state has been reached. The block error counter (RDS) and the adaptation of the receiver coefficients are enabled even if RSY is sent. If synchronization has been lost the U-transceiver issues RSY on the C/I-channel until it has resynchronized again. Wait 1ms If the transparent state has been reached, the U-Transceiver in the exchange waits 1ms to ensure that the whole link is already transparent before it is indicated by C/I code AI to the exchange. If synchronization has been lost the U-transceiver issues RSY on the C/I-channel until it has resynchronized again. The user data (B + B + D) on pin DOUT is clamped to high. Wait for U1W The U-transceiver is awaking the U-interface and waits for the acknowledge by the NT or for the time-out (12ms) after sending the awake signal. The user data (2B + D) on pin DOUT is clamped to high. Preliminary Data Sheet 3-43 06.99 PEF 24901 Functional Description 3.7 Clock Generation The 15.36MHz master clock is generated by a crystal oscillator connected to the AFE V2.1. In case FSC differs from the 8kHz PTT reference clock an integrated crystal based phase locked loop (PLL) is provided in the AFE to retain system synchronization. The AFE-PLL accepts either a 8kHz or 2048kHz system clock. The AFE supplies the DFE-T V2.1 with the synchronized 15.36MHz clock at pin CL15. Below the clock characteristics are summarized: Master clock nominal frequency: 15.36 MHz Max. Difference of phase deviations of Master clock and FSC: ± 25 µs Max. low freq. phase wander within 1 period: ± 0.85 ps Jitter (peak-to-peak): see)LJXUH Jitter on the 15.36 MHz master clock is passed to the U-interface without change. Hence, Figure 3-16 reflects the maximum tolerable input jitter as given by FTZ 1 TR 220. UI (15.36 MHz) 32 3.2 3 30 60000 jitter frequency (Hz) Figure 3-16 Maximum Tolerable Input Jitter of the 15.36MHz Clock Preliminary Data Sheet 3-44 06.99 PEF 24901 Operational Description 4 Operational Description The scope of this section is to describe how the DFE-T V2.1 works and behaves in the system environment. Activation/ deactivation control procedures are exemplary given for SW programmers reference. 4.1 Reset There are two different ways to apply a reset, • either as a hardware reset by setting pin RES to low • or as a software reset by applying ’C/I= RES’ Hardware Reset A hardware reset affects all design components and takes effect immediately (asynchronous reset style). No clock signal other than the master clock shall be required for reset execution. Software Reset A software reset triggered by ’C/I= RES’ has only effect on the addressed line port. The remaining line ports, the system interface, the relay driver/ status pins and any global functions are not affected. A clock signal must be provided for the C/I code processing. C/I ’RES’ resets the receiver and the activation/deactivation state machine. Transmission on U is stopped. It is an unconditional command and is therefore applicable in any state. 4.2 Power Down Each building block of the DFE-T V2.1 is optimized with respect to power consumption and support a power down mode. See chapter 7.6.2 page 7-8 for the specified max. power consumption. The DFE-T V2.1 goes in power down mode • if the U-transceiver is in state ’Power Down’ There are two events that awake the DFE-T V2.1 again from power down mode, • when a wake up tone (U1W) has been detected on U • when any of the C/I codes AR, ARL, ARL2 or ARL1A is applied at DIN Regarding the DFE-T V2.1 power down mode means that • the DSP clock is turned off • all other digital circuits (excluding the IOM®-2 interface) go in power down mode Preliminary Data Sheet 4-1 06.99 PEF 24901 Operational Description • no timing signals are delivered (CLS0, ... , CLS3) Regarding a connected AFE power down mode means that • no signal is sent on the U-interface • only functions that are necessary to detect the wake up conditions are kept active • transmit path, receive path and auxiliary functions of the analog line port are switched to a low power consuming mode when the power down function is activated. This implies the following: • the ADC, the relevant output is tied to GND. • the DAC and the output buffer; the outputs AOUTx/ BOUTx are tied to GND. • the internal DC voltage reference is switched off. • the range and the loop functions are deactivated. Preliminary Data Sheet 4-2 06.99 PEF 24901 Operational Description 4.3 Layer 1 Activation/ Deactivation Procedures This chapter illustrates the interactions during activation and deactivation between the LT and NT station. An activation can be initiated by either of the two stations involved. A deactivation procedure can be initiated only by the exchange. The status of a transmission line is classified by one of the seven activation/deactivation states (also referred to by number in the activation/ deactivation procedures on the following sides): 1. Activation States: 1.1 Line awake Each individual line is being awoken, but is not yet synchronized, data transmission is not yet possible 1.2 Synchronization downstream Synchronization is always done downstream first, the whole line has to synchronize on the exchange 1.3 Synchronization upstream Because the delay differs from line to line, bit synchronization is necessary in the LT 1.4 Synchronized All layer-1 units of the link are told by the exchange that synchronization has been finished 2. Transparent State: In the activated state, the user data is transmitted from exchange to TE and vice versa. 3. Deactivation States: Deactivation is done in two steps on each individual line separately. 3.1 Deactivation request downstream 3.2 Deactivation acknowledge upstream The transmission link is totally deactivated thereafter. The exchange of control information is partially state oriented on the U-interface. Some signal elements are given as long as no other information has to be transferred, other signal elements have distinct durations. Preliminary Data Sheet 4-3 06.99 PEF 24901 Operational Description 4.3.1 Complete Activation Initiated by Exchange • ,20 ,20 8/LQH '& ,1)28 '& ', ,1)28 ', $5 56< ,1)28: $5 ,1)28: ,1)28$ ,1)28 $5 ,1)28 $5 $, ,1)28 8$, ,1)28+ ,1)28 $, PV ,1)28 $, /D\HU /D\HU ')(79 87UDQVFHLYHU &RQWUROOHU &RQWUROOHU 17 /7 'RZQVWUHDP 8SVWUHDP actbyLT_4b3t.emf Figure 4-1 Activation Initiated by Exchange Preliminary Data Sheet 4-4 06.99 PEF 24901 Operational Description 4.3.2 Complete Activation Initiated by TE • ,20 ,20 8/LQH '& ,1)28 '& ', ,1)28 ', 7,0 $5 ,1)28: $5 ,1)28: 56< ,1)28$ ,1)28 $5 ,1)28 $5 $, ,1)28 8$, ,1)28+ ,1)28 $, PV ,1)28 $, /D\HU /D\HU ')(79 87UDQVFHLYHU &RQWUROOHU &RQWUROOHU 17 /7 'RZQVWUHDP 8SVWUHDP actbyNT_4b3t.emf Figure 4-2 Activation Initiated by TE Preliminary Data Sheet 4-5 06.99 PEF 24901 Operational Description 4.3.3 Complete Activation Initiated by Exchange with Repeater • ,20 ,20 8/LQH ,20 8/LQH '& ,1)28 '& ,1)28 '& ', ,1)28 ', ,1)28 ', $5 ,1)28: $5 56< ,1)28: ,1)28: $5 56< ,1)28: ,1)28$ ,1)28$ ,1)28 ,1)28$ $5 ,1)28 ,1)28 ,1)28 $5 ,1)28 ,1)28 $, $, 8$, ,1)28 ,1)28 $, 8$, ,1)28+ ,1)28+ PV $, ,1)28 $, ,1)28 $, 67UDQVFHLYHU 87UDQVFHLYHU 87UDQVFHLYHU 87UDQVFHLYHU /D\HU ')(79 &RQWUROOHU 5HSHDWHUPD\EHRPLWWHG 17 'RZQVWUHDP /7 8SVWUHDP actwithLTRP_4b3t.emf Figure 4-3 Activation with Repeater Initiated by LT Preliminary Data Sheet 4-6 06.99 PEF 24901 Operational Description 4.3.4 Complete Activation Initiated by Terminal with Repeater • ,20 8/LQH ,20 ,20 8/LQH '& ,1)28 '& ,1)28 '& ', ,1)28 ', ,1)28 ', 7,0 $5 ,1)28: 7,0 ,1)28: $5 56< 56< ,1)28: $5 ,1)28: ,1)28$ ,1)28$ ,1)28$ ,1)28 ,1)28 $5 ,1)28 ,1)28 $5 ,1)28 ,1)28 $, $, 8$, ,1)28 ,1)28 $, 8$, ,1)28+ ,1)28+ PV $, ,1)28 $, ,1)28 $, 87UDQVFHLYHU 67UDQVFHLYHU 87UDQVFHLYHU 87UDQVFHLYHU 5HSHDWHUPD\EHRPLWWHG 17 'RZQVWUHDP /D\HU ')(79 &RQWUROOHU /7 8SVWUHDP actwithNTRP_4b3t.emf Figure 4-4 Activation with Repeater Initiated by TE Preliminary Data Sheet 4-7 06.99 PEF 24901 Operational Description 4.3.5 Deactivation • ,20 ,20 8/LQH ,20 8/LQH '5 '5 ,1)28 '($& ', ,1)28 '& ', ', '& '& /D\HU '($& ,1)28 '5 87UDQVFHLYHU &RQWUROOHU ,1)28 87UDQVFHLYHU 87UDQVFHLYHU 5HSHDWHUPD\EHRPLWWHG 17 /D\HU ')(79 &RQWUROOHU /7 8SVWUHDP 'RZQVWUHDP deac_4b3t.emf Figure 4-5 Deactivation (Always Initiated by the Exchange) Preliminary Data Sheet 4-8 06.99 PEF 24901 Operational Description 4.3.6 Activation of Loop#1 • ,20 ,20 8/LQH '& ,1)28 '& ', ,1)28 ', $5/ $5 ,1)28 ,1)28 8$, ,1)28 ,1)28 PV $, /D\HU /D\HU ')(79 87UDQVFHLYHU &RQWUROOHU &RQWUROOHU 17 /7 'RZQVWUHDP 8SVWUHDP act_loop1_4b3t.emf Figure 4-6 Activation of Loop#1 Preliminary Data Sheet 4-9 06.99 PEF 24901 Operational Description 4.3.7 Activation of Loop#1A • ,20 ,20 8/LQH ,20 8/LQH '& ,1)28 '& ,1)28 '& ', ,1)28 ', ,1)28 ', $5/$ ,1)28: $5 56< ,1)28: ,1)28: $5 ,1)28$ evtl. ,1)28$ ,1)28 ,1)28 $5 ,1)28 ,1)28 8$, $, ,1)28 ,1)28+ 8$, $,/ ,1)28 ,1)28 PV $, 67UDQVFHLYHU 87UDQVFHLYHU 87UDQVFHLYHU 87UDQVFHLYHU /D\HU ')(79 &RQWUROOHU 5HSHDWHU 17 'RZQVWUHDP /7 8SVWUHDP act_loop1a_4b3t.emf Figure 4-7 Activation of Loop#1A (Repeater) Preliminary Data Sheet 4-10 06.99 PEF 24901 Operational Description 4.3.8 Activation of Loop#2 • ,20 ,20 8/LQH $, ,1)28 $5 $, ,1)28 $, %' $5/ ,1)280%LW [ $,/ %' $5 ,1)280%LW [ $, %' /D\HU /D\HU ')(79 87UDQVFHLYHU &RQWUROOHU &RQWUROOHU 17 /7 'RZQVWUHDP 8SVWUHDP act_loop2_4b3t.emf Figure 4-8 Activation of Loop#2 Preliminary Data Sheet 4-11 06.99 PEF 24901 Operational Description 4.4 Maintenance and Test Functions This chapter summarizes all features provided by the U-transceiver to support maintenance functions and system measurements. They are classified into three main groups: – maintenance functions to close and open test loopbacks – features facilitating the recognition of transmission errors – test modes required for system measurements The next four sections describe how these maintenance functions are used in applications. 4.4.1 Test Loopbacks Four different loopbacks are defined for maintenance purposes and in order to facilitate the location of defect systems. The position of each loopback is illustrated in Figure 49. Remote control by the exchange is featured. When a test loop is closed all channels (B1 + B2 + D) are looped back and data from the other end of the line is ignored. There are no separate loops for single channels. • U U IOM®-2 S-BUS Loop 2 Loop 2 S-Transceiver U-Transceiver IOM®-2 Loop 1 A NT U-Transceiver IOM®-2 Loop 2 Layer-1 Controller IOM®-2 U-Transceiver Repeater (optional) Loop 1 U-Transceiver Exchange U-Transceiver IOM®-2 Loop 3 Layer-1 Controller U-Transceiver PBX or TE Figure 4-9 loop.emf Test Loopbacks All test loops are transparent loops. The line signal is still transmitted although the analog loop is closed. Nevertheless the NT receives this signal and synchronizes on it. The NT can not distinguish between line signals sent from the LT during loop 1 or loop 1A and Preliminary Data Sheet 4-12 06.99 PEF 24901 Operational Description signals sent during normal operation. Loopback no.1 is closed by the DFE-T V2.1 itself, whereas loopback no 1A and no.2 are remote controlled by C/I code ’ARL1A’ and ’ARL2’ and are closed in the NT. Loopback no.3 is not supported since the DFE-T V2.1 operates only in LT mode. 4.4.1.1 Analog Loopback (No.1) The analog loop no.1 is closed in the DFE-T V2.1 as close to the U-interface as possible. The signal from the line driver is fed back directly to the input. It is like a short-circuit between the pins AOUT and AIN as well as between BOUT and BIN. The input signal from the hybrid is ignored in this mode. The analog loop mode is controlled via the IOM®2 C/I-channel code ’ARL’. To request a LT-repeater to close the analog loop no.1A, C/I code ’ARL1A’ must be applied to the DFE-T V2.1. It will send in turn alternating plus and zero polarity within 8 subsequent frames in the M-channel (+ 0 + 0 + 0 + 0 ...). 4.4.1.2 Loopback No.2 Loopback no. 2 is controlled by the exchange. It is transparent which means that all bits that are looped back are also passed on to the S-bus. The DFE-T V2.1 features the remote control of loop no.2 via its C/I channel. C/I code ’ARL2’ requests the NT to close the loop, ’AR’ or ’DR’ requests the NT to open the loop again. • U U Repeater S-Bus NT Loop 1a Loop 2 LT NTC-T U-Transceiver Loop 1 ITS09867 Figure 4-10 Loopback No.2 Preliminary Data Sheet 4-13 06.99 PEF 24901 Operational Description The DFE-T V2.1 translates the received C/I codes into the following pattern sequence in the M-channel of the U-interface: • continuous ’+’ polarity The NT closes loopback no.2 after 8 consecutive pulses with plus polarity has been received in the M-channel (+ + + + + + + + ...). • continuous ’0’ polarity The NT closes loopback no.2 after 8 consecutive zeros has been received in the Mchannel (0 0 0 0 0 0 0 0 ...) or on a deactivation request. During normal transmission without loops, the M-symbol is set to zero or minus. The loopback comprises both B-channels and the D-channel. It is closed in the NT as close to the S-transceiver as possible. The NT U-transceiver passes the request on to the S-transceiver by issuing C/I-code AIL in the “Transparent” state or C/I-code ARL in all other states. 4.4.1.3 Available Loopbacks by Register Map Besides the remote loopback stimulation and the local analog loopback (C/I= ARL) the DFE-T V2.1 features digital local loopbacks via its internal register set. The loopbacks that are additionally available with the internal LOOP register are shown in Figure 4-11. They can be activated regardless of the current activation status using the MON-12 protocol and have direct effect. By the LOOP register it can be configured whether the digital looback is closed only for the B1 and/or B2 or for all ISDN-BA channels and whether the loopback is closed towards the IOM®-2 interface or towards the U-Interface. By default the loopbacks are set to transparent mode. In transparent mode the data is both passed on and looped back. In non-transparent mode the data is not forwarded but substituted by 1s (idle code). Besides the loopbacks in the system interface a further digital loopback, the Framer/ Deframer loopback is featured. It allows to test all digital functions of the 4B3T Utransceiver besides the signal processing blocks. Preliminary Data Sheet 4-14 06.99 PEF 24901 Operational Description • /223/% RU /223/% RU /223/%%' /2238,20 /223/% RU /223/% RU /223/%%' /2238,20 ')(79 /D\HU&RQWUROOHU '63 0 8 %7 6FUDPEOHU &RGHU 6,8 8 )UDPLQJ ; (FKR &DQFHOOHU 3'0 )LOWHU ,20 6\QF:RUG $ * 0 (TXDOL]HU & 8 ; %7 'H 8'H 'HFRGHU 6FUDPEOHU )UDPLQJ 7LPLQJ 5HFRYHU\ 6\VWHP $FWLYDWLRQ'HDFWLYDWLRQ ,QWHUIDFH &RQWUROOHU 8QLW /223'/% ')(79 /D\HU&RQWUROOHU '63 0 8 %7 6FUDPEOHU &RGHU 6,8 8 )UDPLQJ ; (FKR &DQFHOOHU 3'0 )LOWHU ,20 6\QF:RUG $ * & 0 (TXDOL]HU 8 ; %7 'H 8'H 'HFRGHU 6FUDPEOHU )UDPLQJ 7LPLQJ 5HFRYHU\ 6\VWHP $FWLYDWLRQ'HDFWLYDWLRQ ,QWHUIDFH &RQWUROOHU 8QLW loopreg.vsd Figure 4-11 Loopbacks Featured by Register LOOP Preliminary Data Sheet 4-15 06.99 PEF 24901 Operational Description 4.4.2 Block Error Counter The DFE-T V2.1 provides a block error counter per channel. This feature allows a comfortable surveillance of the transmission quality on the U-interface. A block error is given if a U-frame with at least one code violation has been detected in the LT (near-end block error) or a positive M-symbol has been received from the NT (farend block error). The NT transmits a positive M-symbol upstream if any code error has been detected within a frame (position 25 upstream in the U-frame from NT to LT). The current status of the block error counter can be retrieved by the MON-8 command ’RDS’. Upon reception of ’RDS’ the counter value is issued with the corresponding MON8 message. If the block error counter is read it is automatically reset. The counter is also automatically reset in the course of a deactivation procedure. It is enabled again to count code violations from the moment the C/I code ’UAI’ is written into the C/I-channel indicating that the U-line is sychronized (in state ’Line Active’). The counter does not overflow but stops at its maximum value (255). Note that each counted frame with a detected code violation causes about 10 to 20 binary bit errors on average. So a bit error rate of 10–7 in both directions results in 2 detected frame errors within 1000 s in the LT (1 frame error detected in the NT and transmitted via M-symbol). 4.4.3 Bit Error Rate Counter For bit error rate monitoring the DFE-T V2.1 features an 16-bit Bit Error Rate counter (BERC) per line. The measurement is performed for the B1, B2 and the D channel. Prerequisite is that loop #2 of the addressed line port has been closed before on the NT side via the M-channel. The measurement is initiated by two BER control bits in the TEST register. As soon as the BER function is enabled zeros are sent in the selected channels and incoming ones are counted until the BER function has been disabled again by the user. Preliminary Data Sheet 4-16 06.99 PEF 24901 Operational Description 4.4.4 System Measurements The DFE-T V2.1 features dedicated test modes to enable and ease system measurements. How these test modes can be used to conduct the most frequently needed system measurements is described in the following sections. 4.4.4.1 Send Single Pulses Test Mode (SSP) In the send-single-pulses test mode, the U-transceiver transmits on the U-interface +1 pulses spaced by 1 ms. Two options exist for selecting the “Send-Single-Pulses” (SSP) mode: – hardware selection: – software selection: Pin-SSP= ’1’ C/I code= SSP (0101B) Both methods are fully equivalent besides the fact that the HW selection impacts all line ports while the SW selection impacts only the chosen line. The SSP-test mode is required for pulse mask measurements. 4.4.4.2 Data Through Mode (DT) If selected the data-through mode forces the DFE-T V2.1 directly into the “Transparent” state. This is possible from any state in the state diagram. The Data-Through option (DT) provides the possibility to transmit a standard scrambled U-signal even if no U-interface wake-up protocol is possible. This feature is of interest if no counter station can be connected to supply the wake-up protocol signals. As with the SSP-mode, two options are available. – hardware selection: – software selection: Pin-DT= ’1’ C/I code= DT (0110B) Note that the hardware selection offers the option to initiate further actions via C/I-code (e.g. simultaneous stimulation of an analog loop-back by C/I ’ARL’). The DT-mode is required for power spectral density and total power measurements. 4.4.4.3 Master Reset Mode The master-reset mode characterizes the mode where the U-transceiver does not transmit any signals. The chip is in the “Reset” state. All echo canceller and equalizer coefficients are reset. As can be seen from the state diagram, no activation is possible if the device is in the “Reset” state. For measurements two methods are recommended in order to transfer the U-transceiver into the master-reset mode: – hardware selection: – software selection: Preliminary Data Sheet Pin-RES= ’0’ C/I-code= RES (0001B) 4-17 06.99 PEF 24901 Operational Description Both alternatives are fully compatible besides the fact that the SW selection is channel selective. The master-reset test mode is used for the return-loss measurements. 4.4.4.4 – – – – Pulse mask is defined in FTZ Guideline 1TR 220 and ETSI TS 102 080 U-interface has to be terminated with 150 Ω U-transceiver is in “Send-Single-Pulses” mode (C/I = ’SSP’ or Pin-SSP = ’1’) Measurements are done using an oscilloscope 4.4.4.5 – – – – Power Spectral-Density Measurement PSD is defined in FTZ Guideline 1TR 220 and ETSI TS 102 080 U-interface has to be terminated with 150 Ω U-transceiver is in “Data-Through” mode (C/I = ’DT’ or Pin-DT= ’1’) For measurements a spectrum analyzer is employed 4.4.4.6 – – – – Pulse Mask Measurement Return-Loss Measurement Return loss is defined in FTZ Guideline 1TR 220 and ETSI TS 102 080 U-transceiver is in “Reset” state (C/I = ’RES’ or Pin-RES= ’0’) Measure complex impedance “Z” from 5 kHz – 100 kHz Calculate return loss with formula: RL(dB) = 20log (abs((Z + 150) / (Z –150))) 4.4.4.7 Quiet Mode Measurement – Quite mode is defined in FTZ Guideline 1TR 220 and ETSI TS 102 080 – U-transceiver is in the “Reset” state (C/I = ’RES’ or Pin-RES= ’0’) – Trigger and exit criteria have to be realized externally 4.4.4.8 Insertion Loss Measurement – Insertion loss is defined in FTZ Guideline 1TR 220 and ETSI TS 102 080 – U-transceiver is in “Data-Through” mode (C/I = ’DT’ or Pin-DT= ’1’) – Trigger and exit criteria have to be realized externally Preliminary Data Sheet 4-18 06.99 PEF 24901 Operational Description 4.4.5 Retrieving DSP Data Beyond the test and maintenance features described in the previous sections, the DFET V2.1 permits access to specific DSP data. Access is provided via the MON-12 protocol. The data transfer between the DSP and an external device is synchronized by two handshake signals, ’DATA_REQ’ and ’DATA_ACK’. In the following text the technical term ’read’ stands for the process of sending a read request via the Monitor channel using the MON-12 protocol. DSP Data Exchange via Handshake Signals The handshake signal DATA_REQ is accommodated at bit position 0 in register DSP_DREQ, the handshake signal DATA_ACK at bit position 0 in register DSP_DACK. • ')(79 )6& '63&RUH '&/ +DQGVKDNH &RQWURO B$ 7$ .& '$ '63B'$&. ,20 ,QWHUIDFH B$ 7$ 4 ' (5 ',1 '287 021 &RQWUROOHU '63B'5(4 dsp_acs1.vsd Figure 4-12 DSP Data Transfer Synchronization by Handshake Signals Significance of DATA_REQ Via DATA_REQ an external device is able to control the data exchange and to adapt the data rate to its needs. • During a read access the layer-1 controller indicates with an active DSP_REQ signal (=’1’) that it requests new data. • DATA_REQ set to ’0’ signals that the layer-1 controller is busy. Preliminary Data Sheet 4-19 06.99 PEF 24901 Operational Description Significance of DATA_ACK Signal DATA_ACK is controlled by the DSP. • During a read access the DSP informs an external controller by DATA_ACK set to ’0’ that the data in the DSP Read Registers (DSP_RD1..3) has been updated. • An active DATA_ACK bit (= ’1’) signals that the DSP is busy. Below the single steps of the handshake protocol in the course of a read access is given. Read direction (DSP -> Layer-1 controller): 1. Layer-1 controller polls if DATA_ACK bit is set to ’0’ 2. Layer-1 controller signals its readiness for a read access by DATA_REQ= ’1’ 3. DSP signals with DATA_ACK= ’0’ that the DSP_RD1..3 registers have been loaded 4. Layer-1 controller reads the DSP Read Registers, DSP_RD1..3 For subsequent read accesses this procedure has to be repeated Preliminary Data Sheet 4-20 06.99 PEF 24901 Operational Description 4.4.5.1 Reading Coefficient Values By means of the DSP_RD1..3 registers it is possible to read coefficient values. The coefficient subsets of the various filter banks are addressable by the 3-bit DAT_TYP field in register DSP_CR2. Below the accessible coefficient clusters are listed: ’100’ ’110’ ’001’ ’011’ Coefficient Set 1 Coefficient Set 2 Coefficient Set 3 Coefficient Set 4 Figure 4-13 shows the register structure that is provided for the access to coefficient values. • ')(79 '63&RUH 4 (5 B$ 7$ ' +DQG VKDNH . & $ B$ 7$ ' '63B'5(4 '63B'$&. /( 6B + & $ $ ' '63B&5 3< 7B $ 7$ ' : 5 B$ 7$ ' '63B5' '63B&5 '63B5' '63B5' 021 &RQWUROOHU ,20 dsp_acs2_ds.emf Figure 4-13 Provided DSP Registers for Access to Coefficient Data Preliminary Data Sheet 4-21 06.99 PEF 24901 Operational Description To read out coefficient data the following programming sequence must be carried out 1. Select the addressed line port by CH_SEL in register DSP_CR1 2. Set DAA to ’1’ in register DSP_CR1. Thereby all coefficients are freezed. 3. Program the DSP Control Register No.2, DSP_CR2 as follows: - Select the proper coefficient type by DATA_TYP (e.g. coefficient set= ’100’) If the same coefficient set is repeatedly read out DSP_TYP must be set to another value and then reset again to the desired coefficient type. This is required to reset internal counters. - Set COM_MOD to ’1’ to enable the handshake mechanism 4. Trigger the read procedure by setting DATA_RW to ’01’ in register DSP_CR2. 5. Read out DSP_RD1..3 registers using either the handshake procedure as described in the chapter before. Preliminary Data Sheet 4-22 06.99 PEF 24901 Operational Description 4.4.6 Boundary Scan The DFE-T V2.1 provides a boundary scan support for a cost effective board testing. It consists of: • • • • • • • Complete boundary scan for 47 signals (pins) according to IEEE 1149.1 specification Test Access Port controller (TAP) Five dedicated pins (TCK, TMS, TDI, TDO, TRST) Pins TRST, TDI and TMS are provided with an internal pullup resistor One 32-bit IDCODE register Pin TRST tied to low resets the Boundary Scan TAP Controller Instructions CLAMP and HIGHZ were added, instruction SSP was removed in V2.1 Boundary Scan All pins except the power supply pins, the "Not Connected" pins and the pins TDI, TDO, TCK, TMS, and TRST are included in the boundary scan chain. Depending on the pin functionality one, two or three boundary scan cells are provided. Table 4-1 Boundary Scan Cells. Pin Type Number of Boundary Scan Cells Usage Input 1 input Output 2 output, enable I/O 3 input, output, enable When the TAP controller is in the appropriate mode data is shifted into or out of the boundary scan via the pins TDI/TDO using the 6.25 MHz clock on pin TCK. The pins are included in the following sequence in the boundary scan chain: • Boundary Scan Number TDI ––> Pin Number Pin Name Type Number of Scan Cells 1. 62 DT I 1 2. 61 CLS3 I/O 3 3. 60 RES I 1 4. 56 SSP I 1 5. 55 SLOT0 I 1 In V2.1 pin 53 is not provided with a BScan cell (N.C.) Preliminary Data Sheet 4-23 06.99 PEF 24901 Operational Description Boundary Scan Number TDI ––> Pin Number Pin Name Type 6. 52 CLS2 I/O 3 7. 51 D3D I/O 3 8. 50 D2D I/O 3 9. 49 TP1 I 1 10. 48 D1D I/O 3 11. 47 D0D I/O 3 12. 46 D3C I/O 3 13. 45 SLOT1 I 1 14. 44 D2C I/O 3 15. 43 D1C I/O 3 16. 42 D0C I/O 3 17. 40 D3B I/O 3 18. 39 D2B I/O 3 19. 37 D1B I/O 3 20. 35 D0B I/O 3 21. 34 D3A I/O 3 22. 33 D2A I/O 3 23. 32 PUP I 1 24. 31 D1A I/O 3 25. 30 D0A I/O 3 26. 29 CLS0 I/O 3 27. 28 ST00 I 1 28. 27 ST01 I 1 29. 26 ST10 I 1 30. 24 ST11 I 1 31. 23 ST20 I/O 3 32. 21 ST21 I/O 3 33. 20 CLS1 I/O 3 34. 19 ST30 I/O 3 35. 18 ST31 I/O 3 Preliminary Data Sheet 4-24 Number of Scan Cells 06.99 PEF 24901 Operational Description Boundary Scan Number TDI ––> Pin Number Pin Name Type Number of Scan Cells 36. 17 SDX I/O 3 37. 16 MTO I 1 38. 15 DOUT I/O 3 39. 14 DIN I 1 40. 13 FSC I 1 41. 12 DCL I 1 42. 11 PDM0 I 1 43. 10 PDM1 I 1 44. 8 PDM2 I 1 45. 7 PDM3 I 1 46. 5 SDR I 1 47. 4 CL15 I 1 TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. Before operation the TAP controller has to be reset by TRST. According to the IEEE 1149 standard 7 instructions are executable. The instructions ’CLAMP’ and ’HIGHZ’ were added. Instruction ’SSP’ is no more supported since its function is identical to that of the SSP pin. • Table 4-2 Code TAP Controller Instructions: Instruction Function 0000 EXTEST External testing 0001 INTEST Internal testing 0010 SAMPLE/PRELOAD Snap-shot testing 0011 IDCODE Reading ID code 0100 CLAMP Reading outputs Preliminary Data Sheet 4-25 06.99 PEF 24901 Operational Description Code Instruction Function 0101 HIGHZ Z-State of all boundary scan output pins 11XX BYPASS Bypass operation EXTEST is used to examine the board interconnections. When the TAP controller is in the state "update DR", all output pins are updated with the falling edge of TCK. When it has entered state "capture DR" the levels of all input pins are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When the TAP controller is in the state "update DR", all inputs are updated internally with the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. 0001 (INTEST) is the default value of the instruction register. SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both activities are transparent to the system functionality. IDCODE Register The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to "1". Version Device Code Manufacturer Code 0001 0000 0000 0110 0111 0000 1000 001 Output 1 --> TDO Note: In the state "test logic reset" the code "0011" is loaded into the instruction code register. CLAMP allows the state of the signals included in the boundary scan driven from the PEF 24901 to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO. These output signals driven from the DFE-T V2.1 will not change while CLAMP is selected. Preliminary Data Sheet 4-26 06.99 PEF 24901 Operational Description HIGHZ sets all output pins included to the boundary scan path into a high impedance state. In this state, an in-circuit test system may drive signals onto the connections normally driven by the DFE-T V2.1 outputs without incurring the risk of damage to the DFE-T V2.1. BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip testing of selected ICs on a printed circuit board. Preliminary Data Sheet 4-27 06.99 PEF 24901 Monitor Commands 5 Monitor Commands This chapter summarizes the Monitor commands and messages that are available in an 4B3T U-Transceiver application. Please refer to section "IOM®-2 Monitor Channel" on page 3-5 for a detailed description of the Monitor handshake procedure. Besides the existing MON-8 commands two new MON classes, MON-0 and MON-12 are introduced. MON-0 commands/messages provide access to the 1kbit/s transparent channel of the 4B3T frame. MON-12 commands allow to address new functions that are available with the 4B3T register map. Defined MON-8 Commands Chip identification, echocanceller coefficients and the block error counter can be readout with two-byte MON-8 commands as given in Table 5-1. Each command is executed after having been transferred by proper use of the handshake procedure. MON-8 commands have the 3rd highest priority. • Table 5-1 Code NT (Hex) D MON-8 Commands LT Function U D U 80 00 RID RID Read Identification requests the U-Transceiver to issue the ID code 80 EF RDS RDS Read and Reset the Block Error Counter ')(7 Specific MON-8 Functions 81 7X SETD Set Relay Driver Pins DiA, DiB, DiC, DiD per port the status of 4 output pins can be set via this MON-8 command, Binary: 1000 0001 0111 DCBA RST Read Request of Status Pins via this MON-8 command information on the current status of general purpose input pins can be retrieved, per port 2 status pins are provided (X= DCBA) 81 00 The indications are summarized in Table 5-2. The messages "Answer Identification", "Answer Block Error Counter Read Request" and "Answer ’RST’ Request" are two-byte messages. Preliminary Data Sheet 5-1 06.99 PEF 24901 Monitor Commands • Table 5-2 Code MON-8 Indications NT LT U D Function (Hex) D U 80 08 AID AID Answer Identification The DFE-T V2.1 replies the ID code. 80 XX ARDS ARDS Answer Block Error Counter Read Request 2nd monitor byte contains the 8-bit counter value ’XX’ ')(7 Specific MON-8 Functions 88 0X (X= 00S1S0) Preliminary Data Sheet AST Answer ’RST’ Request also issued without request on change of either STi0, STi1 pin, Binary: 1000 1000 0000 00S1S0 5-2 06.99 PEF 24901 Monitor Commands Defined MON-0 Commands Following the systematics of 2B1Q MON-0 commands and messages are used to exchange transparent messages via the 4B3T Maintenance-channel. With the MON-0 command ’MWR’ a 8-bit message can be transferred to the DFE-T V2.1. The DFE-T V2.1 then inserts the data bit for bit in the 1kbit/s transparent channel. The NT station stores the received bits until a 8-bit word is complete and sends out an autonomous MON-0 message ’MRD’ which carries the received information. The usage of the transparent channel must be enabled first by bit ’MTRANS’ in register OPMODE. This can be done by a single MON-12 write command. MON-0 commands have the 2nd highest priority (1st MON-12). For more details on the access and synchronization issues please refer to the chapter "IOM®-2 Monitor Channel" on page 3-5. • Table 5-3 Code NT (Hex) D 00 XX MON-0 Commands LT U D MWR MWR Function U Send Transparent Message data ’XX’ is sent via the Transparent channel (M-Bit) across the U-interface • Table 5-4 Code MON-0 Indications NT (Hex) D 00 XX MRD LT U Preliminary Data Sheet D Function U MRD Receive Transparent Message data ’XX’ that was received across the U-interface via the Transparent channel (M-Bit) is output 5-3 06.99 PEF 24901 Register Description 6 Register Description In this section the complete register map is described that is provided with the new MON12 protocol. For the protocol details please refer to page 3-11. The register address arrangement is given in Figure 6-1. The U-interface registers are provided per line port. By register LP_SEL it can be determined which U register bank and by that which line port number is addressed. LP_SEL adds an offset value to the current address. The offset value is latched as long as register LP_SEL is overwritten again. For access to DSP registers the MSB of the 8-bit wide address must be set to ’1’. • + /3B6(/ 5HVHUYHG + %(5& 85HJLVWHUV 85HJLVWHUV $'5 85HJLVWHU %DQNV 2IIVHW /LQH3RUW /3B6(/ + /LQH3RUW /LQH3RUW $'5 + /LQH3RUW + 2302'( ,19 8B&6 + $'5 '635HJLVWHU%DQN + '63B&6 regmap_cust.emf Figure 6-1 DFE-T V2.1 Register Map Preliminary Data Sheet 6-1 06.99 PEF 24901 Register Description 6.1 Register Summary • LP_SEL ADR 7 6 5 4 3 2 1 0 WR/RD 1/n Ch. 10H 0 0 0 0 0 0 LN2 LN1 WR/RD* 1 0 M TRANS 0 0 0 1 0 WR/RD* 1 U-Interface Registers OPMODE 00H 0 MRD 01H M-Bit data of the last 8 received U-frames RD 1/4 MWR 02H M-Bit data of the next 8 transmit U-frames WR 1/4 TEST 05H 0 0 LOOP 06H 0 DLB RDS 07H BERC BER 0 0 0 0 WR/RD* 1/4 0 LBBD LB2 LB1 WR/RD* 1/4 Block Error Counter Value RD 1/4 08H BERC Counter Value (Bit 15-8) RD 1/4 09H BERC Counter Value (Bit 7-0) TRANS U/IOM DSP Registers 7 6 5 4 3 2 1 0 DAA 0 0 0 0 WR/RD* 1 DATA_RW WR/RD* 1 DSP_CR1 80H 0 DSP_CR2 81H 0 0 1 DSP_DREQ 82H 0 0 0 0 0 0 0 DATA _REQ WR 1 DSP_DACK 90H 0 0 0 0 0 0 0 DATA _ACK RD 1 DSP_RD1 91H Coefficient Data RD 1 DSP_RD2 92H Coefficient Data RD 1 DSP_RD3 93H RD 1 CH_SEL DATA_TYP Reserved Coefficient Data *) read-back function for test use Preliminary Data Sheet 6-2 06.99 PEF 24901 Register Description •l Table 6-1 Register Map Reference Table Reg Name Access Address Reset Value Comment Page No. WR 10H 00H Line Port Selection Reg. line port 1 is selected by default 6-4 OPMODE WR 00H 02H Opmode Register LT mode, C/I channel controlled via IOM®-2 6-5 MRD RD 01H 00H M-Bit Read Register value meaningful after an activation 6-6 MWR WR 02H 00H M-Bit Write Register appropriate value must be loaded 6-7 TEST WR 05H 00H TEST Register all test modes disabled 6-8 LOOP WR 06H 00H LOOP Register 6-9 transparent loop mode set, all local loops deactivated RDS RD 07H 00H Running Digital Sum Counter 6-10 BERC RD 08H − 09H 0000H BER Counter Value 6-11 DSP_CR1 WR 80H 00H DSP Control Register 1 all functions enabled 6-12 DSP_CR2 WR 81H 20H DSP Control Register 2 normal operation mode 6-12 DSP_ DREQ WR 82H 00H DSP Data Request Register 6-14 DSP_ DACK RD 90H 00H DSP Data Acknowl. Register 6-15 DSP_RD RD 91H−93H 00H DSP Read Registers U-Interface Registers LP_SEL DSP Registers Preliminary Data Sheet 6-3 6-16 06.99 PEF 24901 Register Description 6.2 Detailed Register Description 6.2.1 LP_SEL - Line Port Selection Register The Line Port Selection register selects the register bank that is associated with the addressed line port. All line port specific register operations - line port specific registers are indicated by a ’4’ in the last column of the register summary - are performed on the line port that is addressed by the value of LP_SEL. LP_SEL read/write Address: 10H Reset value: 00H LN2,1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 LN2 LN1 Line Port Number 00 = Line port no. 0 is addressed by the following command 01 = Line port no. 1 is addressed by the following command 10 = Line port no. 2 is addressed by the following command 11 = Line port no. 3 is addressed by the following command Preliminary Data Sheet 6-4 06.99 PEF 24901 Register Description U-Interface Registers 6.2.2 OPMODE - Operation Mode Register The Operation Mode register determines the operating mode of the DFE-T V2.1. read*)/write OPMODE Address: 00H Reset value: 02H 7 6 5 4 3 2 1 0 0 0 M TRANS 0 0 0 MODE1 =1 MODE0 =0 MTRANS Enable/Disable Transparent Channel (see "Exchanging Transparent Messages" on page 3-22) MODE 1,0 0= Transparent Channel disabled M-channel transports only loop (LT-> NT) and code violation information (NT-> LT), no data is exchanged 1= Transparent Channel enabled transparent messages can be exchanged across the 1kbit/s Mchannel using MON-0 commands and messages Operation Mode Setting 10 = LT mode Preliminary Data Sheet 6-5 06.99 PEF 24901 Register Description 6.2.3 MRD - M-Bit Read The M-Bit Read register contains the data of the last received eight M-bits. Data is shifted into the MRD register as soon as the transmission line is transparent. In combination with the MWR register it is possible to exchange transparent messages across the Uinterface. The value of MRD is output on IOM®-2 in a MON-0 message each time a 8-bit word has been stacked in the MRD register. The autonomous MON-0 message can be used to synchronize the MON-0 ’MWR’ command transmission in the opposite direction. MRD read Address: 01H Reset value: 00H 7 6 5 4 3 2 1 0 M Bit data of the last 8 received U-frames Received transparent channel messages are interpreted as follows ’0’= ’+’= ’-’= is mapped to logic ’1’ if no loop is requested is mapped to logic ’1’ if a loop is requested simultaneously is mapped to logic ’0’ Preliminary Data Sheet 6-6 06.99 PEF 24901 Register Description 6.2.4 MWR - M-Bit Write Register The M-Bit Write register allows to transmit transparent messages across the U-interface. New data that is written to the MWR register is sent in the next 8 subsequent U-frames. After 8 U-frames zeros are sent if the MWR register is not reloaded again in time. A MON-0 command ’MWR’ is provided which allows to overwrite the MWR register value. Use the periodic MON-0 ’MRD’ messages to synchronize the transmission of MON-0 ’MWR’ commands. Note that transparent messages have priority and may override loopback commands. MWR write Address: 02H Reset value: 00H 7 6 5 4 3 2 1 0 M Bit data of the next 8 transmit U-frames MWR data is mapped to the following symbol values 0= is mapped to symbol ’0’ if no loopback is requested is mapped to symbol ’+’ if a loopback is requested at the same time 1= is mapped to symbol ’-’ Preliminary Data Sheet 6-7 06.99 PEF 24901 Register Description 6.2.5 TEST - Test Register The Test register sets the U-transceiver in the desired test mode. Note that the test modes ’Data Through’ and ’Send Single Pulses’ are activated via the C/I channel or by pin strapping. read*)/write TEST Address: 05H Reset value: 00H BER 7 6 0 0 5 4 BER 3 2 1 0 0 0 0 0 Bit Error Rate Measurement Function allows to measure the BER of the B1-, B2- and D-channel in the Transparent state, prerequisite: closed loopback on the NT side a continuous series of zeros is sent 00 = Bit Error Rate (BERC) counter disabled 01 = Reserved 10 = Reserved 11 = Bit Error Rate counter (BERC) is enabled, starts BER measurement for the B1-, B2- and D-channel, zeros are sent in channel B1, B2 and D Preliminary Data Sheet 6-8 06.99 PEF 24901 Register Description 6.2.6 LOOP - Loopback Register The Loop register controls local digital loopbacks of the DFE-T V2.1. The analog loopback (No. 1) and remote loopbacks are closed by use of C/I codes. For the loopback configurations that are available by the LOOP register see also Chapter 4.4.1 on page 4-12. read*)/write LOOP Address: 06H Reset value: 00H DLB TRANS 7 6 5 4 3 2 1 0 0 DLB TRAN S U/ IOM® 0 LBBD LB2 LB1 Close Framer/Deframer loopback 0= Framer/Deframer loopback open 1= Framer/Deframer loopback closed Transparent/ Non-Transparent Loopback in transparent mode data is both passed on and looped back whereas in non-transparent mode data is not forwarded but substituted by ’1’s (idle code) and just looped back Note: has no effect on the analog loopback since ’ARL’ operates always in transparent mode U/IOM® LBBD 0= transparent mode 1= non-transparent mode ’1’s are sent on the IOM®-2 interface in the corresponding time-slot Switch that selects whether looback LB1, LB2 or LBBD is closed towards U or IOM®-2 0= LB1, LB2, LBBD loops are closed towards IOM® 1= LB1, LB2, LBBD loops are closed towards U Close complete loop (B1, B2, D) near the system interface the direction towards the loop is closed is determined by bit ’U/IOM®’ Preliminary Data Sheet 6-9 06.99 PEF 24901 Register Description LB2 0= complete loopback open 1= complete loopback closed Close loop B2 near the system interface the direction towards the loop is closed is determined by bit ’U/IOM®’ LB1 0= loopback B2 open 1= loopback B2 closed Close loop B1 near the system interface the direction towards the loop is closed is determined by bit ’U/IOM®’ 6.2.7 0= loopback B1 open 1= loopback B1 closed RDS - Block Error Counter Register The Block Error Counter register ’RDS’ monitors and counts code violations of the nearend and far-end side. The counter stops at 255 and does not overflow. If the register is read out or if the line is deactivated the block error counter is automatically reset to ’0’. The register value can be requested either by the MON-8 command ’RDS’ or can be directly addressed using the MON-12 protocol. RDS read Address: 07H Reset value: 00H 7 6 5 4 3 2 1 0 Block Error Counter Value Preliminary Data Sheet 6-10 06.99 PEF 24901 Register Description 6.2.8 BERC - Bit Error Rate Counter Register The Bit Error Rate Counter register contains the number of bit errors that occurred during the period the bit TEST.BER was set active. If the register is read out it is automatically reset to ’0’ BERC read Address: 08/09H Reset value: 0000H 15 14 13 12 11 10 9 8 1 0 Bit Error Rate Counter Value 7 6 5 4 3 2 Bit Error Rate Counter Value Preliminary Data Sheet 6-11 06.99 PEF 24901 Register Description 6.2.9 DSP Registers DSP_CR - DSP Control Registers Via the DSP Control register 1 the operational function of the DSP core can be controlled. With the DSP Control register 2 the data type and access direction is determined for the data exchange between the DSP and an external controller. read*)/write DSP_CR1 Address: 80H Reset value: 00H 7 6 0 CH_SEL DAA 5 CH_SEL 4 3 2 1 0 DAA 0 0 0 0 Channel Selection selects the addressed line port - subsequent data transfers are assigned to the selected line port no. 00= selects line port no. 0 01= selects line port no. 1 10= selects line port no. 2 11= selects line port no. 3 Disable all adjust - freeze coefficients line port selective command: takes only effect for the selected line port as set by CH_SEL 0= inactive 1= disables coefficient update Preliminary Data Sheet 6-12 06.99 PEF 24901 Register Description read*)/write DSP_CR2 Address: 81H Reset value: 20H DATA_ TYP DATA_ RW 7 6 5 0 0 1 4 3 DATA_TYP 2 1 0 DATA_RW DSP Data Access Type ’100’ coefficients set 1 ’110’ coefficients set 2 ’001’ coefficients set 3 ’011’ coefficients set 4 Read DSP Data 00 = disabled 01 = read DSP data 10, 11 reserved Preliminary Data Sheet 6-13 06.99 PEF 24901 Register Description DSP_DREQ - DSP Data Request Register The DSP Data Request register contains the handshake signal ’DATA_REQ’ for communication between the DSP and an external microcontroller. DATA_REQ is controlled by an external controller and signals when the layer-1 controller requests new data. DSP_DREQ write Address: 82H Reset value: 00H DATA_ REQ 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DATA _REQ DSP Data Request 0= External controller busy or inactive 1= indicates that the layer-1 controller has read the data and requests new data Preliminary Data Sheet 6-14 06.99 PEF 24901 Register Description DSP_DACK - DSP Data Acknowledge Register The DSP Data Acknowledge register contains the handshake signal ’DATA_ACK’ for communication between the DSP and an external microcontroller. DATA_ACK is controlled by the DSP and signals whether the DSP is busy or ready for new data access. DSP_DACK read Address: 90H Reset value: 00H DATA_ ACK 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DATA _ACK DSP Data Acknowledge 0= DSP DATA register value has been updated 1= DSP busy Preliminary Data Sheet 6-15 06.99 PEF 24901 Register Description DSP_RD - DSP Read Registers The DSP Read Data registers contain the data that have been requested by an external controller. The data type is determined by the setting of the DSP_CR2 register. DSP_RD1 read Address: 91H Reset value: 00H 7 6 5 4 3 2 1 0 Coefficient Data DSP_RD2 read Address: 92H Reset value: 00H 7 6 5 4 3 2 1 0 Coefficient Data DSP_RD3 read Address: 93H Reset value: 00H 7 6 5 4 3 Reserved Preliminary Data Sheet 2 1 0 Coefficient Data 6-16 06.99 PEF 24901 Electrical Characteristics 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit – 40 to 85 °C – 65 to 125 °C – 0.3 to 6 V – 0.3 to VDD + 0.3 (max. 6) V Maximum current on all lines connected to the Imax backplane when the DFE-T V2.1 is without power supply; at 3.3V external signal level TBD mA ESD robustness1) HBM: 1.5 kΩ, 100 pF 2000 V Ambient temperature under bias PEF Storage temperature IC supply voltage Input/Output voltage on any pin with respect to ground 1) TA Tstg VDD VS VESD,HBM According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Operating Range Parameter Symbol Ambient temperature Supply voltage Ground TA VDD VSS Limit Values Unit Test Condition min. max. – 40 85 °C 3.0 3.6 V 0 0 V Note: In the operating range, the functions given in the circuit description are fulfilled. 7.3 DC Characteristics Parameter Input low voltage Input high voltage Preliminary Data Sheet Symbol VIL VIH Limit Values Unit Notes min. max. – 0.3 0.8 2.0 VDD + 0.3 V 7-1 V 06.99 PEF 24901 Electrical Characteristics Parameter Symbol Limit Values min. Output low voltage VOL Output high voltage VOH Avg. power supply current ICC (AV) Unit Notes max. 0.45 2.4 V V TBD mA IOL = 7 mA 1) IOL = 2 mA 2) IOH = – 7 mA 1) IOH = – 2 mA 2) VDD = 3.3 V, TA = 25 °C: DCL = 4.096 MHz Clock = 15.36 MHz Input leakage current IIL -1 1 µA VDD = 3.3 V, VSS = 0 V; all other pins are floating; 0 V< VIN < VDD Output leakage current IOZ -1 1 1) Apply to: DOUT 2) Apply to all the I/O and O pins that do not appear in the list in note 1) µA VDD = 3.3 V, VSS = 0 V; 0 V< VOUT < VDD The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Preliminary Data Sheet 7-2 06.99 PEF 24901 Electrical Characteristics 7.4 AC Characteristics Inputs are driven to 2.4 V for a logical ’1’ and to 0.45 V for a logical ’0’. Timing measurements are made at 2.0 V for a logical ’1’ and 0.8 V for a logical ’0’. The AC testing input/output waveforms are shown in Figure 7-1. • 2.4 V 2.0 V 2.0 V Device Under Test Test Points 0.4 V 0.8 V 0.8 V CL = 100 pF AC_char.vsd Figure 7-1 7.4.1 Input/Output Waveform for AC Tests Reset Timing • Parameter Symbol Limit Values min. Active Low Period tRES Unit Remark ns reset max. 200 is executed 400µs after the low active phase 15.36MHz clock has applied master to be • tRES RES Figure 7-2 Reset Timing Preliminary Data Sheet 7-3 06.99 PEF 24901 Electrical Characteristics 7.4.2 IOM®-2 Interface Timing The dynamic characteristics of the IOM®-2-interface are given in Figure 7-3. In case the period of signals is stated the time reference will be at 1.4 V; in all other cases 0.8 V (low) and 2.0 V (high) thresholds are used as reference. • thF Figure 7-3 IOM®-2 Interface Timing (Double Clock Mode) Table 7-1 IOM®-2 Dynamic Input Characteristics Parameter Symbol Limit Values min. typ. Unit max. DCL rise/fall time tr, tf DCL period TDCL 122 DCL pulse width, high low twH twL <53 <53 FSC rise/fall tr, tf FSC setup time tsF <30 ns FSC hold time thF twFH – tsF ns FSC advance tdF Preliminary Data Sheet 7-4 <60 ns ns 1/2 xTDCL 1/2 xTDCL ns ns <60 ns twL – 30 ns 06.99 PEF 24901 Electrical Characteristics Parameter Symbol Limit Values min. typ. Unit max. FSC pulse width, high low twFH twFL 100 2 × TDCL ns Superframe FSC pulse width, high low twFH twFL 100 1 × TDCL ns DIN setup time tsD <twH + 20 ns DIN hold time thD 50 ns Table 7-2 IOM®-2 Dynamic Output Characteristics Parameter Symbol Limit Values min. typ. Unit max. Test Condition DCL Data delay clock 1) tdDC <100 ns CL = 150 pF FSC Data delay frame 1) tdDF <150 ns CL = 150 pF Notes:1) The point of time at which the output data will be valid is referred to the rising edges of either FSC (tdDF ) or DCL (tdDC ). The rising edge of the signal appearing last (normally DCL) shall be the reference. Preliminary Data Sheet 7-5 06.99 PEF 24901 Electrical Characteristics 7.4.3 Interface to the Analog Front End • SDX tl th tD CL15 tCW tds tdh PDM 0..3 tds tdh SDR Figure 7-4 Dynamic Input and Output Requirements at the Analog Interface • Table 7-3 Dynamic Input Characteristics Parameter Signal Symbol Limit Values min. typ. Unit max. 65 ns Clock period CL15 tcw Pulse width high/ low CL15 th tl 25 25 ns ns Data setup SDR PDM0..3 tds 0 12 ns Data hold SDR PDM0..3 tdh 15 8 ns • Table 7-4 Dynamic Output Characteristics Parameter Signal Symbol Limit Values min. SDX data delay Preliminary Data Sheet SDX typ. max. 22 tD 7-6 Unit ns 06.99 PEF 24901 Electrical Characteristics 7.4.4 Boundary Scan Timing • Figure 7-5 Boundary Scan Timing • Table 7-5 Boundary Scan Dynamic Timing Requirements Parameter Symbol Limit Values min. Unit max. test clock period tTCP 160 - ns test clock period low tTCPL 70 - ns test clock period high tTCPH 70 - ns TMS set-up time to TCK tMSS 30 - ns TMS hold time from TCK tMSH 30 - ns TDI set-up time to TCK tDIS 30 - ns TDI hold time from TCK tDIH 30 - ns TDO valid delay from TCK tDOD - 60 ns Preliminary Data Sheet 7-7 06.99 PEF 24901 Electrical Characteristics 7.5 Capacitances Parameter Symbol Limit Values min. Clock input capacitance CXIN Unit Notes max. TBD pF fC = 1 MHz The pins, which are not under test, are connected to GND CIN COUT Input capacitance Output capacitance 7.6 Power Supply 7.6.1 Supply Voltage VDD to GND 7.6.2 7 pF 10 pF = +3.3V ±0.3V Power Consumption All measurements with random 2B+D data in active states, 3.3V (0°C - 70°C) • Table 7-6 Power Consumption Mode Typ. values Max. values Unit Test conditions Power-up all Channels <50 <70 mA 3.3 V, open outputs, inputs at VDD /VSS Power-down <15 <25 mA 3.3 V, open outputs, inputs at VDD /VSS Preliminary Data Sheet 7-8 06.99 PEF 24901 Package Outlines 8 Package Outlines • GPM05247 P-MQFP-64 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Preliminary Data Sheet 8-1 Dimensions in mm 06.99 PEF 24901 Appendix A: Standards and Specifications 9 Appendix A: Standards and Specifications The table below lists the relevant standards concerning transmission performance the DFE-T V2.1 claims to comply with. • 2UJDQL]DWLRQ 9DOLG IRU 'RFXPHQW ETSI European Telecommunications Standards Institute EU TS 102 080 V1.3.1 (1998-11), formerly called ETR080 Transmission and Multiplexing (TM); Integrated Services Digital Network (ISDN) basic rate access; Digital transmission system on metallic local lines FTZ Fernmeledetechnisches Zentralamt D 1 TR 220 08/91 Spezifikation der ISDNSchnittstelle Uk0 Schicht 1 1 TR 210 11/87 ISDN Aktivierung/ Deaktivierung des Basisanschlusses Schicht 1 1 TR 215 04/90 Euro-ISDN Aktivierung/ Deaktivierung des Basisanschlusses Schicht 1 Preliminary Data Sheet 9-1 06.99 PEF 24901 Glossary 10 Glossary • A/D Analog to digital ADC Analog to digital converter AGC Automatic gain control AIN Differential U-interface input ANSI American National Standardization Institute AOUT Differential U-interface output B1, B2 64-kbit/s voice and data transmission channel BIN Differential U-interface input BOUT Differential U-interface output C/I Command/Indicate (channel) D 16-kbit/s data and control transmission channel D/A Digital-to-analog DAC Digital-to-analog converter DCL Data clock DD Data downstream DT Data through test mode DU Data upstream EC Echo canceller EOM End of message ETSI European Telephone Standards Institute FEBE Far-end block error FIFO First-in first-out (memory) FSC Frame synchronizing clock GND Ground HDLC High-level data link control IEC-Q ISDN-echo cancellation circuit conforming to 2B1Q-transmission code IOM®-2 ISDN-oriented modular 2nd generation INFO U- and S-interface signal as specified by ANSI/ ETSI ISDN Integrated services digital network LBBD Loop-back of B- and D-channels Preliminary Data Sheet 10-1 06.99 PEF 24901 Glossary LT Line termination MON Monitor channel command MR Monitor read bit MTO Monitor procedure time-out MX Monitor transmit bit NEBE Near-end block error NT Network termination PLL Phase locked loop PSD Power spectral density PTT Post, telephone, and telegraph administration PU Power-up RMS Root mean square S/T Two-wire pair interface SSP Send single pulses (test mode) TE Terminal equipment U Single wire pair interface 4B3T Transmission code requiring 120-kHz bandwidth Preliminary Data Sheet 10-2 06.99 PEF 24901 Index 11 Index F FTZ 9-1 Functional Description A G Absolute Maximum Ratings 7-1 AC Characteristics 7-3 Activation 4-3 Activation of Loop#1 4-9 Activation of Loop#2 4-11 Awake Protocol 3-30 Initiated by Exchange 4-4 Initiated by TE 4-5 Analog Loopback (No.1) 4-13 Awake Protocol 3-30 General Purpose I/Os IDCODE 4-26 Insertion Loss Measurement 4-18 Interface to the Analog Front End SDX/SDR Frame Structure 3-14 Timing 7-6 IOM®-2 Interface 3-3 C/I Channel 3-5 Channel Assignment 1-9 Data Rates 1-9 Frame Structure 3-4 Monitor Channel 3-5 Timing 7-4 Bit Error Rate Counter 4-16 Block Diagram 3-2 Block Error Counter 4-16 Boundary Scan 4-23 Timing 7-7 L Local Loopbacks 4-14 Logic Symbol 1-4 Loopback No.2 4-13 C M Maintenance and Test Functions 4-12 Maintenance Channel 3-20 Master-Reset Mode 4-17 MON-0 Commands 5-3 MON-8 Commands 5-1 Monitor Channel 3-5 Monitor Commands 5-1 MONITOR Procedure Time-Out 3-9 3-5 D Data-Through Mode 4-17 DC Characteristics 7-1 Deactivation 4-3 Deactivation 4-8 Descrambler 3-26 O E Electrical Characteristics 7-1 ETSI 9-1 Exchanging Transparent Messages Preliminary Data Sheet 3-16 I B C/I Codes 3-32 Capacitances 7-8 Clock Generation 3-44 Code Violations 3-25 Command/ Indicate Channel 3-1 Operating Range 7-1 P 3-22 Package Outlines 8-1 Pin Descriptions 2-1 I-1 06.99 PEF 24901 Index Pin Diagram 2-1 Pinning Changes 2-8 Power Consumption 7-8 Power Down 4-1 Power Spectral-Density Measurement 18 Power Supply 7-8 Pulse Mask Measurement 4-18 U U-Transceiver 3-17 (De)Scrambler 3-26 4B3T Frame Structure 3-17 4B3T Signal Elements 3-28 C/I Codes 3-32 Decoding Table 3-25 M-Channel 3-20 MMS 43 Coding Table 3-24 State Machine Notation 3-34 4- Q Quiet Mode Measurement 4-18 R Reading/Writing Coefficient Values Register Summary 6-2 Registers DSP 6-12 U-Interface 6-5 Relay Driver Pins 3-16 Pin Description 2-5 Reset 4-1 Timing 7-3 Retrieving DSP Data 4-19 Return-Loss Measurement 4-18 4-21 S Scrambler 3-26 Signal Elements 4B3T 3-28 Single-Pulses Test Mode 4-17 State Machine 3-34 Inputs 3-38 LT State Diagram 3-35 Outputs 3-40 State Description 3-41 State Machine Notation 3-34 Status Pins 3-16 Pin Description 2-5 Supply Voltage 7-8 System Integration 1-5 System Measurements 4-17 T TAP Controller 4-25 Preliminary Data Sheet I-2 06.99