ETC PEF80912

Data Sheet, DS 1, March 2001
Q-SMINT®O
2B1Q Second Gen. Modular ISDN NT
(Ordinary)
PEF 80912/80913 Version 1.3
Wired
C om mu n i ca t i o n s
N e v e r
s t o p
t h i n k i n g .
Edition March 2001
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, DS 1, March 2001
Q-SMINT®O
2B1Q Second Gen. Modular ISDN NT
(Ordinary)
PEF 80912/80913 Version 1.3
Wired
C om mu n i ca t i o n s
N e v e r
s t o p
t h i n k i n g .
PEF 80912/80913
Revision History:
March 2001
Previous Version:
Preliminary Data Sheet 10.00
Page
Subjects (major changes since last revision)
All
Editorial changes, addition of notes for clarification etc.
DS 1
Table 1,
introduced new version 80913 with extended performance of the U-interface
Chapter 1.3
Chapter
2.4.5.1
S-transceiver NT state machine:
added note : ’By setting the Test Mode pins TM0-2 to ’010’ / ’011’: Continuous
Pulses / Single Pulses, the S-transceiver starts sending the corresponding test
signal, but no state transition is invoked.’
Chapter
2.4.5.1
C/I commands: removed ’unconditional command’ from description C/I-command
’DR’
Figure 16
Corrected figure: ’Complete Activation Initiated by Exchange’:
info4 is sent by the NT (not byTE)
Chapter 4.1 Absolute Maximum Ratings: Maximum Voltage on VDD: 4.2V (before: 4.6V)
Chapter 4.1 Refined references for ESD requirements:’ ...(CDM), EIA/JESD22-A114B (HBM) ---’
Chapter 4.2 Input/output leakage current set to 10µA (before: 1µA)
Table 19
U-transceiver characteristics: enhanced S/N+D for 80913 and threshold level for
80912 and 80913 distinguished
Chapter
4.6.3
Parameters of the UVD/POR Circuit:
defined reduced range of hysteresis: min. 30mV/max. 90mV
relaxed upper limit of Detection Threshold to 2.92V (before: 2.9V)
defined max. rising VDD for power-on
Chapter 6.3 External circuitry for T-SMINT updated
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 80912/80913
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.7.1
1.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features PEF 80912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features PEF 80913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Specific Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
2.1
2.2
2.2.1
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.4
2.3.5.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM‚-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2B1Q Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Redundancy Check / FEBE bit . . . . . . . . . . . . . . . . . . . . . . . . . .
Scrambling/ Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine for Line Activation / Deactivation . . . . . . . . . . . . . . . . . .
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard NT State Machine (IEC-Q / NTC-Q Compatible) . . . . . . . .
Inputs to the U-Transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outputs of the U-Transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Metallic Loop Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer between IOM‚-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
15
15
18
18
19
20
20
21
22
24
27
30
32
32
33
34
34
34
37
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . .
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation from Exchange with U Active . . . . . . . . . . . . . . . . . . . . . . . .
Activation from TE with U Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
41
42
43
44
45
46
Data Sheet
2001-03-29
PEF 80912/80913
Table of Contents
Page
3.1.7
3.1.8
3.2
3.2.1
3.2.1.1
3.2.1.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Partial Deactivation with U Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . . .
External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
48
49
50
50
50
51
51
51
53
55
56
4
4.1
4.2
4.3
4.4
4.5
4.6
4.6.1
4.6.2
4.6.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
57
57
58
60
60
61
62
63
65
66
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
Appendix: Differences between Q- and T-SMINT‚O . . . . . . . . . . . . . . .
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Data Sheet
69
69
70
70
71
73
74
2001-03-29
PEF 80912/80913
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Page
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application Example Q-SMINT‚O: Standard NT1 . . . . . . . . . . . . . . . . 12
IOM-2 Frame Structure of the Q-SMINT‚O . . . . . . . . . . . . . . . . . . . . 14
U-Superframe Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
U-Basic Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
U2B1Q Framer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 17
U2B1Q Deframer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . 18
Explanation of State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . 20
Standard NT State Machine (IEC-Q / NTC-Q Compatible) (Footnotes: see
“Dependence of Outputs” on Page 26)
21
Pulse Streams Selecting Quiet Mode . . . . . . . . . . . . . . . . . . . . . . . . . 31
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 33
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . 41
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Complete Deactivation Initiated by Exchange . . . . . . . . . . . . . . . . . . . 43
Partial Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Activation from LT with U Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Activation from TE with U Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Partial Deactivation with U Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Circuitry U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . . 54
External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . . 55
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . . 61
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 62
IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . . 63
IOM-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . . . 63
Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
NTC-Q Compatible State Machine Q-SMINT‚O: 2B1Q . . . . . . . . . . . . 71
IEC-T/NTC-T Compatible State Machine T-SMINT‚O: 4B3T . . . . . . . . 72
External Circuitry Q- and T-SMINT‚O . . . . . . . . . . . . . . . . . . . . . . . . . 74
Data Sheet
2001-03-29
PEF 80912/80913
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Data Sheet
Page
NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LP2I States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
U-Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
U - Transceiver C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timers Used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
U-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
States with Operational Data on IOM‚-2 . . . . . . . . . . . . . . . . . . . . . . . 26
Signal Output on Uk0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
C/I-Code Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ANSI Maintenance Controller States . . . . . . . . . . . . . . . . . . . . . . . . . . 30
U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Reset Input Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Related Documents to the U-Interface. . . . . . . . . . . . . . . . . . . . . . . . . 70
C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Dimensions of External Components. . . . . . . . . . . . . . . . . . . . . . . . . . 75
2001-03-29
PEF 80912/80913
Overview
1
Overview
The PEF 80912 / 80913 (Q-SMINT®O) offers all NT1 features known from the PEB / PEF
8091 [11] and can hence replace the latter in all NT1 applications.
Table 1 summarizes the 2nd generation NT products.
•
Table 1
NT Products of the 2nd Generation
PEF80912 PEF80913 PEF81912 PEF81913 PEF82912 PEF82913
Q-SMINT®O
Q-SMINT®IX
Q-SMINT®I
Package
P-MQFP-44
P-MQFP-64
P-TQFP-64
P-MQFP-64
P-TQFP-64
Register
access
no
U+S+HDLC+ IOM-2
U+S+ IOM-2
Access via
n.a.
parallel (or SCI or
IOM-2)
parallel (or SCI or
IOM-2)
MCLK,
watchdog
timer, SDS,
BCL, Dchannel
arbitration,
IOM-2 access
and
manipulation
etc. provided
no
yes
yes
HDLC
controller
no
yes
no
NT1 mode
available
yes (only)
no
no
Extended UPerformance
20kft
Data Sheet
no
yes
no
1
yes
no
yes
2001-03-29
PEF 80912/80913
Overview
1.1
References
[1]
TS 102 080, Transmission and Multiplexing ; ISDN basic rate access; Digital
transmission system on metallic local lines, ETSI, November 1998
[2]
T1.601-1998 (Revision of ANSI T1.601-1992), ISDN-Basic Access Interface
for Use on Metallic Loops for Application on the Network Side of the NT
(Layer 1 Specification), ANSI, 1998
[3]
ST/LAA/ELR/DNP/822, CNET, France
[4]
RC7355E, 2B1Q Generic Physical Layer Specification, British
Telecommunications plc., 1997
[5]
FZA TS 0095/01:1997-10, Technische Spezifikationen für
Netzabschlußgeräte für den ISDN Basisanschluß (NT-BA), Post & Telekom
Austria, 1997
[6]
pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI,
November 1996
[7]
T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points
(Layer 1 Specification), ANSI, 1991
[8]
I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU,
November 1988
[9]
IEC-Q, ISDN Echocancellation Circuit, PEB 2091 V4.3, User’s Manual
02.95, Siemens AG, 1995
[10]
SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User’s Manual
11.96, Siemens AG, 1996
[11]
NTC-Q, Network Termination Controller (2B1Q), PEB / PEF 8091 V1.1, Data
Sheet 10.97, Siemens AG, 1997
[12]
INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB / PEF 8191
V1.1, Data Sheet 10.97, Siemens AG, 1997
[13]
IOM-2 Interface Reference Guide, Siemens AG, 03.91
[14]
SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.3,
Preliminary Data Sheet 8.99, Infineon Technologies, 1999
[15]
PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH,
September 1997
[16]
Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data
Sheet DS2, Infineon Technologies, July 2000.
Data Sheet
2
2001-03-29
PEF 80912/80913
Overview
•
2B1Q Second Gen. Modular ISDN NT (Ordinary)
Q-SMINT®O
PEF 80912/80913
Version 1.3
1.2
Features PEF 80912
Features known from the PEB / PEF 8091
•
•
•
•
•
•
•
•
Single chip solution including U- and S-transceiver
Perfectly suited for the NT1 in the ISDN
Fully automatic activation and deactivation
P-MQFP-44-2
U-interface (2B1Q) conform to ETSI [1], ANSI [2] and
CNET [3]:
P-MQFT-44
– Meets all transmission requirements on all ETSI,
ANSI and CNET loops with margin
– Conform to British Telecom’s RC7355E [4]
– Compliant with ETSI 10 ms micro interruptions
– MLT input and decode logic (ANSI [2])
S/T-interface conform to ETSI [6], ANSI [7] and ITU [8]
– Supports point-to-point and bus configurations
– Meets and exceeds all transmission requirements
Pin programmable CSO-bit
Optional IOM-2 interface eases chip testing and evaluation
Activation status LED supported
Type
Package
PEF 80912/80913
P-MQFT-44
Data Sheet
3
2001-03-29
PEF 80912/80913
Overview
•
New Features
•
•
•
•
•
•
•
•
•
•
Reduced number of external components for external U-hybrid required
Optional use of up to 2x20Ω resistors on the line side of the transformer (e.g. PTCs)
Pin Uref and the according external capacitor removed
Improved ESD (2 kV instead of <850 V)
Inputs accept 3.3 V and 5 V
I/O (open drain) accepts pull-up to 3.3 V1)
Pin compatible with T-SMINT®O (2nd Generation)
LED indicates Loopback 2 (LBBD)
Power-on reset and Undervoltage Detection with no external components
Lowest power consumption due to
– Low power CMOS technology (0.35µ)
– Newly optimized low power libraries
– High output swing on U- and S-line interface leads to minimized power
consumption
– Single 3.3 Volt power supply
• 200 mW (NTC-Q: 285 mW) power consumption with random data over ETSI Loop 2.
• 15 mW typical power consumption in power down (NTC-Q: 28 mW)
1.3
Features PEF 80913
The Q-SMINT®O PEF 80913 provides all features of the PEF 80912. Additionally, a
significantly enhanced performance of the U-interface as compared to ETSI [1], ANSI
[2] and CNET [3] requirements is guaranteed:
Transparent transmission on 20kft AWG26 with a BER < 10-7 (without noise).
1)
Pull-ups to 5 V must be avoided. A so-called ’hot-electron-effect’ would lead to long term degradation.
Data Sheet
4
2001-03-29
PEF 80912/80913
Overview
1.4
Not Supported are ...
• Integrated U-hybrid
• ’NT-Star’ with star point on the IOM®-2 bus (already not supported in NTC-Q).
• The oscillator architecture was changed with respect to the NTC-Q to reduce power
consumption. As a consequence, the Q-SMINT®O always needs a crystal and pin XIN
can not be connected to an external clock as it was possible for IEC-Q and NTC-Q.
This does not limit the use of the Q-SMINT®O in NTs since all NT designs use crystals
anyway.
1.5
Pin Configuration
33 32 31 30 29
28 27 26
DD
/LP2I
DU
TP1
PS2
SX1
VDDa_SX
VSSa_SX
SX2
SR2
SR1
•
25 24 23
/VDDDET
TP2
34
22
FSC
35
21
VDDa_SR
VSSa_SR
PS1
XOUT
XIN
BOUT
VDDa_UX
VSSa_UX
AOUT
36
20
DCL
VSSD
37
19
VDDD
18
BUS
17
CSO
16
AUA
41
15
42
14
43
13
TM2
TM1
TM0
/ACT
Q-SMINTO
PEF 80912
PEF 80913
38
39
40
44
Figure 1
Data Sheet
7
8
9
10 11
MTI
6
VSSD
/TLL
5
VDDD
4
/RSTO
DIO
3
AIN
BIN
VSSa_UR
VDDa_UR
2
/RST
12
1
pin_2.vsd
Pin Configuration
5
2001-03-29
PEF 80912/80913
Overview
1.6
Block Diagram
•
XIN
VDDDET
XOUT
RST RSTO
PS1
PS2
MTI
SR1
Clock Generation
POR/UVD
AOUT
SR2
BOUT
SX1
SX2
S-Transceiver
U-Tansceiver
AIN
BIN
TM0
TM1
TM2
Factory Test
TP1
TP2
Test Modes
LED
DIO
IOM-2 Interface
FSC
DCL
DU
ACT
LP2I
U/S Transceiver Control
DD
BUS
AUA CSO
TLL
block diagram.vsd
Figure 2
Data Sheet
Block Diagram
6
2001-03-29
PEF 80912/80913
Overview
1.7
Pin Definitions and Functions
•
Table 2
Pin Definitions and Functions
Pin
Symbol
Type
Function
2
VDDa_UR
–
Supply voltage for U-Receiver
(3.3 V ± 5 %)
1
VSSa_UR
–
Analog ground (0 V) U-Receiver
42
VDDa_UX
–
Supply voltage for U-Transmitter
(3.3 V ± 5 %)
43
VSSa_UX
–
Analog ground (0 V) U-Transmitter
36
VDDa_SR
–
Supply voltage for S-Receiver
(3.3 V ± 5 %)
37
VSSa_SR
–
Analog ground (0 V) S-Receiver
31
VDDa_SX
–
Supply voltage for S-Transmitter
(3.3 V ± 5 %)
30
VSSa_SX
–
Analog ground (0 V) S-Transmitter
19
VDDD
–
Supply voltage digital circuits
(3.3 V ± 5 %)
20
VSSD
–
Ground (0 V) digital circuits
8
VDDD
–
Supply voltage digital circuits
(3.3 V ± 5 %)
9
VSSD
–
Ground (0 V) digital circuits
22
FSC
O
Frame Sync:
8-kHz frame synchronization signal
21
DCL
O
Data Clock:
IOM-2 interface clock signal (double clock):
512 kHz
25
LP2I
O
Loopback 2 indication:
Can directly drive a LED (4 mA).
0: LBBD received, Loopback 2 closed
1: Loopback 2 not closed.
23
DD
O
Data Downstream:
Data on the IOM-2 interface
24
DU
O
Data Upstream:
Data on the IOM-2 interface
Data Sheet
7
2001-03-29
PEF 80912/80913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
7
DIO
I
Disable IOM-2:
1: FSC, DCL, DU and DD high Z
0: FSC, DCL, DU and DD push-pull
16
AUA
I
Auto U Activation:
1: U-transceiver attempts one automatic
activation after reset. Tie to ’0’ in applications
that do not require auto-start after reset.
17
CSO
I
Cold Start Only:
’1’ selects CSO-bit to ’0’. (normal)
’0’ selects CSO-bit to ’1’. (special cases)
The pin only controls the CSO-bit in the Uframe. The U-transceiver itself is always a
warm-start transceiver according to ANSI and
ETSI.
18
BUS
I
(PU)
Bus mode on S-interface:
1: passive S-bus (fixed timing)
0: point-to-point / extended passive S-bus
(adaptive timing)
5
RST
I
Reset:
Low active reset input. Schmitt-Trigger input
with hysteresis of typical 360 mV. Tie to ’1’ if not
used.
6
RSTO
OD
Reset Output:
Low active reset output.
10
TLL
I
Triple-Last-Look
Select validation algorithm for received M4 bit
towards state machine:
’0’: CRC & TLL
’1’: CRC
13
TM0
I
Test Mode 0
Selects test pattern (see Page 11).
14
TM1
I
Test Mode 1
Selects test pattern (see Page 11).
15
TM2
I
Test Mode 2
Selects test pattern (see Page 11).
Data Sheet
8
2001-03-29
PEF 80912/80913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
28
SX1
O
S-Bus Transmitter Output (positive)
29
SX2
O
S-Bus Transmitter Output (negative)
32
SR1
I
S-Bus Receiver Input
33
SR2
I
S-Bus Receiver Input
40
XIN
I
Crystal 1:
Connected to a 15.36 MHz crystal
39
XOUT
O
Crystal 2:
Connected to a 15.36 MHz crystal
44
AOUT
O
Differential U-interface Output
41
BOUT
O
Differential U-interface Output
3
AIN
I
Differential U-interface Input
4
BIN
I
Differential U-interface Input
34
VDDDET
I
VDD Detection:
This pin selects if the VDD detection is active
(’0’) and reset pulses are generated on pin
RSTO or whether it is deactivated (’1’) and an
external reset has to be applied on pin RST.
11
MTI
I
Metallic Termination Input.
Input to evaluate Metallic Termination pulses.
Tie to ’1’ if not used.
38
PS1
I
Power Status (primary).
The pin status is passed to the overhead bit
’PS1’ in the U frame to indicate the status of the
primary power supply (’1’ = ok).
26
PS2
I
Power Status (secondary).
The pin status is passed to the overhead bit
’PS2’ in the U frame to indicate the status of the
secondary power supply (’1’ = ok).
Data Sheet
9
2001-03-29
PEF 80912/80913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
12
ACT
O
Activation LED.
Indicates the activation status of U- and Stransceiver. Can directly drive a LED (4 mA).
27
TP1
I
Test Pin 1.
Used for factory device test.
Tie to VSS
35
TP2
I
Test Pin 2.
Used for factory device test.
Tie to VSS
PU: Internal pull-up resistor (typ. 100 µA)
I: Input
O: Output (Push-Pull)
OD: Output (Open Drain)
1.7.1
Specific Pins
LED Pins ACT, LP2I
A LED can be connected to pin ACT to display four different states (off, slow flashing,
fast flashing, on). It displays the activation status of the U- and S-transceiver according
to Table 3.
with:
Table 3
ACT States
Pin ACT
LED
U_Deactivated
U_Activated
S_Activated
VDD
off
1
x
x
8Hz
8Hz
0
0
x
1Hz
1Hz
0
1
0
GND
on
0
1
1
U_Deactivated: ’Deactivated State’ as defined in Chapter 2.3.5.5.
U_Activated: ’Synchronized 1’, ’Synchronized 2’, ’Wait for ACT’, ’Transparent’, ’Error S/
T’, ’Pend. Deact. S/T’, ’Pend. Deact. U’ as defined in Chapter 2.3.5.5.
S-Activated: ’Activated State’ as defined in Chapter 2.4.5.
Data Sheet
10
2001-03-29
PEF 80912/80913
Overview
Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this
additional LED to 3.3 V only).
Another LED can be connected to pin LP2I to indicate an active Loopback 2 according
to Table 4.
Table 4
LP2I States
Pin LP2I
LED
EOC-Command LBBD
VDD
off
received no EOC-LBBD or received RTN after an LBBD
command.
GND
on
EOC-command LBBD (50) has been received. Complete
analog loop is being closed on the S-interface.
Test Modes
Different test patterns on the U- and S-interface can be generated via pins TM0-2
according to Table 5.
Table 5
Test Modes
TM0
TM1
TM2
U-transceiver
S-transceiver
0
0
0
0
0
1
Reserved for future use. Normal operation in this
version.
0
1
0
Normal operation
0
1
1
1
0
0
Data Through3)
1
0
1
Send Single Pulses4)
1
1
0
Quiet Mode5)
1
1
1
normal operation
96 kHz1)
Continuous Pulses
2 kHz2) Single Pulses
Normal operation
1)
The S-transceiver transmits pulses with alternating polarity at a rate of 192 kHz resulting in a 96 kHz envelope.
2)
The S-transceiver transmits pulses with alternating polarity at a rate of 4 kHz resulting in a 2 kHz envelope.
3)
Forces the U-transceiver into the state ’Transparent’ where it transmits signal SN3T.
4)
Forces the U-transceiver to go into state ’Test’ and to send single pulses. The pulses are issued at 1.5 ms
intervals and have a duration of 12.5 µs.
5)
The U-transceiver is hardware reset.
Data Sheet
11
2001-03-29
PEF 80912/80913
Overview
1.8
System Integration
The Q-SMINTO provides NT1 functionality without a microcontroller being necessary.
Special selections can be done via pin strapping (CSO, TLL, BUS, etc.). The device has
no µP interface.
The IOM-2 Interface serves only for monitoring and debugging purposes. It can be
regarded as a window to the internal IOM-2.
.
•
DC/DC-Converter
IDCC
PEB2023
S/T - Interface
Q-SMINTO
PEF80912
PEF 80913
S
IOM-2
LEDs
U - Interface
U
Pin Strap - Mode Selection
- Loop 2 Ind. - Disable IOM - 2
- P - to - P / Bus Selection
- Activation
- M4 Bit Validation Algorithm
Status
- CSO - bit Polarity
- U - Activation after Reset
- Test Pattern Selection
Figure 3
Data Sheet
MLT
NT1_appl.vsd
Application Example Q-SMINTO: Standard NT1
12
2001-03-29
PEF 80912/80913
Functional Description
2
Functional Description
2.1
Reset Generation
External Reset Input
At the RST input an external reset can be applied forcing the Q-SMINTO in the reset
state. This external reset signal is additionally fed to the RSTO output.
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
tDEACT (see Table 22).
Reset Generation
The Q-SMINTO has an on-chip reset generator based on a Power-On Reset (POR)
and Under Voltage Detection (UVD) circuit (see Table 22). The POR/UVD requires no
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on VDD ramp-up during power-on reset are described in
Chapter 4.6.3.
Clocks and Data Lines During Reset
During reset the data clock (DCL) and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD is ’DR’ = 0000
• The output C/I code from the S-Transceiver on DU is ’TIM’ = 0000.
Data Sheet
13
2001-03-29
PEF 80912/80913
Functional Description
2.2
IOM-2 Interface
The IOM-2 interface always operates in NT mode according to the IOM-2 Reference
Guide [13].
2.2.1
IOM-2 Functional Description
The IOM-2 interface consists of four lines: FSC, DCL, DD, DU. The rising edge of FSC
indicates the start of an IOM-2 frame. The DCL clock signal synchronizes the data
transfer on both data lines DU and DD. The DCL is twice the bit rate. The bits are shifted
out with the rising edge of the first DCL clock cycle.
Note: It is not possible to write any data via IOM-2 into the Q-SMINTO.
The IOM-2 interface can be enabled/disabled with pin DIO.
The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the
transmit line is determined by the frequency of the DCL clock, with the 512 kHz clock 1
channel consisting of 4 timeslots is available.
IOM®-2 Frame Structure of the Q-SMINTO
The frame structure on the IOM-2 data ports (DU,DD) of the Q-SMINTO with a DCL
clock of 512 kHz is shown in Figure 4.
•
Figure 4
IOM-2 Frame Structure of the Q-SMINTO
The frame is composed of one channel:
Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (not available in Q-SMINTO) and a command/indication channel
(CI0) for control of e.g. the U-transceiver.
Data Sheet
14
2001-03-29
PEF 80912/80913
Functional Description
2.3
U-Transceiver
The state machine of the U-Transceiver is based on the NT state machine in the PEB /
PEF 8091 documentation [11].
Basic configurations are selected via pin strapping.
2.3.1
2B1Q Frame Structure
Transmission on the U2B1Q-interface is performed at a rate of 80 kbaud. The code used
is reducing two bits to one quaternary symbol (2B1Q).
Data is grouped together into U-superframes of 12 ms each. Each superframe consists
of eight basic frames which begin with a synchronization word and contain 222 bits of
information. The first basic frame of a superframe starts with an inverted synchword
(ISW) compared to the other basic frames (SW). The structure of one U-superframe is
illustrated in Figure 5 and Figure 6.
ISW
1. Basic Frame
SW
2. Basic Frame
...
SW
8. Basic Frame
<---12 ms--->
Figure 5
U-Superframe Structure
•
(I) SW
(Inverted) Synch Word
18 Bit (9 Quat)
12 × 2B + D
User Data
216 Bits (108 Quat)
M1 – M6
Maintenance Data
6 Bits (3 Quat)
<---1,5 ms--->
Figure 6
U-Basic Frame Structure
Out of the 222 information bits 216 contain 2B + D data from 12 IOM®-frames, the
remaining 6 bits are used to transmit maintenance information. Thus 48 maintenance
bits are available per U-superframe. They are used to transmit two EOC-messages (24
bit), 12 Maintenance (overhead) bits and one checksum (12 bit).
Data Sheet
15
2001-03-29
PEF 80912/80913
Functional Description
•
Table 6
U-Superframe Format
Framing
2B +
D
Overhead Bits (M1 – M6)
Quat
Position
s
1–9
10 –
117
118 s
118 m 119 s
119 m
120 s
120 m
Bit
Position
s
1 – 18
19 –
234
235
236
237
238
239
240
2B +
D
M1
M2
M3
M4
M5
M6
Super
Basic
Sync
Frame # Frame # Word
1
1
ISW
2B +
D
EOC
a1
EOC
a2
EOC
a3
ACT/
ACT
1
1
2
SW
2B +
D
EOC
dm
EOC
i1
EOC
i2
DEA /
PS1
1
FEBE
3
SW
2B +
D
EOC
i3
EOC
i4
EOC
i5
SCO/
PS2
CRC1 CRC2
4
SW
2B +
D
EOC
i6
EOC
i7
EOC
i8
1/ NTM CRC3 CRC4
5
SW
2B +
D
EOC
a1
EOC
a2
EOC
a3
1/ CSO CRC5 CRC6
6
SW
2B +
D
EOC
dm
EOC
i1
EOC
i2
1
CRC7 CRC8
7
SW
2B +
D
EOC
i3
EOC
i4
EOC
i5
UOA /
SAI
CRC9 CRC
10
8
SW
2B +
D
EOC
i6
EOC
i7
EOC
i8
AIB /
NIB
CRC
11
CRC
12
2,3…
LT- to NT dir. > /
–
–
–
–
ISW
SW
CRC
EOC
– ACT
Inverted Synchronization Word (quad):
Synchronization Word (quad):
Cyclic Redundancy Check
Embedded Operation Channel
a
d/m
i
Activation bit
ACT
Data Sheet
< NT- to LT dir.
–3–3+3+3+3–3+3–3–3
+3+3–3–3–3+3–3+3+3
= address bit
= data / message bit
= information (data / message)
= (1) –> Layer 2 ready for communication
16
2001-03-29
PEF 80912/80913
Functional Description
–
–
–
–
–
–
–
–
–
–
–
–
DEA
CSO
UOA
SAI
FEBE
PS1
PS2
NTM
AIB
NIB
SCO
1
Deactivation bit
DEA
Cold Start Only
CSO
U-Only Activation
UOA
S-Activity Indicator
SAI
Far-end Block Error
FEBE
Power Status Primary Source
PS1
Power Status Secondary Source PS2
NT-Test Mode
NTM
Alarm Indication Bit
AIB
Network Indication Bit
NIB
Start on Command only bit
(currently not defined by ANSI/ETSI)
= (0) –> LT informs NT that it will turn off
= (1) –> NT-activation with cold start only
= (0) –> U-only activated
= (0) –> S-interface is deactivated
= (0) –> Far-end block error occurred
= (1) –> Primary power supply ok
= (1) –> Secondary power supply ok
= (0) –> NT busy in test mode
= (0) –> Interruption (according to ANSI)
= (1) –> no function (reserved for network use)
can be accessed by the system interface for proprietary use
The principle signal flow is depicted in Figure 7 and Figure 8. The data is first grouped
in bits that are covered by the CRC and bits that are not. After the CRC generation the
bits are arranged in the proper sequence according to the 2B1Q frame format, encoded
and finally transmitted.
In receive direction the data is first decoded, descrambled, deframed and handed over
for further processing.
•
U2B1Q-Fram e r
Tone/Pulse
Patterns
M
U
X
(M-bit handling acc. to ETR080)
Sync/Inv. Sync
M1,2,3 (EOC)
2B+D, M4
2B1Q Encoding
M
U
X
Scrambler
M5,6 except CRC
M
U
X
CRC Generation
M
U
X
M4
2B+D
Control
uframer.emf
Figure 7
Data Sheet
U2B1Q Framer - Data Flow Scheme
17
2001-03-29
PEF 80912/80913
Functional Description
•
U2B1Q-Deframer
M1,2,3 (EOC)
(M-bit handling acc. to ETR080)
M5,6 except CRC
2B1Q Decoding
D
E
M
U
X
D
E
M
U
X
Descrambler
Sync/Inv. Sync
CRC Check
D
E
M
U
X
M4
2B+D
Control
udeframer.emf
Figure 8
2.3.2
U2B1Q Deframer - Data Flow Scheme
Cyclic Redundancy Check / FEBE bit
An error monitoring function is implemented covering the 2B + D and M4 data
transmission of a U-superframe by a Cyclic Redundancy Check (CRC).
The computed polynomial is:
G (u) = u12 + u11 + u3 + u2 + u + 1
(+ modulo 2 addition)
The check digits (CRC bits CRC1, CRC2, …, CRC12) generated are transmitted in the
U-superframe. The receiver will compute the CRC of the received 2B + D and M4 data
and compare it with the received CRC-bits generated by the transmitter.
A CRC-error will be indicated to both sides of the U-interface, as a NEBE (Near-end
Block Error) on the side where the error is detected, as a FEBE (Far-end Block Error) on
the remote side. The FEBE-bit will be placed in the next available U-superframe
transmitted to the originator.
2.3.3
Scrambling/ Descrambling
The scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are
transmitted. The scrambling / descrambling process is controlled fully by the QSMINTO. Hence, no influence can be taken by the user.
Data Sheet
18
2001-03-29
PEF 80912/80913
Functional Description
2.3.4
C/I Codes
The operational status of the U-transceiver is controlled by the Control/Indicate channel
(C/I-channel).
Table 7 presents all defined C/I codes.
An indication is issued permanently by the U-transceiver on DD until a new indication
needs to be forwarded. Because a number of states issue identical indications it is not
possible to identify every state individually.
•
Table 7
U - Transceiver C/I Codes
Code
IN
OUT
0000
TIM
DR
0001
RES
–
0010
–
–
0011
–
–
0100
EI1
EI1
0101
SSP
–
0110
DT
–
0111
–
PU
1000
AR
AR
1001
–
–
1010
ARL
ARL
1011
–
–
1100
AI
AI
1101
–
–
1110
–
AIL
1111
DI
DC
AI: Activation Indication
AIL: Activation Indication Loop
AR: Activation Request
ARL: Activation Request Local Loop
DC: Deactivation Confirmation
DI: Deactivation Indication
DR: Deactivation Request
Data Sheet
19
2001-03-29
PEF 80912/80913
Functional Description
DT: Data Through test mode
EI1: Error Indication 1
PU: Power-Up
RES: Reset
SSP: Send Single Pulses test mode
TIM: Timing request
2.3.5
State Machine for Line Activation / Deactivation
2.3.5.1
Notation
The state machines control the sequence of signals at the U-interface that are generated
during the start-up procedure. The informations contained in the following state diagrams
are:
–
–
–
–
–
–
State name
U-signal transmitted
Overhead bits transmitted
C/I-code transmitted
Transition criteria
Timers
Figure 9 shows how to interpret the state diagrams.
•
IN
Signal Transmitted
to U-Interface
(general)
Single Bit
Transmitted
to U-Interface
State Name
Indication Transmitted on C/I-Channel
(DOUT)
ITD04257.vsd
OUT
Figure 9
Explanation of State Diagram Notation
Combinations of transition criteria are possible. Logical “AND” is indicated by “&” (TN &
DC), logical “OR” is written “or” and for a negation “/” is used. The start of a timer is
indicated with “TxS” (“x” being equivalent to the timer number). Timers are always
started when entering the new state. The action resulting after a timer has expired is
indicated by the path labelled “TxE”.
Data Sheet
20
2001-03-29
PEF 80912/80913
Functional Description
2.3.5.2
Standard NT State Machine (IEC-Q / NTC-Q Compatible)
•
T14S
.
SN0
T14S
TL
Pending Timing
DC
Any State
SSP or
C/I= 'SSP'
.
SN0
Deactivated
DC
T14E
T14S
DI
SP
TIM
.
DI
Test
DR
.
SN0
.
SN0
IOM Awaked
PU
AR or TL
T1S, T11S
DI
DI & NT-AUTO
Reset
Any State
Pin-RST or
C/I= 'RES'
AR or TL
DR
.
TN
Alerting 1
DR
.
TN
Alerting
PU
T1S
T11S
DC
T11E
T11E
ARL
T12S
.
SN1
EC-Training
DC
EC-Training AL
DC
LSUE
or T1E
BBD1 & SFD
SN3T
act=0
Analog Loop Back
.
SN1
EC-Training 1
DR
DI
LSEC or T12E
LSEC or T12E
act=0
SN3
Wait for SF AL
DC
T12S
T12S
.
SN1
T1S,
T11S
..
SN0
EQ-Training
DC
BBD0 & FD
T20S
LSUE
or T1E
AR
.
SN2
Wait for SF
DC
T20E &
BBD0 & SFD
LOF
LOF
SN3/SN3T 1) act=0
Synchronized 1
DI
1)
SN3/SN3T act=1/0
Pend.Deact. S/T
DR
3)
dea=0
LSUE
dea=0
LSUE
DC
uoa=1
LOF
SN3/SN3T 1) act=0
Synchronized 2
2)
AR/ARL
uoa=0
dea=0
LSUE
Al
LOF
SN3/SN3T 1) act=1
Wait for Act
2)
El1
AR/ARL
act=1
LOF
Any State
DT or
C/I='DT'
El1
uoa=0
dea=0
LSUE
act=0
act=1
SN3T
Transparent
2)
AI/AIL
uoa=0
LSUE
act=1 & Al
SN3/SN3T 1) act=0
Error S/T
act=0
2)
AR/ARL
.
SN0
Pend Receive Res.
T13S
EI1
LSU or ( /LOF & T13E )
T7E & DI
Figure 10
Data Sheet
T7S
.
SN0
Receive Reset
DR
LOF
Yes
dea=0
dea=0
uoa=1
?
No
uoa=0
LSUE
dea=1
1)
SN3/SN3T act=1/0 3)
LOF
Pend.Deact. U
DC
LSU
T7S
TL
Standard NT State Machine (IEC-Q / NTC-Q Compatible) (Footnotes:
see “Dependence of Outputs” on Page 26)
21
2001-03-29
PEF 80912/80913
Functional Description
Note: The test modes ’Data Through‘ (DT), ‘Send Single Pulses‘ (SSP) and ‘Quiet Mode‘
(QM) can be generated via pins TM0-2 according to Table 5.
If the Metallic Loop Termination is used, then the U-transceiver is forced into the
states ‘Reset‘ and ‘Transparent‘ by valid pulse streams on pin MTI according to
Table 13.
2.3.5.3
Inputs to the U-Transceiver:
C/I-Commands:
AI
Activation Indication
The downstream device issues this indication to announce that its layer-1 is
available. The U-transceiver informs the LT side by setting the “ACT” bit to “1”.
AR
Activation Request
The U-transceiver is requested to start the activation process by sending the wakeup signal TN.
ARL
Activation Request Local Loop-back
The U-transceiver is requested to operate an analog loop-back (close to the Uinterface) and to begin the start-up sequence by sending SN1 (without starting timer
T1). This command may be issued only after the U-transceiver has been HW- or SWreset. This eases that the EC- and EQ-coefficient updating algorithms converge
correctly. The ARL-command has to be issued continuously as long as the loop-back
is required.
DI
Deactivation Indication
This indication is used during a deactivation procedure to inform the U-transceiver
that it may enter the deactivated (power-down) state.
DT
Data Through
This unconditional command is used for test purposes only and forces the Utransceiver into the “Transparent” state.
EI1
Error Indication 1
The downstream device indicates an error condition (loss of frame alignment or loss
of incoming signal). The U-transceiver informs the LT-side by setting the ACT-bit to
“0” thus indicating that transparency has been lost.
RES
Reset
Unconditional command which resets the U-transceiver.
SSP
Send Single Pulses
Unconditional command which requests the transmission of single pulses on the
U-interface.
TIM
Timing
The U-transceiver is requested to enter state ’IOM-2 Awaked’.
Data Sheet
22
2001-03-29
PEF 80912/80913
Functional Description
U-Interface Events:
ACT = 0/1
ACT-bit received from LT-side.
– ACT = 1 requests the U-transceiver to transmit transparently in both directions. In
the case of loop-backs, however, transparency in both directions of transmission is
established when the receiver is synchronized.
– ACT = 0 indicates that layer-2 functionality is not available.
DEA = 0/1
DEA-bit received from the LT-side
– DEA = 0 informs the U-transceiver that a deactivation procedure has been started
by the LT-side.
– DEA = 1 reflects the case when DEA = 0 was detected by faults due to e.g.
transmission errors and allows the U-transceiver to recover from this situation.
UOA = 0/1
UOA-bit received from network side
– UOA = 0 informs the U-transceiver that only the U-interface is to be activated. The
S/T-interface must be deactivated.
– UOA = 1 requests the S/T-interface (if present) to activate.
Timers
The start of timers is indicated by TxS, the expiry by TxE. Table 8 shows which timers
are used:
•
Table 8
Timers Used
Timer
Duration
(ms)
Function
T1
15000
Supervisor for start-up
T7
40
Hold time
Receive reset
T11
9
TN-transmission
Alerting
T12
5500
Supervisor EC-converge
EC-training
T13
15000
Frame synchronization
Pend. receive
reset
T14
0.5
Hold time
Pend. timing
T20
10
Hold time
Wait for SF
Data Sheet
State
23
2001-03-29
PEF 80912/80913
Functional Description
2.3.5.4
Outputs of the U-Transceiver:
The following signals and indications are issued on IOM®-2 (C/I-indications) and on the
U-interface (predefined U-signals):
C/I-Indications
AI
Activation Indication
The U-transceiver has established transparency of transmission. The downstream
device is requested to establish layer-1 functionality.
AIL
Activation Indication Loopback
The U-transceiver has established transparency of transmission. The downstream
device is requested to establish a loopback #2.
AR
Activation Request
The downstream device is requested to start the activation procedure.
ARL
Activation Request Loop-back
The U-transceiver has detected a loop-back 2 command in the EOC-channel and has
established transparency of transmission in the direction IOM®-2 to U-interface. The
downstream device is requested to start the activation procedure and to establish a
loopback #2.
DC
Deactivation Confirmation
Idle code on the IOM®-2-interface.
DR
Deactivation Request
The U-transceiver has detected a deactivation request command from the LT-side for
a complete deactivation or a S/T only deactivation. The downstream device is
requested to start the deactivation procedure.
EI1
Error Indication 1
The U-transceiver has entered a failure condition caused by loss of framing on the
U-interface or expiry of timer T1.
Signals on U-Interface
The signals SNx, TN and SP transmitted on the U-interface are defined in Table 9.
•
Table 9
U-Interface Signals
Signal
Synch. Word
(SW)
Superframe
(ISW)
2B + D
M-Bits
TN 1)
±3
±3
±3
±3
SN0
no signal
no signal
no signal
no signal
SN1
present
absent
1
1
SN2
present
absent
1
1
SN3
present
present
1
normal
Data Sheet
24
2001-03-29
PEF 80912/80913
Functional Description
Table 9
U-Interface Signals(cont’d)
Signal
Synch. Word
(SW)
Superframe
(ISW)
2B + D
M-Bits
SN3T
present
present
normal
normal
test signal
test signal
test signal
test signal
Test Mode
SP2)
Note:
1)
Note:
2)
Alternating ± 3 symbols at 10 kHz.
A series of single pulses spaced at intervals of 1.5 ms; alternating +/-3.
Input Signals of the State Machine and related U-Signals
The table below summarizes the input signals that control the NT state machine and that
are extracted from the U-interface signal sequences.
•
LOF
Loss of framing
This condition is fulfilled if framing is lost for 573 ms.
LSEC
Loss of signal behind echo canceller
Internal Signal which indicates that the echo canceller has converged
LSU
Loss of Signal on U-Interface
This signal indicates that a loss of signal level for a duration of 3 ms has
been detected on the U-interface. This short response time is relevant in
all cases where the NT waits for a response (no signal level) from the LTside.
LSUE
Loss of Signal on U-Interface - Error condition
After a loss of signal has been noticed, a 588 ms timer is started. When
it has elapsed , the LSUE-criterion is fulfilled. This long response time
(see also LSU) is valid in all cases where the NT is not prepared to lose
signal level i.e. the LT has stopped transmission because of loss of
framing, an unsuccessful activation, or the transmission line is
interrupted.
FD
Frame Detected
SFD
Super Frame Detected
Data Sheet
25
2001-03-29
PEF 80912/80913
Functional Description
BBD0 /
BBD1
BBD0/1 Detected
These signals are set if either ’1' (BBD1) or ’0' (BBD0) were detected in
4 subsequent basic frames. It is used as a criterion that the receiver has
acquired frame synchronization and both its EC- and EQ-coefficients
have converged. BBD0 corresponds to the received signal SL2 in case
of a normal activation, BBD1 corresponds to the internally received
signal SN3 in case of analog loop back.
TL
Awake tone detected
The U-transceiver is requested to start an activation procedure.
Signals on IOM-2
The Data (B+B+D) is set to all ’1’s in all states besides the states listed in Table 10.
•:
Table 10
States with Operational Data on IOM-2
Synchronized1
Synchronized2
Wait for ACT
Transparent
Error S/T
Pend. Deac. S/T
Pend. Deac. U
Analog Loop Back
Dependence of Outputs
• Outputs denoted with 1) in Figure 10:
Signal output on Uk0 depends on the received EOC command and on the history of
the state machine according to Table 11:
•
Table 11
Signal Output on Uk0
EOC Command
History of the State Machine
received ’LBBD’
no influence
SN3T
received no ’LBBD’ or ’RTN’ state ’Transparent’ has not been
after an ’LBBD’
reached previously during this
activation procedure
state ’Transparent’ has been
reached previously during this
activation procedure
Data Sheet
Signal output on Uk0
26
SN3
SN3T
2001-03-29
PEF 80912/80913
Functional Description
• Outputs denoted with 2) in Figure 10:
C/I-code output depends on received EOC-command ’LBBD’ according to Table 12:
•
Table 12
C/I-Code Output
EOC Command
Synchroni
zed 2
Wait for Act Transparent
Error S/T
received no ’LBBD’ or
’RTN’ after an ’LBBD’
AR
AR
AI
AR
received ’LBBD’
ARL
ARL
AIL
ARL
• Outputs denoted with 3) in Figure 10:
In States ’Pend. Deact. S/T’ and ’Pend. Deact. U’ the ACT-bit output depends on its
value in the previous state.
• The value of the issued SAI-bit depends on the received C/I-code: DI and TIM lead to
SAI = 0, any other C/I-code sets the SAI-bit to 1 indicating activity of the downstream
device.
• If state Alerting is entered from state Deactivated, then C/I-code ’PU’ is issued, else
C/I-code ’DC’ is issued.
2.3.5.5
Description of the NT-States
The following states are used:
Alerting
The wake-up signal TN is transmitted for a period of T11 either in response to a received
wake-up signal TL or to start an activation procedure on the LT-side.
Alerting 1
“Alerting 1” state is entered when a wake-up tone was received in the “Receive Reset”
state and the deactivation procedure on the NT-side was not yet finished. The
transmission of wake-up tone TN is started.
Analog Loop-Back
Transparency is achieved in both directions of transmission. This state can be left by
making use of any unconditional command.
Deactivated
Only in state Deactivated the device may enter the power-down mode.
Data Sheet
27
2001-03-29
PEF 80912/80913
Functional Description
EC Training
The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the
EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ
updating algorithm are disabled.
EC-Training 1
The “EC-Training 1” state is entered if transmission of signal SN1 has to be started and
the deactivation procedure on the NT-side is not yet finished.
EC-Training AL
The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the
EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ
updating algorithm are disabled.
EQ-Training
The receiver waits for signal SL1 or SL2 to be able to update the AGC, to recover the
timing phase, to detect the synch-word (SW), and to update the EQ-coefficients.
Error S/T
The downstream device is in an error condition (EI1). The LT-side is informed by setting
the ACT-bit to “0” (loss of transparency on the NT-side).
IOM-2-Awaked
The U-transceiver is deactivated, but may not enter the power-down mode.
Pending Deactivation of S/T
The U-transceiver has received the UOA-bit at zero after a complete activation of the S/
T-interface. The U-transceiver requests the downstream device to deactivate by issuing
DR.
Pending Deactivation of U-Interface
The U-transceiver waits for the receive signal level to be turned off (LSU) to start the
deactivation procedure.
Pending Receive Reset
The “Pending Receive Reset” state is entered upon detection of loss of framing on the
U-interface or expiry of timer T1. This failure condition is signalled to the LT-side by
turning off the transmit level (SN0). The U-transceiver then waits for a response (no
signal level LSU) from the LT-side.
Data Sheet
28
2001-03-29
PEF 80912/80913
Functional Description
Pending Timing
In the NT-mode the pending timing state assures that the C/I-channel code DC is issued
four times before entering the ’Deactivated’ state.
Receive Reset
In state ’Receive Reset’ a reset of the Uk0-receiver is performed, except in case that
state ’Receive Reset’ was entered from state ’Pend. Deact. U’. Timer T7 assures that no
activation procedure is started from the NT-side for a minimum period of time of T7. This
gives the LT a chance to activate the NT.
Reset
In state ’Reset’ a software-reset is performed.
Synchronized 1
State ’Synchronized 1’ is the fully active state of the U-transceiver, while the downstream
device is deactivated.
Synchronized 2
In this state the U-transceiver has received UOA = 1. This is a request to activate the
downstream device.
Test
The test signal SSP is issued as long as TM2-0 = ’101’ . For further details see Table 9.
Transparent
This state is entered upon the detection of ACT = 1 received from the LT-side and
corresponds to the fully active state.
Wait for ACT
Upon the receipt of AI, the NT waits for a response (ACT = 1) from the LT-side.
Wait for SF
The signal SN2 is sent on the U-interface and the receiver waits for detection of the
superframe.
Wait for SF AL
This state is entered in the case of an analog loop-back and allows the receiver to update
the AGC, to recover the timing phase, and to update the EQ-coefficients.
Data Sheet
29
2001-03-29
PEF 80912/80913
Functional Description
2.3.6
Metallic Loop Termination
For North American applications a maintenance controller according to ANSI T1.601
section 6.5 is implemented. The maintenance pulse stream from the U-interface Metallic
Loop Termination circuit (MLT) is fed to pin MTI, usually via an optocoupler. It is digitally
filtered for 20 ms and decoded independently on the polarity by the maintenance
controller according to Table 13. Therefore, the maintenance controller is capable of
detecting the DC and AC signaling format. The Q-SMINTO automatically sets the Utransceiver in the proper state and issues an interrupt. The state selected by the MLT is
indicated via two bits.
The Q-SMINTO reacts on a valid pulse stream independently of the current Utransceiver state. This includes the power-down state.
A test mode is valid for 75 seconds. If during the 75 seconds a valid pulse sequence is
detected the 75 s timer starts again. After expiry of the 75 s timer the MLT maintenance
controller goes back to normal operation.
•
Table 13
ANSI Maintenance Controller States
Number of
counted pulses
ANSI maintenance
controller state
U-transceiver State Machine
<= 5
ignored
no impact
6
Quiet Mode
transition to state ’Reset’
start timer 75s
7
ignored
no impact
8
Insertion Loss Measurement transition to state ’Transparent’
start timer 75s
9
ignored
no impact
10
normal operation
transition to state ’Reset’
>= 11
ignored
no impact
Figure 11 shows examples for pulse streams with inverse polarity selecting Quiet Mode.
Data Sheet
30
2001-03-29
PEF 80912/80913
Functional Description
•
20 ms < tHIGH < 500 ms
4 ms < tLOW < 500 ms
Pin 1
MTI 0
1
2
3
4
5
6
≥ 500 ms
≥ 500 ms
20 ms < tLOW < 500 ms
4 ms < tHIGH < 500 ms
Pin 1
MTI 0
1
2
3
4
≥ 500 ms
5
6
≥ 500 ms
mlt.vsd
Figure 11
Data Sheet
Pulse Streams Selecting Quiet Mode
31
2001-03-29
PEF 80912/80913
Functional Description
2.4
S-Transceiver
The S-Transceiver offers the NT state machine described in the User’s Manual V3.4 [10].
The S-transceiver basic configurations are performed via pin strapping.
2.4.1
Line Coding, Frame Structure
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
•
0 1 1
code violation
Figure 12
S/T -Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 12).
In the direction TE → NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT → TE and TE → NT) with all framing
and maintenance bits.
Data Sheet
32
2001-03-29
PEF 80912/80913
Functional Description
•
Figure 13
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) → identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) → number of binary ZEROs sent
after the last L. bit was odd
– D
D-Channel Data Bit
Signaling data specified by user
– E
D-Channel Echo Bit
E = D → received E-bit is equal to transmitted
D-bit
– FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
– N
N = FA
– B1
B1-Channel Data Bit
User data
– B2
B2-Channel Data Bit
User data
– A
Activation Bit
A = (0b) → INFO 2 transmitted
A = (1b) → INFO 4 transmitted
– S
S-Channel Data Bit
S1 channel data (see note below)
– M
Multiframing Bit
M = (1b) → Start of new multi-frame
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
2.4.2
S/Q Channels, Multiframing
The S/Q channels are not supported.
Data Sheet
33
2001-03-29
PEF 80912/80913
Functional Description
2.4.3
Data Transfer between IOM-2 and S0
In the state G3 (Activated) the B1, B2 and D bits are transferred transparently from the
S/T to the IOM-2 interface and vice versa. In all other states ’1’s are transmitted to the
IOM-2 interface.
2.4.4
Loopback 2
C/I commands ARL and AIL close the analog loop as close to the S-interface as possible.
ETSI refers to this loop under ’loopback 2’. ETSI requires, that B1, B2 and D channels
have the same propagation delay when being looped back.
The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The
loop is transparent.
Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped
back in the B and D-channels (DU) for four frames.
2.4.5
State Machine
The state diagram notation is given in Figure 14.
The information contained in the state diagrams are:
–
–
–
–
–
–
state name
Signal received from the line interface (INFO)
Signal transmitted to the line interface (INFO)
C/I code received (commands)
C/I code transmitted (indications)
transition criteria
The transition criteria are grouped into:
– C/I commands
– Signals received from the line interface (INFOs)
– Reset
Data Sheet
34
2001-03-29
PEF 80912/80913
Functional Description
•
OUT
IOM-2 Interface
C/I code
IN
Unconditional
Transition
Ind. Cmd.
S ta te
S/T Interface
INFO
ix
ir
macro_17.vsd
Figure 14
State Diagram Notation
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “∗” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
Test Signals
• 2 kHz Single Pulses (TM1)
One pulse with a width of one bit period per frame with alternating polarity.
• 96 kHz Continuous Pulses (TM2)
Continuous pulses with a pulse width of one bit period.
Note: The test signals TM1 and TM2 can be generated via pins TM0-2 according to
Table 5.
Reset States
After an active signal on the reset pin RST the S-transceiver state machine is in the reset
state.
C/I Codes in Reset State
In the reset state the C/I code 0000 (TIM) is issued. This state is entered after a hardware
reset (RST).
C/I Codes in Deactivated State
If the S-transceiver is in state ‘Deactivated‘ and receives i0, the C/I code 0000 (TIM) is
issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued.
Data Sheet
35
2001-03-29
PEF 80912/80913
Functional Description
Receive Infos on S/T
I0
INFO 0 detected
I0
Level detected (signal different to I0)
I3
INFO 3 detected
I3
Any INFO other than INFO 3
Transmit Infos on S/T
I0
INFO 0
I2
INFO 2
I4
INFO 4
It
Send Single Pulses (TM1).
Send Continuous Pulses (TM2).
Data Sheet
36
2001-03-29
PEF 80912/80913
Functional Description
2.4.5.1
State Machine NT Mode
•
RST
TIM RES
TIM
DR
Reset
i0
ARD
i0
DI
Any
State
ARD1)
Test Mode i
i0
it
(i0*16ms)+32ms
DC
RES
DR
G4 Pend. Deact.
1)
*
TM1
TIM TM2
DR
DC
DR
*
TM1
TM2
Any
State
G4 Wait for DR
i0
*
DC
DI
TIM
DR
DC
G1 Deactivated
ARD1)
i0
i0
(i0*8ms)
AR
DC
G1 i0 Detected
i0
DR
*
ARD1)
AR ARD
G2 Pend. Act
i2
DR
i3
i3
AID
RSY ARD
G2 Lost
Framing S/T
i2
i3*ARD
AI
i3*ARD1)
i3*AID2)
i3
ARD
G2 Wait for AID
RSY
i2
DR
i3
AID2)
RSY
DR
ARD1)
AID2)
RSY RSY
AI
G3 Lost
Framing U
i2
*
ARD1)
i3*AID2)
AID
G3 Activated
RSY
i4
i3
DR
1)
2)
Figure 15
: ARD = AR or ARL
: AID =AI or AIL
statem_nt_s.vsd
State Machine NT Mode
Note: By setting the Test Mode pins TM0-2 to ’010’ / ’011’: Continuous Pulses / Single
Pulses, the S-transceiver starts sending the corresponding test signal, but no state
transition is invoked.
Data Sheet
37
2001-03-29
PEF 80912/80913
Functional Description
G1 Deactivated
The S-transceiver is not transmitting. There is no signal detected on the S/T-interface,
and no activation command is received in the C/I channel. Activation is possible from the
S/T interface and from the IOM-2 interface.
G1 I0 Detected
An INFO 0 is detected on the S/T-interface, translated to an “Activation Request”
indication in the C/I channel. The S-transceiver is waiting for an AR command, which
normally indicates that the transmission line upstream is synchronized.
G2 Pending Activation
As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not
yet received. In case of ARL command, loop 2 is closed.
G2 wait for AID
INFO 3 was received, INFO 2 continues to be transmitted while the S-transceiver waits
for a “switch-through” command AID from the device upstream.
G3 Activated
INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the
B and D-channels are transparent. On the command AIL, loop 2 is closed.
G2 Lost Framing S/T
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G3 Lost Framing U
On receiving an RSY command which usually indicates that synchronization has been
lost on the transmission line, the S-transceiver transmits INFO 2.
G4 Pending Deactivation
This state is triggered by a deactivation request DR, and is an unstable state. Indication
DI (state “G4 wait for DR”) is issued by the transceiver when:
either INFO0 is received for a duration of 16 ms
or an internal timer of 32 ms expires.
Data Sheet
38
2001-03-29
PEF 80912/80913
Functional Description
G4 wait for DR
Final state after a deactivation request. The S-transceiver remains in this state until DC
is issued.
Unconditional States
Test Mode TM1
Send Single Pulses
Test Mode TM2
Send Continuous Pulses
C/I Commands
•
Command
Abbr.
Code
Remark
Deactivation Request
DR
0000
Deactivation Request. Initiates a complete
deactivation by transmitting INFO 0.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
TM1
0010
Send Single Pulses.
Send Continuous
Pulses
TM2
0011
Send Continuous Pulses.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
Activation Request. This command is used to
start an activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
Activation Indication
AI
1100
Activation Indication. Synchronous receiver,
i.e. activation completed.
Data Sheet
39
2001-03-29
PEF 80912/80913
Functional Description
Command
Abbr.
Code
Remark
Activation Indication
Loop
AIL
1110
Activation Indication Loop
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which
it can be activated from a terminal (detection
of INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Interim indication during deactivation
procedure.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous.
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code Ciolation
CVR
1011
Illegal code violation received. This function
has to be enabled in S_CONF0.EN_ICV.
Activation Indication
AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
DI
1111
Timer (32 ms) expired or INFO 0 received for
a duration of 16 ms after deactivation
request.
•
Data Sheet
40
2001-03-29
PEF 80912/80913
Operational Description
3
Operational Description
3.1
Layer 1 Activation/Deactivation
3.1.1
Complete Activation Initiated by Exchange
Figure 16 depicts the procedure if activation has been initiated by the exchange side
(LT).
•
NT
IOM-2
TE
S/T-Reference Point
DC
INFO 0
DI
INFO 0
U-Reference Point
S0
DC
DI
Uk0
LT
IOM-2
SL0
DC
SN0
DI
AR
TL
SL0
PU
TN
DC
SN1
AR
SN0
SL1
SL2 (act = 0, dea = 1, uoa = 0)
ARM
SN2
AR
INFO 2
AR
SN3 (act = 0, sai = 0)
UAI
SN3 (act = 0, sai = 1)
SL3T (act = 0, dea = 1, uoa = 1)
AR
INFO 3
AI
SN3 (act = 1, sai = 1)
SL3T (act = 0, dea = 1, uoa = 0)
INFO 4
AI
AI
SN3T
AI
AR8/10
SBCX-X or
IPAC-X
Q-SMINTO
DFE-Q
ITD10035.vsd
Figure 16
Data Sheet
Complete Activation Initiated by Exchange
41
2001-03-29
PEF 80912/80913
Operational Description
3.1.2
Complete Activation Initiated by TE
Figure 17 depicts the procedure if activation has been initiated by the terminal side (TE).
•
IOM-2
TE
S/T-Reference Point
NT
S0
DC
INFO 0
DC
DI
INFO 0
DI
INFO 1
TIM
U-Reference Point
Uk0
LT
IOM-2
SL0
DC
SN0
DI
TN
AR
TIM
PU
AR8/10
8ms
PU
AR
DC
SN1
SN0
SL1
ARM
SL2 (act = 0, dea = 1, uoa = 0)
SN2
SN3 (act = 0, sai = 1)
UAI
SL3T (uoa = 1)
AR
INFO 2
RSY
INFO 0
AR
INFO 3
AI
AI
SN3 (act = 1, sai = 1)
SL3T (act = 1, dea = 1, uoa = 1)
INFO 4
AI
SBCX-X or
IPAC-X
AI
SN3T
Q-SMINTO
DFE-Q
ITD10041.vsd
Figure 17
Data Sheet
Complete Activation Initiated by TE
42
2001-03-29
PEF 80912/80913
Operational Description
3.1.3
Complete Deactivation
Figure 18 depicts the procedure if deactivation has been initiated. Deactivation of layer
1 is always initiated by the exchange.
•
NT
IOM-2
TE
S/T-Reference Point
AI
INFO 4
AR
INFO 3
U-Reference Point
S0
AI
Uk0
IOM-2
LT
SL3T (act = 1, dea = 1, uoa = 1)
AR
AI
SN3T (act = 1, sai = 1)
AI
DC1)
SL3T (act = 0, dea = 0)
DEAC
DR
SL0
INFO 0
RSY
3 ms
DR
40 ms
SN0
TIM
DR
DI
INFO 0
DC
DI
DI
&
DC
DC
DFE-Q
SBCX-X or
IPAC-X
Q-SMINTO
ITD10040.vsd
1)C/I-Code
Figure 18
Data Sheet
AR might be issued before C/I-Code DC in case of M4
Validation Algorithm CRC&TLL is selected
Complete Deactivation Initiated by Exchange
43
2001-03-29
PEF 80912/80913
Operational Description
3.1.4
Partial Activation
Figure 19 depicts the procedure if partial activation has been initiated by the exchange.
•
NT
IOM-2
TE
S/T-Reference Point
DC
INFO 0
DI
INFO 0
U-Reference Point
S0
DC
DI
Uk0
LT
IOM-2
SL0
DC
SN0
DI
UAR
TL
SL0
PU
TN
DC
SN1
AR
SN0
SL1
SL2 (act = 0, dea = 1, uoa = 0)
ARM
SN2
SN3 (act = 0, sai = 0)
SL3T (act = 0, dea = 1, uoa = 0)
UAI
(DC)
SBCX-X or
IPAC-X
Q-SMINTO
DFE-Q
ITD10036.vsd
Figure 19
Data Sheet
Partial Activation
44
2001-03-29
PEF 80912/80913
Operational Description
3.1.5
Activation from Exchange with U Active
Figure 20 depicts the procedure if activation has been initiated by the exchange with U
already being active.
•
NT
IOM-2
TE
S/T-Reference Point
DC
INFO 0
DI
INFO 0
U-Reference Point
S0
DC
Uk0
DI
IOM-2
LT
SL3T (act = 0, dea = 1, uoa = 0)
DC/UAR
SN3 (act = 0, sai = 0)
UAI
AR
INFO 2
AR
AR
SL3T (act = 0, dea = 1, uoa = 1)
SN3 (act = 0, sai = 1)
AR
AR
INFO 3
INFO 4
AI
AI
AI
SN3 (act = 1, sai = 1)
SL3T (act = 1, dea = 1, uoa = 1)
UAI
SN3T
AI
AR8/10
SBCX-X or
IPAC-X
Q-SMINTO
DFE-Q
ITD10037.vsd
Figure 20
Data Sheet
Activation from LT with U Active
45
2001-03-29
PEF 80912/80913
Operational Description
3.1.6
Activation from TE with U Active
Figure 21 depicts the procedure if activation has been initiated by the TE with U already
being active.
•
IOM-2
NT
TE
S/T-Reference Point
DC
INFO 0
DI
INFO 0
U-Reference Point
S0
DC
Uk0
DI
IOM-2
LT
SL3T (act = 0, dea = 1, uoa = 0)
UAR
SN3 (act = 0, sai = 0)
UAI
TIM
PU
AR8/10
INFO 1
TIM
8ms
AR
SN3 (act = 0, sai = 1)
AR
AR
SL3T (act = 0, dea = 1, uoa = 1)
INFO 2
RSY
INFO 0
AR
INFO 3
INFO 4
AI
AI
AI
SN3 (act = 1, sai = 1)
SL3T (act = 1, dea = 1, uoa = 1)
UAI
SN3T
SBCX-X or
IPAC-X
Q-SMINTO
AI
DFE-Q
ITD10038.vsd
Figure 21
Data Sheet
Activation from TE with U Active
46
2001-03-29
PEF 80912/80913
Operational Description
3.1.7
Partial Deactivation with U Active
Figure 22 depicts the procedure if partial deactivation has been initiated by the
exchange; i.e. U remains active.
•
NT
IOM-2
TE
S/T-Reference Point
AI
INFO 4
AR
INFO 3
U-Reference Point
S0
AI
Uk0
IOM-2
LT
SL3T (act = 1, dea = 1, uoa = 1)
AR
AI
SN3T (act = 1, sai = 1)
AI
DR
SL3T (act = 1, dea = 1, uoa = 0)
UAR
INFO 0
DR
INFO 0
TIM
DI
DI
SN3T (act = 1, sai = 0)
SN3T (act = 0, sai = 0)
DC
UAI
SL3T (act = 0, dea = 1, uoa = 0)
DC
SBCX-X or
IPAC-X
Q-SMINTO
DFE-Q
ITD10039.vsd
Figure 22
Data Sheet
Partial Deactivation with U Active
47
2001-03-29
PEF 80912/80913
Operational Description
3.1.8
Loop 2
Figure 23 depicts the procedure if loop 2 is closed and opened.
•
NT
IOM-2
TE S/T-Reference Point
INFO 4
AI
AR8/10
INFO 3
U-Reference Point
S0
AI
Uk0
AI
LT
IOM-2
SL3T (act = 1, dea = 1, uoa = 1)
AR
SN3T (act = 1, sai = 1)
AI
2B+D
MON0: LBBD
EOC: LBBD; act = 1
AIL
LP2I = 0
2B+D
MON0: RTN
EOC: RTN; act = 1
AI
LP2I = 1
2B+D
SBCX-X or
IPAC-X
Figure 23
Q-SMINTO
DFE-Q
ITD10042.vsd
Loop 2
Note: Closing / resolving loop 2 may provoke the S-transceiver to resynchronize. In this
case, the following C/I-codes are exchanged immediately upon receipt of AIL / AI,
respectively: DU: ’RSY’, DD: ’ARL’, DU: ’AI’, DD: ’AIL’ / ’AI’.
Data Sheet
48
2001-03-29
PEF 80912/80913
Operational Description
3.2
Layer 1 Loopbacks
Test loopbacks are specified by the national PTTs in order to facilitate the location of
defect systems. Four different loopbacks are defined. The position of each loopback is
illustrated in Figure 24.
•
U
U
IOM®-2
S-BUS
Loop 2
Loop 2
S-Transceiver
U-Transceiver
IOM®-2
Loop 1 A
NT
U-Transceiver
IOM®-2
Loop 2
Layer-1 Controller
IOM®-2
U-Transceiver
Repeater (optional)
Loop 1
U-Transceiver
Exchange
U-Transceiver
IOM-2
Loop 3
Layer-1 Controller
U-Transceiver
PBX or TE
Figure 24
loop_2b1q.emf
Test Loopbacks
Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled
locally on the remote side. All four loopback types are transparent. This means all bits
that are looped back will also be passed onwards in the normal manner. Only the data
looped back internally is processed; signals on the receive pins are ignored. The
propagation delay of actually looped B and D channels data must be identical in all
loopbacks.
Data Sheet
49
2001-03-29
PEF 80912/80913
Operational Description
3.2.1
Loopback No.2
For loopback #2 several alternatives exist. Both the type of loopback and the location
may vary. The following loopback types belong to the loopback-#2 category:
• complete loopback (B1,B2,D), in a downstream device
• B1-channel loopback, always performed in the U-transceiver
• B2-channel loopback, always performed in the U-transceiver
All loop variations performed by the U-transceiver are closed as near to the internal
IOM-2 interface as possible.
Normally loopback #2 is controlled by the exchange. The maintenance channel is used
for this purpose. All loopback functions are latched. This allows channel B1 and channel
B2 to be looped back simultaneously.
3.2.1.1
Complete Loopback
When receiving the request for a complete loopback, the U transceiver passes it on to
the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/Icode AIL in the “Transparent” state or C/I = ARL in states different than “Transparent”
3.2.1.2
Loopback No.2 - Single Channel Loopbacks
Single channel loopbacks are always performed directly in the U-Transceiver. No
difference between the B1-channel and the B2-channel loopback control procedure
exists.
Data Sheet
50
2001-03-29
PEF 80912/80913
Operational Description
3.3
External Circuitry
3.3.1
Power Supply Blocking Recommendation
The following blocking circuitry is suggested.
•
VDDa_UR
VDDa_UX
VDDa_SR
VDDa_SX
3.3V
VDDD
VDDD
1)
100nF
1)
100nF
1)
1)
100nF
100nF
1)
100nF
1)
100nF
1µF
VSSD
VSSD
GND
VSSa_SX
VSSa_SR
VSSa_UX
VSSa_UR
1)
These capacitors should be located as near to the pins as possible
blocking_caps_Smint.vsd
Figure 25
3.3.2
Power Supply Blocking
U-Transceiver
The Q-SMINTO is connected to the twisted pair via a transformer. Figure 26 shows the
recommended external circuitry. The recommended protection circuitry is not displayed.
Note: The integrated hybrid as specified for Version 1.1 is no more available in Version
1.3 and an external hybrid is required.
Data Sheet
51
2001-03-29
PEF 80912/80913
Operational Description
•.
RT
R3
AOUT
n
R4
BIN
RCOMP
RPTC
>1µ
C
AIN
RCOMP
RPTC
R3
R4
Loop
extcirc_U_Q2_exthybrid.emf
BOUT
Figure 26
RT
External Circuitry U-Transceiver
U-Transformer Parameters
The following Table 14 lists parameters of typical U-transformers:
Table 14
U-Transformer Parameters
U-Transformer Parameters
Symbol Value
Unit
U-Transformer ratio;
Device side : Line side
n
1:2
Main inductance of windings on the line side
LH
14.5
mH
Leakage inductance of windings on the line side LS
<75
µH
Coupling capacitance between the windings on CK
the device side and the windings on the line side
100
pF
DC resistance of the windings on device side
RB
2.51)
Ω
DC resistance of the windings on line side
RL
51)
Ω
1)
RB / RL according to equation[2]
Data Sheet
52
2001-03-29
PEF 80912/80913
Operational Description
Resistors of the External Hybrid R3, R4 and RT
R3 = 1.3 kΩ
R4 = 1.0 kΩ
RT = 9.5 Ω
Resistors on the Line Side RPTC / Chip Side RT
Optional use of up to 2x20 Ω resistors (2xRPTC) on the line side of the transformer
requires compensation resistors RCOMP depending on RPTC:
2RPTC + 8RCOMP = 40 Ω
(1)
2RPTC + 4(2RCOMP + 2RT + ROUT + RB) + RL = 135 Ω
(2)
RB, RL : see Table 14
ROUT : see Table 19
27 nF Capacitor C
To achieve optimum performance the 27 nF capacitor should be MKT. A Ceramic
capacitor is not recommended.
Tolerances
• Rs: ±1%
• C=27 nF: ±10-20%
• L=14.5 mH: ±10%
3.3.3
S-Transceiver
In order to comply to the physical requirements of ITU recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the S-transceiver needs some additional circuitry.
S-Transformer Parameters
The following Table 15 lists parameters of a typical S-transformer:
Data Sheet
53
2001-03-29
PEF 80912/80913
Operational Description
Table 15
S-Transformer Parameters
Transformer Parameters
Symbol Value
Unit
Transformer ratio;
Device side : Line side
n
2:1
Main inductance of windings on the line side
LH
typ. 30
mH
Leakage inductance of windings on the line side LS
typ. <3
µH
Coupling capacitance between the windings on CK
the device side and the windings on the line side
typ. <100
pF
DC resistance of the windings on device side
RB
typ. 2.4
Ω
DC resistance of the windings on line side
RL
typ. 1.4
Ω
Transmitter
The transmitter requires external resistors Rstx = 47Ω in order to adjust the output
voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the
test mode “TM1”) on the one hand and in order to meet the output impedance of
minimum 20 Ω on the other hand (to be tested with the testmode ’Continuous Pulses’)
on the other hand.
Note: The resistance of the S-transformer must be taken into account when
dimensioning the external resistors Rstx. If the transmit path contains additional
components (e.g. a choke), then the resistance of these additional components
must be taken into account, too.
•
47
SX1
2:1
20...40
VDD
GND
SX2
47
DC Point
extcirc_S.vsd
Figure 27
Data Sheet
External Circuitry S-Interface Transmitter
54
2001-03-29
PEF 80912/80913
Operational Description
Receiver
The receiver of the S-transceiver is symmetrical. 10 kΩ overall resistance are
recommended in each receive path. It is preferable to split the resistance into two
resistors for each line. This allows to place a high resistance between the transformer
and the diode protection circuit (required to pass 96 kHz input impedance test of
ITU I.430 [8] and ETS 300012-1). The remaining resistance (1.8 kΩ) protects the Stransceiver itself from input current peaks.
•
1k8
8k2
SR1
2:1
VDD
GND
SR2
8k2
1k8
DC Point
extcirc_S.vsd
Figure 28
3.3.4
External Circuitry S-Interface Receiver
Oscillator Circuitry
Figure 29 illustrates the recommended oscillator circuit.
•
CLD
XOUT
15.36 MHz
XIN
CLD
Figure 29
Data Sheet
Crystal Oscillator
55
2001-03-29
PEF 80912/80913
Operational Description
Table 16
Crystal Parameters
Parameter
Symbol
Limit Values
Unit
Frequency
f
15.36
MHz
+/-60
ppm
Frequency calibration tolerance
Load capacitance
CL
20
pF
Max. resonance resistance
R1
20
Ω
Max. shunt capacitance
C0
7
pF
Oscillator mode
fundamental
External Components and Parasitics
The load capacitance CL is computed from the external capacitances CLD, the parasitic
capacitances CPar (pin and PCB capacitances to ground and VDD) and the stray
capacitance CIO between XIN and XOUT:
( C LD + C Par ) × ( C LD + C Par )
C L = -----------------------------------------------------------------------+ C IO
( C LD + C Par ) + ( C LD + C Par )
For a specific crystal the total load capacitance is predefined, so the equation must be
solved for the external capacitances CLD, which is usually the only variable to be
determined by the circuit designer. Typical values for the capacitances CLD connected
to the crystal are 22 - 33 pF.
3.3.5
General
• low power LEDs
• MLT input supports
– APC13112
– AT&T LH1465AB
– discrete as proposed by Infineon
Data Sheet
56
2001-03-29
PEF 80912/80913
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
•
Parameter
Symbol Limit Values
TA
Storage temperature
TSTG
VDD
Maximum Voltage on VDD
Maximum Voltage on any pin with respect to VS
Ambient temperature under bias
ground
Unit
-40 to 85
°C
– 65 to 150
°C
4.2
V
-0.3 to VDD + 3.3
(max. < 5.5)
V
ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV
Note: Stress above those listed here may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
Line Overload Protection
The Q-SMINTO is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993
(CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA /
JESD78. From these tests the following max. input currents are derived (Table 17):
•
Table 17
Maximum Input Currents
Test
Pulse Width
Current
Remarks
ESD
100 ns
1.3 A
3 repetitions
Latch-up
5 ms
+/-200 mA
2 repetitions, respectively
DC
--
10 mA
Data Sheet
57
2001-03-29
PEF 80912/80913
Electrical Characteristics
4.2
DC Characteristics
•
VDD/VDDA = 3.3 V +/- 5% ; VSS/VSSA = 0 V; TA = -40 to 85 °C
Digital
Pins
Parameter
All
Input low voltage
All except
DD/DU
ACT,LP2I
MCLK
DD/DU
ACT,LP2I
MCLK
All
Symbol Limit Values
Unit
Test
Condition
min.
max.
VIL
-0.3
0.8
V
Input high voltage
VIH
2.0
5.25
V
Output low voltage
VOL1
0.45
V
IOL1 = 3.0 mA
Output high voltage
VOH1
V
IOH1 = 3.0 mA
Output low voltage
VOL2
V
IOL2 = 4.0 mA
Output high voltage
(DD/DU push-pull)
VOH2
V
IOH2 = 4.0 mA
Input leakage current
ILI
10
µA
0 V ≤ VIN ≤ VDD
10
µA
0 V ≤ VIN ≤ VDD
200
µA
0 V ≤ VIN ≤ VDD
70
µA
0 V ≤ VIN ≤ VD
2.4
0.45
2.4
Output leakage current ILO
Input leakage current
(internal pull-up)
ILIPU
Input leakage current
ILI
50
Analog
Pins
AIN, BIN
D
Table 18
Pin
S-Transceiver Characteristics
Parameter
Symbol Limit Values
min.
typ.
max.
2.31
SX1,2
Absolute value of
output pulse
amplitude
(VSX2 - VSX1)
VX
2.03
2.2
SX1,2
S-Transmitter
output impedance
ZX
10
34
SR1,2 S-Receiver input
impedance
Data Sheet
Unit
Test
Condition
V
RL = 50 Ω
kΩ
see 1)
see 2)3)
0
ZR
10
100
58
kΩ
Ω
VDD = 3.3 V
VDD = 0 V
2001-03-29
PEF 80912/80913
Electrical Characteristics
1)
Requirement ITU-T I.430, chapter 8.5.1.1a): ’At all times except when transmitting a binary zero, the output
impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template
in Figure 11. The requirement is applicable with an applied sinusoidal voltage of 100 mV (r.m.s value)’
2)
Requirement ITU-T I.430, chapter 8.5.1.1b): ’When transmitting a binary zero, the output impedance shall be
> 20 Ω.’: Must be met by external circuitry.
3)
Requirement ITU-T I.430, chapter 8.5.1.1b), Note: ’The output impedance limit shall apply for a nominal load
impedance (resistive) of 50 Ω. The output impedance for each nominal load shall be defined by determining
the peak pulse amplitude for loads equal to the nominal value +/- 10%. The peak amplitude shall be defined
as the the amplitude at the midpoint of a pulse. The limitation applies for pulses of both polarities.’
Table 19
U-Transceiver Characteristics
Limit Values
min.
typ.
Unit
max.
Receive Path
Signal / (noise + total harmonic distortion)1) 652)
dB
DC-level at AD-output
45
50
55
%3)
Threshold of level detect
(measured between AIN and BIN with
respect to zero signal)
4
5
16 (PEF
80912)
mV
peak
Input impedance AIN/BIN
80
kΩ
Signal / (noise + total harmonic distortion)4) 70
dB
9 (PEF
80913)
Transmit Path
Common mode DC-level
1.61
1.65
1.69
V
35
mV
2.5
2.58
V
0.8
3
1.5
6
Ω
Ω
Offset between AOUT and BOUT
Absolute peak voltage for a single +3 or -3
pulse measured between AOUT and
BOUT5)
Output impedance AOUT/BOUT:
Power-up
Power-down
2.42
1)
Test conditions: 1.4 Vpp differential sine wave as input on AIN/BIN with long range (low, critical range).
2)
Versions PEF 8x913 with enhanced performance of the U-interface are tested with tightened limit values
3)
The percentage of the "1 "-values in the PDM-signal.
4)
Interpretation and test conditions: The sum of noise and total harmonic distortion, weighted with a low pass
filter 0 to 80 kHz, is at least 70 dB below the signal for an evenly distributed but otherwise random sequence
of +3, +1, -1, -3.
Data Sheet
59
2001-03-29
PEF 80912/80913
Electrical Characteristics
5)
The signal amplitude measured over a period of 1 min. varies less than 1%.
4.3
Capacitances
TA = 25 °C, 3.3 V ± 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded.
•
Table 20
Pin Capacitances
Parameter
Symbol
Limit Values Unit
min.
max.
Digital pads:
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
Analog pads:
Load Capacitance
CL
3
pF
4.4
Remarks
pin AIN, BIN
Power Consumption
•
Power Consumption
VDD=3.3 V, VSS=0 V, Inputs at VSS/VDD, no LED connected, 50% bin. zeros, no output
loads except SX1,2 (50 Ω1))
Parameter
Limit Values
min.
Operational
U and S enabled, IOM-2 off
Power Down
1)
typ.
Unit Test Condition
max.
235
mW
U: ETSI loop 1 (0 m)
200
mW
U: ETSI Loop 2.(typical
line)
15
mW
50 Ω (2 x TR) on the S-bus.
Data Sheet
60
2001-03-29
PEF 80912/80913
Electrical Characteristics
4.5
Supply Voltages
VDDD = + Vdd ± 5%
VDDA = + Vdd ± 5%
The maximum sinusoidal ripple on VDD is specified in the following figure:
•
mV
(peak)
200
Supply Voltage Ripple
100
10
60
80
100
Frequency / kHz
Frequency Ripple
ITD04269.vsd
Figure 30
Data Sheet
Maximum Sinusoidal Ripple on Supply Voltage
61
2001-03-29
PEF 80912/80913
Electrical Characteristics
4.6
AC Characteristics
TA = -40 to 85 °C, VDD = 3.3 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in Figure 31.
•
2.4
2.0
2.0
Device
Under
Test
Test Points
0.8
0.8
0.45
CLoad=50 pF
ITS00621.vsd
Figure 31
Input/Output Waveform for AC Tests
Parameter
All Output Pins
Symbol
Limit values
Min
Unit
Max
Fall time
30
ns
Rise time
30
ns
Data Sheet
62
2001-03-29
PEF 80912/80913
Electrical Characteristics
4.6.1
IOM-2 Interface
•
DCL
t7
t6
DU/DD
(Output)
last bit
first bit
t8
DU/DD
(Output)
Figure 32
bit n
bit n+1
IOM®-2 Interface - Bit Synchronization Timing
•
t9
FSC
t10
DCL
t2
t3
t1
Figure 33
IOM-2 Interface - Frame Synchronization Timing
•
Note: At the start and end of a reset period, a frame jump may occur. This results in a
DCL and FSC high time of min. 130 ns after this specific event.
Data Sheet
63
2001-03-29
PEF 80912/80913
Electrical Characteristics
Parameter
IOM®-2 Interface
Symbol Limit values
DCL period
Unit
Min
Typ
Max
t1
1875
1953
2035
ns
DCL high
t2
850
960
1105
ns
DCL low
t3
850
960
1105
ns
Output data from high impedance to t6
active
(FSC high or other than first timeslot)
100
ns
Output data from active to high
impedance
t7
100
ns
Output data delay from clock
t8
80
ns
FSC high
t9
FSC advance to DCL
t10
DCL, FSC rise/fall
Data out rise/fall
(CL = 50 pF, tristate)
Data Sheet
50% of
FSC
cycle
time
65
195
ns
t15
30
ns
t17
150
ns
64
130
ns
2001-03-29
PEF 80912/80913
Electrical Characteristics
4.6.2
Table 21
Reset
Reset Input Signal Characteristics
Parameter
Symbol
Limit Values
min.
Length of active
low state
tRST
typ.
Unit
Test Conditions
ms
Power On
the 4 ms are assumed to
be long enough for the
oscillator to run correctly
max.
4
2x
DCL
clock
cycles
+ 400
ns
After Power On
•
RST
tRST
ITD09823.vsd
Figure 34
Data Sheet
Reset Input Signal
65
2001-03-29
PEF 80912/80913
Electrical Characteristics
4.6.3
Undervoltage Detection Characteristics
•
VDD
VDET
VHYS
VDDmin
t
RSTO
tACT
tACT
tDEACT
tDEACT
t
VDDDET.VSD
Figure 35
Data Sheet
Undervoltage Control Timing
66
2001-03-29
PEF 80912/80913
Electrical Characteristics
Table 22
Parameters of the UVD/POR Circuit
VDD= 3.3 V ± 5 %; VSS= 0 V; TA = -40 to 85 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
2.8
2.92
V
90
mV
0.1
V/µs
0.1
V/
ms
Detection Threshold1)
VDET
2.7
Hysteresis
VHys
30
Max. rising/falling VDD
edge for activation/
deactivation of UVD
dVDD/dt
Max. rising VDD for
power-on2)
Min. operating voltage
VDDmin
Delay for activation
of RSTO
tACT
Delay for deactivation
of RSTO
tDEACT
Unit Test Condition
1.5
VDD = 3.3 V ± 5 %
V
10
64
µs
ms
1)
The Detection Threshold VDET is far below the specified supply voltage range of analog and digital parts of the
®
Q-SMINT O. Therefore, the board designer must take into account that a range of voltages is existing, where
®
neither performance and functionality of the Q-SMINT O are guaranteed, nor a reset is generated.
2)
If the integrated Power-On Reset of the Q-SMINTO is selected (VDDDET = ’0’) and the supply voltage VDD is
ramped up from 0V to 3.3V +/- 5%, then the Q-SMINTO is kept in reset during VDDmin < VDD < VDET + VHys.
VDD must be ramped up so slowly that the Q-SMINTO leaves the reset state after the oscillator circuit has
already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and
12ms.
Data Sheet
67
2001-03-29
PEF 80912/80913
Package Outlines
5
Package Outlines
Plastic Package, P-MQFT-44
(Metric Quad Flat Package)
•
•
Data Sheet
68
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
6
Appendix: Differences between Q- and T-SMINTO
The Q- and T-SMINTO have been designed to be as compatible as possible. However,
some differences between them are unavoidable due to the different line codes 2B1Q
and 4B3T used for data transmission on the Uk0 line.
Especially the pin compatibility between Q- and T-SMINTO allows for one single PCB
design for both series with only some mounting differences.
The following chapter summarizes the main differences between the Q- and TSMINTO.
6.1
Table 23
Pinning
Pin Definitions and Functions
Pin
MQFT-44
Q-SMINTO: 2B1Q
T-SMINTO: 4B3T
10
Triple-Last-Look (TLL)
Tie to ‘1‘
11
Metallic Termination Input
(MTI)
Tie to ‘1‘
16
Auto U Activation (AUA)
Tie to ‘1‘
17
Cold Start Only (CSO)
Tie to ‘1‘
38
Power Status (primary)
(PS1)
Tie to ‘1‘
26
Power Status (secondary)
(PS2)
Tie to ‘1‘
Data Sheet
69
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
6.2
U-Transceiver
6.2.1
U-Interface Conformity
Table 24
Related Documents to the U-Interface
Document
Q-SMINTO: 2B1Q
T-SMINTO: 4B3T
ETSI: TS 102 080
conform to annex A
compliant to 10 ms
interruptions
conform to annex B
ANSI: T1.601-1998
(Revision of ANSI T1.6011992)
conform
not required
MLT input and decode logic
CNET: ST/LAA/ELR/DNP/
822
conform
not required
RC7355E
conform
not required
FTZ-Richtlinie 1 TR 220
not required
conform
Data Sheet
70
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
6.2.2
U-Transceiver State Machines
•
T14S
.
SN0
T14S
TL
Pending Timing
DC
Any State
SSP or
C/I= 'SSP'
.
SN0
Deactivated
DC
T14E
T14S
DI
SP
TIM
.
.
SN0
IOM Awaked
PU
DI
Test
DR
.
SN0
AR or TL
T1S, T11S
DI
Alerting
PU
DR
.
TN
Alerting 1
DR
.
TN
DI & NT-AUTO
Reset
Any State
Pin-RST or
C/I= 'RES'
AR or TL
T1S
T11S
DC
T11E
T11E
ARL
T12S
.
SN1
EC-Training
DC
EC-Training AL
DC
LSUE
or T1E
EC-Training 1
DR
DI
..
SN0
EQ-Training
DC
BBD1 & SFD
SN3T
act=0
Analog Loop Back
.
SN1
LSEC or T12E
LSEC or T12E
act=0
SN3
Wait for SF AL
DC
T12S
T12S
.
SN1
T1S,
T11S
T20S
LSUE
or T1E
BBD0 & FD
.
SN2
LOF
Wait for SF
DC
AR
T20E &
BBD0 & SFD
LOF
SN3/SN3T 1) act=0
Synchronized 1
DI
1)
SN3/SN3T act=1/0
Pend.Deact. S/T
DR
3)
dea=0
LSUE
dea=0
LSUE
DC
uoa=1
LOF
SN3/SN3T 1) act=0
Synchronized 2
2)
AR/ARL
uoa=0
dea=0
LSUE
Al
LOF
SN3/SN3T 1) act=1
Wait for Act
2)
El1
AR/ARL
act=1
LOF
Any State
DT or
C/I='DT'
El1
uoa=0
dea=0
LSUE
act=0
act=1
SN3T
Transparent
2)
AI/AIL
uoa=0
LSUE
act=1 & Al
SN3/SN3T 1) act=0
Error S/T
act=0
2)
AR/ARL
.
SN0
Pend Receive Res.
T13S
EI1
LSU or ( /LOF & T13E )
T7E & DI
Figure 36
Data Sheet
T7S
.
SN0
Receive Reset
DR
LOF
Yes
dea=0
dea=0
uoa=1
?
No
uoa=0
LSUE
dea=1
1)
SN3/SN3T act=1/0 3)
LOF
Pend.Deact. U
DC
LSU
T7S
TL
NTC-Q Compatible State Machine Q-SMINTO: 2B1Q
71
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
•
AWR
U0
IOM Awaked
DC
TIM
AR
DI
U0
Deactivated
DC U0, DA
AWR
AR
T6S
T05E
U1W
Start Awaking Uk0
T6S
T05S
T05S
RSY
U0
Deactivating
DC
AWR
AWT
T6S
T6E
U0
Awake Signal Sent
RSY
AWR
T13S
T13E
U0
Ack. Sent / Received
RSY
AWT
AWR
T13S
U1W
Sending Awake-Ack.
T13S
RSY
(DI & T05E)
T12S
(U0 & T12E)
U1A
Synchronizing
T05S
RSY
U2
U0
Pend. Deactivation
DR
DI
T05S
SSP
DT
U1
SBC Synchronizing
AR / ARL
U0
LOF
ANY STATE
RES
AI
DI
U3
Wait for Info U4H
AR / ARL
SP / U0
Test
DR
U0
Reset
DR
U0
LOF
U4H
U0
U5
Transparent
AI / AIL
Figure 37
Data Sheet
U0
LOF
U0
Loss of Framing
RSY
NT_SM_4B3T_cust.emf
IEC-T/NTC-T Compatible State Machine T-SMINTO: 4B3T
72
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
6.2.3
Table 25
Command/Indication Codes
C/I Codes
Q-SMINTO: 2B1Q
T-SMINTO: 4B3T
IN
OUT
IN
OUT
0000
TIM
DR
TIM
DR
0001
RES
–
–
–
0010
–
–
–
–
0011
–
–
–
–
0100
EI1
EI1
–
RSY
0101
SSP
–
SSP
–
0110
DT
–
DT
–
0111
–
PU
–
–
1000
AR
AR
AR
AR
1001
–
–
–
–
1010
ARL
ARL
–
ARL
1011
–
–
–
–
1100
AI
AI
AI
AI
1101
–
–
RES
–
1110
–
AIL
–
AIL
1111
DI
DC
DI
DC
Code
Data Sheet
73
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
6.3
External Circuitry
The external circuitry of the Q- and T-SMINTO is equivalent; however, some external
components of the U-transceiver hybrid must be dimensioned different for 2B1Q and
4B3T. All information on the external circuitry is preliminary and may be changed in
future documents.
•
RT
R3
AOUT
n
R4
BIN
RCOMP
RPTC
C
AIN
RCOMP
Loop
RPTC
R3
R4
>1µ
extcirc_U_Q2_exthybrid.emf
BOUT
Figure 38
RT
External Circuitry Q- and T-SMINTO
the necessary protection circuitry is not displayed in Figure 38
Data Sheet
74
2001-03-29
PEF 80912/80913
Appendix: Differences between Q- and T-SMINT‚O
Table 26
Dimensions of External Components.
Component
Q-SMINTO: 2B1Q
T-SMINTO: 4B3T
Transformer:
Ratio
Main Inductivity
1:2
14.5 mH
1:1.6
7.5 mH
Resistance R3
1.3 kΩ
1.75 kΩ
Resistance R4
1.0 kΩ
1.0 kΩ
Resistance RT
9.5 Ω
25 Ω
Capacitor C
27 nF
15 nF
RPTC and RComp
2RPTC + 8RComp = 40 Ω
n2 × (2RCOMP + RB) + RL =
20Ω
Data Sheet
75
2001-03-29
PEF 80912/80913
Index
7
Index
P
Block Diagram 6
Package Outlines 68
Pin Configuration 5
Pin Definitions and Functions 7
Power Consumption 60
Power Supply Blocking 51
Power-On Reset 13, 66
C
R
C/I Codes
U-Transceiver 19
Cyclic Redundancy Check 18
D
Reset
Generation 13
Input Signal Characteristics 65
Power-On Reset 13, 66
Under Voltage Detection 13, 66
DC Characteristics 58
Differences between Q- and T-SMINT 69
S
A
Absolute Maximum Ratings 57
B
S/Q Channels 33
Scrambling/ Descrambling 18
S-Transceiver
Functional Description 32
State Machine, NT 37
Supply Voltages 61
System Integration 12
E
External Circuitry
S-Transceiver 53
U-Transceiver 51
F
Features 3
T
I
Test Modes 11
IOM®-2 Interface
AC Characteristics 63
Frame Structure 14
Functional Description 14
U
U-Interface Hybrid 51
Under Voltage Detection 13, 66
U-Transceiver
Functional Description 15
State Machine, Standard NT 21
L
Layer 1
Loopbacks 49
LED Pins 10
Line Overload Protection 57
M
Metallic Loop Termination 30
O
Oscillator Circuitry 55
Data Sheet
76
2001-03-29
Infineon goes for Business Excellence
“Business excellence means intelligent approaches and clearly
defined processes, which are both constantly under review and
ultimately lead to good operating results.
Better operating results and business excellence mean less
idleness and wastefulness for all of us, more professional
success, more accurate information, a better overview and,
thereby, less frustration and more satisfaction.”
Dr. Ulrich Schumacher
http://www.infineon.com
Published by Infineon Technologies AG