ETC PEF81902F

Da ta S h ee t, D S 1, N ov . 20 01
T - S M I NT I X
4B3 T S e co n d G e n .
M od ul ar I S D N N T
( I nt e ll ige n t e X t e nd e d)
PEF 81902 Version 1.1
Wired
C o m m u n i ca t i o n s
N e v e r
s t o p
t h i n k i n g .
Edition 2001-11-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Da ta S h ee t, D S 1, N ov . 20 01
T - S M I NT I X
4B3 T S e co n d G e n .
M od ul ar I S D N N T
( I nt e ll ige n t e X t e nd e d)
PEF 81902 Version 1.1
Wired
C o m m u n i ca t i o n s
N e v e r
s t o p
t h i n k i n g .
PEF 81902
Revision History:
2001-11-12
Previous Version:
Preliminary Data Sheet 06.01
Page
DS 1
Subjects (major changes since last revision)
Table 18
Additional C/I-command LTD
Figure 34
Chapter 2.4.7.4
Chapter 3.2.3
Chapter 4.3
Chapter 4.9.4
The Framer / Deframer Loopback (DLB) is no more supported
Chapter 4.3
Reset value of MASKU is FFh (not 00h)
Chapter 4.3
Chapter 4.9.8
Reset value of FW-Version is 3Eh
Chapter 4.9.4
Restriction of LOOP.LB1, LB2 and LBBD to Transparent state
Chapter 5.2
Input Leakage Current AIN, BIN: max. 30µA
Chapter 5.4
Reduced power consumption
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 81902
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Specific Pins and Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
2.1
2.1.1
2.1.1.1
2.1.2
2.1.3
2.2
2.3
2.3.1
2.3.2
2.3.2.1
2.3.2.2
2.3.3
2.3.3.1
2.3.3.2
2.3.3.3
2.3.3.4
2.3.3.5
2.3.3.6
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.4
2.3.5.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM‚-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM‚-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM‚-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MONITOR Channel Programming as a Master Device . . . . . . . . . . .
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . .
Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example for D-Channel Access Control . . . . . . . . . . . . .
TIC Bus Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop/Go Bit Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine of the D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . .
Activation/Deactivation of IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . .
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4B3T Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coding from Binary to Ternary Data . . . . . . . . . . . . . . . . . . . . . . . . . . .
Decoding from Ternary to Binary Data . . . . . . . . . . . . . . . . . . . . . . . . .
Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
16
16
16
19
21
23
24
27
27
28
30
40
41
41
45
47
47
48
48
49
51
51
51
53
53
54
56
58
58
62
62
63
64
2001-11-12
PEF 81902
Table of Contents
Page
2.4.4.2
2.4.5
2.4.6
2.4.7
2.4.7.1
2.4.7.2
2.4.7.3
2.4.7.4
2.4.7.5
2.4.7.6
2.4.8
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.5.1
2.5.5.2
2.5.5.3
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.2.1
2.6.2.2
2.6.3
2.6.3.1
2.6.3.2
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.6.9
Block Error Counter (RDS Error Counter) . . . . . . . . . . . . . . . . . . . . . 64
Scrambler / Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
State Machine for Activation and Deactivation . . . . . . . . . . . . . . . . . . . 66
State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Awake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
NT State Machine (IEC-T / NTC-T Compatible) . . . . . . . . . . . . . . . . 70
Inputs to the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Outputs of the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
U-Transceiver Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Data Transfer between IOM‚-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . . 81
Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Control of S-Transceiver / State Machine . . . . . . . . . . . . . . . . . . . . . . . 81
C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
S-Transceiver Enable / Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interrupt Structure S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . . 96
Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . 104
Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Access to IOM‚-2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generation of 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . .
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
115
115
115
118
119
120
2001-11-12
PEF 81902
Table of Contents
Page
3.1.5
3.1.6
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Loop-Back S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . .
Local Loopbacks Featured By the LOOP Register . . . . . . . . . . . . . . .
External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
122
123
123
124
125
125
125
127
127
127
129
132
132
4
4.1
4.2
4.3
4.3.1
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset of U-Transceiver Functions During Deactivation or with
C/I-Code RESET 143
Mode Register Evaluation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . .
RFIFO - Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISTAH - Interrupt Status Register HDLC . . . . . . . . . . . . . . . . . . . . . . .
MASKH - Mask Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STAR - Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMDR - Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEH - Mode Register HDLC Controller . . . . . . . . . . . . . . . . . . . . .
EXMR - Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RBCL - Receive Frame Byte Count Low . . . . . . . . . . . . . . . . . . . . . . .
RBCH - Receive Frame Byte Count High for D-Channel . . . . . . . . . .
TEI1 - TEI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RSTA - Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMH -Test Mode Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . .
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . .
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . .
133
133
134
136
4.3.2
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.4.12
4.4.13
4.4.14
4.4.15
4.4.16
4.4.17
4.4.18
4.4.19
4.4.20
Data Sheet
144
145
145
145
145
147
148
149
150
152
153
154
155
155
156
156
157
157
159
160
161
162
2001-11-12
PEF 81902
Table of Contents
4.4.21
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.7.8
4.7.9
4.7.10
4.7.11
4.7.12
4.7.13
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.9
4.9.1
4.9.2
Data Sheet
Page
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . .
Detailed S-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S_CONF0 - S-Transceiver Configuration Register 0 . . . . . . . . . . . . . .
S_CONF2 - S-Transmitter Configuration Register 2 . . . . . . . . . . . . . .
S_STA - S-Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . .
S_CMD - S-Transceiver Command Register . . . . . . . . . . . . . . . . . . . .
SQRR - S/Q-Channel Receive Register . . . . . . . . . . . . . . . . . . . . . . .
SQXR- S/Q-Channel Transmit Register . . . . . . . . . . . . . . . . . . . . . . .
ISTAS - Interrupt Status Register S-Transceiver . . . . . . . . . . . . . . . . .
MASKS - Mask S-Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . .
S_MODE - S-Transceiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt and General Configuration Registers . . . . . . . . . . . . . . . . . . . .
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed IOM®-2 Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . .
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . .
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . .
S_CR - Control Register S-Transceiver Data . . . . . . . . . . . . . . . . . . .
HCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . . .
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . .
SDS1_CR - Control Register Serial Data Strobe 1 . . . . . . . . . . . . . . .
SDS2_CR - Control Register Serial Data Strobe 2 . . . . . . . . . . . . . . .
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . .
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . .
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . .
Detailed MONITOR Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . .
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . .
Detailed U-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . .
UCIR - C/I Code Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
163
163
164
165
166
167
167
168
169
170
171
171
172
173
174
175
176
176
176
177
178
179
180
182
182
183
184
186
186
187
187
188
188
188
189
189
190
191
191
191
192
2001-11-12
PEF 81902
Table of Contents
Page
4.9.3
4.9.4
4.9.5
4.9.6
4.9.7
4.9.8
UCIW - C/I Code Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LOOP - Loopback Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDS - Block Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .
ISTAU - Interrupt Status Register U-Interface . . . . . . . . . . . . . . . . . . .
MASKU - Mask Register U-Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
FW_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
192
192
194
194
195
195
5
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . .
197
197
198
200
200
200
202
203
205
206
209
210
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
Appendix: Differences between Q- and T-SMINT‚IX . . . . . . . . . . . . . .
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Pin ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Data Sheet
214
215
215
215
216
216
217
220
221
223
226
2001-11-12
PEF 81902
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Page
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application Example T-SMINT ®IX: Low Cost Intelligent NT . . . . . . . . 13
Control via µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Control via IOM‚-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset Generation of the T-SMINT‚IX . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IOM-2 Frame Structure of the T-SMINT‚IX . . . . . . . . . . . . . . . . . . . . 27
Architecture of the IOM‚-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Access via CDAx0 and CDAx1 register pairs . . . . . . . . . . . . . . . 31
Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . 32
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 33
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 34
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 38
Examples for the Synchronous Transfer Interrupt Control with one STIxy
enabled 39
Data Strobe Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MONITOR Channel Protocol (IOM®-2) . . . . . . . . . . . . . . . . . . . . . . . . 43
Monitor Channel, Transmission Abort requested by the Receiver. . . . 46
Monitor Channel, Transmission Abort requested by the Transmitter. . 46
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 46
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
D-Channel Arbitration: µC has no HDLC and no Direct Access to TIC Bus
51
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 52
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 53
State Machine of the D-Channel Arbiter (Simplified View). . . . . . . . . . 55
Deactivation of the IOM®-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
State Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Awake Procedure initiated by the LT . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Awake Procedure initiated by the NT. . . . . . . . . . . . . . . . . . . . . . . . . . 68
NT State Machine (IEC-T/NTC-T Compatible). . . . . . . . . . . . . . . . . . . 70
Interrupt Structure U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 79
S-Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Data Sheet
2001-11-12
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
PEF 81902
List of Figures
Page
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data Reception Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Receive Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Interrupt Status Registers of the HDLC Controller . . . . . . . . . . . . . . . 113
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 125
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 126
Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
External Circuitry U-Transceiver with External Hybrid . . . . . . . . . . . . 128
External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 131
External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 131
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
T-SMINT‚IX Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . 134
Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . 201
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 202
IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . 203
IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . 203
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Data Sheet
2001-11-12
PEF 81902
List of Figures
Figure 83
Figure 84
Figure 85
Figure 86
Figure 87
Figure 88
Data Sheet
Page
NTC-Q Compatible State Machine Q-SMINT‚IX: 2B1Q . . . . . . . . . . .
Simplified State Machine Q-SMINT‚IX: 2B1Q . . . . . . . . . . . . . . . . . .
IEC-T/NTC-T Compatible State Machine T-SMINT‚IX: 4B3T . . . . . .
Interrupt Structure U-Transceiver Q-SMINT‚IX: 2B1Q . . . . . . . . . . . .
Interrupt Structure U-Transceiver T-SMINT‚IX: 4B3T . . . . . . . . . . . .
External Circuitry Q- and T-SMINT‚IX . . . . . . . . . . . . . . . . . . . . . . . .
217
218
219
221
222
226
2001-11-12
PEF 81902
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Data Sheet
Page
NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interface Selection for the T-SMINT‚IX . . . . . . . . . . . . . . . . . . . . . . . . 16
Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MCLK Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 37
Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
T-SMINT‚IX Configuration Settings in Intelligent NT Applications . . . . 54
Frame Structure A for Downstream Transmission LT to NT . . . . . . . . 59
Frame Structure B for Upstream Transmission NT to LT. . . . . . . . . . . 61
MMS 43 Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4B3T Decoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Active States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Differences to the former NT-SM of the IEC-T/NTC-T . . . . . . . . . . . . . 71
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
M Symbol Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Signal Output on Uk0 in State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C/I-Code Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
S/Q-Bit Position Identification and Multi-Frame Structure . . . . . . . . . . 80
Receive Byte Count with RBC11...0 in the RBCH and RBCL registers 98
Receive Information at RME Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 104
XPR Interrupt (availability of the XFIFO) after XTF, XME Commands 106
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Generation of the 4B3T Signal Elements. . . . . . . . . . . . . . . . . . . . . . 116
S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Reset of U-Transceiver Functions During Deactivation or with C/I- Code
RESET 144
Mode Register with Immediate Evaluation and Execution . . . . . . . . . 144
Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Reset Input Signal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 209
2001-11-12
PEF 81902
List of Tables
Table 42
Table 43
Table 45
Data Sheet
Page
Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 210
Design Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
2001-11-12
PEF 81902
Overview
1
Overview
The PEB 81902 (T-SMINTâIX) offers many features in addition to the PEB 8090 [9]
which ease the realization of an intelligent NT.
The T-SMINTâIX features U-transceiver, S-transceiver, HDLC controller and an IOMâ2 interface on a single chip. A microcontroller interface provides access to both
transceivers, the HDLC controller as well as to the IOMâ-2 interface.
Main target applications of the T-SMINTâIX are intelligent NT applications which require
one single HDLC controller.
Table 1 on Page 1 summarizes the 2nd generation NT products.
•
Table 1
NT Products of the 2nd Generation
PEF 80902
PEF 81902
PEF 82902
T-SMINT®O
T-SMINT®IX
T-SMINT®I
Package
P-MQFP44
P-MQFP-64
P-TQFP-64
P-MQFP-64
P-TQFP-64
Register
access
no
U+S+HDLC+ IOMâ−2
U+S+IOMâ−2
Access via
n.a
MCLK,
watchdog timer,
SDS, BCL, Dchannel
arbitration,
IOMâ−2 access
and
manipulation
etc. provided
no
yes
yes
HDLC
controller
no
yes
no
NT1 mode
available
yes (only)
no
no
Data Sheet
parallel (or SCI or IOMâ−2) parallel (or SCI or IOMâ−2)
1
2001-11-12
PEF 81902
Overview
1.1
References
[1]
TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital
transmission system on metallic local lines, ETSI, November 1998
[2]
FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle
Uk0 Schicht 1, Deutsche Telecom AG, August 1991
[3]
TS 0284/96 Technische Spezifikation Intelligenter Netzabschluß (iNT) mit
den Funktionen eines Terminaladapters TA 2a/b (ohne Internverkehr),
Deutsche Telekom AG, März 2001
[4]
pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI,
November 1996
[5]
T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points
(Layer 1 Specification), ANSI, 1991
[6]
I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU,
November 1988
[7]
IEC-T, ISDN Echocancellation Circuit, PEB 20901 (IEC - TD) / PEB 20902
(IEC - TA), preliminary Target Specification 11.88, Siemens AG, 1988
[8]
SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User’s Manual
11.96, Siemens AG, 1996
[9]
NTC-T, Network Termination Controller (4B3T), PEB 8090 V1.1, Data Sheet
06.98, Siemens AG, 1998
[10]
INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB 8191 V1.1,
Data Sheet 10.97, Siemens AG, 1997
[11]
Q-SMINTO, 2B1Q Second Gen. Modular ISDN NT (Ordinary), PEF 80912
Q-SMINTIX, 2B1Q Second Gen. Modular ISDN NT (Intelligent eXended),
PEF 81912
Q-SMINTI, 2B1Q Second Gen. Modular ISDN NT (Intelligent), PEF 82912
V1.3, Data Sheets 03.01, Infineon AG, 2001
[12]
IOMâ-2 Interface Reference Guide, Siemens AG, 03.91
[13]
SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.1,
Preliminary Data Sheet 08.98, Infineon Technologies AG, 1999
[14]
PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH,
September1997
[15]
Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data
Sheet DS2, Infineon Technologies, July 2000.
Data Sheet
2
2001-11-12
4B3T Second Gen. Modular ISDN NT (Intelligent
eXtended)
T-SMINT®IX
PEF 81902
Version 1.1
1.2
Features
Features known from the PEB 8090
• U-transceiver and S-transceiver on one chip
• U-interface (4B3T) conform to ETSI [1] and FTZ [2] :
– Meets all transmission requirements on all ETSI
and FTZ loops with margin
• S/T-interface conform to ETSI [4], ANSI [5] and ITU
[6]
– Supports point-to-point and bus configurations
– Meets and exceeds all transmission requirements
• Access to IOMâ-2 C/I and Monitor channels
• Power-on reset and Undervoltage Detection with no
external components
• ESD robustness 2kV
New Features
P-MQFP-64-1,-2
•
P-TQFP-64-1
• Conforms to ’Technische Spezifikation Intelligenter
Netzabschluß (iNT) mit den Funktionen eines
Terminaladapters TA 2a/b’ of Deutsche Telekom AG [3]
• Perfectly suited for low cost intelligent NTs that require one single HDLC controller
• Pin compatible with Q-SMINTâIX (2nd Generation)
• HDLC controller on chip, including
– HDLC access to B-channels, D-channel and any combination of them.
– Improved FIFO structure
– HDLC extended transparent mode
– Automatic D-channel arbitration between S-bus and local HDLC controller
• Parallel or serial µP-interface
– Siemens/Intel non-multiplexed (direct or indirect addressing)
Type
Package
PEF 81902
P-MQFP-64
PEF 81902
P-TQFP-64
Data Sheet
3
2001-11-12
PEF 81902
Overview
•
•
•
•
•
•
•
•
•
– Siemens/Intel multiplexed
– Motorola
– programmable MCLK (can be disabled)
Enhanced IOMâ−2 interface
– Timeslot access and manipulation
– BCL output; programmable and flexible strobes SDS1/2, e.g. active during several
timeslots.
– Optional: All registers can be read and written to via new Monitor channel concept
– External Awake (EAW)
Optional use of transformers with non-negligible resistance corresponding to up to
20Ω on the line side
Optional: Implementation of S-transceiver statemachine in software
Power-down mode and reset states (e.g. S-transceiver) for individual circuits
Pin Vref and the according external capacitor removed
Inputs accept 3.3V and 5V
I/O (open drain) accepts pull-up to 3.3V1)
LED signal is programmable to display the states specified in [3];
but can also automatically indicate the activation status (mode select via 1 bit).
Lowest power consumption due to
– Low power CMOS technology (0.35µ)
– Newly optimized low power libraries
– High output swing on U- and S-line interface leads to minimized power consumption
– Single 3.3 Volt power supply
1.3
Not Supported are ...
• No integrated hybrid is provided by the T-SMINTâIX. Therefore, an external hybrid is
always required, which consists of only two additional resistors as compared to an
integrated hybrid, but allows for more flexibility in board design.
• Auxiliary IOMâ−2 interface
• SRA (capacitive receiver coupling is not suited for S-feeding)
• NT-Star with star point on the IOM®-2 bus (already not supported in NTC-T).
• HDLC Automode
• No access to S2-5 channels. Access only to S1 and Q channel as in Scout-S. No
selection betweeen transparent and non-auto mode provided.
1)
Pull-ups to 5V must be avoided. A so-called ’hot-electron-effect’ would lead to long term degradation.
Data Sheet
4
2001-11-12
PEF 81902
Overview
1.4
Pin Configuration
A4
A3
A2
A1
A0
BCL
DU
DD
SR2
SR1
VDDa_SX
VSSa_SX
SX2
SX1
TP1
•
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
/VDDDET
TP2
VDDa_SR
VSSa_SR
A5
A6
33
49
50
32
51
30
31
52
53
®
T-SMINT IX
PEF 81902
54
55
56
57
60
61
21
20
19
62
63
18
64
2
3
4
5
6
7
VSSa_UR
VDDa_UR
AIN
BIN
/RST
/RSTO
SDS2
Data Sheet
26
24
23
22
58
59
1
Figure 1
28
27
25
8
9 10 11 12 13 14 15 16
SDS1
ALE
/WR or R/W
/RD or /DS
/CS
VDDD
VSSD
/INT
XOUT
XIN
BOUT
VDDa_UX
VSSa_UX
AOUT
29
17
FSC
DCL
VSSD
VDDD
AD7 or SDX
AD6 or SDR
AD5 or SCLK
AD4
AD3
AD2
AD1
AD0
/EAW
M CLK
/ACT
pin_2.vsd
Pin Configuration
5
2001-11-12
PEF 81902
Overview
1.5
Block Diagram
•
XIN
SR1
XOUT
VDDDET
Clock Generation
SR2
RST RSTO
POR/UVD
AOUT
BOUT
SX1
S-Transceiver
SX2
U-Tansceiver
AIN
D-Channel
Arbitration
TP1
HDLC
Controller
Factory
Tests
TP2
FIFO
M
O
N
C/I
TIC
C
D
A
W
D
T
LED
ACT
µP Interface
(e.g. Multiplexed Mode)
IOM-2 Interface
FSC DCL BCL DU DD SDS1 SDS2
BIN
AD0-AD7
ALE
RD
WR
CS
INT MCLK
EAW
block diagram.vsd
Figure 2
Data Sheet
Block Diagram
6
2001-11-12
PEF 81902
Overview
1.6
Pin Definitions and Functions
•
Table 2
Data Sheet
Pin Definitions and Functions
Pin
Symbol
Type
Function
2
VDDa_UR
–
Supply voltage for U-Receiver
(3.3 V ± 5 %)
1
VSSa_UR
–
Analog ground (0 V) U-Receiver
62
VDDa_UX
–
Supply voltage for U-Transmitter
(3.3 V ± 5 %)
63
VSSa_UX
–
Analog ground (0 V) U-Transmitter
51
VDDa_SR
–
Supply voltage for S-Receiver
(3.3 V ± 5 %)
52
VSSa_SR
–
Analog ground (0 V) S-Receiver
46
VDDa_SX
–
Supply voltage for S-Transmitter
(3.3 V ± 5 %)
45
VSSa_SX
–
Analog ground (0 V) S-Transmitter
29
VDDD
–
Supply voltage digital circuits
(3.3 V ± 5 %)
30
VSSD
–
Ground (0 V) digital circuits
13
VDDD
–
Supply voltage digital circuits
(3.3 V ± 5 %)
14
VSSD
–
Ground (0 V) digital circuits
32
FSC
O
Frame Sync:
8-kHz frame synchronization signal
31
DCL
O
Data Clock:
IOMâ-2 interface clock signal (double clock):
1.536 MHz
35
BCL
O
Bit Clock:
The bit clock is identical to the IOMâ-2 data rate
(768 kHz)
33
DD
I/O
OD
Data Downstream:
Data on the IOMâ-2 interface
34
DU
I/O
OD
Data Upstream:
Data on the IOMâ-2 interface
7
2001-11-12
PEF 81902
Overview
Table 2
Data Sheet
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
8
SDS1
O
Serial Data Strobe1:
Programmable strobe signal for time slot and/or
D-channel indication on IOMâ-2
7
SDS2
O
Serial Data Strobe2:
Programmable strobe signal for time slot and/or
D-channel indication on IOMâ-2
12
CS
I
Chip Select:
A low level indicates a microcontroller access to
the T-SMINTâIX
26
SCLK
I
26
AD5
I/O
Serial Clock:
Clock signal of the SCI interface if a serial
interface is selected
Multiplexed Bus Mode:
Address/data bus
Address/data line AD5 if the parallel interface is
selected
Non-Multiplexed Bus Mode:
Data bus
Data line D5 if the parallel interface is selected
27
SDR
I
27
AD6
I/O
Serial Data Receive:
Receive data line of the SCI interface if a serial
interface is selected
Multiplexed Bus Mode:
Address/data bus
Address/data line AD6 if the parallel interface is
selected
Non-Multiplexed Bus Mode:
Data bus
Data line D6 if the parallel interface is selected
8
2001-11-12
PEF 81902
Overview
Table 2
Data Sheet
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
28
SDX
OD/O
28
AD7
I/O
Serial Data Transmit:
Transmit data line of the SCI interface if a serial
interface is selected
Multiplexed Bus Mode:
Address/data bus
Address/data line AD7 if the parallel interface is
selected
Non-Multiplexed Bus Mode:
Data bus
Data line D7 if the parallel interface is selected
21
22
23
24
25
AD0
AD1
AD2
AD3
AD4
I/O
I/O
I/O
I/O
I/O
Multiplexed Bus Mode:
Address/data bus
Transfers addresses from the microcontroller to
the T-SMINTâIX and data between the
microcontroller and the T-SMINTâIX.
Non-Multiplexed Bus Mode:
Data bus.
Transfers data between the microcontroller and
the T-SMINTâIX (data lines D0-D4).
36
37
38
39
40
53
54
A0
A1
A2
A3
A4
A5
A6
I
I
I
I
I
I
I
Non-Multiplexed Bus Mode:
Address bus transfers addresses from the
microcontroller to the T-SMINTâIX. For indirect
address mode only A0 is valid.
Multiplexed Bus Mode
Not used in multiplexed bus mode. In this case
A0-A6 should directly be connected to VDD.
11
RD
I
DS
I
Read
Indicates a read access to the registers (Intel
bus mode).
Data Strobe
The rising edge marks the end of a valid read or
write operation (Motorola bus mode).
9
2001-11-12
PEF 81902
Overview
Table 2
Data Sheet
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
10
WR
I
R/W
I
Write
Indicates a write access to the registers (Intel
bus mode).
Read/Write
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host
access as a write operation (Motorola bus
mode).
9
ALE
I
Address Latch Enable
An address on the external address/data bus
(multiplexed bus type only) is latched with the
falling edge of ALE.
ALE also selects the microcontroller interface
type (multiplexed or non multiplexed).
5
RST
I
Reset:
Low active reset input. Schmitt-Trigger input
with hysteresis of typical 360mV. Tie to ’1’ if not
used.
6
RSTO
OD
Reset Output:
Low active reset output.
15
INT
OD
Interrupt Request:
INT becomes active if the T-SMINTâIX requests
an interrupt.
18
MCLK
O
Microcontroller Clock:
Clock output for the microcontroller
20
EAW
I
External Awake:
A low level on EAW during power down
activates the clock generation of the TSMINTâIX, i.e. the IOMâ-2 interface provides
FSC, DCL and BCL for read and write access.1)
43
SX1
O
S-Bus Transmitter Output (positive)
44
SX2
O
S-Bus Transmitter Output (negative)
47
SR1
I
S-Bus Receiver Input
10
2001-11-12
PEF 81902
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol
Type
Function
48
SR2
I
S-Bus Receiver Input
60
XIN
I
Crystal 1:
Connected to a 15.36 MHz crystal
59
XOUT
O
Crystal 2:
Connected to a 15.36 MHz crystal
64
AOUT
O
Differential U-interface Output
61
BOUT
O
Differential U-interface Output
3
AIN
I
Differential U-interface Input
4
BIN
I
Differential U-interface Input
49
VDDDET
I
VDD Detection:
This pin selects if the VDD detection is active
(’0’) and reset pulses are generated on pin
RSTO or whether it is deactivated (’1’) and an
external reset has to be applied on pin RST.
17
ACT
O
Activation LED.
Indicates the activation status of U- and Stransceiver. Can directly drive a LED (4mA).
42
TP1
I
Test Pin 1.
Used for factory device test.
Tie to ’VSS’
50
TP2
I
Test Pin 2.
Used for factory device test.
Tie to ’VSS’
16, 19,
41, 55
56, 57,
58
1)
Tie to ‘1‘
res
Reserved
These pins are reserved for future use. Do not
connect.
This function of pin EAW is different to that defined in Ref. [13]
Data Sheet
11
2001-11-12
PEF 81902
Overview
I: Input
O: Output (Push-Pull)
OD: Output (Open Drain)
1.6.1
Specific Pins and Test Modes
LED Pin ACT
A LED can be connected to pin ACT to display four different states (off, slow flashing,
fast flashing, on). It displays the activation status of the U- and S-transceiver according
to Table 3. or it is programmable via two bits (LED1 and LED2 in register MODE2).
Table 3
ACT States
Pin ACT
LED
U_Deactivated
U_Activated
S_Activated
VDD
OFF
1
x
x
0
0
x
1Hz (3 : 1)* slow flashing 0
1
0
GND
1
1
2Hz (1 : 1)* fast flashing
ON
0
Note: * denotes the duty cycle ’high’ : ’low’.
with:
U_Deactivated: ’Deactivated State’ as defined in Chapter 2.4.7.6.
U_Activated: ’SBC Synchronizing’, ’Wait for Info U4H’, and ‘Transparent‘ as defined in
Chapter 2.4.7.6.
S-Activated: ’Activated State’ as defined in Chapter 2.5.5.2.
Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this
additional LED to 3.3V only).
Test Modes
The test patterns on the S-interface (‘2 kHz Single Pulses‘, ‘96 kHz Continuous Pulses‘)
and on the U-interface (‘Data Through‘, ‘Send Single Pulses‘,) are invoked via C/I codes
(TM1, TM2, DT, SSP). Setting SRES.RES_U to ‘1‘ forces the U-transceiver into test
mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver is hardware reset.
Data Sheet
12
2001-11-12
PEF 81902
Overview
1.7
System Integration
•
DC/DC-Converter
IDCC
PEB2023
S/T - Interface
S
U - Interface
T-SMINTIX
PEF81902
U
HDLC /
FIFO
POTS Interface
µP
HV - SLIC
SLICOFI-2
HV - SLIC
C513
IOM-2
LCNTappl.vsd
Figure 3
Application Example T-SMINT®IX: Low Cost Intelligent NT
The U-transceiver, the S-transceiver, the IOMâ-2 channels and the HDLC-controller can
be controlled and monitored via:
a) the parallel or serial microprocessor interface
- Access of on-chip registers via µP interface Address/Data format
- Activation/Deactivation control of U- and S-transceiver via µP interface and C/I
handler
- T-SMINTâIX is Monitor channel master
- TIC bus is transparent on IOMâ−2 interface and is used for D-channel arbitration
between S-transceiver and on-chip HDLC controller.
Data Sheet
13
2001-11-12
PEF 81902
Overview
•
S
C/I0
U
C/I1
Mon
MON
IOM -2
C/I
Register
µc - Interface
IOM-2 Slave
e.g. SLICOFI-2
µc
iommaster.vsd
Figure 4
Control via µP Interface
Alternatively, the T-SMINTâIX can be controlled via
b) the IOMâ-2 Interface
- Access of on-chip registers via the Monitor channel with Header/Address/Data
format (Device is Monitor slave)
- Activation/Deactivation control of U- and S-transceiver via the C/I channels CI0
and CI1
- TIC bus is transparent on IOMâ−2 interface and is used for D-channel arbitration
between S-transceiver and on-chip HDLC controller.
Data Sheet
14
2001-11-12
PEF 81902
Overview
•
S
C/I1
C/I0
MON
U
Register
IOM -2
INT
IOM-2 Master
e.g. UTAH
iomslave.vsd
Figure 5
Data Sheet
Control via IOMâ-2 Interface
15
2001-11-12
PEF 81902
Functional Description
2
Functional Description
2.1
Microcontroller Interfaces
The T-SMINTâIX supports either a serial or a parallel microcontroller interface. For
applications where no controller is connected to the T-SMINTâIX microcontroller
interface, register programming is done via the IOMâ-2 MONITOR channel from a
master device. In such applications the T-SMINTâIX operates in the IOMâ-2 slave mode
(refer to the corresponding chapter of the IOMâ-2 MONITOR handler).
The interface selections are all done by pinstrapping. The possible interface selections
are listed in Table 4. The selection pins are evaluated when the reset input RST is
released. For the pin levels stated in the tables the following is defined:
’High’:dynamic pin value which must be ’High’ when the pin level is evaluated
VDD, VSS:static ’High’ or ’Low’ level (tied to VDD, VSS)
•
Interface Selection for the T-SMINTâIX
Table 4
PINS
WR
(R/W)
RD
(DS)
’High’ ’High’
VSS
VSS
Serial /Parallel
Interface
Parallel
Serial
PINS
ALE
Interface
Type/Mode
VDD
Motorola
VSS
Siemens/Intel Non-Mux
edge
Siemens/Intel Mux
’High’
VSS
Serial Control Interface(SCI)
VSS
VSS
IOMâ-2 MONITOR Channel
(Slave Mode)
CS
‘High’
Note: For a selected interface mode which does not require all pins (e.g. address pins)
the unused pins must be tied to VDD.
The microcontroller interface also consists of a microcontroller clock generation at pin
MCLK, an interrupt request at pin INT, a reset input pin RST and a reset output pin
RSTO.
The interrupt request pin INT (open drain output) becomes active if the T-SMINTâIX
requests an interrupt.
2.1.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred via the lines
SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning
Data Sheet
16
2001-11-12
PEF 81902
Functional Description
of a serial access to the registers. The T-SMINTâIX latches incoming data at the rising
edge of SCLK and shifts out at the falling edge of SCLK. Each access must be
terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB
first.
Pad mode of SDX can be selected ’open drain’ or ’push-pull’ by programming
MODE2.PPSDX.
Figure 6 shows the timing of a one byte read/write access via the serial control interface.
Data Sheet
17
2001-11-12
PEF 81902
Functional Description
•
Write Access
CS
SCLK
Header
Command/Address
Data
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SDR
`0`
write
SDX
Read Access
CS
SCLK
Header
SDR
Command/Address
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
`1`
read
Data
7 6 5 4 3 2 1 0
SDX
SCI_TIM.VSD
Figure 6
Data Sheet
Serial Control Interface Timing
18
2001-11-12
PEF 81902
Functional Description
2.1.1.1
Programming Sequences
The basic structure of a read/write access to the T-SMINTâIX registers via the serial
control interface is shown in Figure 7.
•
write sequence:
write
byte 2
0
header
SDR
7
0 7
read sequence:
byte 3
address (command)
6
0
write data
7
0
read
byte 2
header
SDR
1
7
0 7
address (command)
6
0
SDX
Figure 7
7
byte 3
0
read data
Serial Command Structure
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the T-SMINTâIX.
The possible sequences are listed in Table 5 and are described after that.
•
Table 5
Header
Byte
40H
Header Byte Code
Sequence
Adr-Data-Adr-Data
48H
43H
Sequence Type
non-interleaved
Access to
Address Range 00H-7FH
interleaved
Adr-Data-Data-Data
Read-/Write-only
41H
non-interleaved
49H
interleaved
Address Range 00H-7FH
Header 40H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequences give direct read/write access to the address
range 00H-7FH and can have any length. In this mode SDX and SDR can be connected
Data Sheet
19
2001-11-12
PEF 81902
Functional Description
together allowing data transmission on one line.
Example for a read/write access with header 40H:
SDR
header
wradr
wrdata
rdadr
SDX
rdadr
rddata
wradr
wrdata
rddata
Header 48H: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequences give direct read/write access to the address range
00H-7FH and can have any length. This mode allows a time optimized access to the
registers by interleaving the data on SDX and SDR.
Example for a read/write access with header 48H:
SDR
header
wradr
wrdata
rdadr
SDX
rdadr
wradr
rddata
rddata
wrdata
Header 43H: Read-/Write- only A-D-D-D Sequence
This mode (header 43H) can be used for a fast access to the HDLC FIFO data. Any
address (rdadr, wradr) in the range between 00H-1FH gives access to the current FIFO
location selected by an internal pointer which is automatically incremented with every
data byte following the first address byte. Generally, it can be used for any register
access to the address range 00H-7DH. The sequence can have any length and is
terminated by the rising edge of CS.
Example for a write access with header 43H:
SDR
header
wradr
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR
header
SDX
rdadr
rddata
rddata
rddata
rddata
rddata
rddata
rddata
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. This mode is useful for reading status information
before writing to the HDLC XFIFO. Generally, it can be used for any register access to
Data Sheet
20
2001-11-12
PEF 81902
Functional Description
the address range 00H-7DH. The termination condition of the read access is the
reception of the wradr. The sequence can have any length and is terminated by the rising
edge of CS.
Example for a read/write access with header 41H:
SDR
header
rdadr
SDX
rdadr
rddata
wradr
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved
A-D-A-D read access. This mode is useful for reading status information before writing
to the HDLC XFIFO. Generally, it can be used for any register access to the address
range 00H-7DH. The termination condition of the read access is the reception of the
wradr. The sequence can have any length and is terminated by the rising edge of CS.
Example for a read/write access with header 49H:
SDR
header
SDX
rdadr
rdadr
rddata
2.1.2
wradr
wrdata
wrdata
wrdata
(wradr)
(wradr)
(wradr)
rddata
Parallel Microcontroller Interface
The 8-bit parallel microcontroller interface with address decoding on chip allows an easy
and fast microcontroller access.
The parallel interface of the T-SMINTâIX provides three types of µP busses which are
selected via pin ALE. The bus operation modes with corresponding control pins are listed
in Table 6.
•
Table 6
Bus Operation Modes
Bus Mode
Pin ALE
Control Pins
(1) Motorola
VDD
CS, R/W, DS
(2) Siemens/Intel non-multiplexed
VSS
CS, WR, RD
(3) Siemens/Intel multiplexed
Edge
CS, WR, RD, ALE
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Note: For a selected interface mode which does not require all pins (e.g. address pins)
the unused pins must be tied to VDD.
Data Sheet
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PEF 81902
Functional Description
A read/write access to the T-SMINTâIX registers can be done in multiplexed or nonmultiplexed mode.
In non-multiplexed mode the register address must be applied to the address bus (A0A6) for the data access via the data bus (D0-D7).
In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE
before a read/write access via the address/data bus is performed.
The T-SMINTâIX provides two different ways to address the register contents which can
be selected with the AMOD bit in the MODE2 register. The address mode after reset is
the indirect address mode (AMOD = ’0’). Reprogramming into the direct address mode
(AMOD = ’1’) has to take place in the indirect address mode. Figure 8 illustrates both
register addressing modes.
Direct address mode (AMOD = ’1’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’0’):
• non-muxed: only the LSB of the address bus (A0)
• muxed: only the LSB of the address-data bus (AD0)
gets evaluated to address a virtual ADDRESS (0H) and a virtual DATA (1H) register.
Every access to a target register consists of:
• a write access (muxed or non-muxed) to ADDRESS to store the target register´s
address, as well as
• a read access (muxed or non-muxed) from DATA to read from the target register or
• a write access (muxed or non-muxed) to DATA to write to the target register
Data Sheet
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2001-11-12
PEF 81902
Functional Description
•
Direct Address Mode
AMOD = ´1´
Indirect Address Mode
AMOD = ´0´ (default)
D7 - D0
A6 - A0
D7 - D0
Data
A0
Data
7Fh
7Eh
7Dh
7Ch
04h
03h
02h
01h
1h
DATA
00h
0h
ADDRESS
regacces.vsd
Figure 8
2.1.3
Direct/Indirect Register Address Mode
Microcontroller Clock Generation
The microcontroller clock is derived from the unregulated 15.36 MHz clock from the
oscillator and provided by the pin MCLK. Five clock rates are selectable by a
programmable prescaler which is controlled by the bits MODE1.MCLK and
MODE1.CDS corresponding to the following table.
Table 7
MCLK Frequencies
MODE1.
MCLK
Bits
MCLK frequency
with
MODE1.CDS = ’0’
MCLK frequency
with
MODE1.CDS = ’1’
0
0
3.84 MHz
7.68 MHz
0
1
0.96 MHz
1.92 MHz
1
0
7.68 MHz
15.36 MHz
1
1
disabled
disabled
The clock rate is changed after CS becomes inactive.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
2.2
Reset Generation
Figure 9 shows the organization of the reset generation of the T-SMINTâIX.
•.
RSS1
125µs ≤ t ≤ 250µs
C/I0 Code Change
(Exchange Awake)
´0´
RSTO
´1,x´
´1´
≥1
´0,0´
RSS2,1
t = 125µs
Watchdog
´0,1´= open
RSS2,1
Deactivation
Delay
Reset MODE1
Register
Software Reset
Register (SRES)
´1´
´0´
VDDDET
RES_CI
Reset
Functional
Block
POR/UVD
RES_HDLC
RES_S
´0´
´1´
RES_U
VDDDET
≥1
Internal Reset
of all Registers
RST Pin
RESETGEN.VSD
Figure 9
Reset Generation of the T-SMINTâIX1)
Reset Source Selection
The internal reset sources C/I code change and Watchdog timer can be output at the low
active reset pin RSTO. These reset sources can be selected with the RSS2,1 bits in the
MODE1 register according to Table 8.
1)
The ’OR’-gates shall illustrate in a symbolic way, that ’source A active’ or ’source B active’ is forwarded. The
real polarity of the different sources is not considered.
Data Sheet
24
2001-11-12
PEF 81902
Functional Description
The internal reset sources set the MODE1 register to its reset value.
Table 8
1)
Reset Source Selection
RSS2
Bit 1
RSS1
Bit 0
C/I Code
Change
Watchdog
Timer
POR/UVD1) and
RST
0
0
--
--
x
0
1
1
0
x
--
x
1
1
--
x
x
/RSTO disabled (= high impedance)
POR/UVD can be enabled/disabled via pin VDDDET
•
• C/I Code Change (Exchange Awake)
A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 µs ≤ t
≤ 250 µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
1.
2.
WTC1
WTC2
1
0
0
1
Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset
out pulse on pin RSTO of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset (including
expiration of the watchdog timer).
As in the SCOUT-S, the watchdog timer is clocked with the IOMâ-2 clocks and works
only if the internal IOMâ-2 clocks are active. Hence, the power consumption is
minimized in state power down.
Software Reset Register (SRES)
Several main functional blocks of the T-SMINTâIX can be reset separately by software
setting the corresponding bit in the SRES register. This is equivalent to a hardware reset
of the corresponding functional block. The reset state is activated as long as the bit is set
to ’1’.
Data Sheet
25
2001-11-12
PEF 81902
Functional Description
External Reset Input
At the RST input an external reset can be applied forcing the T-SMINTâIX in the reset
state. This external reset signal is additionally fed to the RSTO output.
After release of an external reset, the µC has to wait for min. tµC before it starts read or
write access to the T-SMINTâIX (see Table 41).
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
tDEACT (see Table 42).
Reset Generation
The T-SMINTâIX has an on-chip reset generator based on a Power-On Reset (POR)
and Under Voltage Detection (UVD) circuit (see Table 42). The POR/UVD requires no
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on VDD ramp-up during power-on reset are described in
Chapter 5.6.5.
Clocks and Data Lines During Reset
During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock1) (MCLK)
and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD IOMâ-2 channel 0 is ’DR’ = 0000
(Value after reset of register UCIR = ’00H’)
• The output C/I code from the S-Transceiver on DU IOMâ-2 channel 1 is ’TIM’ = 0000.
1)
during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as
timer tDEAC is started.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
2.3
IOM-2 Interface
The T-SMINTâIX supports the IOMâ-2 interface in terminal mode (DCL=1.536 MHz)
according to the IOMâ-2 Reference Guide [12].
2.3.1
IOMâ-2 Functional Description
The IOMâ-2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The
rising edge of FSC indicates the start of an IOMâ-2 frame. The DCL and the BCL clock
signals synchronize the data transfer on both data lines DU and DD. The DCL is twice
the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising
edge of the first DCL clock cycle and sampled at the falling edge of the second clock
cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling
edge of the single clock cycle.
The IOMâ-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
registerThe FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on
the receive and transmit lines is determined by the frequency of the DCL clock (or BCL),
with the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are
available.
IOM®-2 Frame Structure of the T-SMINTâIX
The frame structure on the IOMâ-2 data ports (DU,DD) of the T-SMINTâIX with a DCL
clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS)
is shown in Figure 10.
•
macro_19
Figure 10
Data Sheet
IOM-2 Frame Structure of the T-SMINTâIX
27
2001-11-12
PEF 81902
Functional Description
The frame is composed of three channels:
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of e.g. the U-transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC), a MONITOR
programming channel (MON1) and a command/indication channel (CI1) for control
and programming of e.g. the S-transceiver.
• Channel 2 is used for D-channel access mechanism (TlC-bus, S/G bit). Additionally,
channel 2 supports further IC and MON channels.
2.3.2
IOMâ-2 Handler
The IOMâ-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the T-SMINTâIX and voice/data devices connected to the
IOMâ-2 interface. Additionally it provides a microcontroller access to all time slots of the
IOMâ-2 interface via the four controller data access registers (CDA).
The PCM data of the functional units
• S-transceiver (S) and the
• Controller data access (CDA)
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 12 PCM time slots of the IOMâ-2 frame. With the DPS bit
(Data Port Selection) the output of each functional unit is assigned to DU or DD
respectively. The input is assigned vice versa. With the control registers (CR) the access
to the data of the functional units can be controlled by setting the corresponding control
bits (EN, SWAP).
The IOMâ-2 handler also provides access to the
•
•
•
•
•
U and S transceiver
MONITOR channel
C/I channels (CI0,CI1)
TIC bus (TIC) and
D- and/or B-channel for HDLC control
The access to these channels is controlled by the registers S_CR, HCI_CR and
MON_CR.
The IOMâ-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The following Figure 11 shows the architecture of the IOMâ-2 handler.
Data Sheet
28
2001-11-12
PEF 81902
Functional Description
•
IOM-2 Handler
Control Data
Access
Controller Data Access (CDA)
CDA
Registers
CDA10
CDA11
CDA20
CDA21
(TSDP, DPS, EN,
SWAP, TBM,
MCDA, STI)
CDA_TSDPxy
CDA_CRx
MCDA
STI
MSTI
ASTI
SDS1/2_CR
IOM_CR
DU
MON_CR
Control
Monitor
Data
Monitor Data
MON Handler
DD
IOM-2 Interface
(EN, OD)
TIC Bus
Disable
DCL
BCL/SCLK
C/I0
Data
C/I0 Data
(EN, TLEN, TSS)
SDS1
Microcontroller Interface
IOM_CR
TIC
SDS2
C/I1
Control
HDLC
B1-Data EN
B2-Data EN
D-Data EN
D Data
B1/B2/D-ch
FIFOs
HCI_CR
Control
C/I1 Data
C/I1 Data
FSC
TIC Bus Data
Control
Transceiver
Data Access
(TSS, DPS,
EN)
D/B1/B2 Data
C/I0 Data
S_TSDP_B1
S_TSDP_B2
S_CR
Transceiver
Data
(TR=U/S)
TR_B1_X
TR_B2_X
TR_D_X
TR_B1_R
TR_B2_R
TR_D_R
TR represents the
U and S transceiver
21150_0
7
2001-11-12
29
Data Sheet
Architecture of the IOMâ-2 Handler
Figure 11
CDA Data
PEF 81902
Functional Description
2.3.2.1
Controller Data Access (CDA)
The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide
microcontroller access to the 12 IOMâ-2 time slots and more:
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting or switching of two independent PCM channels to another two independent
PCM channels on both data ports (DU, DD). Between reading and writing the data can
be manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed.
• monitoring of up to four time slots on the IOMâ-2 interface simultaneously
• microcontroller read and write access to each PCM channel
The access principle, which is identical for the two channel register pairs CDA10/11 and
CDA20/21, is illustrated in Figure 12. The index variables x,y used in the following
description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output
of the CDAxy register is defined by its own TSDPxy register.
If the SWAP bit = ’1’ (swap is enabled) the input port and time slot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and time slot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for time slot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOMâ-2 (e.g. for B-channel transmission in
upstream direction the S-transceiver writes data onto IOMâ-2 and the U-transceiver
reads data from IOMâ-2). For monitoring data in such cases a CDA register is
programmed as described below under “Monitoring Data”. Besides that none of the
IOMâ-2 timeslots must be assigned more than one input and output of any functional
unit.
Data Sheet
30
2001-11-12
PEF 81902
Functional Description
•.
TSa
TSb
DU
Control
Register
CDA_CRx
1
output
(EN_O1)
input
(EN_I1)
1
CDAx1
CDAx0
1
1
1
1
1
0
CDA_TSDPx1
Input
Swap
(SWAP)
input
(EN_I0)
0
Time Slot
Selection (TSS)
Enable
Enable
1
1
Data Port
Selection (DPS)
Time Slot
Selection (TSS)
0
0
output
(EN_O0)
Data Port
Selection (DPS)
CDA_TSDPx0
1
DD
TSa
TSb
x = 1 or 2; a,b = 0...11
Figure 12
IOM_HAND.FM4
Data Access via CDAx0 and CDAx1 register pairs
Looping and Shifting Data
Figure 13 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOMâ-2 time slot data from DU to DD or vice versa (SWAP = ’0’)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= ’1’)
c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd
and looping from DD to DU .
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
Data Sheet
31
2001-11-12
PEF 81902
Functional Description
•
a) Looping Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
TSc
’1’
TSd
’1’
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’0’
’0’
b) Shifting Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’1’
c) Switching Data
TSa
TSb
CDA10
TSc
’0’
TSd
’1’
’1’
TSc
TSd
CDA11
CDA20
CDA21
TSb
’0’
TSc
’1’
TSd
’1’
DU
DD
.TSS: TSa
.DPS ’0’
.SWAP
Figure 13
’1’
’1’
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Switching and Looping Data
Data Sheet
32
2001-11-12
PEF 81902
Functional Description
Figure 14 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is
read in the CDAxy register from DU and is written one frame later on DD.
Figure 15 shows the timing of shifting data from TSa to TSb on DU(DD). In Figure 15a)
shifting is done in one frame because TSa and TSb didn’t succeed directly one another
(a = 0...9 and b ≥ a+2). In Figure 15b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomously.
•.
FSC
DU
TSa
TSa
µC *)
DD
TSa
STOV
ACK
WR
RD
STI
CDAxy
TSa
*) if access by the µC is required
Figure 14
Data Sheet
Data Access when Looping TSa from DU to DD
33
2001-11-12
PEF 81902
Functional Description
•
a) Shifting TSa → TSb within one frame
(a,b: 0...11 and b ≥ a+2)
FSC
DU
(DD)
TSa
TSa
TSb
µC *)
STI
STOV
ACK
WR
RD
STI
CDAxy
b) Shifting TSa → TSb in the next frame
(a,b: 0...11 and (b = a+1 or b <a)
FSC
DU
(DD)
TSa TSb
TSa TSb
µC *)
STOV
WR
RD
STI
CDAxy
ACK
*) if access by the µC is required
Figure 15
Data Sheet
Data Access when Shifting TSa to TSb on DU (DD)
34
2001-11-12
PEF 81902
Functional Description
Monitoring Data
Figure 16 gives an example for monitoring of two IOMâ-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate time slots.
This mode is only valid if two blocks (e.g. both transceivers) are programmed to these
timeslots and communicating via IOMâ-2.
However, if only one block is programmed to this timeslot the timeslots for CDAx0 and
CDAx1 can be programmed completely independently.
•.
a) Monitoring Data
EN_O: ’0’
CDA_CR1. EN_I: ’1’
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
TS(2n+1)
DU
CDA10
CDA11
CDA20
CDA21
TSS: TS(2n)
CDA_CR2. DPS: ’1’
EN_I: ’1’
EN_O: ’0’
Figure 16
TS(2n+1)
’1’
’1’
’0’
DD
Example for Monitoring Data
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
Data Sheet
35
2001-11-12
PEF 81902
Functional Description
bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU
or 88h for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and
the odd numbered D-channel (TS3) simultaneously on DU and DD.
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt
(STOV).
The microcontroller access to each of the CDAxy registers can be synchronized by
means of four programmable synchronous transfer interrupts (STIxy)1) and synchronous
transfer overflow interrupts (STOVxy)2) in the STI register.
Depending on the DPS bit in the corresponding TSDPxy register the STIxy is generated
two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy0 and xy1 are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
A STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not
acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other
STIxy1 which is enabled and not acknowledged.
Table 9 gives some examples for that. It is assumed that a STOV interrupt is only
generated because a STI interrupt was not acknowledged before.
In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is
disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is
generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is
enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0.
In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only
generated due to STIxy0 and STOVxy1 is only generated due to STIxy1.
Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is
not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0.
1)
2)
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
•
Table 9
Examples for Synchronous Transfer Interrupts
Enabled Interrupts
(Register MSTI)
Generated Interrupts
(Register STI)
STI
STOV
STI
STOV
xy0
-
xy0
-
Example 1
-
xy0
-
-
Example 2
xy0
xy1
xy0
xy1
Example 3
xy0
xy0 ; xy1
xy0
xy0 ; xy1
Example 4
xy0 ; xy1
xy0 ; xy1
xy0
xy1
xy0
xy1
Example 5
xy0 ; xy1
xy1
xy0
xy1
xy1
Example 6
xy0 ; xy1
xy0 ; xy1 ; xy2
xy0
xy1
xy0 ; xy2
xy1 ; xy2
Example 7
Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is
generated additionally for both STIxy0 and STIxy1.
A STOV interrupt is not generated if all stimulating STI interrupts are acknowledged.
A STIxy must be acknowledged by setting the ACKxy bit in the ASTI register two BCL
clock (for DPS=’0’) or one BCL clocks (for DPS=’1’) before the time slot which is selected
for the appropriate STIxy. The interrupt structure of the synchronous transfer is shown
in Figure 17.
Data Sheet
37
2001-11-12
PEF 81902
Functional Description
•.
INT
U
ST
CIC
TIN
U
ST
CIC
TIN
WOV
S
MOS
HDLC
WOV
S
MOS
HDLC
MASK
ISTA
Figure 17
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
STI
ACK21
ACK20
ACK11
ACK10
ASTI
Interrupt Structure of the Synchronous Data Transfer
Figure 18 shows some examples based on the timeslot structure. Figure a) shows at
which point in time a STI and STOV interrupt is generated for a specific timeslot. Figure
b) is identical to example 3 above, figure c) corresponds to example 5 and figure d)
shows example 4.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
•.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
21
TS5
'1'
'1'
TS11 TS0 TS1 TS2 TS3
20
TS11
'1'
'1'
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA
access"; MSTI.STI10 and MSTI.STOV20 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'1'
11
TS1
'1'
'1'
21
TS5
'1'
'1'
TS11 TS0 TS1 TS2 TS3
20
TS11
'1'
'0'
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10,
MSTI.STI11 and MSTI.STOV11 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'0'
'0'
21
TS5
'1'
'1'
TS11 TS0 TS1 TS2 TS3
20
TS11
'1'
'1'
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV20 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
21
TS5
'1'
'1'
TS11 TS0 TS1 TS2 TS3
20
TS11
'1'
'0'
TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 18
Examples for the Synchronous Transfer Interrupt Control with one
STIxy enabled
•
.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
2.3.2.2
Serial Data Strobe Signal
For time slot oriented standard devices at the IOMâ-2 interface, the T-SMINTâIX
provides two independent data strobe signals SDS1 and SDS2.
The two strobe signals can be generated with every 8-kHz-frame and are controlled by
the registers SDS1/2_CR. By programming the TSS bits and three enable bits
(ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOMâ-2
time slots TS, TS+1 and TS+3 (bit7,6) and the combinations of them.
The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
•
FSC
DD,DU
B1
B2
MON0
TS0
TS1
TS2
D CI0
MM
RX
TS3
IC1
IC2 MON1
TS4
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1,2
(Example1)
SDS1,2
(Example2)
SDS1,2
(Example3)
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '0'
= '1'
= '0'
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '5H'
= '1'
= '1'
= '0'
Example 3:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '1'
= '1'
= '1'
Figure 19
Data Sheet
strobe.vsd
Data Strobe Signal Generation
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2001-11-12
PEF 81902
Functional Description
Figure 19 shows three examples for the generation of a strobe signal. In example 1 the
SDS is active during channel B2 on IOMâ-2, whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which is used
e.g. at an IDSL (144 kbit/s) transmission.
2.3.3
IOMâ-2 Monitor Channel
The IOMâ-2 MONITOR channel is utilized for information exchange between the TSMINTâIX and other devices in the MONITOR channel.
The MONTIOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the transmission of the MONITOR data one of the 3 IOMâ-2
channels can be selected by setting the MONITOR channel selection bits (MCS) in the
MONITOR control register (MON_CR).
The DPS bit in the same register selects between an output on DU or DD respectively
and with EN_MON the MONITOR data can be enabled/disabled. The default value is
MONITOR channel 0 (MON0) enabled and transmission on DD.
The MONITOR channel of the T-SMINTâIX can be used in the following applications
(refer also to and ):
• As a master device the T-SMINTâIX can program and control other devices (e.g.
PSB 2161) attached to the IOMâ-2, which therefore, do not need a microcontroller
interface.
• As a slave device the T-SMINTâIX is programmed and controlled from a master
device on IOMâ-2 (e.g. UTAH). This is used in applications where no microcontroller
is connected directly to the T-SMINTâIX.
The MONITOR channel operates according to the IOMâ-2 Reference Guide [12].
Note: In contrast to the NTC-T, the T-SMINTâIX does neither issue nor react on Monitor
commands (MON0,1,2,8). Instead, the T-SMINTâIX operated in IOMâ-2 slave
mode must be programmed via new MONITOR channel concept (see
Chapter 2.3.3.4), which provides full register access. The Monitor time out
procedure is available. Reporting of the T-SMINTâIX is performed via interrupts.
2.3.3.1
Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
The MONITOR channel protocol is described In the following section and Figure 22
shall illustrate this. The relevant control and status bits for transmission and reception
are listed in Table 10 and Table 11.
Table 10
Transmit Direction
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MXC
MX Bit Control
MIE
Transmit Interrupt (MDA, MAB, MER) Enable
MDA
Data Acknowledged
MAB
Data Abort
MAC
Transmission Active
Status
MOSR
MSTA
Table 11
Receive Direction
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MRC
MR Bit Control
MRE
Receive Interrupt (MDR) Enable
MDR
Data Received
MER
End of Reception
Status
Data Sheet
MOSR
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2001-11-12
PEF 81902
Functional Description
•
µP
Transmitter
MIE = 1
MOX = ADR
MXC = 1
MAC = 1
MDA Int.
MOX = DATA1
MDA Int.
MOX = DATA2
MDA Int.
MXC = 0
µP
Receiver
MON
MX
MR
FF
FF
ADR
1
1
0
1
1
1
ADR
DATA1
DATA1
0
1
0
0
0
0
DATA1
DATA1
0
0
1
0
DATA2
DATA2
1
0
0
0
DATA2
DATA2
0
0
1
0
FF
FF
1
1
0
0
FF
FF
1
1
1
1
125 µs
MDR Int.
RD MOR (=ADR)
MRC = 1
MDR Int.
RD MOR (=DATA1)
MDR Int.
RD MOR (=DATA2)
MER Int.
MRC = 0
MAC = 0
ITD10032
Figure 20
MONITOR Channel Protocol (IOM®-2)
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microprocessor
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(0), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates a MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol. In addition,
Data Sheet
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2001-11-12
PEF 81902
Functional Description
it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable
(MIE) to ’1’.
As a result, the first MONITOR byte is acknowledged by the receiving device setting the
MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the
transmitter.
A new MONITOR data byte can now be written by the microprocessor in MOX. The MX
bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR
channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the MONITOR byte in MOR and generates a new MDR
interrupt status. When the microprocessor has read the MOR register, the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive
state. This in turn causes the transmitter to generate a MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send. Note that the
MONITOR channel protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microprocessor sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an
inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a MONITOR Channel End of Reception MER interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the MONITOR Channel Active MAC bit return to ’0’.
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending an inactive MR bit value in two consecutive frames. This is effected
by the microprocessor writing the MR control bit MRC to ’0’. An aborted transmission is
indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
The MONITOR transfer protocol rules are summarized in the following section
• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
an idle state or an end of transmission.
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
• The internal MX, MR control indicates or acknowledges a new byte in the MON slot
by toggling MX, MR from the active to the inactive state for one frame.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOMâ-2 frame following the
first byte occurrence. Delaying a transmission sequence is only possible while the
receiver MR-bit and the transmitter MX-bit are active.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
• Since a double last-look criterion is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
• To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
• Two frames with the MX bit in the inactive state indicates the end of a message
(EOM).
• Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the device to send back the response before the transmission
from the controller is completed (the device does not wait for EOM from controller).
2.3.3.2
Error Treatment
In case the device does not detect identical monitor messages in two successive frames,
transmission is not aborted. Instead the device will wait until two identical bytes are
received in succession.
A transmission is aborted by the device if
• an error in the MR handshaking occurs
• a collision on the IOMâ-2 bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the device if
• an error in the MX handshaking occurs or
• an abort request from the opposite device occurs
MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOMâ-2 frames. The
controller must react with EOM.
Figure 21 shows an example for an abort requested by the receiver, Figure 22 shows
an example for an abort requested by the transmitter and Figure 23 shows an example
for a successful transmission.
Data Sheet
45
2001-11-12
PEF 81902
Functional Description
•
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MX (DU)
EOM
0
1
MR (DD)
0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 21
Monitor Channel, Transmission Abort requested by the Receiver
•
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MR (DU)
EOM
0
1
MX (DD)
0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 22
Monitor Channel, Transmission Abort requested by the Transmitter
•
IOM -2 Frame No.
MR (DU)
1
2
3
4
5
6
8
1
EOM
0
MX (DD)
7
1
0
mon_norm.vsd
Figure 23
Data Sheet
Monitor Channel, Normal End of Transmission
46
2001-11-12
PEF 81902
Functional Description
2.3.3.3
MONITOR Channel Programming as a Master Device
The master mode is selected by default if one of the microcontroller interfaces is
selected. The monitor data is written by the microcontroller in the MOX register and
transmitted via IOMâ-2 DD(DU) line to the programmed/controlled device e.g. ARCOFIBA PSB 2161. The transfer of the commands in the MON channel is regulated by the
handshake protocol mechanism with MX, MR.
2.3.3.4
MONITOR Channel Programming as a Slave Device
MONITOR slave mode can be selected by pinstrapping the microcontroller interface pins
according to Table 4. All programming data required by the device is received in the
MONITOR time slot on the IOMâ-2 and is transferred to the MOR register. The transfer
of the commands in the MON channel is regulated by the handshake protocol
mechanism with MX, MR which is described in the previous Chapter 2.3.3.1.
The first byte of the MONITOR message must contain in the higher nibble the MONITOR
channel address code which is ’1000’ for the T-SMINTâIX. The lower nibble
distinguishes between a programming command and an identification command.
Identification Command
In order to be able to identify unambiguously different hardware designs of the TSMINTâIX by software, the following identification command is used:
DU 1st byte value
1
0
0
0
0
0
0
0
DU 2nd byte value
0
0
0
0
0
0
0
0
The T-SMINTâIX responds to this identification sequence by sending a identification
sequence:
DD 1st byte value
1
0
DD 2nd byte value
0
0
0
0
0
0
DESIGN
0
0
<IDENT>
DESIGN: six bit code, specific for each device in order to identify differences in operation
(see “ID - Identification Register” on Page 175).
This identification sequence is usually done once, when the T-SMINTâIX is connected
for the first time. This function is used so that the software can distinguish between
different possible hardware configurations. However this sequence is not compulsory.
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte is equivalent to the
structure of the serial control interface described in chapter Chapter 2.1.1.
Data Sheet
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2001-11-12
PEF 81902
Functional Description
•
DU 1st byte value
1
0
0
DU 2nd byte value
DU 3rd byte value
0
0
0
0
1
Header Byte
R/W
Command/
Register Address
DU 4th byte value
Data 1
DU (nth + 3) byte value
Data n
All registers can be read back when setting the R/W bit to ’1’. The T-SMINTâIX responds
by sending his IOMâ-2 specific address byte (81h) followed by the requested data.
Note: Application Hint:
It is not allowed to disable the MX- and MR-control in the programming device at
the same time! First, the MX-control must be disabled, then the µC has to wait for
an End of Reception before the MR-control may be disabled. Otherwise, the TSMINTâIX does not recognize an End of Reception.
2.3.3.5
Monitor Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device or for transmit data from the microcontroller. After 40 IOMâ-2
frames (5 ms) without reply the timer expires and the transmission will be aborted with
an EOM (End of Message) command by setting the MX bit to ’1’ for two consecutive
IOMâ-2 frames.
2.3.3.6
MONITOR Interrupt Logic
Figure 24 shows the interrupt structure of the MONITOR handler. The MONITOR Data
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE set to “0” prevents the occurrence of MDR status, including when the first byte of
a packet is received. When MRE is set to “1” but MRC is set to “0”, the MDR interrupt
status is generated only for the first byte of a receive packet. When both MRE and MRC
are set to “1”, MDR is always generated and all received MONITOR bytes - marked by
a 1-to-0 transition in MX bit - are stored. Additionally, a MRC set to “1” enables the control
of the MR handshake bit according to the MONITOR channel protocol.
Data Sheet
48
2001-11-12
PEF 81902
Functional Description
•
MASK
U
ST
CIC
TIN
ISTA
U
ST
CIC
TIN
WOV
S
MOS
HDLC
WOV
S
MOS
HDLC
MRE
MIE
MOCR
MDR
MER
MDA
MAB
MOSR
INT
Figure 24
2.3.4
MONITOR Interrupt Structure
C/I Channel Handling
The Command/Indication channel carries real-time status information between the TSMINTâIX and another device connected to the IOM â-2.
1) C/I0 channel lies in IOMâ-2 channel 0 and access may be arbitrated via the TIC bus
access protocol. In this case the arbitration is done in IOM â-2 channel 2.
The C/I0 channel is accessed via register CIR0 (received C/I0 data from DD) and
register CIX0 (transmitted C/I0 data to DU). The C/I0 code is four bits long.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated any time a change occurs (ISTA.CIC).
C/I0 only: a new code must be found in two consecutive IOMâ-2 frames to be considered
valid and to trigger a C/I code change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) lies in IOMâ-2 channel 1 and is used to convey real
time status information of the on-chip S-transceiver or an external device. The C/I1
channel consists of four or six bits in each direction. The width can be changed from 4
bit to 6 bit by setting bit CIX1.CICW.
Data Sheet
49
2001-11-12
PEF 81902
Functional Description
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. The connection of CIR1 and
CIX1 to DD and DU, respectively, can be selected by setting bit HCI_CR.DPS_CI1. A
change in the received C/I1 code is indicated by an interrupt status without double last
look criterion.
CIC Interrupt Logic
Figure 25 shows the CIC interrupt structure.
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code are obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
•
MASK
U
ST
CIC
TIN
WOV
S
MOS
HDLC
ISTA
U
ST
CIC
TIN
WOV
S
MOS
HDLC
CI1E
CIX1
CIC0
CIC1
CIR0
INT
Figure 25
Data Sheet
CIC Interrupt Structure
50
2001-11-12
PEF 81902
Functional Description
2.3.5
D-Channel Access Control
The upstream D-channel is arbitrated between the S-bus, the internal HDLC controller
and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the
IOMâ-2 Reference Guide1). Further to the implementation in the INTC-Q it is possible,
to set the priority (8 or 10) of all HDLC-controllers connected to IOMâ-2, which is
particularly useful for use of the T-SMINTâIX together with the UTAH.
2.3.5.1
Application Example for D-Channel Access Control
Figure 26 shows a scenario for the local D-channel arbitration between the S-bus and
the microcontroller.
•
T-SMINTâIX
E-Bit
D
BAC, TBA
S
Arbitr.
Prio
U
S/G
IOM-2 i/f
HDLC
D
CIX0
CIR0
µP - i/f
µC
e.g. C513,
C161-RI
µC writes data into FIFO,
transmission happens.automatically
Q-SMINTIX delivers an interrupt,
when transmission is complete
IOM-2
Figure 26
2.3.5.2
D-Channel Arbitration: µC has no HDLC and no Direct Access to TIC
Bus
TIC Bus Handling
The TIC bus is implemented to organize the access to the C/I0-channel and to the Dchannel from up to 7 D-channels HDLC controllers. The arbitration mechanism must be
activated by setting MODEH.DIM2-0=00x.
The arbitration mechanism is implemented in the last octet in IOMâ-2 channel 2 of the
IOMâ-2 interface (see Figure 27). An access request to the TIC bus may either be
generated by software (µC access to the C/I0-channel via CIX0 register) or by an internal
1)
The A/B-bit is not supported by the U-transceiver
Data Sheet
51
2001-11-12
PEF 81902
Functional Description
or an external D-channel HDLC controller (transmission of an HDLC frame in the Dchannel). A software access request to the bus is effected by setting the BAC bit in
register CIX0 to ’1’ (resulting in BAC = ’0’ on IOMâ-2).
In the case of an access request by the T-SMINTâIX, the Bus Accessed-bit BAC (bit 5
of last octet of CH2 on DU, see Figure 27) is checked for the status "bus free“, which is
indicated by a logical ’1’. If the bus is free, the T-SMINTâIX transmits its individual TIC
bus address TAD programmed in the CIX0 register (CIX0.TBA2-0). While being
transmitted the TIC bus address TAD is compared bit by bit with the value read back on
DU. If a sent bit set to ’1’ is read back as ’0’ because of the access of an external device
with a lower TAD, the T-SMINTâIX withdraws immediately from the TIC bus, i.e. the
remaining TAD bits are not transmitted. The TIC bus is occupied by the device which
sends and reads back its address error-free. If more than one device attempt to seize
the bus simultaneously, the one with the lowest address values wins. This one will set
BAC=0 on TIC bus and starts D-channel transmission in the same frame.
•
MR
MX
DU
B1
B2
MON0
D CI0
IC1
MR
MX
IC2
MON1
CI1
BAC
TAD
2
1
0
TAD
BAC
ITD02575.vsd
TIC-BUS Address (TAD 2 - 0)
Bus Accessed ("1" no TIC-BUS Access)
Figure 27
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the T-SMINTâIX, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the T-SMINTâIX is automatically set into a
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOMâ-2 interface request access to the D and C/
I0 channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I0 channels.
Note: Bit BAC (CIX0 register) should be reset by the µC when access is no more
requested, to grant other devices access to the D and C/I0 channels.
Data Sheet
52
2001-11-12
PEF 81902
Functional Description
2.3.5.3
Stop/Go Bit Handling
The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet
in DD channel 2 (Figure 28). The arbitration mechanism must be activated by setting
MODEH.DIM2-0=0x1.
S/G = 1 : stop
S/G = 0 : go
The Stop/Go bit is available to other layer-2 devices connected to the IOMâ-2 interface
to determine if they can access the D channel in upstream direction.
•
MR
MX
DD
B1
B2
MON
0
D CI0
IC1
MR
MX
IC2
MON1
S/G
A/B
CI1
S/G A/B
Stop/Go
Figure 28
2.3.5.4
Available/Blocked
ITD09693.vsd
Structure of Last Octet of Ch2 on DD
D-Channel Arbitration
In intelligent NT applications (selected via register S_MODE.MODE2-0) the TSMINTâIX has to share the upstream D-channel with one or more D-channel controllers
on the IOMâ-2 interface and with all connected TEs on the S interface.
The S-transceiver incorporates an elaborate state machine for D-channel priority
handling on IOMâ-2 (Chapter 2.3.5.5). For the access to the D-channel a similar
arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is
performed for all D-channel sources on IOMâ-2. Due to this an equal and fair access is
guaranteed for all D-channel sources on both the S interface and the IOMâ-2 interface.
The access to the upstream D-channel is handled via the S/G bit for the HDLC
controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the
terminals on S). Furthermore, if more than one HDLC source is requesting D-channel
access on IOMâ-2 the TIC bus mechanism is used (see Chapter 2.3.5.2).
The arbiter permanently counts the “1s” in the upstream D-channel on IOMâ-2. If the
necessary number of “1s” is counted and an HDLC controller on IOMâ-2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOMâ-2 can be configured to 8 or
10 (S_CMD.DPRIO).
Data Sheet
53
2001-11-12
PEF 81902
Functional Description
The configuration settings of the T-SMINTâIX in intelligent NT applications are
summarized in Table 12.
•
Table 12
T-SMINTâIX Configuration Settings in Intelligent NT Applications
Functional Configuration
Block
Description
Configuration Setting
Layer 1
S-Transceiver Mode Register:
S_MODE.MODE0 = 0 (NT state machine)
or
S_MODE.MODE0 = 1 (LT-S state machine)
Select Intelligent
NT mode
S_MODE.MODE1 = 1
S_MODE.MODE2 = 1
Layer 2
Enable S/G bit and
TIC bus evaluation
D-channel Mode Register:
MODEH.DIM2-0 = 001
Note: For mode selection in the S_MODE register the MODE1/2 bits are used to select
intelligent NT mode, MODE0 selects NT or LT-S state machine.
With the configuration settings shown above the T-SMINTâIX in intelligent NT
applications provides for equal access to the D-channel for terminals connected to the
S-interface and for D-channel sources on IOMâ-2.
2.3.5.5
State Machine of the D-Channel Arbiter
Figure 29 gives a simplified view of the state machine of the D-channel arbiter. CNT is
the number of ’1’ on the IOMâ-2 D-channel and BAC corresponds to the BAC-bit on
IOMâ-2. The number n depends on configuration settings (selected priority 8 or 10) and
the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10,
respectively) or if the last transmission was successful (n = 9 or 11, respectively).
Data Sheet
54
2001-11-12
PEF 81902
Functional Description
•
RST=0, A/B=0, Mode=0xx
IN
OUT
READY
S/G = 1
E = D 1)2)
(BAC=0 or DCI=1)
& CNT ≥ n
S ACCESS
S/G = 1
E
CNT ≥ 6
(BAC=1 & DCI=0)
BAC = d.c. DCI = 0
DCI
State
S/G
BAC = 1 & DCI = 0
(CNT ≥ 2 & D=0)
& [BAC = 1 or (BAC = 0 & CNT < n)]
BAC
BAC = d.c. DCI = d.c.
LOCAL ACCESS
Transmit / Stop Flag
S/G = 0
E=D
CNT = 6
E = D1)
BAC = 0 or DCI = 1
LOCAL ACCESS
Wait for Start Flag
1) Setting DCI = 1 causes E = D
2) Setting A/B = 0 causes E = D
S/G = 0
E=D
D-Channel_Arbitration.vsd
Figure 29
State Machine of the D-Channel Arbiter (Simplified View)1)
1. Local D-Channel Controller Transmits Upstream
In the initial state (’Ready’ state) neither the local D-channel sources nor any of the
terminals connected to the S-bus transmit in the D-channel.
The T-SMINTâIX S-transceiver thus receives BAC = “1” (IOMâ-2 DU line) and transmits
S/G = “1” (IOMâ-2 DD line). The access will then be established according to the
following procedure:
• Local D-channel source verifies that BAC bit is set to ONE (currently no bus access).
• Local D-channel source issues TIC bus address and verifies that no controller with
higher priority requests transmission (TIC bus access must always be performed even
if no other D-channel sources are connected to IOMâ-2).
• Local D-channel source issues BAC = “0” to block other sources on IOMâ-2 and to
announce D-channel access.
• T-SMINTâIX S-transceiver pulls S/G bit to ZERO (’Local Access’ state) as soon as
CNT ≥ n (see note) to allow sending D-channel data from the entitled source.
1)
If the S-transceiver is reset by SRES.RES_S = ’1’ or disabled by S_CONF0.DIS_TR = ’1’, then the D-channel
arbiter is in state Ready (S/G = ’1’), too. The S/G evaluation of the HDLC has to be disabled in this case;
otherwise, the HDLC is not able to send data.
Data Sheet
55
2001-11-12
PEF 81902
Functional Description
•
•
•
•
T-SMINTâIX S-transceiver transmits inverted echo channel (E bits) on the S-bus to
block all connected S-bus terminals (E = D).
Local D-channel source commences with D data transmission on IOMâ-2 as long as
it receives S/G = “0”.
After D-channel data transmission is completed the controller sets the BAC bit to
ONE.
T-SMINTâIX S-transceiver transmits non-inverted echo (E = D).
T-SMINTâIX S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel
controller on IOMâ-2.
Note: If right after D-data transmission the D-channel arbiter goes to state ’Ready’ and
the local D-channel source wants to transmit again, then it may happen that the
leading ’0’ of the start flag is written into the D-channel before the D-channel
source recognizes that the S/G bit is pulled to ’1’ and stops transmission. In order
to prevent unintended transitions to state ’S-Access’, the additional condition CNT
≥ 2 is introduced. As soon as CNT ≥ n, the S/G bit is set to ’0’ and the D-channel
source may start transmission again (if TIC bus is occupied). This allows an equal
access for D-channel sources on IOMâ-2 and on the S interface.
2. Terminal Transmits D-Channel Data Upstream
The initial state is identical to that described in the last paragraph. When one of the
connected S-bus terminals needs to transmit in the D-channel, access is established
according to the following procedure:
• S-transceiver recognizes that the D-channel on the S-bus is active via D = ’0’.
• S-transceiver transfers S-bus D-channel data transparently through to the upstream
IOMâ-2 bus.
2.3.6
Activation/Deactivation of IOM®-2 Interface
The deactivation procedure of the IOMâ-2 interface is shown in Figure 30. After
detecting the code DI (Deactivation Indication) the T-SMINTâIX responds by
transmitting DC (Deactivation Confirmation) during subsequent frames and stops the
timing signals after the fourth frame. The clocks stop at the end of the C/I-code in IOMâ2 channel 0.
Data Sheet
56
2001-11-12
PEF 81902
Functional Description
•
a)
IOM R -2 Interface
deactivated
FSC
DI
DI
DI
DI
DI
DI
DR
DR
DC
DC
DC
DC
DIN
DOUT
Detail see Fig.b
b)
IOM R -2 Interface
deactivated
DCL
DIN
D
C/ Ι
C/ Ι
C/ Ι
C/ Ι
ITD10292
Figure 30
Deactivation of the IOM®-2 Clocks
Conditions for Power-Down
If none of the following conditions is true, the IOMâ-2 interface can be switched off,
reducing power consumption to a minimum.
•
•
•
•
•
•
•
S-transceiver is not in state ’Deactivated’
Signal INFO0 on the S-interface
Uk0-transceiver is not in state ’Deactivated’
Pin DU is low (either at the IOMâ-2 interface or via IOM_CR.SPU)
External pin EAW External Awake is low
Bit MODE 1.CFS = ’0’
Stop on the correct place in the IOMâ-2 frame. DCL must be low during power down
(stop on falling edge of DCL) (see Figure 30).
A deactivated IOMâ-2 can be reactivated by one of the following methods:
• Pulling pin DU line low:
– directly at the IOMâ-2 interface
– via the µP interface with "Software Power Up" (IOM_CR:SPU bit)
• Pulling pin EAW ‘External Awake‘ low
• Setting ‘Configuration Select‘ MODE1:CFS bit = ’0’
• Level detection at the S-interface
• Activation from the U-interface
Data Sheet
57
2001-11-12
PEF 81902
Functional Description
2.4
U-Transceiver
The statemachine of the U-Transceiver is compatible to the NT state machine in the PEB
8090 documentation [9], but includes some minor changes for simplification and
compliance to Ref. [1].
The U-transceiver is configured and controlled via the registers described in Chapter 4.
The U-transceiver is always in IOMâ-2 channel 0.
2.4.1
4B3T Frame Structure
The 4B3T U-interface performs full duplex data transmission and reception at the Ureference point according to ETSI TS 102 080 and FTZ 1TR 220. It applies the 4B3T
block code together with adaptive echo cancelling and equalization. Transmission
performance shall be such, that it meets all ETSI and FTZ test loops with margin.
The U-interface is designed for data transmission on twisted pair wires in local telephone
loops, with basic access to ISDN and a user bit rate of 144 kbit/s.
The following information is transmitted over the twisted pair:
• Bidirectional:
– B1, B2, D data channels
– 120 kHz Symbol clock
– 1 kHz Frame
– Activation
– 1 kbit/s Transparent Channel (M symbol), (not implemented)
• From LT to NT side:
– Power feeding
– Deactivation
– Remote control of test loops (M symbol)
• From NT to LT side:
– Indication of monitored code violations (M symbol)
Performance Requirements according to FTZ 1 TR 220 (August 1991):
On the U-interface, the following transmission ranges are achieved without additional
signal regeneration on the loop (bit error rate ≤ 10-7):
• with noise: ≥ 4.2 km on wires of 0.4 mm diameter and ≥ 8 km on 0.6 mm wires
• without noise: ≥ 5 km on wires of 0.4 mm diameter and ≥ 10 km on 0.6 mm wires
Note: Typical attenuation of FTZ wires of 0.4 mm diameter is about 7dB/km in contrast
to ETSI wires of 0.4 mm with about 8dB/km.
The transmission ranges can be doubled by inserting a repeater for signal regeneration.
Performance requirements according to ETSI TS 102 080 are met, too.
1 ms frames are transmitted via the U-interface, each consisting of:
Data Sheet
58
2001-11-12
PEF 81902
Functional Description
• 108 symbols: 144 bit scrambled and coded B1 + B2 + D data
• 11 symbols: Barker code for both symbol and frame synchronization (not scrambled)
• 1 symbol: Ternary maintenance symbol (not scrambled)
The 108 user data symbols are split into four equally structured groups. Each group
(27 ternary symbols, resp. 36 bits) contains the user data of two IOM®-2 frames in the
same order (8B + 8B + 2D + 8B + 8B + 2D).
Different syncwords are used for each direction:
• Downstream from LT to NT
• Upstream from NT to LT
+++–––+––+–
–+––+–––+++
On the NT side, the transmitted Barker code begins 60 symbols after the received Barker
code and vice versa.
Table 13
1
Frame Structure A for Downstream Transmission LT to NT
2
D1
13
D1/2
25
D2
37
D3
49
D4
61
D5
73
D6
85
M
97
D7/8
3
D1
14
D1/2
26
D2
38
D3
50
D4
62
D5
74
D6
86
D7
98
4
D1
15
D1/2
27
D2
39
D3
51
D4
63
D5
75
D6
87
D7
99
5
D1
16
D2
28
D3
40
D3/4
52
D4
64
D5
76
D6
88
6
D1
17
D2
29
D3
41
D3/4
53
D4
65
D5
77
D6
89
7
D1
18
D1
19
D2
30
D2
31
D3
42
D3
43
D3/4
54
D4
55
D4
66
D5
67
D5
78
D5/6
79
D6
90
8
D6
91
9
D1
20
D2
32
D3
44
D4
56
D5
68
D5/6
80
D6
92
10
D1
21
D2
33
D3
45
D4
57
D5
69
D5/6
81
D6
93
D1
22
D2
34
D3
46
D4
58
D5
70
D6
82
D7
94
11
12
D1
23
D1
24
D2
35
D2
36
D3
47
D3
48
D4
59
D4
60
D5
71
D5
72
D6
83
D6
84
D7
95
D7
96
D7
D7
D7
D7
D7
D7
D7
D7/8
D7/8
100
101
102
103
104
105
106
107
108
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
109
110
111
112
113
114
115
116
117
118
119
120
D8
+
+
+
–
–
–
+
–
–
+
–
Data Sheet
59
2001-11-12
PEF 81902
Functional Description
D1 ... D8
M
+, –
Data Sheet
Ternary 2B + D data of IOM®-2 frames 1 ... 8
Maintenance symbol
Syncword
60
2001-11-12
PEF 81902
Functional Description
•
Table 14
1
Frame Structure B for Upstream Transmission NT to LT
2
U1
13
U1
14
U1/2
25
U1/2
26
M
37
U2
38
U3
U3
49
3
50
U4
61
–
62
U4
U4
73
74
U5
85
U5
86
U6
97
U6
98
4
U1
15
U1/2
27
U2
39
U3
51
5
U1
16
U2
28
U2
40
U3
52
+
63
U4
75
U5
87
U6
99
–
64
U4
76
U5
88
6
U1
17
U2
29
U3
41
U3/4
53
–
65
U4
77
U5
89
7
U1
18
U1
19
U2
30
U2
31
U3
42
U3
43
U3/4
54
U3/4
55
+
66
–
67
U4
78
U5
79
U5
90
8
U5/6
91
9
U1
20
U2
32
U3
44
U4
56
–
68
U5
80
U5/6
92
10
U1
21
U2
33
U3
45
U4
57
–
69
U5
81
U5/6
93
U1
22
U2
34
U3
46
U4
58
+
70
U5
82
U6
94
11
12
U1
23
U1
24
U2
35
U2
36
U3
47
U3
48
U4
59
U4
60
+
+
71
72
U5
83
U5
84
U6
95
U6
96
U6
U6
U6
U6
U6
U6
U7
U7
U7
100
101
102
103
104
105
106
107
108
U7
U7
U7
U7
U7
U7
U7
U7
U7
109
110
111
112
113
114
115
116
117
118
119
120
U8
U8
U8
U8
U8
U8
U8
U8
U8
U8
U8
U8
U1 ... U8
Ternary 2B + D data of IOM®-2 frames 1... 8
M
Maintenance symbol
+, -
Syncword
Data Sheet
61
U7/8
U7/8
U7/8
2001-11-12
PEF 81902
Functional Description
2.4.2
Maintenance Channel
The 4B3T frame structure provides a 1 kbit/s M(aintenance)-channel for the transfer of
remote loopback commands and error indications.
Loopback Commands
The LT station uses the M-channel to request remote loopbacks. Loopback commands
are coded with a series of ’0’ and ’+’ symbols.
• A continuous series of ’+’ requests for loopback 2 activation in the NT
• A continuous series of ’0’ requests for deactivation of any loopback
The NT station reacts as soon as the pattern has been detected in 8 consecutive
symbols.
Error Indications
The NT U-transceiver reports line code violations via the M-channel to the exchange by
setting one M-Bit to ’+’ polarity.
Transparent Messages
The exchange of Transparent Messages via the Transparent Channel is not supported
by the T-SMINTâIX.
2.4.3
Coding from Binary to Ternary Data
Each 4 bit block of binary data is coded into 3 ternary symbols of MMS 43 block code
according to Table 15.
The number of the next column to be used, is given at the right hand side of each block.
The left hand signal elements in the table (both ternary and binary) are transmitted first.
•
Table 15
MMS 43 Coding Table
t→
S1
S2
S3
S4
t→
t→
t→
t→
0
0
0
1
0
–
+
1
0
–
+
2
0
–
+
3
0
–
+
4
0
1
1
1
–
0
+
1
–
0
+
2
–
0
+
3
–
0
+
4
0
1
0
0
–
+
0
1
–
+
0
2
–
+
0
3
–
+
0
4
0
0
1
0
+
–
0
1
+
–
0
2
+
–
0
3
+
–
0
4
1
0
1
1
+
0
–
1
+
0
–
2
+
0
–
3
+
0
–
4
1
1
1
0
0
+
–
1
0
+
–
2
0
+
–
3
0
+
–
4
1
0
0
1
+
–
+
2
+
–
+
3
+
–
+
4
–
–
–
1
Data Sheet
62
2001-11-12
PEF 81902
Functional Description
Table 15
MMS 43 Coding Table (cont’d)
S1
S2
S3
S4
0
0
1
1
0
0
+
2
0
0
+
3
0
0
+
4
–
–
0
2
1
1
0
1
0
+
0
2
0
+
0
3
0
+
0
4
–
0
–
2
1
0
0
0
+
0
0
2
+
0
0
3
+
0
0
4
0
–
–
2
0
1
1
0
–
+
+
2
–
+
+
3
–
–
+
2
–
–
+
3
1
0
1
0
+
+
–
2
+
+
–
3
+
–
–
2
+
–
–
3
1
1
1
1
+
+
0
3
0
0
–
1
0
0
–
2
0
0
–
3
0
0
0
0
+
0
+
3
0
–
0
1
0
–
0
2
0
–
0
3
0
1
0
1
0
+
+
3
–
0
0
1
–
0
0
2
–
0
0
3
1
1
0
0
+
+
+
4
–
+
–
1
–
+
–
2
–
+
–
3
2.4.4
Decoding from Ternary to Binary Data
Decoding is done in the reverse manner of coding. The received blocks of 3 ternary
symbols are converted into blocks of 4 bits. The decoding algorithm is given in Table 16.
As in the encoding table, the left hand symbol of each block (both binary and ternary) is
the first bit and the right hand is the last. If a ternary block "0 0 0" is received, it is decoded
to binary "0 0 0 0". This pattern usually occurs only during deactivation.
•
Table 16
4B3T Decoding Table
Ternary Block
0 0 0,
0
0
0
0
0 – +
0
0
0
1
+ – 0
0
0
1
0
0
0
1
1
0
1
0
0
0 0 +,
+ 0 +,
Binary Block
0 – 0
– – 0
– + 0
0 + +,
– 0 0
0
1
0
1
– + +,
– – +
0
1
1
0
0
1
1
1
– 0 +
+ 0 0,
0 – –
1
0
0
0
+ – +,
– – –
1
0
0
1
+ + –,
+ – –
1
0
1
0
1
0
1
1
1
1
0
0
+ 0 –
+ + +,
Data Sheet
– + –
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PEF 81902
Functional Description
Table 16
4B3T Decoding Table (cont’d)
0 + 0,
– 0 –
0 + –
+ + 0,
2.4.4.1
0 0 –
1
1
0
1
1
1
1
0
1
1
1
1
Monitoring of Code Violations
The running digital sum monitor (RDSM) computes the running digital sum from the
received ternary symbols by adding the polarity of the received user data (+ 1, 0, –1). At
the end of each block, the running digital sum is supposed to reflect the number of the
next column in Table 15.
A code violation has occurred if the running digital sum is less than one or more than four
at the end of a ternary block, or if the ternary block 0 0 0 (three user symbols with zero
polarity) is found in the received data.
If at the end of a ternary block no error was found, the running digital sum retains its
current value. If the counter value is greater than 4, it is set to 4 at the beginning of the
next ternary block, if its value is 0 or less, it is set to one. So after a code violation has
been detected, the RDSM synchronizes itself within a period depending on the received
data pattern. Note there are some transmission errors which do not cause a code
violation.
2.4.4.2
Block Error Counter (RDS Error Counter)
The T-SMINTâIX provides a block error counter. This feature allows monitoring the
transmission quality on the U-interface.
On the NT side a block error is given, if a U-frame with at least one code violation has
been detected (near-end block error). In the following frame the NT transmits a positive
M-symbol upstream.
On the LT side a block error is given, if a U-frame with at least one code violation has
been detected (near-end block error) or a positive M-symbol has been received from the
NT (far-end block error).
The current status of the block error counter can be retrieved by the system interface.
When the block error counter is read (register RDS), it is automatically reset. The counter
is enabled in all states listed in Table 17 and reset in all other states. The counter is
saturated at its maximum value (255).
Table 17
Active States
SBC Sychronizing
Wait for INFO U4H
Transparent
Data Sheet
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PEF 81902
Functional Description
Note that every frame with a detected code violation causes about 10 to 20 binary bit
errors on average. So a bit error rate of 10–7 in both directions is equivalent to 2 detected
frame errors within 1000 s in the LT (1 frame error detected in the NT and transmitted
via M-symbol).
2.4.5
Scrambler / Descrambler
Scrambler
The binary transmit data from the IOM®-2 interface is scrambled with a polynomial of
23 bits, before it is sent to the 4B3T coder. The scrambler polynomial is::
z
– 23
+z
– 18
+1
Descrambler
The received data (after decoding from ternary to binary) is multiplied with a polynomial
of 23 bits in order to recover the original data before it is forwarded to the IOM®-2
interface.The descrambler is self synchronized after 23 symbols. The descrambler
polynomial is::
z
– 23
+z
–5
+1
The scrambling / descrambling process is controlled fully by the T-SMINTâIX. Hence, no
influence can be taken by the user.
2.4.6
Command/Indication Codes
Both commands and indications depend on the data direction. Table 18 presents all
defined C/I codes. A new command or indication will be recognized as valid after it has
been detected in two successive IOM®-2 frames (double last-look criterion).
Note: Unconditional C/I-commands must be applied for at least 4 IOM®-2 frames for
reliable recognition by the U-transceiver.
Indications are strictly state orientated. Refer to the state diagrams in the following
sections for commands and indications applicable in various states.
Table 18
C/I Codes
Code
IN
OUT
0000
TIM
DR
0001
–
–
0010
–
–
Data Sheet
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Functional Description
0011
LTD
–
0100
–
RSY
0101
SSP
–
0110
DT
–
0111
–
–
1000
AR
AR
1001
reserved1)
–
1010
–
ARL
1011
–
–
1100
AI
AI
1101
RES
–
1110
–
AIL
1111
DI
DC
1)
C/I code ‘1010‘ must not be input to the U-transceiver.
•
AI
Activation Indication
DI
Deactivation Indication.
AIL
Activation Indication Loop 2
DR
Deactivation Request
AR
Activation Request
LTD
LT Disable
ARL
Activation Request Local Loop
RES
Reset
DT
Data Through Mode
RSY
Resynchronization Indication
DC
Deactivation Confirmation
SSP
Send-Single-Pulses
TIM
Timing Request
2.4.7
State Machine for Activation and Deactivation
2.4.7.1
State Machine Notation
The following state diagram describes all the actions/reactions resulting from any
command or detected signal and resulting from the various operating modes.
The states with its inputs and outputs are interpreted as shown below:
Data Sheet
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Functional Description
Transmitted U-Signal
State Name
C/I Channel Indication
(DOUT)
OUT
Figure 31
State Diagram Example
Each state has one or more transitions to other states. These transitions depend on
certain conditions which are noted next to the transition lines. These conditions are the
only possibility to leave a state. If more conditions have to be fulfilled together, they are
put into parentheses with an AND operator (&). If more than one condition leads to the
same transition, they are put into parentheses with an OR operator (|). The meaning of
a condition may be inverted by the NOT operator (/). Only the described states and
transitions exist.
At some transitions, an internal timer is started. The start of a timer is indicated by TxS
(’x’ is the timer number). Transitions that are caused if a timer has expired are labelled
by TxE.
Some conditions lead to the same target state. To reduce the number of lines and the
complexity of the figures, a state named “ANY STATE” acts on behalf of all state.
The state machines are designed to cope with all ISDN devices with IOM®-2 standard
interfaces. Undefined situations are excluded. In any case, the involved devices will
enter defined conditions as soon as the line is deactivated.
2.4.7.2
Awake Protocol
For the awake process two signals are defined’ U1W’ and ’U2W’. Depending on the call
direction (up-, downstream) U1W and U2W are interpreted as awake or acknowledge
signals (see figures below).
Data Sheet
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Functional Description
•
12 ms
7 ms
LT
INFO U2W
INFO U2 (A)
2.133 ms
13 ms
NT
INFO U1W
INFO U1A
2.133 ms
ITD06385.vsd
Figure 32
Awake Procedure initiated by the LT
•
6 ms
7 ms
LT
INFO U2W
INFO U2 (A)
2.133 ms
13 ms
NT
INFO U1W
INFO U1A
2.133 ms
Figure 33
ITD06386.vsd
Awake Procedure initiated by the NT
Acting as Calling Station
After sending the awake signal, the awaking U-transceiver waits for the acknowledge.
After 12 ms, the awake signal is repeated, if no acknowledge has been recognized.
If an acknowledge signal has been recognized, the U-transceiver waits for its possible
repetition (in case of previous coincidence of two awake signals). If no repetition was
detected, the U-transceiver starts transmitting U2 with a delay of 7 ms.
If such a repetition is detected, the U-transceiver interprets it as an awake signal and
behaves like a device awoken by the far end.
Data Sheet
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PEF 81902
Functional Description
Acknowledging a Wake-Up Call
If a deactivated device detects an awake signal on U, an acknowledge signal is sent out.
After that, the U-transceiver waits for a possible repetition of the awake signal (in case
the acknowledge hasn’t been recognized).
If no repetition is found, the awoken U-transceiver starts sending U2 after 7 ms from
detecting the awake signal. If a repeated awake signal is found, the procedure in the
awoken U-transceiver starts again.
Data Sheet
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Functional Description
2.4.7.3
NT State Machine (IEC-T / NTC-T Compatible)
•
AWR
U0
IOM Awaked
TIM
AR
DI
U0
Deactivated
AWR
DC U0, DA
DC
AR
T6S
T05E
U1W
Start Awaking Uk0
T6S
T05S
T05S
RSY
U0
Deactivating
DC
AWR
AWT
T6S
T6E
U0
Awake Signal Sent
RSY
AWR
T13S
T13E
U0
Ack. Sent / Received
RSY
AWT
AWR
T13S
U1W
Sending Awake-Ack.
T13S
RSY
(DI & T05E)
T12S
U1A
Synchronizing
(U0 & T12E)
T05S
U0
Pend. Deactivation
RSY
DI
DR
DR
U2
T05S
SSP or LTD
DT
U1
SBC Synchronizing
AR / ARL
U0
LOF
ANY STATE
RES
AI
U3
Wait for Info U4H
SP / U0
Test
DI
U0
Reset
DR
U0
LOF
AR / ARL
U4H
U0
U5
Transparent
AI / AIL
Figure 34
U0
LOF
U0
Loss of Framing
RSY
NT_SM_4B3T_cust.emf
NT State Machine (IEC-T/NTC-T Compatible)
Note: The test modes ‘Data Through‘ (DT) and ‘Send Single Pulses‘ (SSP) are invoked
via C/I codes ’DT’ and ’SSP’ according to Table 18. Setting SRES.RES_U to ‘1‘
forces the U-transceiver into test mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver
is hardware reset.
Data Sheet
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Functional Description
•
Table 19
Differences to the former NT-SM of the IEC-T/NTC-T
No. State/ Signal
Change
Comment
1.
State ’Deact.
split into 3 states
Request Rec.’ - ’Pend. Deactivation 1’
- ’Reset’ State
- ’Test’ State
simplifies SM implementation
2.
State ’Loss of
Framing’
new inserted,
results in different behavior
in state ’Transparent’,
no return to normal
transmission possible after
detection of LOF
compliance to ETSI TS 102 080,
corresponds to state NT1.10
3.
C/I-code LTD
new inserted
4.
State
’Power Down’
renamed to state
’Deactivated’
5.
State
’Data
Transmission’
renamed to state
’Transparent’
6.
Timer
variables
introduced
Name Duration
2.4.7.4
for consistency reasons to 2B1Q
see Table 20
Inputs to the U-Transceiver
C/I-Commands
AI
Activation Indication
The downstream device issues this indication to announce that layer 1 is
available. The U-transceiver in turn informs the LT side by transmitting U3.
AR
Activation Request
The U-transceiver is requested to start the activation process (if not already
done) by sending the wake-up signal U1W.
DI
Deactivation Indication
This indication is used during a deactivation procedure to inform the Utransceiver that it may enter the ’Deactivated’ (power-down) state.
DT
Data Through Test Mode
This unconditional command is used for test purposes only and forces the Utransceiver into state ’Transparent’.
Data Sheet
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Functional Description
RES
Reset
Unconditional command which resets the U-transceiver.
SSP
Send Single Pulses
Unconditional command which requests the transmission of single pulses on
the U-interface.
TIM
Timing
The U-transceiver is requested to enter state ’IOM Awaked’.
U-Interface Events
U0
U0 detected
U0 is recognized after 120 symbols (1ms) with zero level in a row. Detection
may last up to 2 ms.
U2
U2 detected
The U-transceiver detects U2 if continuous binary 0‘s are found after
descrambling and LOF = 0 for at least 8 subsequent U-frames. U2 is detected
after 8 to 9 ms.
U4H
U4H detected
U4H is recognized, if the U-transceiver detects 16 subsequent binary 1’s after
descrambling.
AWR
Awake signal (U2W) detected
AWT
Awake signal (U1W) has been sent out
LOF
Loss of Framing on U-interface
TxE
Timer ended, the started timer has expired
Timers
The start of timers is indicated by TxS, the expiry by TxE. The following table shows
which timers are used.
•
Table 20
Timers
Timer
Duration (ms)
Function
State
T05
0.5
C/I code recognition
Pend. Deactivation,
Deactivating
T6
6
Supervises U1W repetition
Start Awaking Uk0
Data Sheet
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Functional Description
Table 20
Timers (cont’d)
Timer
Duration (ms)
Function
State
T12
12
Prevents the U-transceiver in
state Synchronizing from
immediate transition to state
’Pend. Deactivation’ if U0 is
detected
Synchronizing
T13
13
Supervises U2W repetition
Ack. sent / received
Sending awake-ack.
2.4.7.5
Outputs of the U-Transceiver
Below the signals and indications are summarized that are issued on IOM®-2 (C/I
indications) and on the U-interface (predefined U-signals).
C/I Indications
AI
Activation Indication
The U-transceiver has established transparency of transmission. The
downstream device is requested to establish layer-1 functionality.
AIL
Activation Indication Loop-back
The U-transceiver has established transparency of transmission. The
downstream device is requested to establish a loopback #2.
AR
Activation Request
The downstream device is requested to start the activation procedure.
ARL
Activation Request Loop-back
The U-transceiver has detected a loop-back 2 command in the M-channel and
has established transparency of transmission in the direction IOM® to Uinterface. The downstream device is requested to start the activation
procedure and to establish a loopback #2.
DC
Deactivation Confirmation
Idle code on the IOM®-2 interface.
DR
Deactivation Request
The U-transceiver has detected a deactivation request command from the LTside for a complete deactivation. The downstream device is requested to start
the deactivation procedure.
LTD
LT Disable
This unconditional command forces the U-transceiver to state ’Test’, where it
transmits U0. No further action is initiated.
Data Sheet
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Functional Description
RSY
Resynchronizing Indication
RSY informs the downstream device that the U-transceiver is not
synchronous.
Signals on U-Interface
The signals U0, U1W, U1A, U1, U3, U5 and SP are transmitted on the U-interface.They
are defined in Table 29.
Signals on IOM®-2
The Data (B+B+D) is set to all ’1’s in all states besides the states listed in Table 17.
Dependence of Outputs
The M-symbol output in states with valid M-symbol output its value is set according to
Table 21
•:
Table 21
M Symbol Output
RDS Error
not detected
detected
M Symbol Output
’0’
’+’
•
Table 22
Signal Output on Uk0 in State Test
Input
C/I-Code SSP applied
all other except C/I-Code ’DI’
Signal Output on
Uk0
SP
U0
•
Table 23
C/I-Code Output
Loopback
Command
SBC
Synchronizing
Wait for Info U4H
Transparent
not received
AR
AR
AI
received
ARL
ARL
AIL
2.4.7.6
NT-States
In this section each state is described with its function.
Data Sheet
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Functional Description
Acknowledge Sent / Receive
After having sent the awake signal, the U-transceiver has received the acknowledge
wake tone. If being awoken the U-transceiver has sent the acknowledge. In both cases
the U-transceiver waits for possible repetition or time-out.
Awake Signal Sent
The NT has sent out the awake signal U1W and waits now for a response. If the LT does
not react in time timer T6 expires and the NT repeats its wake-up call.
Deactivated
Only in “Deactivated” state the device may enter the power-down mode.
Deactivating
State Deactivating assures that the C/I-channel code DC is issued four times before
entering the ’Deactivated’ state.
IOM® Awaked
The U-transceiver is deactivated, but may not enter the power-down mode.
Loss of Framing
This state is entered on loss of framing (LOF). No signal is transmitted on the U-interface.
A receiver-reset is performed by.
Note that there is no return to the ’Transparent’ state that has been possible before in
the former IEC-T based state machine.
Pending Deactivation
The U-transceiver has received U0. The U-transceiver remains at least 0.5ms in this
state before it accepts DI.
SBC Synchronizing
The NT is now synchronized and indicates this by AR/ARL towards the downstream
device. The NT waits for the acknowledge ’AI’ from the downstream device.
Sending Awake-Ack.
On the receipt of the awake signal U2W the U-transceiver responds with the
transmission of U1W.
Data Sheet
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Functional Description
Start Awaking Uk0
On the receipt of AR in the C/I-channel the U-transceiver sends the awake signal U1W
to start an activation.
Synchronizing
After the successful awake procedure the U-transceiver trains its receiver coefficients
until it is able to detect the signals U2.
Reset
In state ’Reset’ a software-reset is performed.
Test
State “Test” is entered when the unconditional commands C/I=SSP is applied. The test
signal SSP is issued as long as pin SSP is active or C/I=SSP is applied.
Transparent
The transmission line is fully activated. User data is transparently exchanged by U4/U5.
Transparent state is entered in the case of a loopback 2. The downstream device is
informed by C/I code AI that the transparent state has been reached
Note that in contrast to the former IEC-T state machine there is no resynchronization
mechanism. Once loss of framing (LOF) has been detected a deactivation is initiated.
Wait for Info U4H
The NT is synchronized and waits now for the permission (U4H) to go to the
’Transparent’ state.
2.4.8
U-Transceiver Interrupt Structure
The U-Interrupt Status register (ISTAU) contains the interrupt sources of the UTransceiver (Figure 35). Each source can be masked by setting the corresponding bit
of the U-Interrupt Mask register (MASKU) to ’1’. Such masked interrupt status bits are
not indicated when ISTAU is read and do not generate an interrupt request.
The ISTAU register is cleared on read access. The interrupt sources of the ISTAU
register (UCIR, RDS, 1ms) need not be evaluated.
When at time t1 an interrupt source generates an interrupt, all further interrupts are
collected. Reading the ISTAU register clears all interrupts set before t1, even if masked.
All interrupts, which are flagged after t1 remain active. After the ISTAU read access, the
next unmasked interrupt will generate the next interrupt at time t2. After t2 it is possible
to reprogram the MASKU register, so that all interrupts, which arrived between t1 and t2
are accessible.
Data Sheet
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Functional Description
•I
UCIR
7
0
0
0
0
C/I
C/I
C/I
0
C/I
ISTAU
7
1
CI
CI
RDS
0
MASKU
0
RDS
0
1
0
1
0
1
0
1
1ms
1ms
ISTA
MASK
U
S
...
...
...
...
...
...
intstruct_4b3t.emf
INT
Figure 35
Data Sheet
Interrupt Structure U-Transceiver
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PEF 81902
Functional Description
2.5
S-Transceiver
The S-Transceiver offers the NT and LT-S mode state machines described in the User’s
Manual V3.4 [8].
The S-transceiver lies in IOMâ-2 channel 1 (default) and is configured and controlled
via the registers described in Chapter 4.5. The state machine is set to NT mode (default)
but can be set to LT-S mode via register programming.
The TE mode (S-transceiver TE mode, U-transceiver disabled) is not supported.
2.5.1
Line Coding, Frame Structure
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
•
0 1 1
code violation
Figure 36
S/T -Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 36).
In the direction TE → NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT → TE and TE → NT) with all framing
and maintenance bits.
Data Sheet
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Functional Description
•
Figure 37
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) → identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) → number of binary ZEROs sent
after the last L. bit was odd
– D
D-Channel Data Bit
Signaling data specified by user
– E
D-Channel Echo Bit
E = D → received E-bit is equal to transmitted
D-bit
– FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
– N
N = FA
– B1
B1-Channel Data Bit
User data
– B2
B2-Channel Data Bit
User data
– A
Activation Bit
A = (0b) → INFO 2 transmitted
A = (1b) → INFO 4 transmitted
– S
S-Channel Data Bit
S1 channel data (see note below)
– M
Multiframing Bit
M = (1b) → Start of new multi-frame
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
Data Sheet
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Functional Description
2.5.2
S/Q Channels, Multiframing
According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in
the TE-to-NT direction through the use of an extra channel between the TE and NT (Qchannel). The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S- and Q-channels are accessed via µC by reading/writing the SQR or SQX bits in
the S/Q channel registers (SQRR, SQXR).
Table 24 shows the S and Q bit positions within the multi-frame.
Table 24
S/Q-Bit Position Identification and Multi-Frame Structure
Frame Number
NT-to-TE
NT-to-TE
FA Bit Position M Bit
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
1
2
3
4
5
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
S11
S21
S31
S41
S51
Q1
ZERO
ZERO
ZERO
ZERO
6
7
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S12
S22
S32
S42
S52
Q2
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S13
S23
S33
S43
S53
Q3
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S14
S24
S34
S44
S54
Q4
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
S21
Q1
ZERO
The S-transceiver starts multiframing if SQXR1.MFEN is set.
After multi-frame synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE → NT) FA bit position by the TE in each 5th S/T frame, the
Data Sheet
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Functional Description
S data will be inserted at the downstream (NT → TE) S bit position in each 5th S/T frame
(see Table 24). Access to S2-S5-channel is not supported.
Interrupt Handling for Multi-Framing
To trigger the microcontroller for a multi-frame access an interrupt can be generated
once per multi-frame (SQW) or if the received Q-channel have changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
The start of a multiframe can not be synchronized to an external signal.
2.5.3
Data Transfer between IOMâ-2 and S0
In the state G3 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register S_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOMâ-2 interface and vice versa. In all other states ’1’s
are transmitted to the IOMâ-2 interface.
Note: In intelligent NT or intelligent LT-S mode the D-channel access can be blocked by
the IOMâ-2 D-channel handler.
2.5.4
Loopback 2
C/I commands ARL and AIL close the analog loop as close to the S-interface as possible.
ETSI refers to this loop under ’loopback 2’. ETSI requires, that B1, B2 and D channels
have the same propagation delay when being looped back.
The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The
loop is transparent.
Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped
back in the B and D-channels (DU) for four frames.
2.5.5
Control of S-Transceiver / State Machine
The S-transceiver activation/ deactivation can be controlled by an internal statemachine
via the IOMâ-2 C/I-channel or by software via the µC interface directly. In the default
state the internal layer-1 statemachine of the S-transceiver is used. By setting the L1SW
bit in the S_CONF0 register the internal statemachine can be disabled and the layer-1
transmit commands, which are normally generated by the internal statemachine can be
written directly into the S_CMD register or the received status read out from the S_STA
register, respectively. The S-transceiver layer-1 control flow is shown in Figure 38.
Data Sheet
81
2001-11-12
PEF 81902
Functional Description
•
Disable internal
Statemachine
(S_CONF.L1SW)
C/I
Command
IOM-2
C/I
Indication
Layer-1
State
Machine
Transmit
Command Register
INFO
Transmitter
for Transmitter
(S_CMD)
Receive
Status Register
INFO
Receiver
of Receiver
(S_STA)
Layer-1 Control
µ C-Interface
macro_14
Figure 38
S-Transceiver Control
The state diagram notation is given in Figure 39.
The information contained in the state diagrams are:
–
–
–
–
–
–
state name
Signal received from the line interface (INFO)
Signal transmitted to the line interface (INFO)
C/I code received (commands)
C/I code transmitted (indications)
transition criteria
The transition criteria are grouped into:
– C/I commands
– Signals received from the line interface (INFOs)
– Reset
Data Sheet
82
2001-11-12
PEF 81902
Functional Description
•
OUT
IOM-2 Interface
C/I code
IN
Unconditional
Transition
Ind. Cmd.
S ta te
S/T Interface
INFO
ix
ir
macro_17.vsd
Figure 39
State Diagram Notation
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “∗” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
Test Signals
• 2 kHz Single Pulses (TM1)
One pulse with a width of one bit period per frame with alternating polarity.
• 96 kHz Continuous Pulses (TM2)
Continuous pulses with a pulse width of one bit period.
Note: The test signals TM1 and TM2 are invoked via C/I codes ‘TM1‘ and ‘TM2‘
according to Chapter 2.5.5.1.
External Layer-1 Statemachine
Instead of using the integrated layer-1 statemachine it is also possible to implement the
layer-1 statemachine completely in software.
The internal layer-1 statemachine can be disabled by setting the L1SW bit in the
S_CONF0 register to ’1’.
The transmitter is completely under control of the microcontroller via register S_CMD.
The status of the receiver is stored in register S_STA and has to be evaluated by the
microcontroller. This register is updated continuously. If not masked a RIC interrupt is
generated by any change of the register contents. The interrupt is cleared after a read
access to this register.
Reset States
After an active signal on the reset pin RST the S-transceiver state machine is in the reset
state.
Data Sheet
83
2001-11-12
PEF 81902
Functional Description
C/I Codes in Reset State
In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a
hardware reset (RST) or with the C/I code RES.
C/I Codes in Deactivated State
If the S-transceiver is in state ‘Deactivated‘ and receives i0, the C/I code 0000 (TIM) is
issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued.
2.5.5.1
C/I Codes
The table below presents all defined C/I0 codes. A command needs to be applied
continuously until the desired action has been initiated. Indications are strictly state
orientated. Refer to the state diagrams in the following sections for commands and
indications applicable in various states.
•
LT-S
Code
NT
Cmd
Ind
Cmd
Ind
0
0
0
0
DR
TIM
DR
TIM
0
0
0
1
RES
–
RES
–
0
0
1
0
TM1
–
TM1
–
0
0
1
1
TM2
–
TM2
–
0
1
0
0
–
RSY
RSY
RSY
0
1
0
1
–
–
–
–
0
1
1
0
–
–
–
–
0
1
1
1
–
–
–
–
1
0
0
0
AR
AR
AR
AR
1
0
0
1
–
–
–
–
1
0
1
0
ARL
–
ARL
–
1
0
1
1
–
CVR
–
CVR
1
1
0
0
–
AI
AI
AI
1
1
0
1
–
–
–
–
1
1
1
0
–
–
AIL
–
1
1
1
1
DC
DI
DC
DI
Data Sheet
84
2001-11-12
PEF 81902
Functional Description
Receive Infos on S/T
I0
INFO 0 detected
I0
Level detected (signal different to I0)
I3
INFO 3 detected
I3
Any INFO other than INFO 3
Transmit Infos on S/T
I0
INFO 0
I2
INFO 2
I4
INFO 4
It
Send Single Pulses (TM1).
Send Continuous Pulses (TM2).
Data Sheet
85
2001-11-12
PEF 81902
Functional Description
2.5.5.2
State Machine NT Mode
•
RST
TIM RES
TIM
DR
Reset
i0
RES
DR
G4 Pend. Deact.
ARD1)
*
DR
i0
DI
Any
State
ARD1)
Test Mode i
i0
it
(i0*16ms)+32ms
DC
TM1
TIM TM2
DC
DR
*
TM1
TM2
Any
State
G4 Wait for DR
i0
*
DC
DI
TIM
DR
DC
G1 Deactivated
ARD1)
i0
i0
(i0*8ms)
AR
DC
G1 i0 Detected
i0
DR
*
ARD1)
AR ARD
G2 Pend. Act
i2
DR
i3
i3
AID
RSY ARD
G2 Lost
Framing S/T
i2
i3
i3*ARD
AI
i3*ARD1)
i3*AID2)
ARD
G2 Wait for AID
RSY
i2
DR
i3
AID2)
RSY
DR
RSY RSY
G3 Lost
Framing U
i2
*
ARD1)
AID2)
i3*AID2)
ARD1)
AI
AID
G3 Activated
RSY
i4
i3
DR
1):
ARD = AR or ARL
: AID =AI or AIL
2)
Figure 40
statem_nt_s.vsd
State Machine NT Mode
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself, i.e. C/I-code ’TMi’ must not be followed by C/I-code ’TMj’ directly.
Data Sheet
86
2001-11-12
PEF 81902
Functional Description
G1 Deactivated
The S-transceiver is not transmitting. There is no signal detected on the S/T-interface,
and no activation command is received in the C/I channel. Activation is possible from the
S/T interface and from the IOMâ-2 interface.
G1 I0 Detected
An INFO 0 is detected on the S/T-interface, translated to an “Activation Request”
indication in the C/I channel. The S-transceiver is waiting for an AR command, which
normally indicates that the transmission line upstream is synchronized.
G2 Pending Activation
As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not
yet received. In case of ARL command, loop 2 is closed.
G2 wait for AID
INFO 3 was received, INFO 2 continues to be transmitted while the S-transceiver waits
for a “switch-through” command AID from the device upstream.
G3 Activated
INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the
B and D-channels are transparent. On the command AIL, loop 2 is closed.
G2 Lost Framing S/T
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G3 Lost Framing U
On receiving an RSY command which usually indicates that synchronization has been
lost on the transmission line, the S-transceiver transmits INFO 2.
G4 Pending Deactivation
This state is triggered by a deactivation request DR, and is an unstable state. Indication
DI (state “G4 wait for DR”) is issued by the transceiver when:
either INFO0 is received for a duration of 16 ms
or an internal timer of 32 ms expires.
Data Sheet
87
2001-11-12
PEF 81902
Functional Description
G4 wait for DR
Final state after a deactivation request. The S-transceiver remains in this state until DC
is issued.
Unconditional States
Test Mode TM1
Send Single Pulses
Test Mode TM2
Send Continuous Pulses
C/I Commands
•
Command
Abbr.
Code
Remark
Deactivation Request
DR
0000
Deactivation Request. Initiates a complete
deactivation by transmitting INFO 0.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
TM1
0010
Send Single Pulses.
Send Continuous
Pulses
TM2
0011
Send Continuous Pulses.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
Activation Request. This command is used to
start an activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
Activation Indication
AI
1100
Activation Indication. Synchronous receiver,
i.e. activation completed.
Data Sheet
88
2001-11-12
PEF 81902
Functional Description
Command
Abbr.
Code
Remark
Activation Indication
Loop
AIL
1110
Activation Indication Loop
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which
it can be activated from a terminal (detection
of INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Interim indication during deactivation
procedure.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous.
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code Ciolation
CVR
1011
Illegal code violation received. This function
has to be enabled in S_CONF0.EN_ICV.
Activation Indication
AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
DI
1111
Timer (32 ms) expired or INFO 0 received for
a duration of 16 ms after deactivation
request.
Data Sheet
89
2001-11-12
PEF 81902
Functional Description
2.5.5.3
State Machine LT-S Mode
•
RST
TIM RES
TIM DR
DR
Reset
i0
G4 Pend. Deact.
ARD1)
*
i0
DC
RES
DR
DI
ARD1)
Test Mode i
i0
it
(i0*16ms)+32ms
Any
State
TM1
TIM TM2
DC
*
TM1
TM2
Any
State
DR
G4 Wait for DR
i0
*
DC
DI DC
TIM
DR
G1 Deactivated
i0
i0
(i0*8ms)+ARD1)
DC
AR ARD
G2 Pend. Act.
i2
DR
i3
i3
DC
RSY ARD
G2 Lost
Framing S/T
i2
i3
i3
AI
i3
DC
ARD
G3 Activated
i4
DR
i3
DR
1):
ARD = AR or ARL
Figure 41
statem_lts_s.vsd
State Machine LT-S Mode
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself, i.e. C/I-code ’TMi’ must not be followed by C/I-code ’TMj ’directly.
Data Sheet
90
2001-11-12
PEF 81902
Functional Description
G1 deactivated
The S-transceiver is not transmitting. There is no signal detected on the S/T-interface,
and no activation command is received in the C/I channel. Activation is possible from the
S/T interface and from the IOMâ-2 interface.
G2 pending activation
As a result of an INFO 0 detected on the S/T line or an ARD command, the S-transceiver
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command, loop
2 is closed.
G3 activated
Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains
in this state as long as neither a deactivation nor a test mode is requested, nor the
receiver looses synchronism.
When receiver synchronism is lost, INFO 2 is sent automatically. After reception of
INFO 3, the transmitter keeps on sending INFO 4.
G2 lost framing
This state is reached when the S-transceiver has lost synchronism in the state G3
activated.
G4 pending deactivation
This state is triggered by a deactivation request DR. It is an unstable state: indication DI
(state “G4 wait for DR.”) is issued by the S-transceiver when:
either INFO0 is received for a duration of 16 ms,
or an internal timer of 32 ms expires.
G4 wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test mode - TM1
Single alternating pulses are sent on the S/T-interface.
Data Sheet
91
2001-11-12
PEF 81902
Functional Description
Test mode - TM2
Continuous alternating pulses are sent on the S/T-interface.
•
Command
Abbr.
Code
Remark
Deactivation Request
DR
0000
DR - Deactivation Request. Initiates a
complete deactivation by transmitting INFO
0.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
TM1
0010
Send Single Pulses.
Send Continuous
Pulses
TM2
0011
Send Continuous Pulses.
Activation Request
AR
1000
Activation Request. This command is used to
start an activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which
it can be activated from a terminal (detection
of INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Interim indication during activation
procedure in G1.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code Ciolation
CVR
1011
Illegal code violation received. This function
has to be enabled in S_CONF0.EN_ICV.
Activation Indication
AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
DI
1111
Timer (32 ms) expired or INFO 0 received for
a duration of 16 ms after deactivation request
Data Sheet
92
2001-11-12
PEF 81902
Functional Description
2.5.6
S-Transceiver Enable / Disable
The layer-1 part of the S-transceiver can be enabled/disabled with the two bits
S_CONF0.DIS_TR and S_CONF2.DIS_TX.
If DIS_TX=’1’ the transmit buffers are disabled. The receiver will monitor for incoming
data in this configuration. By default the transmitter is disabled (DIS_TX = ’1’).
If the transceiver is disabled (DIS_TR = ’1’, DIS_TX = don’t care) all layer-1 functions are
disabled including the level detection circuit of the receiver. In this case the power
consumption of the S-transceiver is reduced to a minimum.
Data Sheet
93
2001-11-12
PEF 81902
Functional Description
2.5.7
Interrupt Structure S-Transceiver
•
Level Detect
S_STA
7
RINF
0
FECV
0
FSYN
0
0
LD
SQRR
7
MSYN
MFEN
0
0
SQR1
SQR2
SQR3
0
SQR4
SQXR
7
0
ISTAS
MASKS
0
1
0
0
1
SQX1
0
1
SQX2
0
1
MFEN
0
0
7
SQX3
LD
LD
SQX4
RIC
RIC
0
SQC
SQC
SQW
SQW
7
ISTA
MASK
Reserved
S
0
INT
interr.vsd
Figure 42
Data Sheet
Interrupt Structure S-Transceiver
94
2001-11-12
PEF 81902
Functional Description
2.6
HDLC Controller
The T-SMINTâIX contains a HDLC controller which can be used for the layer-2 functions
of the D- channel protocol (LAPD) or B-channel protocols. By setting the enable HDLC
channel bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register the HDLC controller can
access the D or B-channels or any combination of them e.g. 18 bit IDSL data (2B+D).
The HDLC transceiver in the T-SMINT âIX performs the framing functions used in HDLC
based communication: flag generation/recognition, bit stuffing, CRC check and address
recognition.
The HDLC controller contains a 64 byte FIFO in both receive and transmit direction
which is implemented as a cyclic buffer. The transceivers read and write data
sequentially with constant data rate, whereas the data transfer between FIFO and µC
interface uses a block oriented protocol with variable block sizes.
2.6.1
Message Transfer Modes
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus, the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a LAPD two-byte address is shown below.
•
High Address Byte
SAPI1, 2, SAPG
Low Address Byte
C/R 0
TEI 1, 2, TEIG
EA
For the address recognition the T-SMINTâIX contains four programmable registers for
individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the
“group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which is set to ’1’ according to the LAPD protocol.
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODEH register:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
All frames with valid addresses are accepted and the bytes following the address are
transferred to the µP via RFIFO. Additional information is available in RSTA.
Transparent mode 0 (MDS2-0 = ’110’).
Data Sheet
95
2001-11-12
PEF 81902
Functional Description
Characteristics:
no address recognition
Every received frame is stored in RFIFO (first byte after opening flag to CRC field).
Additional information can be read from RSTA.
Transparent mode 1 (MDS2-0 = ’111’).
Characteristics:
SAPI recognition
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FEH/FCH). In the case of a match, all the following bytes are stored in
RFIFO. Additional information can be read from RSTA.
Transparent mode 2 (MDS2-0 = ’101’).
Characteristics:
TEI recognition
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FFH). In case of a match the rest of the frame is stored in the RFIFO.
Additional information is available in RSTA.
Extended transparent mode (MDS2-0 = ’100’).
Characteristics:
fully transparent
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check and bitstuffing mechanism. This allows user specific protocol variations.
Also refer to Chapter 2.6.5.
2.6.2
Data Reception
2.6.2.1
Structure and Control of the Receive FIFO
The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or
32 bytes which can be selected by setting the corresponding RFBS bits in the EXMR
register. The variable block size allows an optimized HDLC processing concerning frame
length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block orientated with
the microcontroller as master. The control of the data transfer between the CPU and the
T-SMINTâIX is handled via interrupts (T-SMINT âIX → Host) and commands (Host → TSMINTâIX).
There are three different interrupt indications in the ISTAH register concerned with the
reception of data:
Data Sheet
96
2001-11-12
PEF 81902
Functional Description
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
(EXMR.RFBS) can be read from RFIFO. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
– RME (Receive Message End) interrupt, indicating that the reception of one message
has been completed and the message has been stored in the RFIFO.
Either
– a short message has been received
(message length ≤ the defined block size (EXMR.RFBS) or
– the last part of a long message has been received
(message length > the defined block size (EXMR.RFBS)).
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
host fails to respond quick enough to RPF/RME interrupts since previous data was not
read by the host.
There are two control commands that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the T-SMINTâIX that a data
block has been read from the RFIFO and the corresponding FIFO space can be
released for new receive data.
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
receive FIFO of any data (e.g. used before start of reception). It has to be used after
a change of the message transfer mode. RRES does not clear pending interrupt
indications of the receiver, but have to be be cleared by reading these interrupts.
Note: The significant interrupts and commands are underlined as only these are usually
used during a normal reception sequence.
The following description of the receive FIFIO operation is illustrated in Figure 43 for a
RFIFO block size (threshold) of 16 and 32 bytes.
The RFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads
status information (RBCH,RBCL), data from the RFIFO and changes the RFIFO block
size (EXMR.RFBS). A block transfer is completed by the microcontroller via a receive
message complete (CMDR.RMC) command. This causes the space of the transferred
bytes being released for new data and in case the frame was complete (RME) the reset
of the receive byte counter RBC (RBCH,RBCL).1)
The total length of the frame is contained in the RBCH and RBCL registers which contain
a 12 bit number (RBC11...0), so frames up to 4095 byte length can be counted. If a frame
is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least significant
1)
If RMC is omitted, then no new interrupt can be generated.
Data Sheet
97
2001-11-12
PEF 81902
Functional Description
bits of RBCL contain the number of valid bytes in the last data block indicated by RME
(length of last data block ≤ selected block size). Table 25 shows which RBC bits contain
the number of bytes in the last data block or number of complete data blocks,
respectively. If the number of bytes in the last data block is ’0’ the length of the last
received block is equal to the block size.
•
Table 25
Receive Byte Count with RBC11...0 in the RBCH and RBCL registers
EXMR.RFBS
bits
Selected
block size
’00’
Number of
complete
data blocks in
bytes in the last
data block in
32 byte
RBC11...5
RBC4...0
’01’
16 byte
RBC11...4
RBC3...0
’10’
8 byte
RBC11...3
RBC2...0
’11’
4 byte
RBC11...2
RBC1...0
The transfer block size (EXMR.RFBS) is 32 bytes by default. If it is necessary to react to
an incoming frame within the first few bytes the microcontroller can set the RFIFO block
size to a smaller value. Each time a CMDR.RMC or CMDR.RRES command is issued,
the RFIFO access controller sets its block size to the value specified in EXMR.RFBS, so
the microcontroller has to write the new value for RFBS before the RMC command.
When setting an initial value for RFBS before the first HDLC activities, a RRES
command must be issued afterwards.
The RFIFO can hold any number of frames fitting in the 64 bytes independent on RFBS.
At the end of a frame, the RSTA byte is always inserted.
All generated interrupts are inserted together with all additional information into a wait
line to be individually passed to the host. For example if several data blocks have been
received to be read by the host and the host acknowledges the current block, a new RPF
or RME interrupt from the wait line is immediately generated to indicate new data.
Data Sheet
98
2001-11-12
PEF 81902
Functional Description
•
RAM
RAM
EXMR.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo a receive pool full
interrupt ISTAH.RPF
is set.
32
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=11
RFACC
RFIFO ACCESS
CONTROLLER
16
RFBS=01
8
4
4
HDLC
Receiver
RPF
RFIFO
32
8
RBC=4h
HDLC
Receiver
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
a CMDR.RMC command.
Following CMDR.RMC
the 4 bytes of the
last block are
deleted.
EXMR.RFBS=01
RMC
µP
RAM
RAM
HDLC
Receiver
32
RSTA
RSTA
RSTA
16
HDLC
Receiver
RSTA
CONTROLLER
RFBS=01
8
RME
RBC=16h
RMC
RFIFO
RPF
RSTA
RSTA
µP
When the RFACC detects 16 valid bytes,
it sets a RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDR.RMC.
This causes the space occupied by the 16 bytes being
released.
Data Sheet
16
RFBS=01
µP
Figure 43
RFIFO ACCESS
CONTROLLER
8
RBC=14h
FIFO.
RFACC
RFIFO ACCESS
RFIFO
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTA)
is appended.
Meanwhile two
more short frames
have been
received.
32
RFACC
After the RMC acknowledgement the
RFACC detects a RSTA byte, i.e. end of
the frame, therefore it asserts
a RME interupt and increments the
RBC counter by 2.
RFIFO Operation
99
2001-11-12
PEF 81902
Functional Description
Possible Error Conditions during Reception of Frames
If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow
(RDO) byte in the RSTA byte will be set. If a complete frame is lost, i.e. if the FIFO is full
when a new frame is received, the receiver will assert a Receive Frame Overflow (RFO)
interrupt.
The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it
reads the same data again and again. On the other hand, if it does not read or does not
want to read all data, they are deleted anyway after the RMC command.
If the microcontroller tries to read data without a prior RME or RPF interrupt, the content
of the RFIFO would not be corrupted, but new data is only transferred to the host as long
as new valid data is available in the RFIFO, otherwise the last data is read again and
again.
The general procedures for a data reception sequence are outlined in the flow diagram
in Figure 44.
Data Sheet
100
2001-11-12
PEF 81902
Functional Description
•
START
Receive
Message End
RME
?
Y
N
N
Receive
Pool Full
RPF
?
Y
Read Counter
RD_Count := RFBS
or
RD_Count := RBC
Read RBC
RD_Count := RBC
*
Read RD_Count
bytes from RFIFO
1)
Change Block Size
Write EXMR.RFBS
(optional)
Receive Message
Complete
Write RMC
*
1)
RBC = RBCH + RBCL register
RFBS: Refer to EXMR register
In case of RME the last byte in RFIFO contains
the receive status information RSTA
HDLC_Rflow.vsd
Figure 44
Data Reception Procedures
Figure 45 gives an example of an interrupt controlled reception sequence, supposed
that a long frame (68 byte) followed by two short frames (12 byte each) are received. The
FIFO threshold (block size) is set to 32 bytes (EXMR.RFBS = ’00’) in this example:
• After 32 bytes have been received off frame 1 a RPF interrupt is generated to indicate
that a data block can be read from the RFIFO.
Data Sheet
101
2001-11-12
PEF 81902
Functional Description
• The host reads the first data block from RFIFO and acknowledges the reception by
RMC. Meanwhile the second data block is received and stored in RFIFO.
• The second 32 byte block is indicated by RPF which is read and acknowledged by the
host as described before.
• The reception of the remaining 4 bytes are indicated by RME (i.e. the receive status
in RSTA register is always appended to the end of a frame).
• The host gets the number of received bytes (COUNT = 5) from RBCL/RBCH and
reads out the RFIFO and optionally the status register RSTA. The frame is
acknowledged by RMC.
• The second frame is received and indicated by RME interrupt.
• The host gets the number of bytes (COUNT = 13) from RBCL/RBCH and reads out
the RFIFO and status registers. The RFIFO is acknowledged by RMC.
• The third frame is transferred in the same way.
•
IOM Interface
Receive
Frame
68
Bytes
32
32
RD
32 Bytes
RPF
12
12
Bytes Bytes
4
12
12
RD
32 Bytes
RMC RPF
RD
RD
Count 5 Bytes
1)
*
RMC RME
RD
RD
Count 13 Bytes
RMC RME
*
RD
RD
Count 13 Bytes
1)
RMC RME
*
1)
RMC
CPU Interface
*
1)
The last byte contains the receive status information <RSTA>
fifoseq_rec.vsd
Figure 45
2.6.2.2
Reception Sequence Example
Receive Frame Structure
The management of the received HDLC frames as affected by the different operating
modes (see Chapter 2.6.1) is shown in Figure 46.
Data Sheet
102
2001-11-12
PEF 81902
Functional Description
•
FLAG
MDS2
MDS1
MDS0
MODE
0
1
1
Non
Auto/16
1
0
Non
Auto/8
1
1
1
0
1
ADDRESS
CONTROL
2)
TEI1
TEI2
TEIG
*
2)
*
Transparent 0
1
FLAG
STATUS
DATA
4)
1)
RSTA *
1)
RSTA *
1)
RSTA *
1)
RSTA *
1)
RSTA *
RFIFO
*
RFIFO
*
RFIFO
*
RFIFO
*
RFIFO
*
4)
4)
Transparent 1
*
0
CRC
3)
SAP1
SAP2
SAPG
1
I
2)
TEI1
TEI2
*
1
CTRL
SAP1
SAP2
SAPG
*
0
ADDR
4)
2)
Transparent 2
TEI1
TEI2
TEIG
*
Description of Symbols:
CRC optionally stored in RFIFO if EXMR.RCRC = 1
2)
Address optionally stored in RFIFO if EXMR.SRA = 1
3)
Start of the Control Field in Case of a 8 Bit Address
4)
Content of RSTA register appended at the frameend into RFIFO.
Compared with Registers
*
Stored in FIFO/Registers
*
*
2)
1)
*
4)
macro_12.vsd
Figure 46
Receive Data Flow
Note: The figure shows all modes except the extended transparent mode as this mode
uses no typical frame structure or address recognition. Data is transferred purely
transparent.
Data Sheet
103
2001-11-12
PEF 81902
Functional Description
The T-SMINTâIX indicates to the host that a new data block can be read from the RFIFO
by means of a RPF interrupt (see previous chapter). User data is stored in the RFIFO
and information about the received frame is available in the RSTA, RBCL and RBCH
registers which are listed in Table 26.
Table 26
Receive Information at RME Interrupt
Information
Register
Bit
Mode
Type of frame
(Command/
Response)
RSTA
C/R
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of SAPI
RSTA
SA1, 0
Non-auto mode,
2-byte address field
Transparent mode 1
Recognition of TEI
RSTA
TA
All except transparent
mode 0 and 1
Result of CRC check
(correct/incorrect)
RSTA
CRC
All
Valid Frame
RSTA
VFR
All
Abort condition detected
(yes/no)
RSTA
RAB
All
Data overflow during reception of RSTA
a frame (yes/no)
RDO
All
Number of bytes received in
RFIFO
RBCL
RBCx-0
All
(see Table 25)
Message length
RBCL
RBCH
RBC11-0
All
RFIFO Overflow
RBCH
OV
All
The RSTA register is appended as last byte to the end of a frame.
2.6.3
Data Transmission
2.6.3.1
Structure and Control of the Transmit FIFO
The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds) of 16 or 32
bytes, selectable by the XFBS bit in the EXMR register.
There are three different interrupt indications in the ISTAH register concerned with the
transmission of data:
Data Sheet
104
2001-11-12
PEF 81902
Functional Description
– XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32
bytes (block size selected via EXMR:XFBS) can be written to the XFIFO.
A XPR interrupt is generated either
– after a XRES (Transmitter Reset) command (which is issued for example for frame
abort) or
– when a data block from the XFIFO is transmitted and the corresponding FIFO
space is released to accept further data from the host.
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
current frame has been aborted (seven consecutive ’1’s are transmitted) as the XFIFO
holds no further transmit data. This occurs if the host fails to respond to a XPR
interrupt quick enough.
– XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
complete last frame has to be repeated as a collision on the S bus has been detected
while the first data bytes have already been overwritten with new data. So the XFIFO
does not hold the first data bytes of the frame (the HDLC transmitter is stopped if a
collision on the S bus has been detected).
The occurrence of a XDU or XMR interrupt clears the XFIFO and a XPR interrupt is
issued together with a XDU or XMR interrupt, respectively. Data cannot be written to
the XFIFO as long as a XDU/XMR interrupt is pending.
Three different control commands are used for transmission of data:
– XTF (Transmit Transparent Frame) command, telling the T-SMINTâIX that up to 16
or 32 bytes (according to selected block size) have been written to the XFIFO and
should be transmitted. A start flag is generated automatically.
– XME (Transmit Message End) command, telling the T-SMINTâIX that the last data
block written to the XFIFO completes the corresponding frame and should be
transmitted. This implies that according to the selected mode a frame end (CRC +
closing flag) is generated and appended to the frame.
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
transmit FIFO of any data. After a XRES command the transmitter always sends an
abort sequence, i.e. this command can be used to abort a transmission. XRES does
not clear pending interrupt indications of the transmitter, but has to be be cleared by
reading these interrupts.
Optionally two additional status conditions can be read by the host:
– XDOV (Transmit Data Overflow), indicating that the data block size has been
exceeded, i.e. more than 16 or 32 bytes were entered and data was overwritten.
– XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFO.
This status flag may be polled instead of or in addition to XPR.
Note: The significant interrupts and commands are underlined as only these are usually
used during a normal transmission sequence.
Data Sheet
105
2001-11-12
PEF 81902
Functional Description
The XFIFO requests service from the microcontroller by setting a bit in the ISTAH
register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read
the status register STAR (XFW, XDOV), write data in the FIFO and it may optionally
change the transmit FIFO block size (EXMR.XFBS) if required.
The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit
control commands is listed in Table 27.
•
Table 27
XPR Interrupt (availability of the XFIFO) after XTF, XME Commands
CMDR.
Transmit pool ready (XPR) interrupt initiated...
XTF
as soon as the selected buffer size in the FIFO is available
XTF &
XME
after the successful transmission of the closing flag. The transmitter
always sends an abort sequence
XME
as soon as the selected buffer size in the FIFO is available, two
consecutive frames share flags (endflag = startflag of next frame).
When setting XME the transmitter appends the FCS and the endflag at the end of the
frame. When XTF & XME have been set, the XFIFO is locked until successful
transmission of the current frame, so a consecutive XPR interrupt also indicates
successful transmission of the frame, whereas after XME the XPR interrupt is asserted
as soon as there is space for one data block in the XFIFO.
The transfer block size is 32 bytes by default, but sometimes, if the microcontroller has
a high computational load, it is useful to increase the maximum reaction time for a XPR
interrupt. The maximum reaction time is:
tmax = (XFIFO size - XFBS) / data transmission rate
With a selected block size of 16 bytes indicates a XPR interrupt when there are still 48
bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the XPR is
initiated when there are still 32 bytes (64 bytes - 32 bytes), i.d. the maximum reaction
time for the smaller block size is 50 % higher with the trade-off of a doubled interrupt
load. A selected block size of 32 or 16 bytes respectively always indicates the available
space in the XFIFO. So any number of bytes smaller than the selected XFBS may be
stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF,XME or XRES command. XRES resets the XFIFO.
The XFIFO can hold any number of frames fitting in the 64 bytes.
Data Sheet
106
2001-11-12
PEF 81902
Functional Description
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly
enough to a XPR interrupt, a XDU (transmit data underrun) interrupt will be raised. If the
HDLC channel becomes unavailable during transmission the transmitter tries to repeat
the current frame as specified in the LAPD protocol. This is impossible after the first data
block has been sent (16 or 32 bytes), in this case a XMR transmit message repeat
interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFO. The XFIFO is locked while a
XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be
ignored as long as the microcontroller has not read the ISTAH register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (16 or 32 bytes) , then the data in the
XFIFO will be corrupted and the STAR.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDR.XRES and start new.
The general procedures for a data transmission sequence are outlined in the flow
diagram in Figure 47.
Data Sheet
107
2001-11-12
PEF 81902
Functional Description
•
START
N
Transmit
Pool Ready
XPR
?
Y
Write Data
(up to 32 Bytes)
to XFIFO
Command
XTF
N
End of
Message
?
Y
Issue Command
- XME or
- XTF+XME
End
macro_13.vsd
Figure 47
Data Transmission Procedure
The following description gives an example for the transmission of a 76 byte frame with
a selected block size of 32 byte (EXMR:XFBS=0):
• The host writes 32 bytes to the XFIFO, issues a XTF command and waits for a XPR
interrupt in order to continue with entering data.
• The T-SMINT âIX immediately issues a XPR interrupt (as remaining XFIFO space is
not used) and starts transmission.
• Due to the XPR interrupt the host writes the next 32 bytes to the XFIFO, followed by
the XTF command, and waits for XPR.
Data Sheet
108
2001-11-12
PEF 81902
Functional Description
• As soon as the last byte of the first block is transmitted, the T-SMINTâIX issues a XPR
interrupt (XFIFO space of first data block is free again) and continues transmitting the
second block.
• The host writes the remaining 12 bytes of the frame to the XFIFO and issues the XTF
command together with XME to indicate that this is the end of frame.
• After the last byte of the frame has been transmitted the T-SMINTâIX releases a XPR
interrupt and the host may proceed with transmission of a new frame.
•
•
IOM Interface
76 Bytes
Transmit
Frame
32
WR
32 Bytes
32
WR
12 Bytes
WR
32 Bytes
XTF XPR
12
XTF
XPR
XTF+XME
XPR
CPU Interface
fifoseq_tran.vsd
Figure 48
2.6.3.2
Transmission Sequence Example
Transmit Frame Structure
The transmission of transparent frames (XTF command) is shown in Figure 49.
For transparent frames, the whole frame including address and control field must be
written to the XFIFO. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in EXMR.XCRC).
Further, the host selects the interframe time fill signal which is transmitted between
HDLC frames (EXMR:ITF). One option is to send continuous flags (’01111110’), or an
idle sequence (continuous ’1’s are transmitted), which is used if D-channel access
handling (collision resolution on the S bus) is required for example. Reprogramming of
ITF takes effect only after the transmission of the current frame has been completed or
after a XRES command.
Data Sheet
109
2001-11-12
PEF 81902
Functional Description
•
FLAG
ADDR
CTRL
ADDRESS
CONTROL
Transmit Transparent Frame
1)
DATA
CRC
The CRC is generated by default.
2.6.4
1)
*
fifoflow_tran.vsd
If EXMR.XCRC is set no CRC is appended
Figure 49
FLAG
CHECKRAM
XFIFO
(XTF)
*
I
Transmit Data Flow
Access to IOMâ-2 channels
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register
the HDLC controller can access the D, B1, B2 channels or any combination of them (e.g.
18 bit IDSL data (2B+D). In all modes (except extended transparent mode) sending
works always frame aligned, i.e. it starts with the first selected channel whereas
reception looks for a flag anywhere in the serial data stream.
2.6.5
Extended Transparent Mode
This non-HDLC mode is selected by setting MODEH.MDS2-0 to ’100’. In extended
transparent mode fully transparent data transmission/reception without HDLC framing is
performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing
mechanism. This allows user specific protocol variations.
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOMâ-2-frame aligned and byte aligned, i.e. transmission starts in the first
selected channel (B1, B2, D, according to the setting of register HCI_CR in the IOMâ-2
Handler) of the next IOMâ-2 frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with a XPR interrupt after
sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled (MODEH.DIM = ’0x1’) the stop go bit (S/G) can be
used as a clear-to-send indication as in any other mode. If the S/G bit is set to ’1’ (stop)
Data Sheet
110
2001-11-12
PEF 81902
Functional Description
during transmission the transmitter responds always with a XMR (transmit message
repeat) interrupt and stops transmission.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert a XDU (transmit data underrun) interrupt.
Receiver
The reception is IOMâ-2-frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR
in the IOMâ-2 Handler) of the next IOMâ-2 frame. The FIFO indications and commands
are the same as in others modes.
All incoming data bytes are stored in the RFIFO. If the FIFO is full a RFO interrupt is
asserted (EXMR.SRA = ’0’).
Note: In the extended transparent mode the EXMR register has to be set to ’xxx00000‘
2.6.6
Timer
The timer provides two modes (Table 28), a count down timer interrupt, i.e. an interrupt
is generated only once after expiration of the selected period, and a periodic timer
interrupt, which means an interrupt is generated continuously after every expiration of
that period.
•
Table 28
Timer
Address
Register
04H
TIMR
Modes
Period
Periodic
64 ... 2048 ms
Count Down
2.048 ... 14.336 s
When the programmed period has expired an interrupt is generated (ISTA.TIN).
The host controls the timer by setting bit CMDR.STI to start the timer and by writing
register TIMR to stop the timer. After time period T1 an interrupt is generated
continuously if CNT=7 or a single interrupt is generated after timer period T if CNT<7
(Figure 50).
Data Sheet
111
2001-11-12
PEF 81902
Functional Description
•
Retry Counter
0 ... 6 : Count Down Timer
7 : Periodic Timer
T = CNT x 2.048 sec + T1
T = T1
Expiration Period
T1 = (VALUE + 1) x 0.064 sec
7 6 5 4 3 2 1 0
TIMR1
Figure 50
2.6.7
CNT
VALUE
24H
21150_14
Timer Register
HDLC Controller Interrupts
All interrupt sources from the ISTAH register are combined (ORed) to a single HDLC
controller interrupt signal hint. Each of the interrupt sources can individually be masked
in the MASKH register. A masked interrupt is not indicated in the ISTAH register but
remains internally stored and pending until the interrupt is unmasked and read by the
host.
The individual interrupt sources of the HDLC controller during reception and
transmission of data are explained in Chapter 2.6.2.1 or Chapter 2.6.3.1 respectively.
The HDLC controller interrupts XDU and XMR have a special impact on the internal
functions. E.g. the transmitter of the HDLC controller is locked if a data underrun
condition occurs and the ISTAH.XDU is not read (the interrupt can only be read if
unmasked), same applies for XMR.
Data Sheet
112
2001-11-12
PEF 81902
Functional Description
•
MASK
U
ST
CIC
TIN
WOV
S
MOS
HDLC
ISTA
U
ST
CIC
TIN
WOV
S
MOS
HDLC
MASKH
ISTAH
RME
RME
RPF
RFO
XPR
RPF
RFO
XPR
XMR
XMR
XDU
XDU
INT
Figure 51
2.6.8
Interrupt Status Registers of the HDLC Controller
Test Function
The T-SMINTâIX provides test and diagnostic functions for the HDLC controller:
Digital loop via TLP (Test Loop, TMH register) command bit (Figure 52): The TX path of
the HDLC controller is still connected to IOMâ-2 but it is internally connected with the RX
path. All incoming data from the IOMâ-2 is ignored. This is used for testing HDLC
functionality excluding layer 1 (U-transceiver (loopback between XFIFO and RFIFO).
•
TMH:TLP = 0
TMH:TLP = 1
IOM-2
IOM-2
Data Out
Data Out
Data In
Data In
HDLC
HDLC
macro_8
Figure 52
Data Sheet
Layer 2 Test Loops
113
2001-11-12
PEF 81902
Functional Description
2.6.9
Reset Behavior
After reset all pointers to the FIFOs are set to “0”, the XPR interrupt is set to “1” but
cannot be read by the host as it is masked, i.e. it must be unmasked so it can be read.
Data Sheet
114
2001-11-12
PEF 81902
Operational Description
3
Operational Description
3.1
Layer 1 Activation/Deactivation
3.1.1
Generation of 4B3T Signal Elements
For control and monitoring purposes of the activation/deactivation progress the following
signal elements are defined by TS 102 080 and FTZ 1 TR 220.
Table 29
U0
4B3T Signal Elements
No signal or deactivation signal that is used in both directions.
Downstream, it requests the NT to deactivate. Upstream, the NT
acknowledges by U0 that it is deactivated.
U1W, U2W Awake or awake acknowledge signal used in the awake procedure of the
U-interface.
U2
The LT sends U2 to enable the own echo canceller to adapt the
coefficients. By the Barker code the NT at the other end is enabled to
synchronize. The detection of U2 is used by the NT as a criterion for
synchronization.
The M-channel on U may be used to transfer loop commands.
U2A
While the NT-RP is synchronizing on the received signal, the LT-RP sends
out U2A to enable its echo canceller to adapt the coefficients, but sending
no Barker code it inhibits the NT to synchronize on the still asynchronous
signal.
Due to proceeding synchronization, the U-frame may jump from time to
time. U2A can not be detected in the NT at the far end.
U1A
U1A is similar to U1 but without framing information. While the NT
synchronizes on the received signal, it sends out U1A to enable its echo
canceller to adapt its coefficients, but sends no Barker code to prevent the
LT from synchronizing on the still asynchronous signal. Due to proceeding
synchronization, the U-frame may jump from time to time. U1A can not be
detected by the far-end LT.
U1
When synchronized, the NT sends the Barker code and the LT may
synchronize itself. U1 indicates additionally that a terminal equipment has
not yet activated. Upon receiving U1 the LT indicates the synchronized
state by C/I ’UAI’ to layer-2.
Usually during activation, no U1 signal is detected in the LT because the
TE is activated first and U1 changes to U3 before being detected.
The M-channel on U may be used to transfer code error indications and 1
kbit/s transparent data.
Data Sheet
115
2001-11-12
PEF 81902
Operational Description
Table 29
U3
4B3T Signal Elements (cont’d)
U3 indicates that the whole link to the TE is synchronous in both directions.
On detecting U3 the LT requests the NT by U4H to establish a fully
transparent connection.
The M-channel on U may be used to transfer code error indications and
1 kbit/s transparent data.
U4H
U4H requires the NT to go to the ’Transparent’ state. On detecting U4H the
NT stops sending signal U3 and informs the S-transceiver or a layer-2
device via the system interface.
The M-channel on U may be used to transfer loop commands and 1 kbit/s
transparent data.
U4
U4 transports operational data on B and D channels. The M-channel on U
may be used to transfer loop commands and 1 kbit/s transparent data.
U5
U5 transports operational data on B and D channels. The M-channel on U
may be used to transfer code error indications and 1 kbit/s transparent
data.
SP
The T-SMINTIX sends periodically single pulses once per millisecond on
the U-interface. The test mode can be used for pulse mask
measurements.
LOF
Loss of frame, generated by flywheel
Table 30
Generation of the 4B3T Signal Elements
Upstream Downstream
(NT to LT) (LT to NT)
symbols
(ternary)
sync
word
(tern
ary)
binary
data
before
scram
bling
n/a
n/a
U1W
U2W
Resulting in a tone of:
Frequency: 7.5 kHz
Duration: 2.13 ms
when sending the
wakeup tone is finished,
signal AWT is set and
ternary "0" is sent
U1A
U2A
scrambled binary data
0
0
0
U1
U2
scrambled binary data
yes
yes
0
scrambled binary data
yes
yes
1
U3
Data Sheet
116
16 times + n/a
+++++
++––––
––––
M
sym
bol
(tern
ary)
2001-11-12
PEF 81902
Operational Description
Table 30
Generation of the 4B3T Signal Elements (cont’d)
U4H
Duration: 1 ms
(warranted by state
machine)
yes
yes
1
U5
U4
Binary data from the
digital interface
yes
yes
BBD
U0
U0
Ternary continuous "0"
0
0
0
n/a
SP
SP
single pulses
once "+", n/a
119 times
"0"
(repeatedl
y)
n/a
n/a
Table 31
S/T-Interface Signals
Signals from NT to TE
Signals from TE to NT
INFO 0
INFO 0
No signal.
INFO 1
A continuous signal with the
following pattern:
Positive ZERO, negative ZERO,
six ONEs.
INFO 3
Synchronized frames with
operational data on B and
D-channels.
INFO 2
INFO 4
Data Sheet
No signal.
Frame with all bits of B, D, and
D-echo channels set to binary
ZERO. Bit A set to binary ZERO.
N and L bits set according to the
normal coding rules.
Frames with operational data on
B, D, and D-echo channels. Bit
A set to binary ONE.
117
2001-11-12
PEF 81902
Operational Description
3.1.2
Complete Activation Initiated by Exchange
•
IOMâ-2
TE
NT
S/T-Reference Point
DC
INFO 0
DI
INFO 0
S0
DC
µC
DI
U-Reference Point
DC
DI
Uk0
LT
IOMâ-2
U0
DC
U0
DI
AR
RSY
AR
U2W
U0
U1W
U0
U1A
U2
AR
INFO 2
AR
AR
U1
UAI
AR
INFO 3
AI
AI
U3
UAI
U4H
AI
AI
U5
U4
INFO 4
AI
1 ms
AI
AR8/10
SBCX-X or
IPAC-X
Figure 53
DFE-T
actbyLT_TSMINT.vsd
Activation Initiated by Exchange
Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This
chronological order is not displayed for clarification.
Data Sheet
118
2001-11-12
PEF 81902
Operational Description
3.1.3
Complete Activation Initiated by TE
•
IOMâ-2
TE
NT
S/T-Reference Point
S0
INFO 0
DC
DI
INFO 0
U-Reference Point
DC
DC
DI
DI
TIM
TIM
Uk0
IOMâ-2
LT
U0
DC
U0
DI
TIM
PU
AR8/10
INFO 1
8ms
AR
AR
U1W
RSY
U0
U2W
AR
U0
U1A
U2
AR
AR
INFO 2
RSY
U1
INFO 0
AR
UAI
INFO 3
AI
AI
U3
AI
INFO 4
AI
AI
UAI
U4H
U5
U4
1 ms
AI
SBCX-X or
IPAC-X
DFE-T
actbyTE_TSMINT.vsd
Figure 54
Activation Initiated by TE
Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This
chronological order is not displayed for clarification.
Data Sheet
119
2001-11-12
PEF 81902
Operational Description
3.1.4
Complete Activation Initiated by NT
•
IOMâ-2
TE
INFO 0
DC
DI
NT
S/T-Reference Point
INFO 0
S0
DC
µC
DI
U-Reference Point
DC
DI
Uk0
IOMâ-2
LT
U0
DC
U0
DI
TIM
AR
U1W
RSY
U0
AR
U2W
U0
U1A
U2
AR
AR
INFO 2
AR
U1
AR
UAI
INFO 3
AI
AI
U3
AI
INFO 4
AI
AI
UAI
U4H
U5
U4
1 ms
AI
AR 8/10
SBCX-X or
IPAC-X
DFE-T
actbyNT_TSMINT.vsd
Figure 55
Activation Initiated by NT
Note: The LT starts issuing signal U2 before the NT starts issuing U1A. This
chronological order is not displayed for clarification.
Data Sheet
120
2001-11-12
PEF 81902
Operational Description
3.1.5
Complete Deactivation
•
IOMâ-2
TE
NT
S/T-Reference Point
AI
INFO 4
AR
INFO 3
S0
U-Reference Point
AI
AI
AI
AI
Uk0
LT
IOMâ-2
U4
AR
U5
AI
U0
DEAC
DR
DR
INFO 0
RSY
DR
U0
DR
DI
TIM
DC
INFO 0
DI
DI
DC
DC
DI
DC
SBCX-X or
IPAC-X
DFE-T
deac_TSMINT.vsd
Figure 56
Data Sheet
Complete Deactivation
121
2001-11-12
PEF 81902
Operational Description
3.1.6
Loop 2
•
NT
IOMâ-2
U-Reference Point
TE S/T-Reference Point
INFO 4
AI
AR8/10
INFO 3
S0
AI
AI
AI
AI
Uk0
LT
IOMâ-2
U4
AR
U5
AI
AR2
2B+D
U4 (M-Bit= 8x '+' )
AIL
AIL
AR
2B+D
U4 (M-Bit= 8x '0' )
AI
AI
2B+D
SBCX-X or
IPAC-X
DFE-T
act_loop2_TSMINT.vsd
Figure 57
Loop 2
Note: Closing/resolving loop 2 may provoke the S-transceiver to resynchronize. In this
case, the following C/I-codes are exchanged immediately on reception of AIL/AI,
respectively: DU: ’RSY’, DU: ’AI’, DD: ’AIL’/’AI’.
Data Sheet
122
2001-11-12
PEF 81902
Operational Description
3.2
Layer 1 Loopbacks
Test loopbacks are specified by the national PTTs in order to facilitate the location of
defect systems. Four different loopbacks are defined. The position of each loopback is
illustrated in Figure 58.
•
U
U
IOM®-2
S-BUS
Loop 2
Loop 2
S-Transceiver
U-Transceiver
IOM®-2
Loop 1 A
NT
U-Transceiver
IOM®-2
Loop 2
Layer-1 Controller
IOM®-2
U-Transceiver
Repeater (optional)
Loop 1
U-Transceiver
Exchange
U-Transceiver
IOM-2
Loop 3
Layer-1 Controller
U-Transceiver
PBX or TE
Figure 58
loop_2b1q.emf
Test Loopbacks
Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled
locally on the remote side. All four loopback types are transparent. This means all bits
that are looped back will also be passed onwards in the normal manner. Only the data
looped back internally is processed; signals on the receive pins are ignored. The
propagation delay of actually looped B and D channels data must be identical in all
loopbacks.
Besides the remote controlled loopback stimulation via the M channel, the T-SMINTâIX
features also direct loopback control via its register set.
3.2.1
Analog Loop-Back S-Transceiver
The T-SMINTâIX provides test and diagnostic functions for the S/T interface:
The internal local loop (internal Loop A) is activated by a C/I command ARL or by
setting the bit LP_A (Loop Analog) in the S_CMD register if the layer-1 statemachine is
disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data of
the IOMâ-2 input B- and D-channels are looped back to the output B- and D-channels.
Data Sheet
123
2001-11-12
PEF 81902
Operational Description
The S/T interface level detector is enabled, i.e. if a level is detected this will be reported
by the Resynchronization Indication (RSY) but the loop function is not affected.
Depending on the DIS_TX bit in the S_CONF2 register the internal local loop can be
transparent or non transparent to the S/T line.
The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the S_CONF0 register has to be
programmed and the loop has to be closed externally as described in Figure 59.
The S/T interface level detector is disabled.
•
SX1
100 Ω
SX2
SCOUT-S(X)
SR1
100 Ω
SR2
Figure 59
3.2.2
External Loop at the S/T-Interface
Loopback No.2
For loopback #2 several alternatives exist. Both the type of loopback and the location
may vary. The following loopback types belong to the loopback-#2 category:
•
•
•
•
complete loopback (B1,B2,D), in the U-transceiver
complete loopback (B1,B2,D), in a downstream device
B1-channel loopback, always performed in the U-transceiver
B2-channel loopback, always performed in the U-transceiver
All loop variations performed by the U-transceiver are closed as near to the internal
IOMâ-2 interface as possible.
Normally loopback #2 is controlled by the exchange. The maintenance channel is used
for this purpose.
Data Sheet
124
2001-11-12
PEF 81902
Operational Description
3.2.2.1
Complete Loopback
When receiving the request for a complete loopback, the U transceiver passes it on to
the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/Icode AIL in the “Transparent” state or C/I = ARL in states different than “Transparent”
•
S-Transceiver
U-Transceiver
loop request
2 B+D
2B+D
Controller
U
loop command
loop command
lp2bymon8.vsd
Figure 60
Complete Loopback Options in NT-Mode
The complete loopback is either opened under control of the exchange via the
maintenance channel or locally controlled via the µC. No reset is required for loopback
#2. The line stays active and is ready for data transmission.
3.2.2.2
Loopback No.2 - Single Channel Loopbacks
Single channel loopbacks are always performed directly in the U-Transceiver. No
difference between the B1-channel and the B2-channel loopback control procedure
exists.
3.2.3
Local Loopbacks Featured By the LOOP Register
Besides the standardized remote loopbacks the U-transceiver features additional local
loopbacks for enhanced test and debugging facilities. The local loopbacks that are
featured by register LOOP are shown in Figure 61. They are closed in the U-transceiver
itself and can be activated regardless of the current operational status.
By the LOOP register it can be configured whether the loopback is closed only for the B1
and/or B2 or for 2B+D channels and whether the loopback is closed towards the internal
IOMâ-2 interface or towards the U-Interface.
By default the loopbacks are set to transparent mode. In transparent mode the data is
both passed on and looped back. In non-transparent mode the data is not forwarded but
substituted by 1s (idle code).
Data Sheet
125
2001-11-12
PEF 81902
Operational Description
•
LOOP.LB1=1
LOOP.LB2=1
LOOP.LBBD= 1
&
LOOP.U/IOM= 0
LOOP.LB1=1
LOOP.LB2=1
LOOP.LBBD= 1
&
LOOP.U/IOM= 1
Analog Part
Digital Part
Line Interface
Unit
DAC
2B1Q
Scrambler
UFraming
Echo
Canceller
Σ∆
ADC
PDM
Filter
+
Tx-FIFO
A
G
C
Rx-FIFO
Equalizer
2B1Q
DeScrambler
U-DeFraming
IOM-2
Interface
Timing
Recovery
Bandgap,
Bias, Refer.
Activation/ Deactivation
Controller
U-Transceiver
loopreg.emf
Figure 61
Data Sheet
Loopbacks Featured by Register LOOP
126
2001-11-12
PEF 81902
Operational Description
3.3
External Circuitry
3.3.1
Power Supply Blocking Recommendation
The following blocking circuitry is suggested.
•
VDDa_UR
VDDa_UX
VDDa_SR
VDDa_SX
3.3V
VDDD
VDDD
1)
100nF
1)
100nF
1)
100nF
1)
100nF
1)
100nF
1)
100nF
1µF
VSSD
VSSD
GND
VSSa_SX
VSSa_SR
VSSa_UX
VSSa_UR
1)
These capacitors should be located as near to the pins as possible
blocking_caps_Smint.vsd
Figure 62
3.3.2
Power Supply Blocking
U-Transceiver
The T-SMINTIX is connected to the twisted pair via a transformer. Figure 63 shows the
recommended external circuitry with external hybrid. The recommended protection
circuitry is not displayed.
Data Sheet
127
2001-11-12
PEF 81902
Operational Description
•
RT
R3
AOUT
BIN
R4
n
RCOMP
>1µ
C
AIN
RCOMP
R3
R4
Loop
Figure 63
extcirc_U_Q2_exthybrid.emf
RT
BOUT
External Circuitry U-Transceiver with External Hybrid
U-Transformer Parameters
The following table lists parameters of typical U-transformers.
Table 32
U-Transformer Parameters
U-Transformer Parameters
Symbol Value
U-Transformer ratio;
Device side : Line side
n
1 : 1.6
Main inductanc of windings on the line side
LH
7.5
mH
Leakage inductance of windings on the line side LS
120
µH
Coupling capacitance between the windings on CK
the device side and the windings on the line side
30
pF
DC resistance of the windings on device side
RB
0.9
Ω
DC resistance of the windings on line side
RL
1.8
Ω
Data Sheet
128
Unit
2001-11-12
PEF 81902
Operational Description
Resistors of the External Hybrid R3, R4 and RT
R3 = 1.75 kΩ
R4 = 1.0 kΩ
RT = 25 Ω
Resistors RCOMP / RT
• Optional use of trafos with non negligible resistance RB, RL requires compensation
resistors RCOMP depending on RB and RL:
n2 × (2RCOMP + RB) + RL = 20Ω
(1)
• Compliance with Return Loss Measurements:
n2 × (2RCOMP + 2RT + Rout + RB) + RL = 150Ω
(2)
RB, RL : see Table 32
ROUT : see Table 39
15nF Capacitor
To achieve optimum performance the 15nF capacitor should be MKT. A Ceramic
capacitor is not recommended.
Tolerances
• Rs: 1%
• C = 15nF: 10-20%
• LH = 7.5mH: 10%
3.3.3
S-Transceiver
In order to comply to the physical requirements of ITU recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the S-transceiver needs some additional circuitry.
Data Sheet
129
2001-11-12
PEF 81902
Operational Description
S-Transformer Parameters
The following Table 33 lists parameters of a typical S-transformer:
Table 33
S-Transformer Parameters
Transformer Parameters
Symbol Value
Unit
Transformer ratio;
Device side : Line side
n
2:1
Main inductance of windings on the line side
LH
typ. 30
mH
Leakage inductance of windings on the line side LS
typ. <3
µH
Coupling capacitance between the windings on CK
the device side and the windings on the line side
typ. <100
pF
DC resistance of the windings on device side
RB
typ. 2.4
Ω
DC resistance of the windings on line side
RL
typ. 1.4
Ω
Transmitter
The transmitter requires external resistors Rstx = 47Ω in order to adjust the output
voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the
test mode “TM1”) on the one hand and in order to meet the output impedance of
minimum 20 Ω on the other hand (to be tested with the testmode ’Continuous Pulses’)
on the other hand.
Note: The resistance of the S-transformer must be taken into account when
dimensioning the external resistors Rstx. If the transmit path contains additional
components (e.g. a choke), then the resistance of these additional components
must be taken into account, too.
Data Sheet
130
2001-11-12
PEF 81902
Operational Description
•
47
SX1
2:1
20...40
VDD
GND
SX2
47
DC Point
extcirc_S.vsd
Figure 64
External Circuitry S-Interface Transmitter
Receiver
The receiver of the S-transceiver is symmetrical. 10 kΩ overall resistance are
recommended in each receive path. It is preferable to split the resistance into two
resistors for each line. This allows to place a high resistance between the transformer
and the diode protection circuit (required to pass 96 kHz input impedance test of
ITU I.430 [6] and ETS 300012-1). The remaining resistance (1.8 kΩ) protects the Stransceiver itself from input current peaks.
•
1k8
8k2
SR1
2:1
VDD
GND
SR2
1k8
8k2
DC Point
extcirc_S.vsd
Figure 65
Data Sheet
External Circuitry S-Interface Receiver
131
2001-11-12
PEF 81902
Operational Description
3.3.4
Oscillator Circuitry
Figure 66 illustrates the recommended oscillator circuit.
•
CLD
XOUT
15.36 MHz
XIN
CLD
Figure 66
Crystal Oscillator
Table 34
Crystal Parameters
Parameter
Symbol
Limit Values
Unit
Frequency
f
15.36
MHz
+/-60
ppm
Frequency calibration tolerance
Load capacitance
CL
20
pF
Max. resonance resistance
R1
20
Ω
Max. shunt capacitance
C0
7
pF
Oscillator mode
fundamental
External Components and Parasitics
The load capacitance CL is computed from the external capacitances CLD, the parasitic
capacitances CPar (pin and PCB capacitances to ground and VDD) and the stray
capacitance CIO between XIN and XOUT:
( C LD + C Par ) × ( C LD + C Par )
C L = ------------------------------------------------------------------------ + C IO
( C LD + C Par ) + ( C LD + C Par )
For a specific crystal the total load capacitance is predefined, so the equation must be
solved for the external capacitances CLD, which is usually the only variable to be
determined by the circuit designer. Typical values for the capacitances CLD connected
to the crystal are 22 - 33 pF.
3.3.5
General
– low power LEDs
Data Sheet
132
2001-11-12
PEF 81902
Register Description
4
Register Description
4.1
Address Space
7DH
U-Transceiver
60H
5CH
40H
3CH
30H
20H
Monitor Handler
IOMâ-2 Handler
(CDA, TSDP, CR, STI)
Interrupt, Global Registers
S-Transceiver
HDLC Controller, CI Reg.
HDLC RFIFO/XFIFO
00H
Figure 67
Data Sheet
Address Space
133
2001-11-12
PEF 81902
Register Description
4.2
Interrupts
Special events in the T-SMINTâIX are indicated by means of a single interrupt output,
which requests the host to read status information from the T-SMINTâIX or transfer data
from/to the T-SMINTâIX.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the T-SMINTâIX.
The structure of the interrupt status registers is shown in Figure 68.
MASKU
1
CI
ISTAU
0
CI
RDS
1
1
RDS
0
0
0
0
1ms
1
1
1ms
MASK
U
ST
CIC
TIN
WOV
S
MOS
HDLC
INT
Figure 68
Data Sheet
ISTA
U
ST
CIC
TIN
WOV
S
MOS
HDLC
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
CIC0
CIC1
CIR0
CI1E
CIX1
STI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
MASKS
LD
RIC
SQC
SQW
MRE
RME
RPF
RFO
XPR
XMR
XDU
RME
RPF
RFO
XPR
XMR
XDU
MASKH
ISTAH
MIE
MOCR
ASTI
ACK21
ACK20
ACK11
ACK10
ISTAS
LD
RIC
SQC
SQW
MDR
MER
MDA
MAB
MOSR
T-SMINTâIX Interrupt Status Registers
134
2001-11-12
PEF 81902
Register Description
After the T-SMINTâIX has requested an interrupt by setting its INT pin to low, the host
must read first the T-SMINTâIX interrupt status register (ISTA) in the associated interrupt
service routine. The INT pin of the T-SMINTâIX remains active until all interrupt sources
are cleared. Therefore, it is possible that the INT pin is still active when the interrupt
service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and writing back the old mask to the MASK register.
Data Sheet
135
2001-11-12
PEF 81902
Register Description
4.3
Register Summary
r(0) = reserved, implemented as zero
HDLC Control Registers, CI Handler
Name
7
6
5
4
3
2
1
0
ADDR R/W RES
RFIFO
D-Channel Receive FIFO
00H1FH
R
XFIFO
D-Channel Transmit FIFO
00H1FH
W
ISTAH
RME
RPF
RFO
XPR
XMR
XDU
r(0)
r(0)
20H
R
10H
MASKH
RME
RPF
RFO
XPR
XMR
XDU
0
0
20H
W
FCH
STAR
XDOV
XFW
r(0)
r(0)
RACI
r(0)
XACI
r(0)
21H
R
40H
CMDR
RMC
RRES
0
STI
XTF
0
XME
XRES
21H
W
00H
MODEH
MDS2 MDS1 MDS0
r(0)
RAC
DIM2
DIM1
DIM0
22H
R/W C0H
EXMR
XFBS
SRA
XCRC
RCRC
r(0)
ITF
23H
R/W 00H
24H
R/W 00H
TIMR
RFBS
CNT
VALUE
SAP1
SAPI1
0
MHA
25H
W
FCH
SAP2
SAPI2
0
MLA
26H
W
FCH
RBC0
26H
R
00H
RBC8
27H
R
00H
RBCL
RBC7
RBCH
r(0)
r(0)
r(0)
OV
RBC11
TEI1
TEI1
EA1
27H
W
FFH
TEI2
TEI2
EA1
28H
W
FFH
R
0FH
RSTA
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
28H
TMH
r(0)
r(0)
r(0)
r(0)
r(0)
r(0)
r(0)
TLP
29H
reserved
Data Sheet
136
R/W 00H
2AH2DH
2001-11-12
PEF 81902
Register Description
CIR0
CODR0
CIC0
CIC1
S/G
BAS
2EH
R
F3 H
CIX0
CODX0
TBA2
TBA1
TBA0
BAC
2EH
W
FEH
CIR1
CODR1
CICW
CI1E
2FH
R
FEH
CIX1
CODX1
CICW
CI1E
2FH
W
FEH
Data Sheet
137
2001-11-12
PEF 81902
Register Description
S-Transceiver
Name
S_
CONF0
7
6
5
4
3
2
1
0
DIS_
TR
BUS
EN_
ICV
0
L1SW
0
EXLP
0
reserved
S_
CONF2
DIS_
TX
S_STA
RINF
S_CMD
SQRR
0
SQXR
0
MFEN
R/W 40H
30H
31H
0
0
0
0
0
0
32H
0
ICV
0
FSYN
0
LD
33H
DPRIO
1
PD
LP_A
0
34H
0
0
SQR1
SQR2
SQR3
SQR4
35H
R
00H
0
0
SQX1
SQX2
SQX3
SQX4
35H
W
00H
R
00H
XINF
MSYN MFEN
ADDR R/W RES
reserved
R/W 80H
R
00H
R/W 08H
36H-37H
ISTAS
0
x
x
x
LD
RIC
SQC
SQW
38H
MASKS
1
1
1
1
LD
RIC
SQC
SQW
39H
R/W FFH
S_
MODE
0
0
0
0
DCH_
INH
3AH
R/W 02H
reserved
Data Sheet
138
MODE2-0
3BH
2001-11-12
PEF 81902
Register Description
Interrupt, General Configuration
Name
7
6
5
4
3
2
1
0
ISTA
U
ST
CIC
TIN
WOV
S
MOS
HDLC
3CH
R
00H
MASK
U
ST
CIC
TIN
WOV
S
MOS
HDLC
3CH
W
FFH
CDS
WTC1
WTC2
CFS
RSS2
RSS1
3DH
R/W 04H
0
0
3EH
R/W 00H
MODE1
MODE2
MCLK
LED2
LED1
ID
0
0
SRES
0
0
Data Sheet
LEDC
AMOD PPSDX
DESIGN
RES_
CI/TIC
0
RES_
HDLC
139
0
RES_
S
RES_
U
ADDR R/W RES
3FH
R
20H
3FH
W
00H
2001-11-12
PEF 81902
Register Description
IOM Handler (Timeslot, Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/W RES
CDA10
Controller Data Access Register
40 H
R/W FFH
CDA11
Controller Data Access Register
41 H
R/W FFH
CDA20
Controller Data Access Register
42 H
R/W FFH
CDA21
Controller Data Access Register
43 H
R/W FFH
CDA_
TSDP10
DPS
0
0
0
TSS
44 H
R/W 00H
CDA_
TSDP11
DPS
0
0
0
TSS
45 H
R/W 01H
CDA_
TSDP20
DPS
0
0
0
TSS
46 H
R/W 80H
CDA_
TSDP21
DPS
0
0
0
TSS
47 H
R/W 81H
reserved
48H4BH
S_
TSDP_
B1
DPS
0
0
0
TSS
4CH
R/W 84H
S_
TSDP_
B2
DPS
0
0
0
TSS
4DH
R/W 85H
CDA1_
CR
0
0
EN_
TBM
EN_I1
EN_I0 EN_O1 EN_O0 SWAP
4EH
R/W 00H
CDA2_
CR
0
0
EN_
TBM
EN_I1
EN_I0 EN_O1 EN_O0 SWAP
4FH
R/W 00H
Data Sheet
140
2001-11-12
PEF 81902
Register Description
IOM Handler (Control Registers, Synchronous Transfer Interrupt
Control)
Name
7
6
5
4
3
2
1
0
reserved
S_CR
50 H
1
CI_CS
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
HCI_CR
DPS_
CI1
EN_
CI1
EN_D
EN_
B2H
EN_
B1H
DPS_
H
MON_
CR
DPS
EN_
MON
0
0
0
0
SDS1_
CR
ENS_
TSS
ENS_ ENS_
TSS+1 TSS+3
0
SDS2_
CR
ENS_
TSS
ENS_ ENS_
TSS+1 TSS+3
0
IOM_CR
SPU
MCDA
STI
0
MCDA21
0
TIC_
DIS
EN_
BCL
MCDA20
ADDR R/W RES
EN_
B1X
51 H
R/W FFH
HCS
52 H
R/W 04H
MCS
53 H
R/W 40H
TSS
54 H
R/W 00H
TSS
55 H
R/W 00H
56 H
R/W 08H
0
MCDA11
DIS_
OD
D_CS
DIS_
IOM
MCDA10
57 H
R
FFH
STOV
21
STOV
20
STOV
11
STOV
10
STI
21
STI
20
STI
11
STI
10
58 H
R
00H
ASTI
0
0
0
0
ACK
21
ACK
20
ACK
11
ACK
10
58 H
W
00H
MSTI
STOV
21
STOV
20
STOV
11
STOV
10
STI
21
STI
20
STI
11
STI
10
59 H
reserved
Data Sheet
141
R/W FFH
5A H5BH
2001-11-12
PEF 81902
Register Description
MONITOR Handler
Name
7
6
5
4
3
2
1
0
ADDR R/W RES
MOR
MONITOR Receive Data
5CH
R
FFH
MOX
MONITOR Transmit Data
5CH
W
FFH
R
00H
MOSR
MDR
MER
MDA
MAB
0
0
0
0
5DH
MOCR
MRE
MRC
MIE
MXC
0
0
0
0
5EH
MSTA
0
0
0
0
0
MAC
0
TOUT
5FH
R
00H
MCONF
0
0
0
0
0
0
0
TOUT
5FH
W
00H
Data Sheet
142
R/W 00H
2001-11-12
PEF 81902
Register Description
U-Transceiver
Name
7
6
5
4
3
2
1
0
OPMODE
0
UCI
0
0
0
0
0
0
reserved
ADDR R/W RES
60H
R*/W 00 H
61H6CH
UCIR
0
0
0
0
C/I code output
6DH
R
00 H
UCIW
0
0
0
0
C/I code input
6EH
W
01 H
reserved
LOOP
0
0
RDS
TRANS U/IOM
1
6FH
LBBD
LB2
LB1
70H
reserved
71H
Block Error Counter Value
72H
reserved
73H79H
ISTAU
0
CI
RDS
0
0
0
0
1 ms
7AH
MASKU
1
CI
RDS
1
1
1
1
1 ms
7BH
FW_
VERSION
reserved
7CH
FW Version Number
7DH
R*/W 08 H
R
00 H
R
00 H
R*/W FFH
R
3EH
Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC,
neither for read nor for write operations.
4.3.1
Reset of U-Transceiver Functions During Deactivation or with
C/I-Code RESET
The following U-transceiver register is reset upon transition to state ’Deactivating’ or with
software reset:
Data Sheet
143
2001-11-12
PEF 81902
Register Description
•
Table 35
Reset of U-Transceiver Functions During Deactivation or with C/ICode RESET
Register
Affected Bits/ Comment
LOOP
only the bits LBBD, LB2 and LB1 are reset
4.3.2
Mode Register Evaluation Timing
Table 36 lists registers, which are evaluated and executed immediately.
•
Table 36
Mode Register with Immediate Evaluation and Execution
Register
Affected Bits
OPMODE
UCI
LOOP
complete register
MASKU
complete register
Data Sheet
Comment
144
2001-11-12
PEF 81902
Register Description
4.4
Detailed HDLC Control and C/I Registers
4.4.1
RFIFO - Receive FIFO
RFIFO
read
Address: 00-1FH
7
0
Receive data
The RFIFO contains up to 32 bytes of received data.
After an ISTAH.RPF interrupt, a complete data block is available. The block size can be
4, 8, 16, 32 bytes depending on the EXMR.RFBS setting.
After an ISTAH.RME interrupt, the number of received bytes can be obtained by reading
the RBCL register.
A read access to any address within the range 00H-1FH gives access to the “current”
FIFO location selected by an internal pointer which is automatically incremented after
each read access. This allows for the use of efficient “move string” type commands by
the microcontroller.
4.4.2
XFIFO - Transmit FIFO
XFIFO
write
Address: 00-1FH
7
0
Transmit data
Depending on EXMR.XFBS up to 16 or 32 bytes of transmit data can be written to the
XFIFO following an ISTAH.XPR interrupt.
A write access to any address within the range 00-1FH gives access to the “current” FIFO
location selected by an internal pointer which is automatically incremented after each
write access. This allows the use of efficient “move string” type commands by the
microcontroller.
4.4.3
ISTAH - Interrupt Status Register HDLC
ISTAH
read
Address:
20H
Value after reset: 10H
Data Sheet
145
2001-11-12
PEF 81902
Register Description
Note: The reset value cannot be read right after reset as all interrupts are masked, i.e.
the XPR interrupt remains internally stored and can only be read as soon as the
corresponding mask bit is set to “0”.
7
6
5
4
3
2
1
0
RME
RPF
RFO
XPR
XMR
XDU
r(0)
r(0)
RME
RPF
RFO
XPR
Receive Message End
0=
inactive
1=
One complete frame of length less than or equal to the defined
block size (EXMR.RFBS) or the last part of a frame of length
greater than the defined block size has been received. The
contents are available in the RFIFO. The message length and
additional information may be obtained from RBCH and RBCL and
the RSTA register.
Receive Full
0=
inactive
1=
A data block of a frame longer than the defined block size
(EXMR.RFBS) has been received and is available in the RFIFO.
The frame is not yet complete.
Receive Frame Overflow
0=
inactive
1=
The received data of a frame could not be stored, because the
RFIFO is occupied. The whole message is lost.
This interrupt can be used for statistical purposes and indicates that
the microcontroller does not respond quickly enough to a RPF or
RME interrupt (ISTAH).
Transmit Pool Ready
0=
Data Sheet
inactive
146
2001-11-12
PEF 81902
Register Description
1=
XMR
A data block of up to the defined block size (EXMR.XFBS) can be
written to the XFIFO.
A XPR interrupt will be generated in the following cases:
• after a XTF or XME command as soon as the 16 / 32 bytes in the
XFIFO are available and the frame is not yet complete.
• after a XTF together with a XME command is issued, when the
whole frame has been transmitted.
• after reset
• after XRES
Transmit Message Repeat
0=
inactive
1=
The transmission of the last frame has to be repeated because a
collision on the S bus has been detected after the 16th/32nd data
byte of a transmit frame.
If a XMR interrupt occurs the transmit FIFO is locked until the XMR
interrupt is read by the host (interrupt cannot be read if masked in
MASKH).
XDU
Transmit Data Underrun
0=
inactive
1=
The current transmission of a frame is aborted by transmitting
seven ‘1’s because the XFIFO holds no further data. This interrupt
occurs whenever the microcontroller has failed to respond to a
XPR interrupt (ISTAH register) quick enough, after having initiated
a transmission and the message to be transmitted is not yet
complete.
If a XMR interrupt occurs the transmit FIFO is locked until the XDU
interrupt is read by the host (interrupt cannot be read if masked in
MASKH).
4.4.4
MASKH - Mask Register HDLC
MASKH
write
Address:
20H
Value after reset: FCH
Data Sheet
147
2001-11-12
PEF 81902
Register Description
7
6
5
4
3
2
1
0
RME
RPF
RFO
XPR
XMR
XDU
0
0
Each interrupt source in the ISTAH register can be selectively masked by setting the
corresponding bit in MASKH to ‘1’. Masked interrupt status bits are not indicated when
ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Bit 0..7
Mask Bits
4.4.5
0=
interrupt active
1=
interrupt masked
STAR - Status Register
STAR
read
Address:
21H
Value after reset: 40H
7
6
5
4
3
2
1
0
XDOV
XFW
r(0)
r(0)
RACI
r(0)
XACI
0
XDOV
XFW
RACI
Transmit Data Overflow
0=
No transmit data overflow
1=
More than the selected block size of 16 or 32 bytes have been
written into the XFIFO, i.e. data has been overwritten.
Transmit FIFO Write Enable
0=
Data can not be written in the XFIFO
1=
Data can be written in the XFIFO. This bit may be polled instead of
(or in addition to) using the XPR interrupt.
Receiver Active Indication
0=
Data Sheet
The HDLC receiver is not active
148
2001-11-12
PEF 81902
Register Description
1=
XACI
The HDLC receiver is active when RACI = ‘1’. This bit may be
polled. The RACI bit is set active after a begin flag has been
received and is reset after receiving an abort sequence.
Transmitter Active Indication
4.4.6
0=
The HDLC-transmitter is not active
1=
The HDLC-transmitter is active when XACI = ‘1’. This bit may be
polled. The XACI-bit is active when a XTF-command is issued and
the frame has not been completely transmitted.
CMDR - Command Register
CMDR
write
Address:
21H
Value after reset: 00H
7
6
5
4
3
2
1
0
RMC
RRES
0
STI
XTF
0
XME
XRES
RMC
RRES
STI
XTF
Receive Message Complete
0=
inactive
1=
Reaction to RPF (Receive Pool Full) or RME (Receive Message
End) interrupt. By setting this bit, the microcontroller confirms that
it has fetched the data, and indicates that the corresponding space
in the RFIFO may be released.
Receiver Reset
0=
inactive
1=
HDLC receiver is reset, the RFIFO is cleared of any data.
Start Timer
0=
inactive
1=
The T-SMINTâIX hardware timer is started (see TIMR register).
Transmit Transparent Frame
0=
Data Sheet
inactive
149
2001-11-12
PEF 81902
Register Description
1=
XME
After having written up to 16 or 32 bytes (EXMR.XFBS) in the
XFIFO, the microcontroller initiates the transmission of a
transparent frame by setting this bit to ‘1’. The opening flag is
automatically added to the message by the T-SMINTâIX except in
the extended transparent mode.
Transmit Message End
XRES
0=
inactive
1=
By setting this bit to ‘1’ the microcontroller indicates that the data
block written last in the XFIFO completes the corresponding frame.
The T-SMINTâIX completes the transmission by appending the
CRC (if XCRC = 0) and the closing flag sequence to the data except
in the extended transparent mode.
Transmitter Reset
0=
inactive
1=
HDLC transmitter is reset and the XFIFO is cleared of any data.
This command can be used by the microcontroller to abort a frame
currently in transmission.
All of these bits must not be set twice within one BCL clock cycle.
Note: After a XPR interrupt further data has to be written to the XFIFO and the
appropriate Transmit Command (XTF) has to be written to the CMDR register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAH).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically except in extended transparent mode.
4.4.7
MODEH - Mode Register HDLC Controller
MODEH
read/write
Address:
22H
Value after reset: C0H
7
MDS2
Data Sheet
0
MDS1
MDS0
r(0)
150
RAC
DIM2
DIM1
DIM0
2001-11-12
PEF 81902
Register Description
MDS2-0
Mode Select
Determines the message transfer mode of the HDLC controller, as follows
:
MDS2-0
Mode
Address
Comparison
1.Byte
2.Byte
Remark
0
0
0 Reserved
–
–
–
0
0
1 Reserved
–
–
–
0
1
0 Non-Auto
TEI1,TEI2
–
One-byte address
compare.
mode/8
0
1
1 Non-Auto
mode/16
1
0
0 Extended
SAP1,SAP2, TEI1,TEI2, Two-byte address
SAPG
TEIG
compare.
–
–
–
0 Transparent –
–
No address
compare. All
frames accepted.
transparent
mode
1
1
mode 0
1
1
1 Transparent SAP1,SAP2, –
mode 1
1
0
SAPG
1 Transparent –
High-byte address
compare.
TEI1,TEI2, Low-byte address
TEIG
compare.
mode 2
Note: SAP1, SAP2: two programmable address values for the first received address
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FEH.
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte; TEIG = fixed value FFH.
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA (see also description of
these bits in Chapter 4.4.10 or Chapter 4.4.11 respectively).
RAC
Data Sheet
Receiver Active
0=
The HDLC data is not evaluated in the receiver
1=
The HDLC receiver is activated
151
2001-11-12
PEF 81902
Register Description
DIM2-0
Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The
DIM0 bit enables/disables the stop/go bit (S/G) evaluation. The DIM1 bit
enables/disables the TIC bus access. The effect of the individual DIM bits is
as follows:
4.4.8
0-0 =
Stop/go bit evaluation is disabled
0-1 =
Stop/go bit evaluation is enabled
00- =
TIC bus access is enabled
01- =
TIC bus access is disabled
1xx =
Reserved
EXMR - Extended Mode Register
EXMR
read/write
Address:
23H
Value after reset: 00H
7
0
XFBS
XFBS
RFBS
SRA
XCRC
RCRC
r(0)
ITF
Transmit FIFO Block Size
0=
Block size for the transmit FIFO data is 32 byte
1=
Block size for the transmit FIFO data is 16 byte
Note: A change of XFBS will take effect after a transmitter command (CMDR.XME,
CMDR.XRES, CMDR.XTF) has been written.
RFBS
Receive FIFO Block Size
00 =
32 byte
01 =
16 byte
10 =
8 byte
11 =
4 byte
Note: A change of RFBS will take effect after a receiver command (CMDR.RMC,
CMDR.RRES) has been written.
Data Sheet
152
2001-11-12
PEF 81902
Register Description
SRA
Store Receive Address
XCRC
0=
Receive Address is not stored in the RFIFO
1=
Receive Address is stored in the RFIFO
Transmit CRC
RCRC
0=
CRC is transmitted
1=
CRC is not transmitted
Receive CRC
ITF
0=
CRC is not stored in the RFIFO
1=
CRC is stored in the RFIFO
Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLCframes.
0=
idle (continuous ‘1’)
1=
flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ‘0’ for power down mode.
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ‘1’). Otherwise the D-channel on
the S/T-bus cannot be accessed.
4.4.9
TIMR - Timer Register
TIMR
read/write
Address:
24H
Value after reset: 00H
7
5
4
0
CNT
Data Sheet
VALUE
153
2001-11-12
PEF 81902
Register Description
CNT
CNT together with VALUE determines the time period T after which
a TIN interrupt (ISTA) will be generated in the normal case:
CNT=0...6: T = CNT x 2.048 sec + T1 with T1 = (VALUE+1) x 0.064
sec
CNT=7: T = T1 = (VALUE+1) x 0.064 sec (generated periodically)
The timer can be started by setting the STI-bit in CMDR and will be
stopped when a TIN interrupt is generated or the TIMR register is
written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration
of T = T1.
VALUE
Determines the time period T1
T1 = (VALUE + 1) × 0.064 sec
4.4.10
SAP1 - SAPI1 Register
SAP1
write
Address:
25H
Value after reset: FCH
7
0
SAPI1
SAPI1
0
MHA
SAPI1 value
Value of the programmable high address byte. In ISDN LADP protocol (Dchannel) this is the Service Access Point Identifier (SAPI) and for B-channel
applications it is the RAH value.
MHA
Data Sheet
Mask High Address
0=
The high address of an incoming frame is compared with SAP1,
SAP2 and SAPG.
1=
The high address of an incoming frame is compared with SAP1 and
SAPG.
SAP1 can be masked with SAP2. Bit positions of SAP1 are not
compared if they are set to ‘1’ in SAP2.
154
2001-11-12
PEF 81902
Register Description
4.4.11
SAP2 - SAPI2 Register
SAP2
write
Address:
26H
Value after reset: FCH
7
0
SAPI2
SAPI2
0
MLA
SAPI2 value
Value of the programmable high address byte. In ISDN LADP protocol (Dchannel) this is the Service Access Point Identifier (SAPI) and for B-channel
applications it is the RAL value.
MLA
Mask Low Address
4.4.12
0=
The TEI address of an incoming frame is compared with TEI1, TEI2
and TEIG.
1=
The TEI address of an incoming frame is compared with TEI1 and
TEIG.
TEI1 can be masked with TEI2. Bit positions of TEI1 are not compared
if they are set to ‘1’ in TEI2.
RBCL - Receive Frame Byte Count Low
RBCL
read
Address:
26H
Value after reset: 00H
7
0
RBC7
RBC0
RBC7-0
Receive Byte Count
Eight least significant bits of the total number of bytes in a received message
(see RBCH register).
Data Sheet
155
2001-11-12
PEF 81902
Register Description
4.4.13
RBCH - Receive Frame Byte Count High for D-Channel
RBCH
read
Address:
27H
Value after reset: 00H.
7
0
r(0)
OV
r(0)
r(0)
OV
RBC11
RBC8
Overflow
0=
Message shorter than (212 – 1) = 4095 bytes.
1=
Message longer than (212 – 1) = 4095 bytes.
RBC8-11 Receive Byte Count
Four most significant bits of the total number of bytes in a received message
(see RBCL register).
Note: Normally RBCH and RBCL should be read by the microcontroller after a RMEinterrupt, in order to determine the number of bytes to be read from the RFIFO,
and the total message length. The contents of the registers are valid only after a
RME or RPF interrupt, and remain so until the frame is acknowledged via the RMC
bit or RRES.
4.4.14
TEI1 - TEI1 Register
TEI1
write
Address:
27H
Value after reset: FFH
7
0
TEI1
Data Sheet
156
EA1
2001-11-12
PEF 81902
Register Description
TEI1
Terminal Endpoint Identifier
In all message transfer modes except for transparent modes 0, 1 and
extended transparent mode, TEI1 is used by the T-SMINTâIX for address
recognition. In the case of a two-byte address field, it contains the value of
the first programmable Terminal Endpoint Identifier according to the ISDN
LAPD-protocol.
EA1
Address Field Extension Bit
This bit is set to ‘1’ according to HDLC/LAPD.
4.4.15
TEI2 - TEI2 Register
TEI2
write
Address:
28H
Value after reset: FFH
7
0
TEI2
TEI2
EA2
Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and
extended transparent mode, TEI2 is used by the T-SMINTâIX for address
recognition. In the case of a two-byte address field, it contains the value of
the second programmable Terminal Endpoint Identifier according of the
ISDN LAPD-protocol.
EA2
Address Field Extension Bit
This bit is to be set to ‘1’ according to HDLC/LAPD.
4.4.16
RSTA - Receive Status Register
RSTA
read
Address:
28H
Value after reset: 0FH
Data Sheet
157
2001-11-12
PEF 81902
Register Description
7
0
VFR
VFR
RDO
CRC
RAB
SA1
SA0
C/R
TA
Valid Frame
Determines whether a valid frame has been received.
A frame is invalid when there is not a multiple of 8 bits between flag and
frame end (flag, abort).
RDO
CRC
RAB
0=
The frame is invalid
1=
The frame is valid
Receive Data Overflow
0=
No receive data overflow
1=
At least one byte of the frame has been lost, because it could not
be stored in RFIFO. As opposed the ISTAH.RFO a RDO indicates
that the beginning of a frame has been received but not all bytes
could be stored as the RFIFO was temporarily full.
CRC Check
0=
The CRC is incorrect
1=
The CRC is correct
Receive Message Aborted
0=
The receive message was not aborted
1=
The receive message was aborted by the remote station, i.e. a
sequence of seven 1’s was detected before a closing flag.
SA1-0
SAPI Address Identification
TA
TEI Address Identification
Data Sheet
158
2001-11-12
PEF 81902
Register Description
These bits are only relevant in modes with address comparison.
The result of the address comparison is given by SA1-0 and TA, as follows:
Address Match with
MDS2-0
SA1
SA0
TA
1st Byte
2nd Byte
010
(Non-Auto/8
Mode)
x
x
x
x
0
1
TEI2
TEI1
-
011
(Non-Auto/16
Mode)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
SAP2
SAP2
SAPG
SAPG
SAP1
SAP1
TEIG
TEI2
TEIG
TEI1 or TEI2
TEIG
TEI1
111
(Transparent
Mode 1)
0
0
1
0
1
0
x
x
x
SAP2
SAPG
SAP1
-
101
(Transparent
Mode 2)
-
-
0
1
-
TEIG
TEI1 or TEI2
1
1
x
reserved
Note: If SAP1 and SAP2 contain identical values, the combination SAP1,2-TEIG will
only be indicated by SAP1,0 = ’10’ (i.e. the value ’00’ will not occur in this case).
C/R
Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI
address).
Note: The contents of RSTA corresponds to the last received HDLC frame; it is
duplicated into RFIFO for every frame (last byte of frame).
4.4.17
TMH -Test Mode Register HDLC
TMH
read/write
Address:
29H
Value after reset: 00H
7
r(0)
Data Sheet
0
r(0)
r(0)
r(0)
159
r(0)
r(0)
r(0)
TLP
2001-11-12
PEF 81902
Register Description
TLP
Test Loop
0=
inactive
1=
The TX path of the HDLC controller is internally connected to its RX
path. Data coming from the IOM-2 will not be forwarded to the
HDLC controller.
Setting of TLP is only valid if IOM-2 is active.
Note: The bits7-1 have to be set to “0”.
4.4.18
CIR0 - Command/Indication Receive 0
CIR0
read
Address:
2EH
Value after reset: F3H
7
0
CODR0
CODR0
CIC0
CIC1
S/G
BAS
C/I0 Code Receive
Value of the received Command/Indication code. A C/I-code is loaded in
CODR0 only after being the same in two consecutive IOM-frames and the
previous code has been read from CIR0.
CIC0
CIC1
Data Sheet
C/I0 Code Change
0=
No change in the received Command/Indication code has been
recognized
1=
A change in the received Command/Indication code has been
recognized. This bit is set only when a new code is detected in two
consecutive IOM-frames. It is reset by a read of CIR0.
C/I1 Code Change
0=
No change in the received Command/Indication code has been
recognized
1=
A change in the received Command/Indication code in IOM-channel 1
has been recognized. This bit is set when a new code is detected in
one IOM-frame. It is reset by a read of CIR0.
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Register Description
S/G
Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel;
BAS
0=
Go
1=
Stop
Bus Access Status
Indicates the state of the TIC-bus:
0=
the T-SMINTâIX itself occupies the D- and C/I-channel
1=
another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code are made available in CIR0 at
the first and second read of that register.
4.4.19
CIX0 - Command/Indication Transmit 0
CIX0
write
Address:
2EH
Value after reset: FEH
7
0
CODX0
CODX0
TBA2
TBA1
TBA0
BAC
C/I0-Code Transmit
Code to be transmitted in the C/I-channel 0. The code is only transmitted if
the TIC bus is occupied, otherwise “1s” are transmitted.
TBA2-0
TIC Bus Address
Defines the individual address for the T-SMINTâIX on the IOM bus.
This address is used to access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the
IOM it should always be given the address value ‘7’.
BAC
Bus Access Control
Only valid if the TIC-bus feature is enabled (MODE:DIM2-0).
Data Sheet
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Register Description
0=
inactive
1=
The T-SMINTâIX will try to access the TIC-bus to occupy the C/Ichannel even if no D-channel frame has to be transmitted. It should
be reset when the access has been completed to grant a similar
access to other devices transmitting in that IOM-channel.
Note: Access is always granted by default to the T-SMINTâIX with TIC-Bus
Address (TBA2-0, CIX0 register) ‘7’, which has the lowest priority in a
bus configuration.
4.4.20
CIR1 - Command/Indication Receive 1
CIR1
read
Address:
2FH
Value after reset: FEH
7
0
CODR1
CICW
CODR1
C/I1-Code Receive
CICW
C/I-Channel Width
Contains the read back value from CIX1 register (see below)
CI1E
4.4.21
0=
4 bit C/I1 channel width
1=
6 bit C/I1 channel width
CI1E
C/I1-channel Interrupt Enable
Contains the read back value from CIX1 register (see below)
0=
Interrupt generation ISTA.CIC of CIR0.CIC1is masked
1=
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled
CIX1 - Command/Indication Transmit 1
CIX1
write
Address:
2FH
Value after reset: FEH
Data Sheet
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PEF 81902
Register Description
7
0
CODX1
CODX1
CICW
CI1E
C/I1-Code Transmit
Bits 5-0 of C/I-channel 1
CICW
C/I-Channel Width
0=
4 bit C/I1 channel width
1=
6 bit C/I1 channel width
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected,
the higher two bits are ignored for interrupt generation. However, in write
direction the full CODX1 code is transmitted, i.e. the host must write the
higher two bits to “1”.
CI1E
C/I1-channel Interrupt Enable
0=
Interrupt generation ISTA.CIC of CIR0.CIC1is masked
1=
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled
4.5
Detailed S-Transceiver Registers
4.5.1
S_CONF0 - S-Transceiver Configuration Register 0
S_ CONF0
read/write
Address:
30H
Value after reset: 40H
7
0
DIS_TR
DIS_TR
EN_
ICV
0
L1SW
0
EXLP
0
Disable Transceiver
0=
Data Sheet
BUS
All S-transceiver functions are enabled.
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Register Description
1=
BUS
EN_ICV
L1SW
EXLP
All S-transceiver functions are disabled and powered down (analog
and digital parts).
Point-to-Point / Bus Selection
0=
Adaptive Timing (Point-to-Point, extended passive bus).
1=
Fixed Timing (Short passive bus), directly derived from transmit
clock.
Enable Far End Code Violation
0=
normal operation.
1=
ICV enabled. The receipt of at least one illegal code violation within
one multi-frame according to ANSI T1.605 is indicated by the C/I
indication ‘1011’ (CVR) in two consecutive IOM frames.
Enable Layer 1 State Machine in Software
0=
Layer 1 state machine of the T-SMINTâIX is used.
1=
Layer 1 state machine is disabled. The functionality must be
realized in software.
The commands are written to register S_CMD and the status read
in the S_STA.
External Loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit
in the S_CMD register the loop is a
0=
internal loop next to the line pins
1=
external loop which has to be closed between SR1/SR2 and SX1/
SX2
Note: For the external loop the transmitter must be enabled (S_CONF2:DIS_TX = 0).
4.5.2
S_CONF2 - S-Transmitter Configuration Register 2
S_ CONF2
read/write
Address:
32H
Value after reset: 80H
Data Sheet
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PEF 81902
Register Description
7
0
DIS_TX
DIS_TX
0
0
0
0
0
0
0
Disable Line Driver
4.5.3
0=
Transmitter is enabled
1=
Transmitter is disabled
S_STA - S-Transceiver Status Register
S_ STA
read
Address:
33H
Value after reset: 00H
7
0
RINF
0
ICV
0
FSYN
0
LD
Important: This register is used only if the Layer 1 state machine of the device is disabled
(S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine
enabled, the signals from this register are automatically evaluated.
RINF
ICV
FSYN
Data Sheet
Receiver INFO
00 =
Received INFO 0 (no signal)
01 =
Received any signal except INFO 0 or INFO 3
10 =
reserved
11 =
Received INFO 3
Illegal Code Violation
0=
No illegal code violation is detected.
1=
Illegal code violation (ANSI T1.605) in data stream is detected.
Frame Synchronization State
0=
The S/T receiver is not synchronized.
1=
The S/T receiver has synchronized to the framing bit F.
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PEF 81902
Register Description
LD
Level Detection
4.5.4
0=
No receive signal has been detected on the line.
1=
Any receive signal has been detected on the line.
S_CMD - S-Transceiver Command Register
S_ CMD
read/write
Address:
34H
Value after reset: 08H
7
0
XINF
DPRIO
1
PD
LP_A
0
Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine
of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the
device layer 1 state machine enabled, the signals from this register are automatically
generated. DPRIO can also be written in intelligent NT mode.
XINF
DPRIO
PD
Transmit INFO
000 =
Transmit INFO 0
001 =
reserved
010 =
Transmit INFO 2
011 =
Transmit INFO 4
100 =
Send continuous pulses at 192 kbit/s alternating or 96 kHz
rectangular, respectively (TM2)
101 =
Send single pulses at 4 kbit/s with alternating polarity
corresponding to 2 kHz fundamental mode (TM1)
11x =
reserved
D-Channel Priority
0=
Priority class 1 for D channel access on IOM
1=
Priority class 2 for D channel access on IOM
Power Down
0=
Data Sheet
The transceiver is set to operational mode
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PEF 81902
Register Description
1=
LP_A
The transceiver is set to power down mode
Loop Analog
The setting of this bit corresponds to the C/I command ARL.
4.5.5
0=
Analog loop is open
1=
Analog loop is closed internally or externally according to the EXLP
bit in the S_CONF0 register
SQRR - S/Q-Channel Receive Register
SQRR
read
Address:
35H
Value after reset: 00H
7
0
MSYN
MSYN
MFEN
MFEN
0
0
SQR1
SQR2
SQR3
SQR4
Multi-frame Synchronization State
0=
The S/T receiver has not synchronized to the received FA and M
bits
1=
The S/T receiver has synchronized to the received FA and M bits
Multiframe Enable
Read-back of the MFEN bit of the SQXR register
SQR1-4
0=
S/T multiframe is disabled
1=
S/T multiframe is enabled
Received S/Q Bits
Received Q bits in frames 1, 6, 11 and 16
4.5.6
SQXR- S/Q-Channel Transmit Register
SQXR
write
Address:
35H
Value after reset: 00H
Data Sheet
167
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PEF 81902
Register Description
7
0
0
MFEN
MFEN
0
0
SQX1
SQX2
SQX3
SQX4
Multiframe Enable
Used to enable or disable the multiframe structure.
SQX1-4
0=
S/T multiframe is disabled
1=
S/T multiframe is enabled
Transmitted S/Q Bits
Transmitted S bits in frames 1, 6, 11 and 16
4.5.7
ISTAS - Interrupt Status Register S-Transceiver
ISTAS
read
Address:
38H
Value after reset: 00H
7
0
x
x
x
x
LD
RIC
SQC
SQW
These bits are set if an interrupt status occurs and an interrupt signal is activated if the
corresponding mask bit is set to “0”. If the mask bit is set to “1” no interrupt is generated,
however the interrupt status bit is set in ISTAS. RIC, SQC and SQW are cleared by
reading the corresponding source register S_STA, SQRR or writing SQXR,
respectively.
x
Reserved
LD
Level Detection
Data Sheet
0=
inactive
1=
Any receive signal has been detected on the line. This bit is set to
“1” (i.e. an interrupt is generated if not masked) as long as any
receive signal is detected on the line.
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PEF 81902
Register Description
RIC
Receiver INFO Change
SQC
inactive
1=
RIC is activated if one of the S_STA bits RINF or ICV has changed.
S/Q-Channel Change
SQW
1)
0=
0=
inactive
1=
A change in the received 4-bit Q-channel has been detected. The
new code can be read from the SQRx bits of registers SQRR within
the next multiframe1). This bit is reset by a read access to the
SQRR register.
S/Q-Channel Writable
0=
inactive
1=
The S channel data for the next multiframe is writable.
The register for the S bits to be transmitted has to be written within
the next multiframe. This bit is reset by writing register SQXR.
This timing signal is indicated with the start of every multiframe.
Data which is written right after SQW-indication will be transmitted
with the start of the following multiframe. Data which is written
before SQW-indication is transmitted in the multiframe which is
indicated by SQW.
SQW and SQC could be generated at the same time.
Register SQRR stays valid as long as no code change has been received.
4.5.8
MASKS - Mask S-Transceiver Interrupt
MASKS
read/write
Address:
39H
Value after reset: FFH
7
1
Bit 3..0
Data Sheet
0
1
1
1
LD
RIC
SQC
SQW
Mask bits
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Register Description
4.5.9
0=
The transceiver interrupts LD, RIC, SQC and SQW are enabled
1=
The transceiver interrupts LD, RIC, SQC and SQW are masked
S_MODE - S-Transceiver Mode
S_ MODE
read/write
Address:
3AH
Value after reset: 02H
7
0
0
DCH_
INH
MODE
Data Sheet
0
0
0
DCH_INH
MODE
D-Channel Inhibit
0=
inactive
1=
The S-transceiver blocks the access to the D-channel on S by
inverting the E-bits.
Mode Selection
000 =
reserved
001 =
reserved
010 =
NT (without D-channel handler)
011 =
LT-S (without D-channel handler)
110
Intelligent NT mode (with NT state machine and with D-channel
handler)
111
Intelligent NT mode (with LT-S state machine and with D-channel
handler)
100
reserved
101
reserved
170
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PEF 81902
Register Description
4.6
Interrupt and General Configuration Registers
4.6.1
ISTA - Interrupt Status Register
ISTA
read
Address:
3CH
Value after reset: 00H
7
0
U
U
ST
CIC
TIN
WOV
ST
TIN
WOV
S
MOS
HDLC
U-Transceiver Interrupt
0=
inactive
1=
An interrupt was generated by the U-transceiver. Read the ISTAU
register.
Synchronous Transfer
0=
inactive
1=
This interrupt enables the microcontroller to lock on to the IOM®-2
timing, for synchronous transfers.
C/I Channel Change
0=
inactive
1=
A change in C/I0 channel or C/I1 channel has been recognized.
The actual value can be read from CIR0 or CIR1.
Timer Interrupt
0=
inactive
1=
The internal timer and repeat counter has expired (see TIMR
register).
Watchdog Timer Overflow
0=
Data Sheet
CIC
inactive
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PEF 81902
Register Description
1=
S
Signals the expiration of the watchdog timer, which means that the
microcontroller has failed to set the watchdog timer control bits
WTC1 and WTC2 (MODE1 register) in the correct manner. A reset
out pulse on pin RSTO has been generated by the T-SMINTâIX.
S-Transceiver Interrupt
MOS
0=
inactive
1=
An interrupt was generated by the S-transceiver. Read the ISTAS
register.
MONITOR Status
HDLC
0=
inactive
1=
A change in the MONITOR Status Register (MOSR) has occurred.
HDLC Interrupt
0=
inactive
1=
An interrupt originated in the HDLC interrupt sources has been
recognized.
Note: A read of the ISTA register clears only the TIN and WOV interrupts. The other
interrupts are cleared by reading the corresponding status register.
4.6.2
MASK - Mask Register
MASK
write
Address:
3CH
Value after reset: FFH
7
0
U
Bit 7..0
Data Sheet
ST
CIC
TIN
WOV
S
MOS
HDLC
Mask bits
0=
Interrupt is not masked
1=
Interrupt is masked
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Register Description
Each interrupt source in the ISTA register can be selectively masked by setting the
corresponding bit in MASK to ‘1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
mask bit in MASK is active, but no interrupt is generated.
4.6.3
MODE1 - Mode1 Register
MODE1
read/write
Address:
3DH
Value after reset: 04H
7
0
MCLK
MCLK
CDS
WTC1
WTC2
CFS
RSS2
RSS1
Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output
depending on MODE1.CDS = ’0’ or ’1’ (Table Table 2.1.3).
CDS
WTC1, 2
MODE1.CDS = ’0’
MODE1.CDS = ’1’
00 =
3.84 MHz
7.68 MHz
01 =
0.96 MHz
1.92 MHz
10 =
7.68 MHz
15.36 MHz
11 =
disabled
disabled
Clock Divider Selection
0=
The 15.36 MHz oscillator clock divided by two is input to the MCLK
prescaler
1=
The 15.36 MHz oscillator clock is input to the MCLK prescaler.
Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ‘11’) the
watchdog timer is started. During every time period of 128 ms the
microcontroller has to program the WTC1 and WTC2 bit in the following
sequence (Chapter 2.2):
10
Data Sheet
first step
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PEF 81902
Register Description
01
second step
to reset and restart the watchdog timer.
If not, the timer expires and a WOV-interrupt (ISTA Register) together with
a reset out pulse on pin RSTO is generated.
The watchdog timer runs only when the internal IOM®-2 clocks are active,
i.e. the watchdog timer is dead when bit CFS = 1 and the U and Stransceivers are in state power down.
CFS
Configuration Select
RSS2,
RSS1
0=
The IOM®-2 interface clock and frame signals are always active,
“Deactivated State” of the U-transceiver and the S-transceiver
included.
1=
The IOM®-2 interface clocks and frame signals are inactive in the
“Deactivated State” of the U-transceiver and the S-transceiver.
Reset Source Selection 2,1
The T-SMINTâIX reset sources can be selected according to the table
below.
00 =
C/I Code Change
Watchdog Timer
POR/UVD and RST
--
--
x
01 =
4.6.4
RSTO disabled (high impedance)
10 =
x
--
x
11 =
--
x
x
MODE2 - Mode2 Register
MODE2
read/write
Address:
3EH
Value after reset: 00H
7
0
LED2
LED2,1
LEDC
0
0
0
AMOD
PPSDX
LED Control on pin ACT
00 =
Data Sheet
LED1
High
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2001-11-12
PEF 81902
Register Description
01 =
flashing at 2 Hz (1 : 1)*
10 =
flashing at 1 Hz (3 : 1)*
11 =
Low
LEDC
LED Control Enable
AMOD
0=
LED is controlled by the state machines as defined in Table 3.
1=
LED is controlled via bits LED2,1.
Address Mode
Selects between direct and indirect register access of the parallel
microcontroller interface.
PPSDX
0=
Indirect address mode is selected. The address line A0 is used to
select between address (A0 = ‘0’) and data (A0 = ‘1’) register
1=
Direct address mode is selected. The address is applied to the
address bus (A0-A6)
Push/Pull Output for SDX
4.6.5
0=
The SDX pin has open drain characteristic
1=
The SDX pin has push/pull characteristic
ID - Identification Register
ID
read
Address:
3FH
Value after reset: 20H
7
0
DESIGN
0
0
DESIGN
Design Number
The design number (DESIGN) allows to identify different hardware
designs1) of the T-SMINTâIX by software.
100000: Version 1.1
Data Sheet
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PEF 81902
Register Description
1)
Distinction of different firmware versions is also possible by reading register (7D)H in the address space of the
U-transceiver (see Chapter 4.9.8).
4.6.6
SRES - Software Reset Register
SRES
write
Address:
3FH
Value after reset: 00H
7
0
0
RES_xx
0
RES_
CI/TIC
0
RES_
HDLC
0
RES_S
RES_U
Reset_xx
0=
Deactivates the reset of the functional block xx
1=
Activates the reset of the functional block xx.
The reset state is activated as long as the bit is set to ‘1’
4.7
Detailed IOM®-2 Handler Registers
4.7.1
CDAxy - Controller Data Access Register xy
These registers are used for microcontroller access to the IOM®-2 timeslots as well as
for timeslot manipulations. (e.g. loops, shifts, ... see also “Controller Data Access
(CDA)” on Page 30).
CDAxy
read/write
Address: 40-43H
7
0
Controller Data Access Register
Data register CDAxy which can be accessed by the controller.
Register
Value after Reset
Register Address
CDA10
FFH
40H
CDA11
FFH
41H
Data Sheet
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2001-11-12
PEF 81902
Register Description
CDA20
FFH
42H
CDA21
FFH
43H
4.7.2
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
XXX_TSDPxy
read/write
Address: 44-4DH
7
0
DPS
0
0
0
TSS
Register
Value after Reset
Register Address
CDA_TSDP10
00H (= output on B1-DD)
44H
CDA_TSDP11
01H (= output on B2-DD)
45H
CDA_TSDP20
80H (= output on B1-DU)
46H
CDA_TSDP21
81H (= output on B2-DU)
47H
reserved
48-4BH
S_TSDP_B1
84H (= output on TS4-DU)
4CH
S_TSDP_B2
85H (= output on TS5-DU)
4DH
This register determines the time slots and the data ports on the IOM®-2 Interface for the
data channels xy of the functional units XXX (Controller Data Access (CDA) and Stransceiver (S)).
Note: The U-transceiver is always in IOM-2 channel 0.
DPS
Data Port Selection
0=
The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1=
The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
CDAx_CR.SWAP bit. If SWAP = ‘0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ‘1’ the input from CDAx0 is vice
versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to
the output setting of CDAx0.
Data Sheet
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2001-11-12
PEF 81902
Register Description
TSS
Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM®-2 interface for the
data channels.
4.7.3
CDAx_CR - Control Register Controller Data Access CH1x
CDAx_CR
read/write
Address: 4E-4FH
7
0
0
0
EN_TBM
EN_I1
EN_I0
Register
Value after Reset Register Address
CDA1_CR
00H
4EH
CDA2_CR
00H
4FH
EN_O1
EN_O0
SWAP
EN_TBM Enable TIC Bus Monitoring
EN_I1,
EN_I0
EN_O1,
EN_O0
Data Sheet
0=
The TIC bus monitoring is disabled
1=
The TIC bus monitoring with the CDAx0 register is enabled. The
TSDPx0 register must be set to 08H for monitoring from DU, or 88H
for monitoring from DD.
Enable Input CDAx1, CDAx0
0=
The input of the CDAx1, CDAx0 register is disabled
1=
The input of the CDAx1, CDAx0 register is enabled
Enable Output CDAx1, CDAx0
0=
The output of the CDAx1, CDAx0 register is disabled
1=
The output of the CDAx1, CDAx0 register is enabled
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Register Description
SWAP
Swap Inputs
4.7.4
0=
The time slot and data port for the input of the CDAxy register is
defined by its own TSDPxy register. The data port for the CDAxy
input is vice versa to the output setting for CDAxy.
1=
The input (time slot and data port) of the CDAx0 is defined by the
TSDP register of CDAx1 and the input of CDAx1 is defined by the
TSDP register of CDAx0. The data port for the CDAx0 input is vice
versa to the output setting for CDAx1. The data port for the CDAx1
input is vice versa to the output setting for CDAx0. The input
definition for time slot and data port CDAx0 are thus swapped to
CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by
the SWAP bit.
S_CR - Control Register S-Transceiver Data
S_CR
read/write
Address:
51H
Value after reset: FFH
7
0
1
CI_CS
CI_CS
EN_D
EN_B2R EN_B1R EN_B2X EN_B1X
D_CS
C/I Channel Selection
This bit is used to select the IOM channel to which the S-transceiver C/Ichannel is related to.
EN_D
EN_B2R
0=
C/I-channel in IOM-channel 0
1=
C/I-channel in IOM-channel 1
Enable Transceiver D-Channel Data
0=
The corresponding data path to the transceiver is disabled
1=
The corresponding data path to the transceiver is enabled.
Enable Transceiver B2 Receive Data (transmitter receives from IOM)
0=
Data Sheet
The corresponding data path to the transceiver is disabled
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Register Description
1=
EN_B1R
The corresponding data path to the transceiver is enabled.
Enable Transceiver B1 Receive Data (transmitter receives from IOM)
EN_B2X
0=
The corresponding data path to the transceiver is disabled
1=
The corresponding data path to the transceiver is enabled.
Enable Transceiver B2 Transmit Data (transmitter transmits to IOM)
EN_B1X
0=
The corresponding data path to the transceiver is disabled
1=
The corresponding data path to the transceiver is enabled.
Enable Transceiver B1 Transmit Data (transmitter transmits to IOM)
0=
The corresponding data path to the transceiver is disabled
1=
The corresponding data path to the transceiver is enabled.
These bits are used to individually enable/disable the D-channel and the
receive/transmit paths for the B-channels for the S-transceiver.
D_CS
D Channel Selection
This bit is used to select the IOM channel to which the S-transceiver Dchannel is related to.
4.7.5
0=
D-channel in IOM-channel 0
1=
D-channel in IOM-channel 1
HCI_CR - Control Register for HDLC and CI1 Data
HCI_CR
read/write
Address:
52H
Value after reset: 04H
7
0
DPS_CI1 EN_CI1
EN_D
EN_B2H EN_B1H DPS_H
HCS
DPS_CI1 Data Port Selection CI1 Handler
Data Sheet
0=
The CI1 data is output on DD and input from DU
1=
The CI1 data is output on DU and input from DD
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Register Description
EN_CI1
Enable CI1 Handler
0=
CI1 data access is disabled
1=
CI1 data access is enabled
Note: The timeslot for the C/I1 handler cannot be programmed but is fixed
to IOM channel 1.
EN_D
EN_B2H
EN_B1H
Enable D-timeslot for HDLC controller
0=
The HDLC controller does not access timeslot data D
1=
The HDLC controller does access timeslot data D
Enable B2-timeslot for HDLC controller
0=
The HDLC controller does not access timeslot data B2
1=
The HDLC controller does access timeslot data B2
Enable B1-timeslot for HDLC controller
0=
The HDLC controller does not access timeslot data B1 respectively
1=
The HDLC controller does access timeslot data B1
The bits EN_D, EN_B2H and EN_B1H are used to select the timeslot length for the Dchannel HDLC controller access as it is capable to access not only the D-channel
timeslot. The host can individually enable two 8-bit timeslots B1- and B2-channel, i.e.
the first and second octett, (EN_B1H, EN_B2H) and one 2-bit timeslot D-channel
(EN_D) on IOM-2. The position is selected via HCS.
DPS_H
HCS
Data Port Selection HDLC
0=
Transmit on DD, receive on DU
1=
Transmit on DU, receive on DD
HDLC Channel Selection
These two bits determine the IOM®-2 channel of the HDLC controller. The
HDLC controller will read and write HDLC data into the selected B1, B2 and
D channel timeslots of the selected IOM®-2 channel.
Data Sheet
00 =
The HDLC data is read and output on IOM-channel 0
01 =
The HDLC data is read and output on IOM-channel 1
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Register Description
1)
10 =
The HDLC data is read and output on IOM-channel 21)
11 =
Not defined
If the TIC-bus is enabled, then an HDLC access in IOM-channel 2 is possible only to the B channels.
4.7.6
MON_CR - Control Register Monitor Data
MON_CR
read/write
Address:
53H
Value after reset: 40H
7
0
DPS
DPS
EN_MON
0
0
0
0
MCS
Data Port Selection
0=
The Monitor data is output on DD and input from DU
1=
The Monitor data is output on DU and input from DD
EN_MON Enable Output
MCS
0=
The Monitor data input and output is disabled
1=
The Monitor data input and output is enabled
MONITOR Channel Selection
00 = The MONITOR data is output on MON0
01 = The MONITOR data is output on MON1
10 = The MONITOR data is output on MON2
11 = Not defined
4.7.7
SDS1_CR - Control Register Serial Data Strobe 1
SDS1_CR
read/write
Address:
54H
Value after reset: 00H
Data Sheet
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Register Description
7
0
ENS_
TSS
ENS_
TSS+1
ENS_
TSS+3
0
TSS
This register is used to select position and length of the strobe signal 1. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
ENS_
TSS
ENS_
TSS+1
ENS_
TSS+3
TSS
Enable Serial Data Strobe of timeslot TSS
0=
The serial data strobe signal SDS1 is inactive during TSS
1=
The serial data strobe signal SDS1 is active during TSS
Enable Serial Data Strobe of timeslot TSS+1
0=
The serial data strobe signal SDS1 is inactive during TSS+1
1=
The serial data strobe signal SDS1 is active during TSS+1
Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0=
The serial data strobe signal SDS1 is inactive during the D-channel
(bit7, 6) of TSS+3
1=
The serial data strobe signal SDS1 is active during the D-channel
(bit7, 6) of TSS+3
Timeslot Selection
Selects one of 12 timeslots on the IOM®-2 interface (with respect to FSC)
during which SDS1 is active high. The data strobe signal allows standard
data devices to access a programmable channel.
4.7.8
SDS2_CR - Control Register Serial Data Strobe 2
SDS2_CR
read/write
Address:
55H
Value after reset: 00H
Data Sheet
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Register Description
7
0
ENS_
TSS
ENS_
TSS+1
ENS_
TSS+3
0
TSS
This register is used to select position and length of the strobe signal 2. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
ENS_
TSS
ENS_
TSS+1
ENS_
TSS+3
TSS
Enable Serial Data Strobe of timeslot TSS
0=
The serial data strobe signal SDS2 is inactive during TSS
1=
The serial data strobe signal SDS2 is active during TSS
Enable Serial Data Strobe of timeslot TSS+1
0=
The serial data strobe signal SDS2 is inactive during TSS+1
1=
The serial data strobe signal SDS2 is active during TSS+1
Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0=
The serial data strobe signal SDS2 is inactive during the D-channel
(bit7, 6) of TSS+3
1=
The serial data strobe signal SDS2 is active during the D-channel
(bit7, 6) of TSS+3
Timeslot Selection
Selects one of 12 timeslots on the IOM®-2 interface (with respect to FSC)
during which SDS2 is active high. The data strobe signal allows standard
data devices to access a programmable channel.
4.7.9
IOM_CR - Control Register IOM Data
IOM_CR
read/write
Address:
56H
Value after reset: 08H
Data Sheet
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Register Description
7
0
SPU
SPU
TIC_DIS
EN_BCL
DIS_OD
0
0
TIC_DIS EN_BCL
0
DIS_OD DIS_IOM
Software Power UP
0=
The DU line is normally used for transmitting data.
1=
Setting this bit to ‘1’ will pull the DU line to low. This will enforce the
T-SMINTâI and other connected layer 1 devices to deliver IOMclocking.
TIC Bus Disable
0=
The last octet of the last IOM time slot (TS 11) is used as TIC bus.
1=
The TIC bus is disabled. The last octet of the last IOM time slot
(TS 11) can be used like any other time slot. This means that the
timeslots TIC, A/B, S/G and BAC are not available any more.
Enable Bit Clock BCL
0=
The BCL clock is disabled (output is high impedant)
1=
The BCL clock is enabled
Disable Open Drain
0=
IOM outputs are open drain driver
1=
IOM outputs are push pull driver
DIS_IOM Disable IOM
DIS_IOM should be set to ‘1’ if external devices connected to the IOM
interface should be “disconnected” e.g. for power saving purposes.
However, the T-SMINTâIX internal operation is independent of the
DIS_IOM bit.
Data Sheet
0=
The IOM interface is enabled
1=
The IOM interface is disabled (FSC, DCL, clock outputs have high
impedance; DU, DD data line inputs are switched off and outputs
are high impedant)
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Register Description
4.7.10
MCDA - Monitoring CDA Bits
MCDA
read
Address:
57H
Value after reset: FFH
7
0
MCDA21
Bit7
MCDA20
Bit6
Bit7
MCDA11
Bit6
Bit7
Bit6
MCDA10
Bit7
Bit6
MCDAxy Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the
“Echo bits” on the TIC bus with the same register.
4.7.11
STI - Synchronous Transfer Interrupt
STI
read
Address:
58H
Value after reset: 00H
7
0
STOV21 STOV20 STOV11 STOV10
STI21
STI20
STI11
STI10
For all interrupts in the STI register the following logical states are applied
STOVxy
0=
Interrupt has not occurred
1=
Interrupt has occurred
Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when
the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI
register. This must be one (for DPS = ‘0’) or zero (for DPS = ‘1’) BCL clock
cycles before the time slot which is selected for the STOV.
Data Sheet
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Register Description
STIxy
Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the
Synchronous Transfer Interrupt STIxy is generated two (for DPS = ‘0’) or
one (for DPS = ‘1’) BCL clock cycles after the selected time slot
(TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
4.7.12
ASTI - Acknowledge Synchronous Transfer Interrupt
ASTI
write
Address:
58H
Value after reset: 00H
7
0
0
ACKxy
0
0
0
ACK21
ACK20
ACK11
ACK10
Acknowledge Synchronous Transfer Interrupt
After a STIxy interrupt the microcontroller has to acknowledge the interrupt
by setting the corresponding ACKxy bit.
4.7.13
0=
No activity is initiated
1=
Sets the acknowledge bit ACKxy for a STIxy interrupt
MSTI - Mask Synchronous Transfer Interrupt
MSTI
read/write
Address:
59H
Value after reset: FFH
7
0
STOV21 STOV20 STOV11 STOV10
STI21
STI20
STI11
STI10
For the MSTI register the following logical states are applied:
0=
Data Sheet
Interrupt is not masked
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Register Description
1=
STOVxy
Interrupt is masked
Mask Synchronous Transfer Overflow xy
Mask bits for the corresponding STOVxy interrupt bits.
STIxy
Synchronous Transfer Interrupt xy
Mask bits for the corresponding STIxy interrupt bits.
4.8
Detailed MONITOR Handler Registers
4.8.1
MOR - MONITOR Receive Channel
MOR
read
Address:
5CH
Value after reset: FFH
7
0
Contains the MONITOR data received in the IOM®-2 MONITOR channel according to
the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by
setting the monitor channel select bit MON_CR.MCS.
4.8.2
MOX - MONITOR Transmit Channel
MOX
write
Address:
5CH
Value after reset: FFH
7
0
Contains the MONITOR data to be transmitted in IOM®-2 MONITOR channel according
to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by
setting the monitor channel select bit MON_CR.MCS
Data Sheet
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Register Description
4.8.3
MOSR - MONITOR Interrupt Status Register
MOSR
read
Address:
5DH
Value after reset: 00H
7
0
MDR
MDR
MER
MDA
MAB
0
0
0
0
MONITOR channel Data Received
MER
0=
inactive
1=
MONITOR channel Data Received
MONITOR channel End of Reception
MDA
0=
inactive
1=
MONITOR channel End of Reception
MONITOR channel Data Acknowledged
The remote end has acknowledged the MONITOR byte being transmitted.
MAB
0=
inactive
1=
MONITOR channel Data Acknowledged
MONITOR channel Data Abort
4.8.4
0=
inactive
1=
MONITOR channel Data Abort
MOCR - MONITOR Control Register
MOCR
read/write
Address:
5EH
Value after reset: 00H
7
MRE
Data Sheet
0
MRC
MIE
MXC
189
0
0
0
0
2001-11-12
PEF 81902
Register Description
MRE
MONITOR Receive Interrupt Enable
MRC
0=
MONITOR interrupt status MDR generation is masked.
1=
MONITOR interrupt status MDR generation is enabled.
MR Bit Control
Determines the value of the MR bit:
MIE
0=
MR is always ‘1’. In addition, the MDR interrupt is blocked, except
for the first byte of a packet (if MRE = 1).
1=
MR is internally controlled by the T-SMINTâIX according to
MONITOR channel protocol. In addition, the MDR interrupt is
enabled for all received bytes according to the MONITOR channel
protocol (if MRE = 1).
MONITOR Interrupt Enable
MXC
0=
MONITOR interrupt status MER, MDA, MAB generation is masked
1=
MONITOR interrupt status MER, MDA, MAB generation is enabled
MX Bit Control
Determines the value of the MX bit:
4.8.5
0=
The MX bit is always ‘1’.
1=
The MX bit is internally controlled by the T-SMINTâIX according to
MONITOR channel protocol.
MSTA - MONITOR Status Register
MSTA
read
Address:
5FH
Value after reset: 00H
7
0
0
MAC
0
0
0
MAC
0
TOUT
MONITOR Transmit Channel Active
0=
Data Sheet
0
No data transmission in the MONITOR channel
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Register Description
1=
TOUT
The data transmission in the MONITOR channel is in progress.
Time-Out
Read-back value of the TOUT bit
4.8.6
0=
The monitor time-out function is disabled
1=
The monitor time-out function is enabled
MCONF - MONITOR Configuration Register
MCONF
write
Address:
5FH
Value after reset: 00H
7
0
0
TOUT
0
0
0
0
0
0
TOUT
Time-Out
0=
The monitor time-out function is disabled
1=
The monitor time-out function is enabled
4.9
Detailed U-Transceiver Registers
4.9.1
OPMODE - Operation Mode Register
The Operation Mode register determines the operating mode of the U-transceiver.
read*)/write
OPMODE
Address:
60H
Reset value: 00H
7
6
5
4
3
2
1
0
0
UCI
0
0
0
0
0
0
Data Sheet
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Register Description
UCI
Enable/Disable µP-control of C/I codes
4.9.2
0=
µP control disabled - C/I codes are exchanged via IOM®-2
Read access to register UCIR by the µP is still possible
1=
µP control enabled - C/I codes are exchanged via UCIR and UCIW
registers
In this case, the according C/I-channel on IOM®-2 is idle ‘1111‘
UCIR - C/I Code Read Register
Via the U-transceiver C/I code Read register a microcontroller can access the C/I code
that is output from the state machine.
UCIR
read
Address:
6DH
Reset value: 00H
7
6
5
4
0
0
0
0
4.9.3
3
2
1
0
C/I code output
UCIW - C/I Code Write Register
The U-transceiver C/I code Write register allows a microcontroller to control the state of
the U-transceiver. To enable this function bit UCI in register OPMODE must be set to ’1’
before.
UCIW
write
Address:
6EH
Reset value: 01H
7
6
5
4
0
0
0
0
4.9.4
3
2
1
0
C/I code input
LOOP - Loopback Register
The Loop register controls local digital loopbacks of the U-transceiver.
Data Sheet
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Register Description
read*)/write
LOOP
Address:
70H
Reset value: 08H
7
6
5
4
3
2
1
0
0
0
TRAN
S
U/IOM
1
LBBD
LB2
LB1
TRANS
U/IOM®
LBBD
LB2
Data Sheet
Transparent/ Non-Transparent Loopback
In transparent mode data is both passed on and looped back, whereas in
non-transparent mode data is not forwarded but substituted by 1s (idle
code) and just looped back
0=
transparent mode
1=
non-transparent mode
’1’s are sent on the IOM®-2 interface in the corresponding time-slot
Close LBBD, LB2, LB1 towards U or towards IOM®
Switch that selects whether loopback LB1, LB2 or LBBD is closed towards
U or towards IOM®-2
the setting affects all test loops, LBBD, LB2 and LB1
an individual selection for LBBD, LB2, LB1 is not possible
0=
LB1, LB2, LBBD loops are closed towards IOM®
1=
LB1, LB2, LBBD loops are closed towards U
Close complete loop (B1, B2, D) near the system interface
– the direction towards which the loop is closed is determined by bit U/IOM®
– the state machine has to be in state ’Transparent’ first (e.g. by C/I = DT)
before data is output on the U-interface
0=
complete loopback open
1=
complete loopback closed
Close loop B2 near the system interface
– the direction towards which the loop is closed is determined by bit U/IOM®
– the state machine has to be in state ’Transparent’ first (e.g. by C/I = DT)
before data is output on the U-interface
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Register Description
LB1
0=
loopback B2 open
1=
loopback B2 closed
Close loop B1 near the system interface
– the direction towards which the loop is closed is determined by bit U/IOM®
– the state machine has to be in state ’Transparent’ first (e.g. by C/I = DT)
before data is output on the U-interface
4.9.5
0=
loopback B1 open
1=
loopback B1 closed
RDS - Block Error Counter Register
see Chapter 2.4.4.2.
RDS
read
Address:
72H
Reset value: 00H
7
6
5
4
3
2
1
0
Block Error Counter Value
4.9.6
ISTAU - Interrupt Status Register U-Interface
The Interrupt Status register U-interface generates an interrupt for the unmasked
interrupt flags. Refer to Chapter 2.4.8 for details on masking and clearing of interrupt
flags.
ISTAU
read
Address:
7AH
Reset value: 00H
7
6
5
4
3
2
1
0
0
CI
RDS
0
0
0
0
1 ms
CI
Data Sheet
C/I code indication
the CI interrupt is generated independently on OPMODE.UCI
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Register Description
RDS
0=
inactive
1=
CI code change has occurred
Code violation occurred
1 ms
0=
inactive
1=
code violation has occurred
Start of a new frame on the U-interface
useful for synchronization of register accesses by an external µC
4.9.7
0=
inactive
1=
signals the start of a new frame on the U-interface
MASKU - Mask Register U-Interface
The Interrupt Mask register U-Interface selectively masks each interrupt source in the
ISTAU register by setting the corresponding bit to ’1’.
read*)/write
MASKU
Address:
7BH
Reset Value: FFH
7
6
5
4
3
2
1
0
1
CI
RDS
1
1
1
1
1 ms
Bit 0..7
4.9.8
Mask bits
0=
interrupt active
1=
interrupt masked
FW_VERSION
FW_VERSION Register contains the Firmware Version number
Data Sheet
195
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PEF 81902
Register Description
FW_VERSION
read
Address:
7DH
Reset value: 3EH
7
6
5
4
3
2
1
0
Firmware Version Number
Data Sheet
196
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PEF 81902
Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
•
Parameter
Symbol Limit Values
Unit
Ambient temperature under bias
TA
TSTG
-40 to 85
°C
– 65 to 150
°C
Maximum Voltage on VDD
4.2
V
V
ground
-0.3 to VDD + 3.3
(max. < 5.5)
Storage temperature
VDD
Maximum Voltage on any pin with respect to VS
ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV
Note: Stress above those listed here may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
Line Overload Protection
The T-SMINTâIX is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993
(CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA /
JESD78. From these tests the following max. input currents are derived (Table 37):
•
Table 37
Maximum Input Currents
Test
Pulse Width
Current
Remarks
ESD
100 ns
1.3 A
3 repetitions
Latch-up
5 ms
+/-200 mA
2 repetitions, respectively
DC
--
10 mA
Data Sheet
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Electrical Characteristics
5.2
DC Characteristics
•
VDD/VDDA = 3.3 V +/- 5% ; VSS/VSSA = 0 V; TA = -40 to 85 °C
Digital
Pins
Parameter
All
Input low voltage
Symbol Limit Values
Unit
Test
Condition
min.
max.
VIL
-0.3
0.8
V
Input high voltage
VIH
2.0
5.25
V
All except
DD/DU
ACT,
MCLK
Output low voltage
VOL1
0.45
V
IOL1 = 3.0 mA
Output high voltage
VOH1
V
IOH1 = 3.0 mA
DD/DU
ACT,
MCLK
Output low voltage
VOL2
V
IOL2 = 4.0 mA
Output high voltage
(DD/DU push-pull)
VOH2
V
IOH2 = 4.0 mA
All
Input leakage current
ILI
10
µA
0 V ≤ VIN ≤ VDD
Output leakage current ILO
10
µA
0 V ≤ VIN ≤ VDD
Input leakage current
30
µA
0 V ≤ VIN ≤ VD
2.4
0.45
2.4
Analog
Pins
AIN, BIN
ILI
D
Table 38
Pin
S-Transceiver Characteristics
Parameter
Symbol Limit Values
min.
typ.
max.
2.31
SX1,2
Absolute value of
output pulse
amplitude
(VSX2 - VSX1)
VX
2.03
2.2
SX1,2
S-Transmitter
output impedance
ZX
10
34
SR1,2 S-Receiver input
impedance
1)
Unit
Test
Condition
V
RL = 50 Ω
kΩ
see 1)
see 2)3)
0
ZR
10
100
kΩ
Ω
VDD = 3.3 V
VDD = 0 V
Requirement ITU-T I.430, chapter 8.5.1.1a): ’At all times except when transmitting a binary zero, the output
impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template
in Figure 11. The requirement is applicable with an applied sinusoidal voltage of 100 mV (r.m.s value)’
Data Sheet
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PEF 81902
Electrical Characteristics
2)
Requirement ITU-T I.430, chapter 8.5.1.1b): ’When transmitting a binary zero, the output impedance shall be
> 20 Ω.’: Must be met by external circuitry.
3)
Requirement ITU-T I.430, chapter 8.5.1.1b), Note: ’The output impedance limit shall apply for a nominal load
impedance (resistive) of 50 Ω. The output impedance for each nominal load shall be defined by determining
the peak pulse amplitude for loads equal to the nominal value +/- 10%. The peak amplitude shall be defined
as the the amplitude at the midpoint of a pulse. The limitation applies for pulses of both polarities.’
Table 39
U-Transceiver Characteristics
Limit Values
min.
typ.
Unit
max.
Receive Path
Signal / (noise + total harmonic distortion) 1) 65
dB
50
55
%2)
23
mV
peak
DC-level at AD-output
45
Threshold of level detect
(measured between AIN and BIN with
respect to zero signal)
10
Input impedance AIN/BIN
80
kΩ
Signal / (noise + total harmonic distortion) 3) 70
dB
Transmit Path
Common mode DC-level
1.61
1.65
1.69
V
35
mV
2.5
2.58
V
0.8
3
1.5
6
Ω
Ω
Offset between AOUT and BOUT
Absolute peak voltage for a single +3 or -3
pulse measured between AOUT and
BOUT4)
2.42
Output impedance AOUT/BOUT:
Power-up
Power-down
1)
Test conditions: 1.4 Vpp differential sine wave as input on AIN/BIN with long range (low, critical range).
2)
The percentage of the "1 "-values in the PDM-signal.
3)
Interpretation and test conditions: The sum of noise and total harmonic distortion, weighted with a low pass
filter 0 to 80 kHz, is at least 70 dB below the signal for an evenly distributed but otherwise random sequence
of +3, +1, -1, -3.
4)
The signal amplitude measured over a period of 1 min. varies less than 1%.
Data Sheet
199
2001-11-12
PEF 81902
Electrical Characteristics
5.3
Capacitances
TA = 25 °C, 3.3 V ± 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded.
•
Table 40
Pin Capacitances
Parameter
Symbol
Limit Values Unit
min.
max.
Digital pads:
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
Analog pads:
Load Capacitance
CL
3
pF
5.4
Remarks
pin AIN, BIN
Power Consumption
•
Power Consumption
VDD=3.3 V, VSS=0 V, Inputs at VSS/VDD, no LED connected, 50% bin. zeros, no output
loads except SX1,2 (50 Ω1))
Parameter
Limit Values
min.
Operational
U and S enabled, IOMâ-2 off
Power Down
1)
typ.
Unit Test Condition
max.
185
mW
U: ETSI loop 1 (0 m)
165
mW
U: ETSI Loop 2.(typical
line)
15
mW
50 Ω (2 x TR) on the S-bus.
5.5
Supply Voltages
VDDD = + Vdd ± 5%
VDDA = + Vdd ± 5%
The maximum sinusoidal ripple on VDD is specified in the following figure:
Data Sheet
200
2001-11-12
PEF 81902
Electrical Characteristics
•
mV
(peak)
200
Supply Voltage Ripple
100
10
60
80
100
Frequency / kHz
Frequency Ripple
ITD04269.vsd
Figure 69
Data Sheet
Maximum Sinusoidal Ripple on Supply Voltage
201
2001-11-12
PEF 81902
Electrical Characteristics
5.6
AC Characteristics
TA = -40 to 85 °C, VDD = 3.3 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in Figure 70.
•
2.4
2.0
2.0
Device
Under
Test
Test Points
0.8
0.8
0.45
CLoad=50 pF
ITS00621.vsd
Figure 70
Input/Output Waveform for AC Tests
Parameter
All Output Pins
Symbol
Limit values
Min
Unit
Max
Fall time
30
ns
Rise time
30
ns
Data Sheet
202
2001-11-12
PEF 81902
Electrical Characteristics
5.6.1
IOM®-2 Interface
•
DCL
t4
DU/DD
(Input)
t5
Data valid
t7
t6
DU/DD
(Output)
last bit
first bit
t8
DU/DD
(Output)
bit n
bit n+1
t18
SDS1,2
IOM-Timing.vsd
Figure 71
IOM®-2 Interface - Bit Synchronization Timing
•
t9
FSC
t10
DCL
t2
t3
t1
BCL
t11
t12
t13
t14
Figure 72
Data Sheet
IOM®-2 Interface - Frame Synchronization Timing
203
2001-11-12
PEF 81902
Electrical Characteristics
•
Parameter
IOM®-2 Interface
Symbol
DCL period
Limit values
Unit
Min
Typ
Max
t1
565
651
735
ns
DCL high
t2
200
310
420
ns
DCL low
t3
200
310
420
ns
Input data setup
t4
20
ns
Input data hold
t5
20
ns
Output data from high impedance to t6
active
(FSC high or other than first timeslot)
100
ns
Output data from active to high
impedance
t7
100
ns
Output data delay from clock
t8
80
ns
FSC high
t9
FSC advance to DCL
t10
65
130
195
ns
BCL high
t11
565
651
735
ns
BCL low
t12
565
651
735
ns
BCL period
t13
1130
1302
1470
ns
FSC advance to BCL
t14
65
130
195
ns
DCL, FSC rise/fall
t15
30
ns
Data out fall (CL = 50 pF, R = 2 kΩ to t16
VDD, open drain)
200
ns
Data out rise/fall
(CL = 50 pF, tristate)
t17
150
ns
Strobe Signal Delay
t18
120
ns
50% of
FSC
cycle
time
ns
Note: At the start and end of a reset period, a frame jump may occur. This results in a
DCL, BCL and FSC high time of min. 130 ns after this specific event.
Data Sheet
204
2001-11-12
PEF 81902
Electrical Characteristics
5.6.2
Serial µP Interface
•
t1
t4
t5
t2
t3
CS
t11
SCLK
t6
t7
SDR
t9
t8
SDX
t10
SCI_timing.vsd
Figure 73
Serial Control Interface
•
Parameter
SCI Interface
Symbol
SCLK cycle time
t1
200
ns
SCLK high time
t2
80
ns
SCLK low time
t3
80
ns
CS setup time
t4
20
ns
CS hold time
t5
10
ns
SDR setup time
t6
15
ns
SDR hold time
t7
15
ns
SDX data out delay
t8
60
ns
CS high to SDX tristate
t9
40
ns
SCLK to SDX active
t10
60
ns
CS high to SCLK
t11
Data Sheet
Limit values
Min
205
10
Unit
Max
ns
2001-11-12
PEF 81902
Electrical Characteristics
5.6.3
Parallel µP Interface
Siemens/Intel Bus Mode
•
tRR
tRI
RD x CS
tDF
tDH
tRD
Data
AD0 - AD7
Itt00712.vsd
Figure 74
Microprocessor Read Cycle
•
tWW
tWI
WR x CS
tDW
tWD
Data
AD0 - AD7
Itt00713.vsd
Figure 75
Microprocessor Write Cycle
•
tAA
tAD
ALE
WR x CS or
RD x CS
AD0 - AD7
tAL
tALS
tLA
Address
Itt00714.vsd
Figure 76
Data Sheet
Multiplexed Address Timing
206
2001-11-12
PEF 81902
Electrical Characteristics
•
WR x CS or
RD x CS
tAS
tAH
Address
A0 - A6
Itt009661.vsd
Figure 77
Non-Multiplexed Address Timing
Motorola Bus Mode
•
R/W
tDSD
tRWD
tRR
tRI
CS x DS
tDF
tDH
tRD
Data
D0 - D7
Itt00716.vsd
Figure 78
Microprocessor Read Timing
•
R/W
tRWD
tDSD
tWI
tWW
CS x DS
tWD
tDW
D0 - D7
Data
Itt09679.vsd
Figure 79
Data Sheet
Microprocessor Write Cycle
207
2001-11-12
PEF 81902
Electrical Characteristics
•
CS x DS
tAS
tAH
Address
A0 - A6
Itt09662.vsd
Figure 80
Non-Multiplexed Address Timing
Microprocessor Interface Timing
•
Parameter
Symbol
Limit Values
min.
Unit
max.
ALE pulse width
tAA
20
ns
Address setup time to ALE
tAL
10
ns
Address hold time from ALE
tLA
10
ns
Address latch setup time to WR, RD
tALS
10
ns
Address setup time
tAS
10
ns
Address hold time
tAH
10
ns
ALE guard time
tAD
10
ns
DS delay after R/W setup
tDSD
10
ns
RD pulse width
tRR
80
ns
Data output delay from RD
tRD
Data hold from RD
tDH
Data float from RD
tDF
RD control interval1)
tRI
70
ns
W pulse width
tWW
60
ns
Data setup time to W x CS
tDW
10
ns
Data hold time W x CS
tWD
10
ns
W control interval
tWI
70
ns
R/W hold from CS x DS inactive
tRWD
10
ns
1)
80
0
ns
ns
25
ns
control interval: tRI is minimal 70ns for all registers except ISTAU and RDS. However, the time between two
consecutive read accesses to one of the registers ISTAU or RDS, respectively, must be longer than 330ns.
This does not limit tRI of read sequences, which involve intermediate read access to other registers, as for
instance: ISTAU -(tRI )- ISTA -(tRI)- ISTAS -(tRI)- ISTAU.
Data Sheet
208
2001-11-12
PEF 81902
Electrical Characteristics
5.6.4
Table 41
Reset
Reset Input Signal Characteristics
Parameter
Symbol
Limit Values
min.
Length of active
low state
tRST
typ.
Unit
Test Conditions
ms
Power On
the 4 ms are assumed to
be long enough for the
oscillator to run correctly
max.
4
2x
DCL
clock
cycles
+ 400
ns
Delay time for µC tµC
access after RST
rising edge
After Power On
500
ns
•
tµC
RST
tRST
ITD09823.vsd
Figure 81
Data Sheet
Reset Input Signal
209
2001-11-12
PEF 81902
Electrical Characteristics
5.6.5
Undervoltage Detection Characteristics
•
VDD
VDET
VHYS
VDDmin
t
RSTO
tACT
tACT
tDEACT
t
tDEACT
VDDDET.VSD
Figure 82
Undervoltage Control Timing
Table 42
Parameters of the UVD/POR Circuit
VDD= 3.3 V ± 5 %; VSS= 0 V; TA = -40 to 85 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
2.8
2.92
V
90
mV
0.1
V/µs
0.1
V/
ms
Detection Threshold1)
VDET
2.7
Hysteresis
VHys
30
Max. rising/falling VDD
edge for activation/
deactivation of UVD
dVDD/dt
Max. rising VDD for
power-on2)
Min. operating voltage
Data Sheet
VDDmin
Unit Test Condition
1.5
VDD = 3.3 V ± 5 %
V
210
2001-11-12
PEF 81902
Electrical Characteristics
VDD= 3.3 V ± 5 %; VSS= 0 V; TA = -40 to 85 °C
Parameter
Symbol
Limit Values
min.
Delay for activation
of RSTO
tACT
Delay for deactivation
of RSTO
tDEACT
typ.
max.
10
64
Unit Test Condition
µs
ms
1)
The Detection Threshold VDET is far below the specified supply voltage range of analog and digital parts of the
®
T-SMINT . Therefore, the board designer must take into account that a range of voltages is existing, where
neither performance and functionality of the T-SMINT® are guaranteed, nor a reset is generated.
2)
If the integrated Power-On Reset of the T-SMINTIX is selected (VDDDET = ’0’) and the supply voltage VDD is
ramped up from 0V to 3.3V +/- 5%, then the T-SMINTIX is kept in reset during VDDmin < VDD < VDET + VHys.
VDD must be ramped up so slowly that the T-SMINTIX leaves the reset state after the oscillator circuit has
already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and
12ms.
Data Sheet
211
2001-11-12
PEF 81902
Package Outlines
6
Package Outlines
•
Plastic Package, P-MQFP-64
(Metric Quad Flat Package)
Data Sheet
212
2001-11-12
PEF 81902
Package Outlines
•
Plastic Package, P-TQFP-64
(Thin Quad Flat Package)
Data Sheet
213
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7
Appendix: Differences between Q- and T-SMINTâIX
The Q- and T-SMINTâIX have been designed to be as compatible as possible. However,
some differences between them are unavoidable due to the different line codes 2B1Q
and 4B3T used for data transmission on the Uk0 line.
Especially the pin compatibility between Q- and T-SMINTâIX allows for one single PCB
design for both series with only some mounting differences. The µC software can
distinguish between the Q- and T-series by reading the hardware Design Number via the
IOMâ-2 (MONITOR channel identification command) or the µC interface (register
ID.DESIGN), respectively (see Table 43).
Table 43
Design Number
Design Number
Q-SMINTâIX:
Version
T-SMINTâIX: 4B3T
2B1Q
Version 1.3: ’000 001’
Version 1.1: ’100 000’
The following chapter summarizes the main differences between the Q- and TSMINTâIX.
Data Sheet
214
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.1
Pinning
7.1.1
Pin Definitions and Functions
•
Table 44
7.1.2
Pin Definitions and Functions
Pin
T/MQFP-64
Q-SMINTâIX: 2B1Q
T-SMINTâIX: 4B3T
16
Metallic Termination Input
(MTI)
Tie to ‘1‘
55
Power Status (primary)
(PS1)
Tie to ‘1‘
41
Power Status (secondary)
(PS2)
Tie to ‘1‘
LED Pin ACT
The 4 LED states (off, fast flashing, slow flashing, on), which can be displayed with pin
ACT, are slightly different for Q- and T-SMINTâIX (see Table 45). This adoption
guarantees full compliance of T-SMINTâIX to the new iNT specification TS 0284/96.
Table 45
ACT States
LED States
Pin ACT
Q-SMINTâIX: 2B1Q
T-SMINTâIX: 4B3T
off
VDD
VDD
fast flashing
8Hz (1 : 1)*
2Hz (1 : 1)*
slow flashing
1Hz (1 : 1)*
1Hz (3 : 1)*
on
GND
GND
Note: * denotes the duty cycle ’high’ : ’low’.
Data Sheet
215
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.2
U-Transceiver
7.2.1
U-Interface Conformity
•
Table 46
Related Documents to the U-Interface
Q-SMINTâIX: 2B1Q
T-SMINTâIX: 4B3T
ETSI: TS 102 080
conform to annex A
compliant to 10 ms
interruptions
conform to annex B
ANSI: T1.601-1998
(Revision of ANSI T1.6011992)
conform
not required
MLT input and decode logic
CNET: ST/LAA/ELR/DNP/
822
conform
not required
RC7355E
conform
not required
FTZ-Richtlinie 1 TR 220
not required
conform
not required
FTZ TS 0284/96
’Intelligenter Netzabschluss
(iNT)’ März 2001
conform
Data Sheet
216
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.2.2
U-Transceiver State Machines
•
T14S
Any State
SSP or
C/I= 'SSP'
.
SN0
T14S
DI
SP
.
SN0
Deactivated
DC
T14E
T14S
TL
Pending Timing
DC
TIM
.
.
SN0
IOM Awaked
PU
DI
Test
DR
.
SN0
Reset
Any State
Pin-RST or
C/I= 'RES'
AR or TL
AR or TL
T1S, T11S
DI
.
TN
DI & NT-AUTO
Alerting
PU
DR
.
TN
Alerting 1
DR
T1S
T11S
DC
T11E
T11E
ARL
T12S
.
SN1
EC-Training
DC
EC-Training AL
DC
LSEC or T12E
act=0
SN3
Wait for SF AL
DC
.
SN1
EC-Training 1
DR
DI
LSEC or T12E
LSUE
or T1E
SN0
LSUE
or T1E
SN2
..
EQ-Training
DC
BBD1 & SFD
SN3T
act=0
Analog Loop Back
T12S
T12S
.
SN1
T1S,
T11S
T20S
BBD0 & FD
.
LOF
Wait for SF
DC
AR
LOF
T20E &
BBD0 & SFD
SN3/SN3T 1) act=0
Synchronized 1
DC
1)
SN3/SN3T act=1/0
Pend.Deact. S/T
3)
DR
dea=0
LSUE
DI
dea=0
LSUE
uoa=1
LOF
SN3/SN3T 1) act=0
Synchronized 2
2)
AR/ARL
Al
LOF
SN3/SN3T 1) act=1
Wait for Act
2)
AR/ARL
El1
act=1
LOF
Any State
DT or
C/I='DT'
El1
LSU or ( /LOF & T13E )
T7E & DI
Figure 83
Data Sheet
T7S
.
SN0
Receive Reset
DR
SN3/SN3T 1) act=0
Error S/T
act=0
2)
AR/ARL
LOF
dea=0
LSUE
uoa=0
dea=0
LSUE
act=0
act=1
SN3T
Transparent
2)
AI/AIL
act=1 & Al
.
SN0
Pend Receive Res.
T13S
EI1
uoa=0
uoa=0
Yes
dea=0
LSUE
uoa=1
?
dea=0
No
uoa=0
LSUE
dea=1
1)
LOF
SN3/SN3T act=1/0 3)
Pend.Deact. U
DC
LSU
T7S
TL
NTC-Q Compatible State Machine Q-SMINTâIX: 2B1Q
217
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
•
T14S
Any State
SSP or
C/I= 'SSP'
.
SN0
T14S
TL
Pending Timing
DC
T14S
DI
SP
.
SN0
Deactivated
DC
T14E
TIM
.
DI
Test
DR
TIM
.
SN0
.
SN0
IOM Awaked
PU
AR or TL
T1S, T11S
DI
.
TN
Reset
Any State
Pin-RST or
C/I= 'RES'
AR or TL
Alerting
PU
DR
.
TN
Alerting 1
DR
T1S
T11S
T11E
T11E
ARL
T12S
.
SN1
EC-Training
PU
EC-Training AL
DR
LSUE
or T1E
BBD1 & SFD
SN3T
act=0
Analog Loop Back
AR
.
SN1
EC-Training 1
DR
DI or TIM
LSEC or T12E
LSEC or T12E
act=0
SN3
Wait for SF AL
DR
T12S
T12S
.
SN1
T1S,
T11S
SN0
..
EQ-Training
PU
T20S
LSUE
or T1E
LOF
BBD0 & FD
.
SN2
Wait for SF
PU
T20E &
BBD0 & SFD
SN3/SN3T 1) act=0
Synchronized 1
PU
SN3/SN3T 1) act=1/0 3)
Pend.Deact. S/T
DR
LOF
DI or
TIM
dea=0
LSUE
dea=0
LSUE
uoa=1
LOF
SN3/SN3T 1) act=0
Synchronized 2
2)
AR/ARL
uoa=0
dea=0
LSUE
Al
LOF
El1
SN3/SN3T 1) act=1
Wait for Act
2)
AR/ARL
act=1
LOF
Any State
DT or
C/I='DT'
El1
act=1 & Al
.
SN0
Pend Receive Res.
T13S
DR
LSU or ( /LOF & T13E )
T7E & TIM
T7E & DI
Figure 84
Data Sheet
T7S
.
SN0
Receive Reset
DR
dea=0
LSUE
act=0
SN3T
act=1
Transparent
2)
AI/AIL
SN3/SN3T 1) act=0
Error S/T
act=0
2)
AR/ARL
LOF
uoa=0
uoa=0
dea=0
Yes
LSUE
uoa=1
?
dea=0
No
uoa=0
LSUE
dea=1
1)
SN3/SN3T act=1/0 3)
LOF
Pend.Deact. U
DR
LSU
T7S
TL
Simplified State Machine Q-SMINTâIX: 2B1Q
218
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
•
AWR
U0
IOM Awaked
TIM
AR
DI
U0
Deactivated
DC
AWR
DC U0, DA
AR
T6S
T05E
U1W
Start Awaking Uk0
T6S
T05S
T05S
RSY
U0
Deactivating
DC
AWR
AWT
T6S
T6E
U0
Awake Signal Sent
RSY
AWR
T13S
T13E
U0
Ack. Sent / Received
AWT
AWR
T13S
U1W
Sending Awake-Ack.
T13S
RSY
RSY
(DI & T05E)
T12S
U1A
Synchronizing
(U0 & T12E)
RSY
U2
T05S
U0
Pend. Deactivation
DR
DI
T05S
SSP or LTD
DT
U1
SBC Synchronizing
AR / ARL
U0
LOF
ANY STATE
RES
AI
U3
Wait for Info U4H
AR / ARL
SP / U0
Test
DR
DI
U0
LOF
U0
Reset
DR
U4H
U0
U5
Transparent
AI / AIL
Figure 85
U0
LOF
U0
Loss of Framing
RSY
NT_SM_4B3T_cust.emf
IEC-T/NTC-T Compatible State Machine T-SMINTâIX: 4B3T
Both the Q- and the T-SMINTâIX U-transceiver can be controlled via state machines,
which are compatible to those defined for the old NT generation INTC-Q and NTC-T.
Additionally, the Q-SMINTâIX possesses a newly defined, so called ‘simplified‘ state
machine. This simplified state machine can be used optionally instead of the INTC-Q
compatible state machine and eases the U-transceiver control by software. Such a
simplified state machine is not available for the T-SMINTâIX.
Data Sheet
219
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.2.3
Table 47
Command/Indication Codes
C/I Codes
Q-SMINTâIX: 2B1Q
T-SMINTâIX: 4B3T
IN
OUT
IN
OUT
0000
TIM
DR
TIM
DR
0001
RES
–
–
–
0010
–
–
–
–
0011
–
–
LTD
–
0100
EI1
EI1
–
RSY
0101
SSP
–
SSP
–
0110
DT
–
DT
–
0111
–
PU
–
–
1000
AR
AR
AR
AR
1001
–
–
–
–
1010
ARL
ARL
–
ARL
1011
–
–
–
–
1100
AI
AI
AI
AI
1101
–
–
RES
–
1110
–
AIL
–
AIL
1111
DI
DC
DI
DC
Code
Data Sheet
220
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.2.4
Interrupt Structure
•
M56R
7
0
OPMODE.MLT
MS2
MS1
+
NEBE
M61
M52
M51
0
CRC,
TLL,
no
Filtering
MFILT
FEBE
M4R
7
+
MFILT
UCIR
M4RMASK
7
AIB
UOA
M46
M45
M44
CRC,
TLL,
no
Filtering
C/I
SCO
C/I
DEA
0
C/I
0
ACT
EOCR
C/I
MFILT
15
11
a1
a2
0
TLL,
CHG,
no
Filtering
ISTAU
7
i8
0
MLT
MASKU
MLT
CI
CI
FEBE/
NEBE
FEBE/
NEBE
M56
M56
M4
M4
EOC
EOC
6ms
6ms
12ms
12ms
ISTA
7
MASK
U
Reserved
interr_U_Q2.vsd
0
INT
Figure 86
Data Sheet
Interrupt Structure U-Transceiver Q-SMINTâIX: 2B1Q
221
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
•
UCIR
7
0
0
0
0
C/I
C/I
C/I
0
C/I
ISTAU
7
0
MASKU
0
1
CI
CI
RDS
RDS
0
1
0
1
0
1
0
1
1ms
1ms
ISTA
MASK
U
S
...
...
...
...
...
...
intstruct_4b3t.emf
INT
Figure 87
Data Sheet
Interrupt Structure U-Transceiver T-SMINTâIX: 4B3T
222
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.2.5
Register Summary U-Transceiver
U-Interface Registers Q-SMINT âIX: 2B1Q
Name
7
6
5
4
3
2
1
0
OPMODE
0
UCI
FEBE
MLT
0
CI_
SEL
0
0
MFILT
M56 FILTER
M4 FILTER
EOC FILTER
reserved
EOCR
EOCW
ADDR R/W RES
60H
R*/W 14H
61H
R*/W 14H
62H
0
0
0
0
a1
a2
a3
d/m
63H
R
0F
i1
i2
i3
i4
i5
i6
i7
i8
64H
0
0
0
0
a1
a2
a3
d/m
65H
i1
i2
i3
i4
i5
i6
i7
i8
66H
00H
FFH
W
01H
M4RMASK
M4 Read Mask Bits
67H
R*/W 00H
M4WMASK
M4 Write Mask Bits
68H
R*/W A8 H
M4R
verified M4 bit data of last received superframe
69H
M4W
M4 bit data to be send with next superframe
6AH
R
BEH
R*/W BEH
M56R
0
MS2
MS1
NEBE
M61
M52
M51
FEBE
6BH
R
1FH
M56W
1
1
1
1
M61
M52
M51
FEBE
6CH
W
FFH
UCIR
0
0
0
0
C/I code output
6DH
R
00H
UCIW
0
0
0
0
C/I code input
6EH
W
01H
TEST
0
0
0
0
LOOP
0
DLB
TRANS U/IOMâ
CCRC
+-1
Tones
0
1
LBBD
LB2
40 KHz 6FH
LB1
70H
R*/W 00H
R*/W 08H
FEBE
FEBE Counter Value
71H
R
00H
NEBE
NEBE Counter Value
72H
R
00H
reserved
73H79H
Data Sheet
223
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
Name
7
6
5
4
3
2
1
0
ISTAU
MLT
CI
FEBE/
NEBE
M56
M4
EOC
6ms
12ms
7AH
MASKU
MLT
CI
FEBE/
NEBE
M56
M4
EOC
6ms
12ms
7BH
FW_
VERSION
ADDR R/W RES
reserved
7CH
FW Version Number
7DH
reserved
7EH-
R
00H
R*/W FFH
R
6xH
7FH
Data Sheet
224
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
U-Interface Registers T-SMINTâIX: 4B3T
Name
7
6
5
4
3
2
1
0
OPMODE
0
UCI
0
0
0
0
0
0
reserved
ADDR R/W RES
60H
R*/W 00 H
61H6CH
UCIR
0
0
0
0
C/I code output
6DH
R
00 H
UCIW
0
0
0
0
C/I code input
6EH
W
01 H
reserved
LOOP
0
0
RDS
TRANS U/IOMâ
1
6FH
LBBD
LB2
LB1
70H
reserved
71H
Block Error Counter Value
72H
reserved
73H79H
ISTAU
0
CI
RDS
0
0
0
0
1 ms
7AH
MASKU
1
CI
RDS
1
1
1
1
1 ms
7BH
FW_
VERSION
Data Sheet
reserved
7CH
FW Version Number
7DH
reserved
7E H7FH
225
R*/W 08 H
R
00 H
R
00 H
R*/W FFH
R
3xH
2001-11-12
PEF 81902
Appendix: Differences between Q- and T-SMINT‚IX
7.3
External Circuitry
The external circuitry of the Q- and T-SMINTâIX is equivalent; however, some external
components of the U-transceiver hybrid must be dimensioned different for 2B1Q and
4B3T. All information on the external circuitry is preliminary and may be changed in
future documents.
•
RT
R3
AOUT
R4
BIN
n
RCOMP
>1µ
C
AIN
RCOMP
Loop
RPTC
R3
R4
RPTC
Figure 88
extcirc_U_Q2_exthybrid.emf
RT
BOUT
External Circuitry Q- and T-SMINTâIX
Note: the necessary protection circuitry is not displayed in Figure 88.
Table 48
Dimensions of External Components
Component
Q-SMINTâIX: 2B1Q
T-SMINTâIX: 4B3T
Transformer:
Ratio
Main Inductivity
1:2
14.5 mH
1:1.6
7.5 mH
Resistance
1.3 kΩ
1.75 kΩ
Resistance
1.0 kΩ
1.0 kΩ
Resistance
9.5 Ω
25 Ω
Capacitor C
27 nF
15 nF
RPTC and RComp
2RPTC + 8RComp = 40 Ω
n2 × (2RCOMP + RB) + RL = 20Ω
Data Sheet
226
2001-11-12
PEF 81902
Index
8
Index
I
Identification
via Monitor Channel 47
via Register Access 175
Interrupts 134
IOM®-2 Interface
AC Characteristics 203
Activation/Deactivation 56
Detailed Registers 176
Frame Structure 27
Functional Description 27
A
Absolute Maximum Ratings 197
Address Space 133
B
Block Diagram 6
Block Error Counter 64
C
C/I Channel
Detailed Registers 145
Functional Description 49
C/I Codes
S-Transceiver 84
U-Transceiver 65
Controller Data Access (CDA) 30
L
Layer 1
Activation / Deactivation 115
Loopbacks 123
LED Pins 12
Line Overload Protection 197
D
M
DC Characteristics 198
D-Channel Access Control
Functional Description 51
State Machine 54
Differences between Q- and T-SMINT 214
Features 3
Maintenance Channel 62
Microcontroller Clock Generation 23
Microcontroller Interfaces
Interface Selection 16
Parallel Microcontroller Interface 21
Serial Control Interface (SCI) 16
Monitor Channel
Detailed Registers 188
Error Treatment 45
Functional Description 41
Handshake Procedure 41
Interrupt Logic 48
Time-Out Procedure 48
H
O
HDLC Controller
Data Reception 96
Data Transmission 104
Detailed Registers 145
Functional Description 95
Message Transfer Modes 95
Oscillator Circuitry 132
E
External Circuitry
S-Transceiver 129
U-Transceiver 127
F
Data Sheet
P
Package Outlines 212
Parallel Microcontroller Interface
AC-Characteristics 206
Functional Description 21
227
2001-11-12
PEF 81902
Index
Pin Configuration 5
Pin Definitions and Functions 7
Power Consumption 200
Power Supply Blocking 127
Power-On Reset 26, 210
W
Watchdog Timer 25
R
Register Summary 136
Reset
Generation 24
Input Signal Characteristics 209
Power-On Reset 26, 210
Under Voltage Detection 26, 210
S
S/Q Channels 80
Scrambler / Descrambler 65
Serial Control Interface (SCI)
AC-Characteristics 205
Functional Description 16
Serial Data Strobe Signal 40
Stop/Go Bit Handling 53
S-Transceiver
Detailed Registers 163
Functional Description 78
State Machine, LT-S 90
State Machine, NT 86
Supply Voltages 200
Synchronous Transfer 36
System Integration 13
T
Test Modes 12
TIC Bus Handling 51
U
U-Interface Hybrid 127
Under Voltage Detection 26, 210
U-Transceiver
4B3T Frame Structure 58
Detailed Registers 191
Functional Description 58
State Machine NT 66
Data Sheet
228
2001-11-12
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