a 10-Bit, 40 MSPS/60 MSPS A/D Converter AD9050 FUNCTIONAL BLOCK DIAGRAM FEATURES Low Power: 315 mW @ 40 MSPS, 345 mW @ 60 MSPS On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or 3 V Logic I/O SNR: 53 dB Minimum at 10 MHz w/40 MSPS APPLICATIONS Medical Imaging Instrumentation Digital Communications Professional Video +5V GND +5V AD9050 AINB REFERENCE CKTS T/H ADC AIN SUM AMP DAC ADC TIMING ENCODE PRODUCT DESCRIPTION The AD9050 is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only +5 V and an encode clock to achieve 40 MSPS or 60 MSPS sample rates with 10-bit resolution. 10 DECODE LOGIC +5V 4 3 AIN (+3.3V ± 0.512V) 10 2, 8, 11, 20, 22 0.1µF +5V 5 The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with 5 V/3 V logic, selected by the user. The two-step architecture used in the AD9050 is optimized to provide the best dynamic performance available while maintaining low power consumption. 10 BITS AD9050 0.1µF (2) 74AC574 6 0.1µF 9 13 1, 7, 12, 21, 23 ENCODE A 2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on an advanced BiCMOS process, the AD9050 is packaged in space saving surface mount packages (SOIC, SSOP) and is specified over the industrial (–40°C to +85°C) temperature range. The 60 MSPS version (AD9050BRS-60) is only available in the SSOP package. Figure 1. Typical Connections REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD9050–SPECIFICATIONS(V , V D DD = +5 V; internal reference; ENCODE = 40 MSPS for BR/BRS, 60 MSPS for BRS-60 ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter Temp Test Level AD9050BR/BRS Min Typ Max RESOLUTION DC ACCURACY Differential Nonlinearity AD9050BRS-60 Min Typ Max 10 10 Bits +25°C Full +25°C Full Full +25°C Full I V I V IV I V +25°C +25°C Full +25°C +25°C +25°C V I IV I V V BANDGAP REFERENCE Output Voltage Temperature Coefficient1 +25°C Full I V 2.4 SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Propagation Delay (tPD)2 +25°C +25°C +25°C +25°C Full I IV V V IV 40 +25°C +25°C V V +25°C +25°C V I 8.51 8.93 8.85 +25°C +25°C V I 53 +25°C +25°C V I 53.5 +25°C +25°C V I –69 –67 –60 –69 –64 –58.5 dBc dBc +25°C +25°C V I –75 –70 –58 –75 –62 –57.5 dBc dBc +25°C +25°C +25°C V V V 65 0.15 0.25 Integral Nonlinearity No Missing Codes Gain Error Gain Tempco1 ANALOG INPUT Input Voltage Range Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time ENOBS fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio (SINAD)3 fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio (Without Harmonics) fIN = 2.3 MHz fIN = 10.3 MHz 2nd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz 3rd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz Two-Tone Intermodulation Distortion (IMD)4 Differential Phase Differential Gain 0.75 1.75 1.0 1.0 1.75 1.25 GUARANTEED ± 1.0 7.5 ± 100 Units –10 –32 3.5 1.024 +7 0.85 1.85 1.1 1.25 2.0 1.50 GUARANTEED ± 1.0 8.5 ± 100 +25 +51 6.5 –10 –32 3.5 2.5 ± 50 2.6 2.4 1.5 2.7 5 3 5.0 5 100 5.0 5 100 +25 +51 6.5 2.5 ± 50 2.6 1.5 2.7 5 3 60 5 15 5 10 10 –2– 1.024 +7 15 LSB LSB LSB LSB % FS ppm/°C V p-p mV mV kΩ pF MHz V ppm/°C MSPS MSPS ns ps, rms ns 10 10 ns ns 8.15 8.93 8.51 ENOBs ENOBs 55.5 55 51 55.5 53 dB dB 56 55.5 51.5 56 54.0 dB dB 65 0.15 0.25 dBc Degrees % REV. B AD9050 Parameter Temp Test Level AD9050BR/BRS Min Typ Max AD9050BRS-60 Min Typ Max ENCODE INPUT Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL) Full Full Full Full +25°C +25°C +25°C IV IV IV IV V IV IV 2.0 2.0 Full Full Full Full IV IV IV IV DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Voltage (3.0 VDD) Logic “0” Voltage (3.0 VDD) Output Coding POWER SUPPLY VD, VDD Supply Current5 Power Dissipation5 Power Supply Rejection Ratio (PSRR)6 Full Full IV IV +25°C I 0.8 1 1 0.8 1 1 10 10 10 10 166 166 4.95 6.7 6.7 166 166 4.95 0.05 2.95 0.05 2.95 Offset Binary 0.05 Code 40 63 315 80 400 Units V V µA µA pF ns ns V V V V Offset Binary 0.05 Code 40 69 345 87.2 486 mA mW ± 10 mV/V ± 10 NOTES 1 “Gain Tempco” is for converter only; “Temperature Coefficient” is for bandgap reference only. 2 Output propagation delay (t PD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF maximum loads. 3 RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency for BR/BRS, 1.0 dB below full scale for BRS-60. 4 Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale. 5 Power dissipation is measured at full update rate with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other conditions. 6 Measured as the ratio of the change in offset voltage for 5% change in +V D. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS* Test Level I – 100% Production Tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V ANALOG IN . . . . . . . . . . . . . . . . . . . . . . –1.0 V to VD + 1.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature AD9050BR/BRS/BRS-60 . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Model Temperature Range Package Option* AD9050BR AD9050BRS AD9050BRS-60 –40°C to +85°C –40°C to +85°C –40°C to +85°C R-28 RS-28 RS-28 *R = Small Outline (SO); RS = Shrink Small Outline (SSOP). REV. B –3– AD9050 Table I. AD9050 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND) Analog Input Voltage Level OR (Out of Range) Digital Output MSB . . . LSB 3.813 3.300 2.787 Positive Full Scale + 1 LSB Midscale Negative Full Scale – 1 LSB 1 0 1 1111111111 0111111111 0000000000 PIN FUNCTION DESCRIPTIONS Pin No Name Function 1, 7, 12, 21, 23 2, 8, 11 3 4 5 6 9 10 13 GND VD VREFOUT VREFIN COMP REFBP AINB AIN ENCODE 14 OR 15 16–19 20, 22 24–27 28 D9 (MSB) D8–D5 VDD D4–D1 D0 (LSB) Ground. Analog +5 V ± 5% power supply. Internal bandgap voltage reference (nominally +2.5 V). Input to reference amplifier. Voltage reference for ADC is connected here. Internal compensation pin, 0.1 µF bypass connected here to VD (+5 V). External connection for (0.1 µF) reference bypass capacitor. Complementary analog input pin (Analog input bar). Analog input pin. Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. Out of range signal. Logic “0” when analog input is in nominal range. Logic “1” when analog input is out of nominal range. Most significant bit of ADC output. Digital output bits of ADC. Digital output power supply (only used by digital outputs). Digital output bits of ADC. Least significant bit of ADC output. PIN CONFIGURATION 28 D0 (LSB) GND 1 VD 2 27 D1 VREFOUT 3 26 D2 VREFIN 4 25 D3 COMP 5 24 D4 REFBP 6 GND 7 23 GND AD9050 22 VDD TOP VIEW VD 8 (Not to Scale) 21 GND AINB 9 20 VDD AIN 10 19 D5 VD 11 18 D6 GND 12 17 D7 ENCODE 13 16 D8 15 D9 (MSB) OR 14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9050 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. B AD9050 N N+1 N+2 N+3 N+4 N+5 AIN MIN tA ENCODE tEH tEL tPD DIGITAL OUTPUTS tA APERTURE DELAY tEH tEL PULSE WIDTH HIGH 10ns* PULSE WIDTH LOW 10ns* tPD OUTPUT PROP DELAY 5.0ns TYP MAX 2.7ns 166ns 166ns 8.2ns 15.0ns *FOR BR/BRS, SEE SPECIFICATION TABLE N–5 N–4 N–3 N–2 N–1 N Figure 2. Timing Diagram VDD (Pins 20, 22) +3V to +5V VD 8k 8k AINB (Pin 9) VD INPUT BUFFER ENCODE (Pin 13) D0–D9, OR AIN (Pin 10) 16k 16k Analog Input Encode Input Output Stage VD VD VREFOUT (Pin 3) AV VREFIN (Pin 4) VREFBF (Pin 6) Reference Circuit VREF Output Figure 3. Equivalent Circuits REV. B –5– AD9050–Typical Performance Curves 350 60 340 59 5V 320 DISSIPATION – mW SIGNAL-TO-NOISE RATIO – dB (SINAD) 330 310 300 290 3V 280 270 260 ENCODE = 40 MSPS AIN = 10.3 MHz 58 57 56 55 54 53 52 51 250 0 10 20 30 40 50 50 –40 60 0 – 20 20 40 60 80 TEMPERATURE – °C CLOCK RATE – MSPS Figure 4. Power Dissipation vs. Clock Rate Figure 7. SNR vs. Temperature 80 0 –10 74 ENCODE = 40 MSPS f1 IN = 9.5 MHz @ –7 dBFS f2 IN = 9.9 MHz @ –7 dBFS 2f1–f2 = –65.4 dBc 2f2–f1 = –65.0 dBc –20 HD 40 –30 68 –40 HD 60 dB –50 dB 62 SNR 40 56 –60 –70 –80 SNR 60 50 –90 –100 44 –110 –120 38 1 10 0 100 2.5 5 ANALOG INPUT FREQUENCY – MHz Figure 5. SNR/Distortion vs. Frequency 15 17.5 20 Figure 8. Two-Tone IMD 58 0.50 DIFF GAIN – % SNR 56 54 0.25 0.00 –0.25 –0.50 52 DIFF PHASE – Degrees SNR – dB 7.5 10 12.5 FREQUENCY – MHz 50 48 46 0 10 20 30 40 50 60 CLOCK RATE – MSPS Figure 6. SNR vs. Clock Rate 1 2 3 4 5 6 1 2 3 4 5 6 0.50 0.25 0.00 –0.25 –0.50 Figure 9. Differential Gain/Differential Phase –6– REV. B AD9050 60 0 SINAD_40 ENCODE = 40 MSPS ANALOG IN = 2.3 MHz SNR = 55.1 dB SNR (W/O HAR) = 55.5 dB 2ND HARMONIC = 69.3 dB 3RD HARMONIC = 72.9 dB –20 –30 –40 –50 dB AIN = 10.3 MHz 54 SIGNAL-TO-NOISE – dB (SINAD) –10 –60 –70 –80 –90 SINAD_60 48 42 36 –100 –110 30 25 –120 0 2.5 5 7.5 10 12.5 FREQUENCY – MHz 15 17.5 20 50 60 55 65 Figure 13. SNR vs. Clock Pulse Width 1.0 0 ENCODE = 60 MSPS ANALOG IN = 10.3 MHz SNR = 55.8 dB SNR (W/O HAR) = 56.2 dB 2ND HARMONIC = 67.2 dB 3RD HARMONIC = 73.2 dB –10 –20 0.5 0.0 –0.5 ADC GAIN – dB –30 –40 dB 45 DUTY CYCLE – % Figure 10. FFT Plot 40 MSPS, 2.3 MHz –50 –60 –70 –1.0 –1.5 –2.0 –2.5 –3.0 –80 –3.5 –90 –4.0 –100 0 5 25 10 15 20 FREQUENCY – MHz –4.5 30 1 10 1000 100 ANALOG INPUT FREQUENCY – MHz Figure 14. ADC Gain vs. AIN Frequency Figure 11. FFT Plot 60 MSPS, 10.3 MHz 15.0 0 –10 ENCODE = 40 MSPS ANALOG IN = 10.3 MHz SNR = 54.6 dB SNR (W/O HAR) = 55.2 dB 2ND HARMONIC = 66.4 dB 3RD HARMONIC = 70.5 dB –20 –30 –40 14.0 13.0 [1] - 5V DATA RISING EDGE [2] - 5V DATA FALLING EDGE [3] - 3V DATA RISING EDGE [4] - 3V DATA FALLING EDGE [3] 12.0 [1] 11.0 tPD – ns –50 dB 40 –60 –70 [4] 10.0 [2] 9.0 –80 8.0 –90 7.0 –100 6.0 –110 –120 0 2.5 5 7.5 10 12.5 FREQUENCY – MHz 15 17.5 5.0 –40 20 0 20 40 60 80 TEMPERATURE – °C Figure 15. tPD vs. Temperature 3 V/5 V Figure 12. FFT Plot 40 MSPS, 10.3 MHz REV. B – 20 –7– 100 AD9050 THEORY OF OPERATION 1kΩ Refer to the block diagram on the front page. +5V VIN –0.5V to +0.5V 10 9 0.1µF +5V AD820 1kΩ 1kΩ 0.1µF Figure 16. Single Supply, Single Ended, DC Coupled AD9050 Error correction and decode logic correct and align data from the two conversions and present the result as a 10-bit parallel digital word. Output data are strobed on the rising edge of the ENCODE command. The subranging architecture results in five pipeline delays for the output data. Refer to the AD9050 Timing Diagram. 1kΩ +5V +5V 1kΩ 0.1µF VIN –0.5V to +0.5V 10 AD9050 AD8011 USING THE AD9050 3 V System 9 –5V 0.1µF The digital input and outputs of the AD9050 can be easily configured to directly interface to 3 V logic systems. The encode input (Pin 13) is TTL compatible with a logic threshold of 1.5 V. This input is actually a CMOS stage (refer to Equivalent Encode Input Stage) with a TTL threshold, allowing operation with TTL, CMOS and 3 V CMOS logic families. Using 3 V CMOS logic allows the user to drive the encode directly without the need to translate to +5 V. This saves the user power and board space. As with all high speed data converters, the clock signal must be clean and jitter free to prevent the degradation of dynamic performance. Analog Input AD9050 AD8041 At the input, the analog signal is buffered by a high speed differential buffer and applied to a track-and-hold (T/H) that holds the analog value present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse. The two stage architecture completes a coarse and then a fine conversion of the T/H output signal. The AD9050 outputs can also directly interface to 3 V logic systems. The digital outputs are standard CMOS stages (refer to AD9050 Output Stage) with isolated supply pins (Pins 20, 22 VDD). By varying the voltage on the VDD pins, the digital output levels vary respectively. By connecting Pins 20 and 22 to the 3 V logic supply, the AD9050 will supply 3 V output levels. Care should be taken to filter and isolate the output supply of the AD9050 as noise could be coupled into the ADC, limiting performance. +5V 1kΩ The AD9050 employs a subranging architecture with digital error correction. This combination of design techniques ensures true 10-bit accuracy at the digital outputs of the converter. Figure 17. Single Ended, Capacitively Coupled AD9050 1kΩ +5V +5V 1kΩ VIN –0.5V to +0.5V 0.1µF T1-1T 10 AD9050 AD8011 50Ω –5V 9 Figure 18. Differentially Driven AD9050 Using Transformer Coupling The AD830 provides a unique method of providing dc level shift for the analog input. Using the AD830 allows a great deal of flexibility for adjusting offset and gain. Figure 19 shows the AD830 configured to drive the AD9050. The offset is provided by the internal biasing of the AD9050 differential input (Pin 9). For more information regarding the AD830, see the AD830 data sheet. The analog input of the AD9050 is a differential input buffer (refer to AD9050 Equivalent Analog Input). The differential inputs are internally biased at +3.3 V, obviating the need for external biasing. Excellent performance is achieved whether the analog inputs are driven single-ended or differential (for best dynamic performance, impedances at AIN and AINB should match). VIN –0.5V to +0.5V 1 2 +5V +15V 3 AD830 4 7 10 AD9050 –5V 9 0.1µF Figure 16 shows typical connections for the analog inputs when using the AD9050 in a dc coupled system with single ended signals. All components are powered from a single +5 V supply. The AD820 is used to offset the ground referenced input signal to the level required by the AD9050. Figure 19. Level Shifting with the AD830 AC coupling of the analog inputs of the AD9050 is easily accomplished. Figure 17 shows capacitive coupling of a single ended signal while Figure 18 shows transformer coupling differentially into the AD9050. –8– REV. B AD9050 Overdrive of the Analog Input Power Dissipation Special care was taken in the design of the analog input section of the AD9050 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +2.788 V to 3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range comparators detect when the analog input signal is out of this range and shut the T/H off. The digital outputs are locked at their maximum or minimum value (i.e., all “0” or all “1”). This precludes the digital outputs from changing to an invalid value when the analog input is out of range. The power dissipation specification in the parameter table is measured under the following conditions: encode is 40 MSPS or 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, the digital outputs are loaded with approximately 7 pF (10 pF maximum) and VDD is 5 V. These conditions intend to reflect actual usage of the device. As shown in Figure 4, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS-type devices. Also the loading determines the power dissipated in the output stages. From an ac standpoint, the capacitive loading will be the key (refer to Equivalent Output Stage). When the analog input signal returns to the nominal range, the out-of-range comparators switch the T/H back to the active mode and the device recovers in approximately 10 ns. The input is protected to one volt outside the power supply rails. For nominal power (+5 V and ground), the analog input will not be damaged with signals from +6.0 V to –1.0 V. The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages, but is not realistic from a usage standpoint. Timing The performance of the AD9050 is very insensitive to the duty cycle of the clock. Pulse width variations of as much as ± 10% will cause no degradation in performance. (see Figure 13, SNR vs. Clock Pulse Width). The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to USING THE AD9050, 3 V System). The lower output swings minimize consumption. Refer to Figure 4 for performance characteristics. The AD9050 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (refer to the AD9050 Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9050; these transients can detract from the converter’s dynamic performance. Voltage Reference A stable and accurate +2.5 V voltage reference is built into the AD9050 (Pin 3, VREF Output). In normal operation the internal reference is used by strapping Pins 3 and 4 of the AD9050 together. The internal reference has 500 µA of extra drive current that can be used for other circuits. The minimum guaranteed conversion rate of the AD9050 is 3 MSPS. Below a nominal of 1.5 MSPS the internal T/H switches to a track function only. This precludes the T/H from drooping to the rail during the conversion process and minimizes saturation issues. At clock rates below 3 MSPS dynamic performance degrades. The AD9050 will operate in burst mode operation, but the user must flush the internal pipeline each time the clock stops. This requires five clock pulses each time the clock is restarted for the first valid data output (refer to Figure 2 Timing Diagram). REV. B Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9050, which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used to connect to Pin 4 of the AD9050. The VREFIN requires 5 µA of drive current. The input range can be adjusted by varying the reference voltage applied to the AD9050. No appreciable degradation in performance occurs when the reference is adjusted ± 5%. The full-scale range of the ADC tracks reference voltage changes linearly. –9– AD9050 Figure 20. Evaluation Board Top Layer Figure 22. Evaluation Board Bottom Layer Figure 21. Evaluation Board Ground Layer Figure 23. Silkscreen –10– REV. B AD9050 U3 74AC574R U1 AD9050R R5 1k R4 1k J2 R3 50 TP3 U2 AD9631Q 2 IN OUT 3 IN 3 4 5 6 9 10 13 14 C9 0.1µF 6 TP1 U6:B 74AC00R 4 5 VREFOUT VREFIN COMP REFBP AINB AIN ENC OR D9/MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 +5V +5V 15 16 17 18 19 24 25 26 27 28 20 22 9 8 7 6 5 4 3 2 C2 0.1µF J7 CK 11 +5V 9 8 7 6 5 4 3 2 +5V E1 3 OUT VCC +5V 12 13 Y1 GND SW41 2 J3 HDR20 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OE 1 1 2 U6:D 74AC00R 8D 7D 6D 5D 4D 3D 2D 1D 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q CK 11 R2 2k U6:A 74AC00R 11 12 13 14 15 16 17 18 19 +5V OE 1 3 9 10 +5V J6 12 13 14 15 16 17 18 19 U4 74AC574R TP2 C3 0.1µF 4 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q C1 0.1µF 6 R1 50 8D 7D 6D 5D 4D 3D 2D 1D 8 U6:C 74AC00R J1 C5 10µF +5V + C7 0.1µF +5V C10 0.1µF C12 0.1µF C13 0.1µF C14 0.1µF C15 0.1µF J5 –5.2V C6 10µF + C8 0.1µF –5.2V C20 0.1µF Figure 24. Evaluation Board Schematic REV. B –11– C16 0.1µF C17 0.1µF C22 0.1µF C23 0.1µF C24 0.1µF AD9050 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead SOIC (R-28) 1 14 PIN 1 0.0118 (0.30) 0.0040 (0.10) C2048b–2–3/97 15 0.4193 (10.65) 0.3937 (10.00) 28 0.2992 (7.60) 0.2914 (7.40) 0.7125 (18.10) 0.6969 (17.70) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0.0192 (0.49) 0° SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead SSOP (RS-28) 0.407 (10.34) 0.397 (10.08) 15 1 14 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 0.07 (1.79) 0.066 (1.67) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.015 (0.38) 0.010 (0.25) SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8° 0° 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. 0.078 (1.98) PIN 1 0.068 (1.73) –12– REV. B