a FEATURES 10-Bit, 100 MSPS ADC Low Power: 600 mW Typical at 100 MSPS On-Chip Track/Hold 230 MHz Analog Bandwidth SINAD = 54 dB @ 41 MHz On–Chip Reference 1 V p-p Analog Input Range Single Supply Operation: +5 V or –5 V Differential Clock Input Available in Standard Military Drawing Version APPLICATIONS Digital Communications Signal Intelligence Digital Oscilloscopes Spectrum Analyzers Medical Imaging Radar HDTV GENERAL DESCRIPTION The AD9070 is a monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and ECL digital interfaces. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. The ADC requires only a single –5 V supply and an encode clock for full performance operation. The digital outputs are ECL compatible, while a differential clock input accommodates a wide range of logic levels. The AD9070 may be operated in a Positive ECL (PECL) environment with a single +5 V supply. An Out-of-Range output (OR) is available in the DIP version to indicate that a conversion result is outside the operating range. In both package styles, the output data are held at saturation levels during an out-of-range condition. 10-Bit, 100 MSPS A/D Converter AD9070 FUNCTIONAL BLOCK DIAGRAM VREF IN –2.5V AD9070 AIN AIN ENCODE SOIC (BR) PACKAGE ONLY ADC T/H 10 D9 – D0 SUM AMP ENCODE VREF REF OUT COMP BYPASS DAC ADC TIMING VEE ENCODE LOGIC OR DIP PACKAGE ONLY GND The input amplifier supports single-ended interfaces. An internal –2.5 V reference is included in the SOIC packaged device (an external voltage reference is required for the DIP version). Fabricated on an advanced bipolar process, the AD9070 is available in a plastic SOIC package specified over the industrial temperature range (–40°C to +85°C), and a full MIL-PRF-38534 QML version (–55°C to +125°C) in a ceramic Dual-in-Line Package (DIP). REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD9070–SPECIFICATIONS Parameter Temp (VEE = –5 V, ENCODE = 100 MSPS, outputs loaded with 100 ⍀ to –2 V unless otherwise noted) Test Level Min AD9070BR Typ Max RESOLUTION DC ACCURACY Differential Nonlinearity 10 ± 0.6 ± 0.7 ± 0.6 ± 0.9 Guaranteed ±1 +25°C Full +25°C Full Full +25°C Full Full I VI I VI VI I VI V Full Full +25°C Full +25°C Full +25°C +25°C Full +25°C V V I I I I V I I V REFERENCE OUTPUT Output Voltage Temperature Coefficient Full Full VI V –2.4 SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulse Width High (t EH) Encode Pulse Width Low (t EL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (t PD)2 Output Rise Time (tR) Output Fall Time (tF) Full Full +25°C +25°C +25°C +25°C Full Full Full Full VI IV IV IV V V VI VI VI VI 100 DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Full Full Full Full +25°C IV IV VI VI V –1.1 DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Output Coding Full Full VI VI –1.1 POWER SUPPLY VEE Supply Current (VEE = –5 V) Power Dissipation3 Power Supply Sensitivity 4 Full Full VI VI 80 400 +25°C I Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (with Respect to AIN) Common-Mode Voltage Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power 5962-9756301HXC Min Typ Max 10 ± 0.6 ± 0.9 ± 0.6 ± 1.5 Guaranteed ±1 ±2 130 +1.25/–1.0 +1.5/–1.0 ± 1.5 ±4 115 10 ± 512 –2.5 ± 0.2 ±7 ± 18 ±8 40 40 3 75 200 75 230 –2.5 170 –2.6 +1.25/–1.0 +2.00/–1.0 ± 1.5 ± 2.25 LSB LSB LSB LSB ±4 ±6 % FS % FS ppm/°C ± 512 –2.5 ± 0.2 ±7 ± 18 ±9 ± 20 40 40 3 75 200 75 200 230 mV p-p V mV mV kΩ kΩ pF µA µA MHz N/A N/A V ppm/°C 0.85 2.5 2.6 3.0 0.5 0.5 40 13 13 4.5 4.5 0.85 2.5 2.6 3.0 0.5 0.5 1.5 4.0 –0.4 –1.5 ± 10 ± 10 –1.1 4.0 1.2 1.2 –0.4 –1.5 ± 10 ± 10 3 3 –1.15 –1.65 Twos Complement –2– Bit 100 40 13 13 4.5 4.5 1.5 10 10 120 600 150 750 0.005 0.012 –1.60 Twos Complement 80 400 Units MSPS MSPS ns ns ns ps rms ns ns ns ns V V µA µA pF V V 120 600 150 750 mA mW 0.005 0.012 V/V REV. B AD9070 Parameter DYNAMIC PERFORMANCE 5 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 41 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 41 MHz Effective Number of Bit fIN = 10.3 MHz fIN = 41 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 41 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 41 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz fIN = 41 MHz Temp Test Level AD9070BR Min Typ Max +25°C +25°C V V +25°C Full +25°C Full I V I V 55 +25°C Full +25°C Full I V I V 54 +25°C +25°C I I +25°C +25°C 5962-9756301HXC Min Typ Max 3 4 Units 3 4 ns ns 57 55 56 54 dB dB dB dB 56 54 54 52 dB dB dB dB 57 56 56 55 55 56 55 54 53 54 8.8 8.3 9.2 8.9 8.8 8.3 9.2 8.9 Bits Bits I I 63 58 70 63 63 58 70 63 dBc dBc +25°C +25°C I I 65 57 71 61 65 57 71 61 dBc dBc +25°C +25°C V V 70 60 dBc dBc 54 51 54 51 70 60 NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed –2.5 V external reference). 2 tV and tPD are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 10 pF. 3 Power dissipation is measured under the following conditions: f S 100 MSPS, analog input is –1 dBfs at 10.3 MHz. Power dissipation does not include the current of the external ECL pull-down resistors that set the current in the ECL output followers. 4 A change in input offset voltage with respect to a change in V EE. 5 SNR/harmonics based on an analog input voltage of –1.0 dBfs referenced to a 1.024 V full-scale input range. Typical thermal impedance for the R style (SOIC) 28-lead package: θJC = 23°C/W, θCA = 48°C/W, θJA = 71°C/W. Typical thermal impedance for the DH style (Ceramic DIP) 28-lead package: θJC = 8°C/W, θCA = 43°C/W, θJA = 51°C/W. Contact DSCC to obtain the latest revision of the 5962-9756301 drawing. Specifications subject to change without notice. SAMPLE N–1 SAMPLE N SAMPLE N+3 SAMPLE N+4 AIN SAMPLE N+1 tA tEH tEL SAMPLE N+2 1/fs ENCODE ENCODE tPD D9–D0 DATA N–4 DATA N–3 DATA N–2 DATA N–1 Figure 1. Timing Diagram REV. B –3– tV DATA N DATA N+1 AD9070 ABSOLUTE MAXIMUM RATINGS* Table I. Output Coding VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . VEE –1 V to +1.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VEE to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. Step AIN–AIN Code Twos Complement OR 1024 1023 1022 • • • 513 512 511 • • • 1 0 –1 ≥ 0.512 V 0.511 V 0.510 V • • • 0.001 V 0.000 V –0.001 V • • • –0.511 V –0.512 V ≤ –0.513 V >511 511 510 • • • 1 0 –1 • • • –511 –512 <512 01 1111 1111 01 1111 1111 01 1111 1110 • • • 00 0000 0001 00 0000 0000 11 1111 1111 • • • 10 0000 0001 10 0000 0000 10 0000 0000 1 0 0 • • • 0 0 0 • • • 0 0 1 II – 100% production tested at +25°C and sample tested at specified temperatures. III – Sample tested only. ORDERING GUIDE IV – Parameter is guaranteed by design and characterization testing. Model Temperature Range Package Option* AD9070BR –40°C to +85°C AD9070/PCB +25°C 5962-9756301HXC –55°C to +125°C V – Parameter is a typical value only. VI – 100% production tested at +25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. R-28 Evaluation Board DH-28 *DH = Ceramic DIP; R = Small Outline IC (SOIC). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9070 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. B AD9070 PIN FUNCTION DESCRIPTIONS Pin Numbers AD9070BR AD9070DIP R Package D Package Name Function 1, 7, 12, 21, 23 2, 8, 11, 20, 22 3 4 5 6 9 10 13 14 28–24, 19–15 N/A VEE GND VREF OUT VREF IN COMP REF BYPASS AIN AIN ENCODE ENCODE D9–D0 OR Negative Power Supply. Nominally –5.0 V. Ground. Internal Reference Output (–2.5 V typical); Bypass with 0.1 µF to Ground. Reference Input for ADC (–2.5 V typical). Internal Amplifier Compensation, 0.1 µF to VEE. Reference Bypass Node, 0.1 µF to VEE. Analog Input – Complement. Analog Input – True. Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE). Encode Clock Complement (ADC Samples on Falling Edge of ENCODE). Digital Outputs of ADC. D9 is the MSB. Data is twos complement. Out-of-Range Output. Goes HIGH when the converted sample is more positive than 1FFh or more negative than 200h (Twos Complement Coding). 1, 7, 9, 14, 21 2, 6, 8, 10, 13, 15, 22 N/A 3 N/A N/A 4 5 11 12 27–23, 20–16 28 PIN CONFIGURATIONS SOIC VEE 1 VEE 1 28 D9 (MSB) 28 OR 27 D9 (MSB) GND 2 27 D8 GND 2 VREF OUT 3 26 D7 VREF IN 3 26 D8 VREF IN 4 25 D6 AIN 4 25 D7 COMP 5 24 D5 AIN 5 24 D6 GND 6 AD9070DIP 23 D5 REF BYPASS 6 VEE 7 GND 8 AD9070BR 23 VEE TOP VIEW 22 GND (Not to Scale) 21 VEE VEE 7 GND 8 TOP VIEW 22 GND (Not to Scale) 21 VEE VEE 9 20 D4 AIN 10 19 D4 GND 10 19 D3 GND 11 18 D3 ENCODE 11 18 D2 VEE 12 17 D2 ENCODE 12 17 D1 ENCODE 13 16 D1 GND 13 ENCODE 14 15 D0 (LSB) AIN REV. B Ceramic DIP 9 20 GND VEE 14 –5– 16 D0 (LSB) 15 GND AD9070–Typical Circuit Applications AIN AIN D9 – D0 OR VEE VEE Figure 5. Equivalent Digital Output Circuit Figure 2. Equivalent Analog Input Circuit VREF OUT VREF IN VEE VEE Figure 6. Equivalent Reference Output Circuit Figure 3. Equivalent Reference Input Circuit ENCODE ENCODE VEE Figure 4. Equivalent Encode Input Circuit –6– REV. B Typical Performance Characteristics–AD9070 0 0 FUNDAMENTAL = –1.0dBfs SNR = 58.5dB SINAD = 58.0dB 2nd HARMONIC = –76.8dB 3rd HARMONIC = –68.1dB –10 –20 –30 –10 –30 –40 dB dB –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 0 5 10 15 20 25 MHz 30 35 40 45 50 0 5 10 15 20 25 MHz 30 35 40 45 50 Figure 10. Two Tone Intermodulation Distortion Figure 7. Spectrum: fS = 100 MSPS, fIN = 10 MHz 60 0 FUNDAMENTAL = –1.0dBfs SNR = 56.8dB SINAD = 55.0dB 2nd HARMONIC = –66.6dB 3rd HARMONIC = –60.8dB –10 –20 –30 55 SNR 50 45 –40 SINAD dB dB F1 = 40.1MHz F2 = 41.0MHz F1 = F2 = –7.0dBfs –20 –50 –60 40 NYQUIST FREQUENCY (50 MHz) 35 –70 30 –80 25 –90 –100 20 0 5 10 15 20 25 MHz 30 35 40 45 50 Figure 8. Spectrum: fS = 100 MSPS, fIN = 40 MHz –20 60 80 100 FIN – MHz 120 140 160 58 SNR 56 –30 54 –40 52 dB dB 40 60 F1 = 9.57MHz F2 = 10.3MHz F1 = F2 = –7.0dBfs –10 –50 SINAD 50 –60 48 –70 46 44 –80 42 –90 40 0 5 10 15 20 25 MHz 30 35 40 45 50 0 20 40 60 80 100 FS – MSPS 120 140 Figure 12. SNR vs. fS: fIN = 10.3 MHz Figure 9. Two Tone Intermodulation Distortion REV. B 20 Figure 11. SNR vs. fIN; fS = 100 MSPS 0 –100 0 –7– 160 AD9070 60 60 59 59 SNR 58 58 57 57 SINAD 56 dB dB 56 55 FS = 100MSPS FIN = 10.1MHz 54 FS = 100MSPS FIN = 10.1MHz 54 55 53 53 52 52 51 51 50 50 –60 0 –40 –20 0 20 40 60 T C – ⴗC 80 100 120 1 2 140 Figure 13. SNR vs. TC: BR Package (SOIC) 3 4 5 6 7 ENCODE PULSEWIDTH – ns 8 10 9 Figure 15. SNR vs. Clock Pulse Width (tEH) 60 0 59 SNR 58 –1 57 SINAD –2 dB dB 56 55 54 NYQUIST FREQUENCY 50MHz –3 FS = 100MSPS FIN = 10.1MHz 53 –4 52 51 –5 50 –60 –40 –20 0 20 40 60 T C – ⴗC 80 100 120 140 Figure 14. SNR vs. TC: DIP Package 0 50 100 150 FIN – MHz 200 250 300 Figure 16. Frequency Response –8– REV. B AD9070 APPLICATION NOTES Theory of Operation The AD9070 employs a two-step subranging architecture with digital error correction. The sampling and conversion process is initiated by a rising edge at the ENCODE input. The analog input signal is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit that captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The coarse quantizer (ADC) produces a five-bit estimate of the input value. Its digital output is reconverted to analog form by the reconstruction DAC and subtracted from the input signal in the SUM AMP. The second stage quantizer generates a six-bit representation of the difference signal. The eleven bits are presented to the ENCODE LOGIC, which corrects for range overlap errors and produces an accurate ten-bit result. Data are strobed to the output on the rising edge of the ENCODE input, with the data from sample N appearing on the output following ENCODE rising edge N+3. USING THE AD9070 ENCODE Input recommended. A better approach is to develop the required voltage from the internal or external converter voltage reference (VREF OUT). Very small timing errors can reduce the performance of an A/D dramatically. Total jitter of only 3.2 ps will limit the performance of an A/D sampling a full-scale 50 MHz signal to nine effective bits. The AD9070’s specified aperture jitter of 2.5 ps leaves only 2.0 ps of jitter budget for the clock source (an RSS calculation). The cleanest clock source is only a crystal oscillator producing a pure sine wave. In this configuration, or with any roughly symmetrical clock input, the input can be ac coupled and biased to a reference voltage that also provides the ENCODE input (Figure 17). This ensures that the reference voltage is centered on the ENCODE signal. Digital Outputs The digital outputs are compatible with 10K ECL logic. The suggested pull-down is 100 Ω to –2 V. However, to reduce power consumption, higher value pull-down resistors can be used when driving very low capacitance loads or at reduced encode rates. The falling edge slew rate of the output bits will be degraded with higher value pull-down resistors. Analog Input Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A Track/Hold circuit is essentially a mixer, and any noise, distortion or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9070 and the user is advised to give commensurate thought to the clock source. The ENCODE input is fully differential and may be operated in a differential or a single-ended mode. It has a common-mode range of –1 V to –3 V, and is easily driven by a differential ECL driver. Proper termination at the A/D is important. The analog input to the AD9070 is a differential amplifier, but the design has been optimized for a single-ended input. The AIN input should be connected or bypassed to the ground reference of the input signal. For best dynamic performance, impedances at AIN and AIN should match. The circuit in Figure 18 illustrates a simple ac-coupled interface. The midscale input voltage and the AIN levels are both provided by the internal reference (VREF OUT). 0.1F VIN 1Vp-p –5V GND AIN RT AD9070 AIN 500⍀ CLKIN (1Vp-p) GND VREF OUT 0.1F AD9070 0.1F ENCODE RT 10k⍀ VREF IN ENCODE ENCODE ENCODE ENCODE ENCODE 0.1F 1k⍀ D9 510⍀ (OR 100⍀ TO –2V) (MSB) D9 500⍀ VEE COMP 3k⍀ –5V (LSB) D0 REF VEE BYPASS D0 510⍀ (OR 100⍀ TO –2V) –5V 0.1F 0.1F –5V Figure 17. Single-Ended ENCODE: AC Coupled –5V In single-ended mode, the ENCODE input must be tied to an appropriate reference voltage, generally midway between the high and the low levels of the incoming logic signal. Many ECL circuits provide a VBB reference voltage intended for this purpose. If a reference voltage is produced by dividing the power supply voltage, any noise on the supply used will couple to the clock input and then to the output data. This is not REV. B Figure 18. AD9070 in –5 V (ECL) Environment –9– AD9070 Figure 19 shows typical connections for the analog inputs when using the AD9070 in a dc-coupled system with single-ended signals. The AD820 is used to offset the ground referenced input signal to the level required by the AD9070. A very high performance amplifier, such as the AD9631, is required to avoid degrading the analog signal presented to the ADC. A buffered ac interface is easily implemented, with even fewer components (Figure 20). –5V 350⍀ +5V VEE 350⍀ VIN ⴞ0.5V GND AIN RT AD9631 –5V AD9070 0.1F 1k⍀ The input is protected to one volt outside of the power supply rails. For nominal power (–5 V and ground), the analog input will not be damaged with signals ranging from –6.0 V to +1.0 V. Voltage Reference A stable and accurate –2.5 V voltage reference is built into the AD9070 (VREF OUT) in the SOIC (BR) package. In normal operation, the internal reference is used by strapping Pins 3 and 4 of the AD9070 together. The internal reference can provide 100 µA of extra drive current that may be used for other circuits. Some applications may require greater accuracy, improved temperature performance or adjustment of the gain of the AD9070, which cannot be obtained by using the internal reference. For these applications, an external –2.5 V reference can be connected to VREF IN, which requires 5 µA of drive current (Figure 21). 1k⍀ –5V AIN AD820 –5V 0.1F 1k⍀ VREF OUT VEE VREF IN NC 0.1F +VIN Figure 19. DC-Coupled Input VREF OUT AD9070 AD780 VOUT GND GND VREF IN 1.25k⍀ 0.1F –5V 350⍀ VIN 1Vp-p 350⍀ –5V +5V VEE 0.1F AIN RT 0.1F AD9631 500⍀ –5V 500⍀ Figure 21. Using the AD780 Voltage Reference GND AD9070 AIN 0.1F VREF OUT VREF IN 0.1F Figure 20. AC-Coupled Input Special care was taken in the design of the analog input section of the AD9070 to prevent damage and corruption of data when the input is overdriven. The nominal input range is –1.988 V to –3.012 V (1.024 V p–p centered at –2.5 V). Out-of-range comparators detect when the analog input signal is out of this range and set the OR output signal HIGH. The digital outputs are locked at plus or minus full scale (1FFh or 200h) for voltages that are out of range but between –1 V and –5 V. Input voltages outside of this range may result in invalid codes at the ADCs output. When the analog input signal returns to the nominal range, the out-of-range comparators return the ADC to its active mode and the device recovers in approximately 3 ns. The input range can be adjusted by varying the reference voltage applied to the AD9070. No appreciable degradation in performance occurs when the reference is adjusted ± 4%. The full-scale range of the ADC tracks reference voltage changes linearly. Timing The performance of the AD9070 is insensitive to the duty cycle of the clock over a wide range of operating conditions: pulse width variations of as much as ± 20% will cause no degradation in performance (see Figure 15). The AD9070 provides latched data outputs, with three pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (Figure 1). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9070; these transients can detract from the converter’s dynamic performance. The minimum guaranteed conversion rate of the AD9070 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance may degrade. The AD9070 will operate in bursts, but the user must flush the internal pipeline each time the clock restarts. Valid data will be produced on the fourth rising edge of the ENCODE signal after the clock is restarted. –10– REV. B AD9070 +5 V Operation Package Options The AD9070 may be operated above ground, with a single +5 V power supply. All power supply ground pins are connected to +5 V, and VEE pins are connected to ground (Figure 22). Care must be taken in connecting signals and determining bypass rails. The AD9070 is available in two packages. The BR package is a standard 28-lead Small Outline IC (SOIC). The DIP package is a ceramic Dual-in-Line Hybrid. The SOIC is offered in a commercial grade, and specified over the industrial (–40°C to +85°C) temperature range. The DIP is a full MIL-PRF-38534 QML version that operates from (–55°C to +125°C). The reference voltage (REF OUT) is still generated with respect to the positive rail, which is now +5 V. It is nominally +2.5 V, but its voltage with respect to ground will vary directly with changes in the power supply voltage (for example, if the power supply goes to +5.1 V, the reference becomes +2.6 V). The reference input is likewise processed with respect to +5 V. This dictates that these pins be bypassed to +5 V as well. However, the COMP and REF BYPASS pins must continue to be bypassed to the most negative supply, which is now ground. The AIN input must still be connected or bypassed to the ground reference of the input signal. The SOIC version includes the on-chip voltage reference, whereas the DIP does not. The DIP, however, provides the Overrange (OR) output, and includes reference and power supply bypassing, along with an internal compensation capacitor. Equivalent performance may be obtained with either part though, due to the internal bypassing, the DIP is not as sensitive to board layout and parasitics. +5V 0.1F VIN 1Vp-p GND AIN RT 500⍀ AD9070 AIN 10H (MSB) D9 D9 510⍀ (OR 100⍀ TO +3V) (LSB) D0 D0 510⍀ (OR 100⍀ TO +3V) VREF OUT 0.1F VREF IN 0.1F +5V ENCODE ENCODE ENCODE ENCODE COMP 0.1F REF VEE BYPASS 0.1F Figure 22. AD9070 in +5 V (PECL) Environment REV. B –11– AD9070 Data Out AD9070BR EVALUATION BOARD E1 E2 E3 AIN 1k⍀ 50⍀ AD780 REFERENCE VREF OUT 1 OF 2 10H176 HEX D FF VREF IN 1k⍀ COMP –5V BYPASS AIN AIN TO CARD CONNECT Voltage Reference AD9070 The AD9070 can be operated using its internal bandgap reference (connect E2 to E3) or the on board AD780 external reference (connect E1 to E3). The board is shipped utilizing the internal voltage reference. 1 OF 4 10H116 ENC ENC J2 CLK 10H176 ECL RECVR 50⍀ Layout E4 E6 E19 J4 Data goes single-ended into the 10H116 flip flops but comes out differentially. The data coming out of the AD9070 is in twos complement format, but is changed to straight binary by inverting the MSB at the connector (on the schematic Bit 1 and Bit 1B are swapped). The AD9070 is not layout sensitive if some important guidelines are met. The evaluation board layout provides an example where these guidelines have been followed to optimize performance. PIN 2 CLKB E8 50⍀ E9 BUFFERED AND LATCHED ON-CARD ENCODE E7 CARD CONNECTOR • Provide a good ground plane connecting the analog and digital sections. E5 PIN 21 Figure 23. The AD9070 evaluation board is a convenient and easy way to evaluate the performance of the AD9070 in the SOIC package. The board consists of an AD780 voltage reference (configured for –2.5 V), two 10H176 (hex D flip flop) for capturing data from the A/D converter and five 10H116 triple line receivers for buffering the encode signal and driving the data via the edge connector. Termination resistors (RP11, RP12, and RP14) are provided for the data leaving the board via the connector; (they can be removed if termination resistors are already provided by the user). • Excellent bypassing is essential. Chip caps with 0.1 µF values and 0603 dimensions are placed flush against the pins. Placing any of the caps on the bottom of the board can degrade performance. These techniques reduce the amount of parasitic inductance which can impact the bypassing ability of the caps. • Separate power planes and supplies for the analog and digital sections are recommended. The AD9070 evaluation board is provided as a design example for customers of Analog Devices. ADI makes no warranties express, statutory, or implied regarding merchantability or fitness for a particular purpose. Analog Input The evaluation board requires a 1 V peak-to-peak signal centered at ground (J1). This signal is ac coupled and then dc shifted –2.5 V before it is input to the A/D converter. Encode The AD9070 encode inputs can be driven single ended (connect E9 to E19 and drive J2 with an ECL signal) or differentially (connect E8 to E19 and drive J2 and J4 with differential ECL signals). The board is shipped in single ended configuration. The differential encode signal leaving the board via the connector can be inverted by interchanging E4, E5, E6, and E7 (connect E4 to E7 and E5 to E6 or E4 to E6 and E7 to E5). This ensures that the user will be able to capture the data coming from the evaluation board. –12– REV. B REV. B Figure 24. Evaluation Board Schematic –13– R4 1k⍀ C4 0.1F 11 C17 0.1F C41 0.1F C18 0.1F C42 0.1F C38 0.1F D1 D2 D3 D4 D5 GND 2 3 4 5 6 7 8 D1 D2 D3 D4 D5 GND 2 3 4 5 6 7 8 C16 0.1F E9 CLKB 8PB - 5.2 RP2 U11 10H116 R3 50⍀ 7 R5 50⍀ –5V C20 0.1F C39 0.1F GND –5V C40 0.1F U1 AD9070BR 2 3 4 5 6 C22 0.1F C28 0.1F C44 0.1F C23 0.1F C24 0.1F C32 0.1F GND ENC ENCB 6PB - 5.2 RP9 C58 C37 0.1F 10F LCLK C43 0.1F C52 0.1F U11 10H116 4 3 CLKB 2 CLK 5 U11 10H116 12 15 CLK DR 14 13 CLKB DRB C3 0.1F E2 GND C8 0.1F E1 OP 7 NC 6 VOUT 5 TRIM 8 C25 0.1F C34 0.1F 22 GND 20 GND 28 27 26 25 24 19 18 17 16 15 21 23 BIT4B BIT4 BIT5B BIT5 BIT6B BIT6 BIT7B BIT7 2 3 4 5 6 7 8 9 ADRB ADR BIT1 BIT1B BIT2B BIT2 BIT3B BIT3 2 3 4 5 6 7 8 9 VEE 3 VREFOUT VEE 4 VREFIN 5 (MSB) D9 COMP 6 D8 C6 REF R6 C7 D7 0.1F BYPASS 1.0k⍀ 0.1F D6 –5V –5V D5 9 AIN D4 10 AIN D3 13 ENCODE D2 14 ENCODE D1 1 V (LSB) D0 –5V EE 7 V –5V EE GND 12 V –5V EE GND 2 GND GND 11 GND GND 8 GND GND E3 NC 2 +VIN 3 TEMP 4 GND ENC R1 1.25k⍀ 6 U11 10H116 10 E19 E8 R10 50⍀ ENCB CLK 9 R2 50⍀ –5.2V GND –5V GND 8PB - 5.2 RP1 BNC J4 BNC J2 BNC J1 TB2 TB1 C2 1F 1 U2 AD780N 10PT - 5.2 RP12 10PT - 5.2 RP11 2 3 4 5 6 7 8 9 LCLK –5.2 LCLK 5 6 7 10 11 12 9 2 3 4 5 6 7 8 GND –5.2V GND R16 160⍀ R15 260⍀ D0 D1 D2 D3 D4 D5 CLK U15 10H176 Q0 Q1 Q2 Q3 Q4 Q5 Q0 Q1 Q2 Q3 Q4 Q5 2 Q6 3 Q7 4 Q8 13 Q9 14 Q10 15 2 Q1 3 Q2 4 Q3 13 Q4 14 Q5 15 Q6 Q7 Q8 Q9 Q10 GND 10PB - 5.2 RP17 U5 10H176 DR DRB Q1 Q2 Q3 Q4 10PT - 5.2 RP15 5 D0 6 D1 7 D2 10 D3 11 D4 12 D5 9 CLK LCLK BIT8B BIT8 BIT9B BIT9 BIT10B BIT10 C26 C29 0.1F 0.1F C35 0.1F 2 3 4 5 6 7 8 9 10PT - 5.2 RP14 13 12 10 9 5 Q9 4 Q10 13 12 10 Q6 9 5 Q7 4 Q8 13 12 Q3 10 9 5 Q4 4 Q5 13 Q2 12 10 DR DRB 9 5 Q1 4 Q2 Q1 Q1 Q0 Q0 VBB D0 Q2 Q2 Q1 Q1 Q0 Q0 VBB D2 D2 D1 D1 D0 Q2 Q2 Q1 Q1 Q0 Q0 VBB D2 D2 D1 D1 D0 D0 U10 10H116 D0 15 14 7 6 3 2 11 BIT1 BIT2B BIT1 BIT2B 15 BIT10 14 BIT10B 7 6 3 BIT9 2 BIT9B 11 15 BIT8 14 BIT8B 7 BIT6 6 BIT6B 3 BIT7 2 BIT7B 11 15 BIT5 Q2 14 Q2 BIT5B 7 Q1 BIT3 6 BIT3B Q1 3 Q0 BIT4 2 Q0 BIT4B 11 VBB U9 10H116 D1 D0 D0 D2 D1 D2 U8 10H116 Q2 D2 D2 D1 D1 D0 U7 10H116 C11 0.1F C12 0.1F C14 0.1F C15 0.1F E4 E5 E6 ADRB E7 ADR 1 GND 2 ADRB 3 BIT1B 4 BIT2B 5 BIT3B 6 BIT4B 7 BIT5B 8 BIT6B 9 BIT7B 10 BIT8B 11 BIT9B 12 BIT10B 13 14 15 16 17 18 19 GND 20 21 ADR 22 BIT1B 23 BIT2 24 BIT3 25 BIT4 26 BIT5 27 BIT6 28 BIT7 29 BIT8 30 BIT9 31 BIT10 32 33 34 35 36 37 C37DRPF CON1 AD9070 AD9070 Figure 25. Component Side Figure 27. Bottom Side Trace + Components Figure 26. Component Side Signal Traces Figure 28. Analog/Digital Split Power Plane –14– REV. B AD9070 Table II. Evaluation Board Bill of Materials ITEM QTY REFD DESCRIPTION 1 2 3 4 5 6 7 8 9 10 5 2 4 1 2 3 1 1 10 24 10H116 – TRIPLE DIFFERENTIAL LINE RECEIVER 10H176 – 10KH HIGH SPEED ECL 10PT-5.2 – 10P TER RES NTWK 6PB-5.2 – 6P BUSED RES NTWK 8291Z2 – 2-PIN TERMINAL BLOCK 8PB-5.2 – 8P BUSED RES NTWK AD780N – HIGH PREC VOLT REF AD9070R – AD9070 SOIC ECL ADC BCAP0603 – CER CHIP CAP 0603, .1 µF BCAP0805 – CER CHIP CAP 0805, .1 µF 11 12 13 14 15 16 17 18 2 3 1 1 2 1 4 1 U7–U11 U5, U15 RP11, RP12, RP14, RP15 RP9 TB1, TB2 RP1, RP2, RP7 U2 U1 C3, C4, C6, C7, C8, C32, C34, C35, C37, C52 C11, C12, C14–C18, C20, C22–C26, C28, C38–C44 C29, C58 J1, J2, J4 R1 R16 R4, R6 R15 R2, R3, R5, R10 CON1 19 20 1 10 C2 E1–E9, E19 REV. B –15– BCAPTAJD – CHIP TANT CAP, 10 µF BNC – BNC COAX CONN PCMT BRES1206 – SURF MT RES 1206, 1.25K BRES1206 – SURF MT RES 1206, 160 BRES1206 – SURF MT RES 1206, 1K BRES1206 – SURF MT RES 1206, 260 BRES1206 – SURF MT RES 1206, 50 C37DRPF – 37P D CONN RT ANG PLASTIC PCMT FEMALE T330A – TANT CAP, 1 µF W-HOLE – WIRE HOLE AD9070 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28–Lead SOIC (R–28) 1 14 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0118 (0.30) 0.0040 (0.10) C2996a–0–3/00 (rev. B) 15 0.4193 (10.65) 0.3937 (10.00) 28 0.2992 (7.60) 0.2914 (7.40) 0.7125 (18.10) 0.6969 (17.70) 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0.0192 (0.49) 0° SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead Hermetic Ceramic DIP (DH-28) 28 15 0.595 ± 0.010 (15.11 ± 0.25) 1 PIN 1 IDENTIFIERS 0.225 (5.72) MAX 14 0.050 ± 0.010 (1.27 ± 0.25) 1.400 ± 0.014 (35.56 ± 0.35) 0.150 (3.81) MIN 0.100 (2.54) 0.05 (1.27) TYP TYP SEATING PLANE 0.600 (15.24) REF PRINTED IN U.S.A. 0.018 ± 0.002 (0.46 ± 0.05) 0.010 ± 0.002 (0.25 ± 0.05) –16– REV. B