LT1019 Precision Reference U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Available at 2.5V, 4.5V, 5V, and 10V Plug-In Replacement for Present References Ultra-Low Drift: 3ppm/°C Typical Curvature Corrected Series or Shunt Operation Ultra-High Line Rejection: ≈0.5ppm/V Low Output Impedance: ≈ 0.02Ω Tight Initial Output Voltage: < 0.05% Can Be Heated for Drifts Below 2ppm/°C 100% Noise Tested Temperature Output The LT1019 is a third generation bandgap voltage reference utilizing thin film technology and a greatly improved curvature correction technique. Wafer level trimming of both reference and output voltage combines to produce units with high yields to very low TC and tight initial tolerance of output voltage. The LT1019 can both sink and source up to 10mA and can be used in either the series or shunt mode. This allows the reference to be used for both positive and negative output voltages without external components. Minimum input/ output voltage is less than 1V in the series mode, providing improved tolerance of low line conditions. UO APPLICATI ■ ■ ■ ■ ■ S The LT1019 is available in four voltages: 2.5V, 4.5V, 5V, and 10V. It is a direct replacement for most bandgap references presently available including AD580, AD581, REF-01, REF-02, MC1400, MC1404, and LM168. A/D and D/A Converters Precision Regulators Constant Current Sources V/F Converters Bridge Excitation For ultra-low drift applications (< 2ppm/°C), the LT1019 can be operated in a heated mode by driving an internal resistor with an external amplifier. Chip temperature can be externally set for minimum power consumption. UO TYPICAL APPLICATI Ultralinear Strain Guage 357Ω* 0.5W IN Output Voltage Drift 1.003 5V R3 2M OUT 350Ω BRIDGE LT1019-5 R2 20k GND + A1† LT301A R4 20k – ACTIVE ELEMENT –5V 357Ω* 0.5W –15V – A2 GAIN = 100 +LT1001 R5 2M R6** 2M LT1019 • TA01 *REDUCES REFERENCE AND AMPLIFIER LOADING TO ≈0. **IF R6 = R3, BRIDGE IS NOT LOADED BY R2 AND R4. † A1 VOS AND DRIFT ARE NOT CRITICAL BECAUSE A2 ACTS AS A DIFFERENTIAL AMPLIFIER. OUTPUT VOLTAGE (NORMALIZED) (V) 15V 1.002 10ppm/°C FULL TEMP RANGE “BOX” 1.001 LT1019 CURVE 1.000 0.999 0.998 0.997 –50 –25 5ppm/°C 0°C TO 70°C “BOX” UNCOMPENSATED “STANDARD” BANDGAP DRIFT CURVE 50 25 75 0 TEMPERATURE (˚C) 100 125 LT1019 • TA02 1 LT1019 W W W AXI U U ABSOLUTE RATI GS Input Voltage .......................................................... 40V Output Voltage (Note 1) LT1019-5, LT1019-10 ........................................ 16V LT1019-2.5, LT1019-4.5 ...................................... 7V Output Short-Circuit Duration (Note 1) VIN < 20V .................................................... Indefinite 20V ≤ VIN ≤ 35V ............................................. 10 sec Trim Pin Voltage ................................................... ±30V Temp Pin Voltage ..................................................... 5V Heater Voltage Continuous ......................................................... 18V Intermittent (30 sec)........................................... 32V Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW TOP VIEW NC* 8 NC* 1 7 6 OUTPUT INPUT 2 TEMP 5 3 NC* 1 8 NC* INPUT 2 7 HEATER TEMP 3 6 OUTPUT GND 4 5 TRIM HEATER TRIM 4 N8 PACKAGE 8-LEAD PLASTIC DIP GND (CASE) H PACKAGE 8-LEAD TO-5 METAL CAN *INTERNALLY CONNECTED. DO NOT CONNECT EXTERNALLY *INTERNALLY CONNECTED. DO NOT CONNECT EXTERNALLY. TJMAX = 100°C, θJA = 130°C/ W (N) TJMAX = 100°C, θJA = 130°C/ W (S) TJMAX = 150°C, θJA = 150°C/ W, θJC = 45°C/W ORDER PART NUMBER LT1019AMH-10 LT1019MH-10 LT1019ACH-10 LT1019CH-10 LT1019AMH-5 LT1019MH-5 LT1019ACH-5 LT1019CH-5 LT1019AMH-4.5 LT1019MH-4.5 LT1019ACH-4.5 LT1019CH-4.5 ORDER PART NUMBER LT1019AMH-2.5 LT1019MH-2.5 LT1019ACH-2.5 LT1019CH-2.5 ELECTRICAL CHARACTERISTICS LT1019ACN8-10 LT1019CN8-10 LT1019CS8-10 LT1019IN8-10 LT1019ACN8-5 LT1019CN8-5 LT1019CS8-5 LT1019IN8-5 S8 PART MARKING LT1019ACN8-4.5 LT1019CN8-4.5 LT1019CS8-4.5 LT1019IN8-4.5 LT1019ACN8-2.5 LT1019CN8-2.5 LT1019CS8-2.5 LT1019IN8-2.5 1910 1905 1945 1925 VIN = 15V, IOUT = 0, TJ = 25°C, unless otherwise noted. SYMBOL PARAMETER TC Output Voltage Temperature Coefficient (Note 2) CONDITIONS LT1019C (0°C to 70°C) LT1019M (– 55°C to 125°C) LT1019I (– 40°C to 85°C) ∆VOUT ∆VIN Line Regulation (Note 3) (VOUT + 1.5V) ≤ VIN ≤ 40V RR Ripple Rejection MIN Output Voltage Tolerance ● ● ● ● 50Hz ≤ f ≤ 400Hz ● 2 S8 PACKAGE 8-LEAD PLASTIC SOIC 90 84 LT1019A TYP MAX MIN LT1019 TYP MAX UNITS 0.002 0.05 0.02 0.2 % 3 5 5 10 5 8 5 20 25 20 ppm/°C ppm/°C ppm/°C 0.5 1.0 3 5 0.5 1.0 3 5 ppm/V ppm/V 110 90 84 110 dB dB LT1019 ELECTRICAL CHARACTERISTICS VIN = 15V, IOUT = 0, TJ = 25°C, unless otherwise noted. SYMBOL PARAMETER CONDITIONS ∆VOUT ∆IOUT Load Regulation Series Mode (Notes 3, 4) 0 ≤ IOUT ≤ 10mA* Load Regulation, Shunt Mode 1mA ≤ ISHUNT ≤ 10mA (Notes 4, 5) 2.5V, 4.5V, 5V 10V Thermal Regulation (Note 6) ∆P = 200mW, t = 50ms IQ MIN Quiescent Current Series Mode ● ● en MIN LTC1019 TYP MAX UNITS 0.02 0.05 0.08 0.02 0.05 0.08 mV/mA (Ω) mV/mA (Ω) 0.1 0.4 0.8 0.1 0.4 0.8 mV/mA (Ω) mV/mA (Ω) 0.1 0.5 0.1 0.5 ppm/mW 0.65 1.0 1.3 0.65 1.2 1.5 mA mA ● ● Minimum Shunt Current (Note 7) ● 0.5 0.8 0.5 0.8 mA Minimum Input/Output Voltage Differential IOUT ≤ 1mA IOUT = 10mA ● ● 0.9 1.1 1.3 0.9 1.1 1.3 V V Trim Range LT1019-2.5 LT1019-5 LT1019-10 ±3.5 ±6 ±3.5 5, – 13 ±3.5 5, – 27 Heater Resistance ISC LTC1019A TYP MAX Short-Circuit Current Output Connected to GND 2V ≤ VIN ≤ 35V Output Voltage Noise (Note 9) 10Hz ≤ f ≤ 1kHz 0.1Hz ≤ f ≤ 10Hz ● The ● denotes specifications which apply over the full operating temperature range. Note 1: These are high power conditions and are therefore guaranteed only at temperatures equal to or below 70°C. Input is either floating, tied to output, or held higher than output. Note 2: Output voltage drift is measured using the box method. Output voltage is recorded at TMIN, 25°C, and TMAX. The lowest of these three readings is subtracted from the highest and the resultant difference is divided by (TMAX – TMIN). Note 3: Line regulation and load regulation are measured on a pulse basis with low duty cycle. Effects due to die heating must be taken into account separately. See thermal regulation and application section. Note 4: Load regulation is measured at a point 1/8" below the base of the package with Kelvin contacts. Note 5: Shunt regulation is measured with the input floating. This parameter is also guaranteed with the input connected (VIN – VOUT) > 1V, 0mA ≤ ISINK ≤ 10mA. Shunt and sink current flow into the output. ±3.5 ±3.5 ±3.5 ±6 5, – 13 5, – 27 % % % 300 400 500 300 400 500 Ω 15 10 25 50 15 10 25 50 mA mA 2.5 2.5 4 2.5 2.5 4 ppm (RMS) ppm (P-P) Note 6: Thermal regulation is caused by die temperature gradients created by load current or input voltage changes. This effect must be added to normal line or load regulation. Note 7: Minimum shunt current is measured with shunt voltage held 20mV below the value measured at 1mA shunt current. Note 8: Minimum input/output voltage is measured by holding input voltage 0.5V above the nominal output voltage, while measuringVIN – VOUT. Note 9: RMS noise is measured with a single highpass filter at 10Hz and a 2-pole lowpass filter at 1kHz. The resulting output is full-wave rectified and then integrated for a fixed period, making the final reading an average as opposed to RMS. A correction factor of 1.1 is used to convert from average to RMS, and a second correction of 0.88 is used to correct the non-ideal bandpass of the filters. 3 LT1019 U W TYPICAL PERFOR A CE CHARACTERISTICS Quiescent Current (LT1019-4.5/LT1019-5) Quiescent Current (LT1019-10) 1.6 1.6 1.4 1.4 1.4 1.2 1.2 1.2 1.0 125°C 0.8 25°C –55°C 0.6 CURRENT (mA) 1.6 CURRENT (mA) CURRENT (mA) Quiescent Current (LT1019-2.5) 125°C 1.0 25°C 0.8 –55°C 0.6 0.4 0.2 0.2 0.2 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 0 45 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) LT1019 • TPC01 40 INPUT VOLTAGE/OUTPUT VOLTAGE (dB) TJ = 25°C OUTPUT CHANGE (mV) TJ = –55°C TJ = 25°C 2.5 LT1019-10 1.0 LT1019-4.5/LT1019-5 0.5 LT1019-2.5 0 –0.5 –1.0 –1.5 0 0 –2.0 –10 –8 –6 –4 –2 0 2 4 6 8 SINKING SOURCING OUTPUT CURENT (mA) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 INPUT/OUTPUT VOLTAGE (V) Shunt Mode Characteristics (LT1019-2.5) 1.0 LT1019-10 100 LT1019-2.5 90 70 60 50 0.4 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT-TO-GROUND VOLTAGE (V) 0.5 0.4 TJ = 125°C 0.2 TJ = 25°C TJ = –55°C TJ = 25°C TJ = –55°C 0.1 0 4.0 0.6 0.3 TJ = 125°C 0.1 LT1019 • TPC07 4 0.5 0.2 TJ = –55°C 0 0.6 0.3 TJ = 25°C 0 CURRENT (mA) 0.7 CURRENT (mA) 0.8 0.1 1M INPUT OPEN 0.9 0.7 0.2 100k 1.0 0.8 TJ = 125°C 1k 10k FREQUENCY (Hz) Shunt Mode Characteristics (LT1019-10) 0.7 0.3 100 LT1019 • TPC06 0.8 0.4 LT1019-4.5 LT1019-5 80 10 INPUT OPEN 0.9 0.5 45 40 10 1.0 INPUT OPEN 40 TJ = 25°C 110 Shunt Mode Characteristics (LT1019-5) 0.6 15 20 25 30 35 INPUT VOLTAGE (V) LT1019 • TPC05 LT1019 • TPC04 0.9 10 Ripple Rejection 1.5 TJ = 125°C 5 120 2.0 5.0 0 LT1019 • TPC03 Load Regulation 10 7.5 –55°C LT1019 • TPC02 Minimum Input/Output Voltage Differential OUTPUT CURRENT (mA) 0 45 25°C 0.6 0.4 0 125°C 0.8 0.4 0 CURRENT (mA) 1.0 0 0 7 6 4 1 3 2 5 OUTPUT-TO-GROUND VOLTAGE (V) 8 LT1019 • TPC08 0 8 2 6 4 10 12 14 OUTPUT-TO-GROUND VOLTAGE (V) 16 LT1019 • TPC09 LT1019 U W TYPICAL PERFOR A CE CHARACTERISTICS Temp Pin Voltage 140 0.85 120 0.75 0.70 0.65 0.60 0.55 0.50 0.45 10 IOUT TJ = 25°C 100 OUTPUT CAPACITOR (µF) OUTPUT VOLTAGE CHANGE (µV) 0.90 0.80 VOLTAGE (V) LT1019-2.5* Stability with Output Capacitance Line Regulation 80 60 LT1019-10 40 20 LT1019-2.5 LT1019-5 0 1 REGION OF POSSIBLE INSTABILITY 0.1 0.01 0.001 –10 –20 0.40 50 25 0 75 100 –50 –25 JUNCTION TEMPERATURE (°C) –30 125 0 5 10 15 20 25 30 INPUT VOLTAGE (V) LT1019 • TPC10 35 40 0.0001 20 0 10 15 20 15 10 5 5 SINK CURRENT SOURCE CURRENT OUTPUT CURRENT (mA) LT1019 • TPC12 LT1019 • TPC11 * LT1019-4.5/LT1019-5/LT1019-10 ARE STABLE WITH ALL LOAD CAPACITANCE. W BLOCK DIAGRA R1 LT1019-2.5 = 11k LT1019-4.5 = 13.9k LT1019-5 = 16k LT1019-10 = 37.1k VIN R3 80k – TRIM HEATER 400Ω R2 LT1019-4.5, LT1019-5, LT1019-10 = 5k LT1019-2.5 = 10k 1.188V VOUT + GND LT1019 • BD U U W U APPLICATIO S I FOR ATIO Line and Load Regulation Line regulation on the LT1019 is nearly perfect. A 10V change in input voltage causes a typical output shift of less than 5ppm. Load regulation (sourcing current) is nearly as good. A 5mA change in load current shifts output voltage by only 100µV. These are electrical effects, measured with low duty cycle pulses to eliminate heating effects. In real world applications, the thermal effects of load and line changes must be considered. Two separate thermal effects are evident in monolithic circuits. One is a gradient effect, where power dissipation on the die creates temperature gradients. These gradients can cause output voltage shifts even if the overall temperature coefficient of the reference is zero. The LT1019, unlike previous references, specifies thermal regulation caused by die temperature gradients.The specification is 0.5ppm/ mW. To calculate the effect on output voltage, simply multiply the change in device power dissipation by the 5 LT1019 U U W U APPLICATIO S I FOR ATIO thermal regulation specification. Example: a 10V device with a nominal input voltage of 15V and load current of 5mA. Find the effect of an input voltage change of 1V and a load current change of 2mA. ∆P (line change) = (∆VIN)(ILOAD) = (1V)(5mA) = 5mA ∆VOUT = (0.5ppm/mW)(5mW) = 2.5ppm ∆P (load change) = (∆ILOAD)(VIN – VOUT) = (2mA)(5V) = 10mW ∆VOUT = (0.5ppm/mW)(10mW) = 5ppm Even though these effects are small, they should be taken into account in critical applications, especially where input voltage or load current is high. The second thermal effect is overall die temperature change. The magnitude of this change is the product of change in power dissipation times the thermal resistance (θJA) of the IC package ≅ (100°C/W – 150°C/W). The effect on reference output is calculated by multiplying die temperature change by the temperature drift specification of the reference. Example: same conditions as above with θJA = 150°C/W and an LT1019 with 20ppm/°C drift specification. ∆P (line change) = 5mW ∆VOUT = (5mW)(150°C/W)(20ppm/°C) = 15ppm ∆P (load change) = 10mW ∆VOUT = (10mW)(150°C/W)(20ppm/°C) = 30ppm These calculations show that thermally induced output voltage variations can easily exceed the electrical effects. In critical applications where shifts in power dissipation are expected, a small clip-on heat sink can significantly improve these effects by reducing overall die temperature change. Alternately, an LT1019A can be used with four times lower TC. If warm-up drift is of concern, these measures will also help. With warm-up drift, total device power dissipation must be considered. In the example given, warm-up drift (worst case) is equal to: 6 Warm-up drift = [(VIN)(IQ) + (VIN – VOUT)(ILOAD)] [(θJA)(TC)] with IQ (quiescent current) = 0.6mA, Warm-up drift = [(15V)(0.6mA) + (5V)(5mA)] [(150°C/W)(25ppm/°C)] = 127.5ppm Note that 74% of the warm-up drift is due to load current times input/output differential. This emphasizes the importance of keeping both these numbers low in critical applications. With heavy loads, warm-up drift can also be improved using the technique described under “Driving Loads Above 10mA” or by heat sinking. Note that line regulation is now affected by reference output impedance. R1 should have a wattage rating high enough to withstand full input voltage if output shorts must be tolerated. Even with load currents below 10mA, R1 can be used to reduce power dissipation in the LT1019 for lower warm-up drift, etc. Output Trimming Output voltage trimming on the LT1019 is nominally accomplished with a potentiometer connected from output to ground with the wiper tied to the trim pin. The LT1019 was made compatible with existing references, so the trim range is large: + 6%, – 6% for the LT1019-2.5, + 5%, – 13% for the LT1019-5, and + 5%, – 27% for the LT1019-10. This large trim range makes precision trimming rather difficult. One solution is to insert resistors in series with both ends of the potentiometer. This has the disadvantage of potentially poor tracking between the fixed resistors and the potentiometer. A second method of reducing trim range is to insert a resistor in series with the wiper of the potentiometer. This works well only for very small trim range because of the mismatch in TCs between the series resistor and the internal thin film resistors. These film resistors can have a TC as high as 500ppm/°C. That same TC is then transferred to the change in output voltage: a 1% shift in output voltage causes a (500ppm)(1%) = 5ppm/°C change in output voltage drift. LT1019 U U W U APPLICATIO S I FOR ATIO The worst case error in initial output voltage for the LT1019 is 0.2%, so a series resistor is satisfactory if the output is simply trimmed to nominal value. The maximum TC shift expected would be 1ppm/°C. Using the Temp Pin The LT1019 has a TEMP pin like several other bandgap references. The voltage on this pin is directly proportional to absolute temperature (PTAT) with a slope of ≈ 2.1mV/°C. Room temperature voltage is therefore ≈ (295°K)(2.1mV/°C) = 620mV. Previous bandgap references have been very sensitive to any loading on the TEMP pin because it is an integral part of the reference “core” itself. The LT1019 “taps” the core at a special point which has much less effect on the reference. The relationship between TEMP pin loading and a change in reference output voltage is less than 0.05%/µA, about ten times improvement over previous references. Output Bypassing The LT1019 is designed to be stable with a wide range of load currents and output capacitors. The 4.5V, 5V, and 10V devices do not oscillate under any combination of capacitance and load. The 2.5V device can oscillate when sinking currents between 1mA and 6mA for load capacitance between 400pF and 2µF (see Figure 1). If output bypassing is desired to reduce high frequency output impedance, keep in mind that loop phase margin is significantly reduced for output capacitors between 500pF and 1µF if the capacitor has low ESR (Effective Series Resistance). This can make the output “ring” with transient loads. The best transient load response is obtained by deliberately adding a resistor to increase ESR as shown in Figure 1. VIN VIN LT1019 LT1019 2Ω TO 5Ω + 2Ω TO 5Ω + 2µF 2µF TO 10µF TANTALUM TANTALUM (a) (b) LT1019 • F01 Figure 1. Output Bypassing Use configuration (a) if DC voltage error cannot be compromised as load current changes. Use (b) if absolute minimum peak perturbation at the load is needed. For best transient response, the output can be loaded with ≥1mA DC current. U TYPICAL APPLICATIO S Wide Range Trim ≥ ±5% OUT VIN Narrow Trim Range (±0.2%) VIN LT1019 TRIM GND LT1019 • TA03 R1 25k VOUT OUT VOUT IN IN LT1019 TRIM GND R2* 1.5M R1 100k LT1019 • TA05 *INCREASE TO 4.7M FOR LT1019A (±0.05%) 7 LT1019 U TYPICAL APPLICATIO S Trimming LT1019-10 Output to 10.240V Trimming LT1019-5 Output to 5.120V VOUT VOUT OUT IN LT1019-5 TRIM GND VIN 41.2k 1% OUT IN LT1019-10 TRIM GND VIN 5k* ±1% TRIM 90.9k 1% 5k* ±1% TRIM 4.02k 1% 4.02k 1% LT1019 • TA04 *LOW TC CERMET LT1019 • TA06 *LOW TC CERMIT Negative Series Reference Precision 1µA Current Source 15V 11.5k 1% 5k* 8.25k 1% 2.49M 1% OUT V+ IN LT1019 R1* IN LT1019-2.5 TRIM GND D1* – Q1 2N2905 VOUT ±11V COMPLIANCE LT1012 *LOW TC CERMET, TRIM RANGE = ±1.5% Output Current Boost with Current Limit V + ≥ (VOUT + 2.8V) LED –VREF AT 50mA LT1019 • TA10 + V – – VREF *R1 = V – 5V , R2 = , D1 = VREF + 5V 1mA 2mA LT1019 • TA07 GLOWS IN CURRENT LIMIT (DO NOT OMIT) R1 220Ω 8.2Ω 2N2905 IN LT1019 OUT GND LT1019 • TA08 8 GND R2* + IOUT = 1mA ZOUT ≥ 1011Ω OUT ILOAD ≤ 100mA 2µF SOLID TANTALUM LT1019 U TYPICAL APPLICATIO S Negative 10V Reference for CMOS DAC OUT 59k 1% LT1019-10 TRIM GND 5k* fB 30pF 5.76k 1% CMOS DAC IOUT REF – + 1.2k VOUT LT1007 LT1019 • TA09 –15V *LOW TC CERMET, TRIM RANGE = ±1.5% W W SCHE ATIC DIAGRA VIN R23 100Ω Q29 R21 20Ω Q27 Q28 Q32 Q31 R20 750Ω Q30 R32 500Ω Q20 Q33 R24 850Ω Q25 Q26 R33 1k VOUT R25 1k R1 R26 3k R28 9k R34 4k R27 9k R17 500Ω R16 3k R15 3k Q4 Q3 Q5 Q6A Q34 R31 22k Q35 Q23 Q19 Q6B Q18 Q21 SHORT FOR 2.5 R19 15Ω Q24 C4 R35 27k C3 Q16 R2 R14 72k R4 R5 Q17 Q14 R6 Q1 780Ω R29 80k TRIM Q15 Q22 Q2 R7 1.6k R8 2.5k R9 3k R36 82k Q8 Q9 Q38 Q36 1k R39 Q10 Q37 R42 4k R12 7.2k R18 2k Q7 R38 3.75k R3 5k R37 2k R11A 1.9k R11B 1k Q11 Q12 Q13 HEATER R13 24.5k R40 400Ω GND 9 LT1019 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. H Package 8-Lead TO-5 Metal Can 0.335 – 0.370 (8.509 – 9.398) DIA 0.305 – 0.335 (7.747 – 8.509) 0.040 (1.016) MAX 0.050 (1.270) MAX SEATING PLANE 0.165 – 0.185 (4.191 – 4.699) REFERENCE PLANE GAUGE PLANE 0.500 – 0.750 (12.700 – 19.050) 0.010 – 0.045 (0.254 – 1.143) 0.016 – 0.021 (0.406 – 0.533) 0.027 – 0.045 (0.686 – 1.143) 45°TYP 0.027 – 0.034 (0.686 – 0.864) 0.200 – 0.230 (5.080 – 5.842) BSC 0.110 – 0.160 (2.794 – 4.064) INSULATING STANDOFF NOTE: LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND SEATING PLANE. H8(5) 0592 H8 Package 8-Lead Plastic DIP 0.400 (10.160) MAX 8 7 6 5 0.250 ± 0.010 (6.350 ± 0.254) 1 0.300 – 0.320 (7.620 – 8.128) 0.009 – 0.015 (0.229 – 0.381) ( 10 +0.025 0.325 –0.015 8.255 +0.635 –0.381 ) 2 0.045 – 0.065 (1.143 – 1.651) 3 4 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.020 (0.508) MIN N8 0392 LT1019 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic SOIC 0.189 – 0.197 (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157 (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0392 11 LT1019 U.S. Area Sales Offices NORTHEAST REGION Linear Technology Corporation One Oxford Valley 2300 E. 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Immeuble "Le Quartz" 58 Chemin de la Justice 92290 Chatenay Malabry France Phone: 33-1-41079555 FAX: 33-1-46314613 KOREA Linear Technology Korea Branch Namsong Building, #505 Itaewon-Dong 260-199 Yongsan-Ku, Seoul Korea Phone: 82-2-792-1617 FAX: 82-2-792-1619 GERMANY Linear Technology GMBH Untere Hauptstr. 9 D-85386 Eching Germany Phone: 49-89-3197410 FAX: 49-89-3194821 SINGAPORE Linear Technology Pte. Ltd. 101 Boon Keng Road #02-15 Kallang Ind. Estates Singapore 1233 Phone: 65-293-5322 FAX: 65-292-0398 TAIWAN Linear Technology Corporation Rm. 801, No. 46, Sec. 2 Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: 886-2-521-7575 FAX: 886-2-562-2285 UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-276-677676 FAX: 44-276-64851 JAPAN Linear Technology KK 5F YZ Bldg. Iidabashi, Chiyoda-Ku Tokyo, 102 Japan Phone: 81-3-3237-7891 FAX: 81-3-3237-8010 World Headquarters Linear Technology Corporation 1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507 06/24/93 12 Linear Technology Corporation LT/GP 0893 10K REV B • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1993