High Accuracy Ultralow IQ, 200 mA, SOT-23, anyCAP™ Low Dropout Regulator ADP3330 a FEATURES High Accuracy Over Line and Load: 60.7% @ +258C, 61.4% Over Temperature Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA Requires Only CO = 0.47 mF for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: <2 mA 2.9 V to 12 V Supply Range –408C to +858C Ambient Temperature Range Ultrasmall Thermally Enhanced Chip-on-Lead™ SOT-23-6 6-Lead Package FUNCTIONAL BLOCK DIAGRAM Q1 IN OUT ADP3330 THERMAL PROTECTION R1 CC ERR gm DRIVER R2 SD BANDGAP REF GND APPLICATIONS Cellular Telephones Notebook, Palmtop Computers Battery Powered Systems PCMCIA Regulator Bar Code Scanners Camcorders, Cameras GENERAL DESCRIPTION The ADP3330 is a member of the ADP330x family of precision low dropout anyCAP voltage regulators. The ADP3330 operates with an input voltage range of 2.9 V to 12 V and delivers a load current up to 200 mA. The ADP3330 stands out from the conventional LDOs with a novel architecture and an enhanced process that enables it to offer performance advantages and higher output current than its competition. Its patented design requires only a 0.47 µF output capacitor for stability. This device is insensitive to output capacitor Equivalent Series Resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types for space-restricted applications. The ADP3330 achieves exceptional accuracy of ± 0.7% at room temperature and ± 1.4% over temperature, line and load variations. The dropout voltage of the ADP3330 is only 140 mV (typical) at 200 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown mode, the ground current is reduced to less than 2 µA. The ADP3330 has ultralow quiescent current 34 µA (typ) in light load situations. The SOT-23-6 package has been thermally enhanced using Analog Devices’ proprietary Chip-on-Lead feature to maximize power dissipation. ERR NR ADP3330 VIN IN CIN 0.47mF + – OUT SD GND VOUT + – C OUT 0.47mF ON OFF Figure 1. Typical Application Circuit anyCAP and Chip-on-Lead are trademarks of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 ADP3330-xx–SPECIFICATIONS (@ TA = –408C to +858C, VIN = +7 V, CIN = 0.47 mF, COUT = 0.47 mF, unless otherwise noted).1, 2 The following specifications apply to all voltage options except –2.5. Parameter Symbol Conditions OUTPUT VOLTAGE ACCURACY VOUT VIN = VOUTNOM +0.25 V to +12 V IL = 0.1 mA to 200 mA TA = +25°C VIN = VOUTNOM +0.25 V to +12 V IL = 0.1 mA to 150 mA TA = –40°C to +85°C VIN = VOUTNOM +0.25 V to +12 V IL = 0.1 mA to 200 mA TA = –20°C to +85°C Min Typ Max Units –0.7 +0.7 % –1.4 +1.4 % –1.4 +1.4 % ∆V O ∆V IN ∆VO ∆I L VIN = VOUTNOM +0.25 V to +12 V TA = +25°C 0.04 mV/V IL = 0.1 mA to 200 mA TA = +25°C 0.04 mV/mA GROUND CURRENT IGND IL = 200 mA, TA = –20°C to +85°C IL = 150 mA IL = 50 mA IL = 0.1 mA 1.6 1.2 0.4 34 4.0 3.1 1.1 50 mA mA mA µA GROUND CURRENT IN DROPOUT IGND VIN = VOUTNOM – 100 mV IL = 0.1 mA 37 55 µA VOUT = 98% of VOUTNOM IL = 200 mA, TA = –20°C to +85°C IL = 150 mA IL = 10 mA IL = 1 mA 0.14 0.11 0.042 0.025 0.23 0.17 0.06 0.052 V V V V ILDPK VIN = VOUTNOM + 1 V 300 mA VNOISE f = 10 Hz–100 kHz, CL = 10 µF IL = 200 mA, CNR = 10 nF, VOUT = 3 V f = 10 Hz–100 kHz, CL = 10 µF IL = 200 mA, CNR = 0 nF, VOUT = 3 V 47 µV rms 95 µV rms LINE REGULATION LOAD REGULATION DROPOUT VOLTAGE PEAK LOAD CURRENT OUTPUT NOISE 3 SHUTDOWN THRESHOLD VDROP VTHSD ON OFF 2.0 0.4 V V SHUTDOWN PIN INPUT CURRENT ISD VIN = 12 V, 0 < SD, ≤ 12 V 0 < SD, ≤ 5 V 1.9 1.4 9 6 µA µA GROUND CURRENT IN SHUTDOWN MODE IGNDSD SD = 0 V, VIN = 12 V 0.01 2 µA OUTPUT CURRENT IN SHUTDOWN MODE IOSD TA = +25°C @ VIN = 12 V TA = +85°C @ VIN = 12 V 1 2 µA µA ERROR PIN OUTPUT LEAKAGE IEL VEO = 5 V 1 µA ERROR PIN OUTPUT “LOW” VOLTAGE VEOL ISINK = 400 µA 0.40 V 0.19 NOTES 1 Ambient temperature of +85°C corresponds to a junction temperature of +125°C under typical full load test conditions. 2 Application stable with no load. 3 See detail in Figure 19 and Application section of data sheet. Specifications subject to change without notice. –2– REV. A ADP3330 ADP3330-2.5–SPECIFICATIONS unless otherwise noted).1, 2 (@ TA = –408C to +858C, VIN = +7 V ,CIN = 0.47 mF, COUT = 0.47 mF, Parameter Symbol Conditions OUTPUT VOLTAGE ACCURACY VOUT VIN = +2.9 V to +12 V IL = 0.1 mA to 200 mA TA = +25°C VIN = +2.9 V to +12 V IL = 0.1 mA to 150 mA TA = –40°C to +85°C VIN = +2.9 V to +12 V IL = 0.1 mA to 200 mA TA = –20°C to +85°C Min Typ Max Units –0.7 +0.7 % –1.4 +1.4 % –1.4 +1.4 % ∆V O ∆V IN ∆VO ∆I L VIN = +2.9 V to +12 V TA = +25°C 0.04 mV/V IL = 0.1 mA to 200 mA TA = +25°C 0.04 mV/mA GROUND CURRENT IGND IL = 200 mA, TA = –20°C to +85°C IL = 150 mA IL = 50 mA IL = 0.1 mA 1.6 1.2 0.4 34 4.0 3.1 1.1 50 mA mA mA µA GROUND CURRENT IN DROPOUT IGND VIN = VOUTNOM – 100 mV IL = 0.1 mA 37 55 µA VOUT = 98% of VOUTNOM IL = 200 mA, TA = –20°C to +85°C IL = 150 mA IL = 10 mA IL = 1 mA 0.14 0.11 0.042 0.025 0.4 0.3 0.06 0.052 V V V V ILDPK VIN = VOUTNOM + 1 V 300 mA VNOISE f = 10 Hz–100 kHz, CL = 10 µF IL = 200 mA, CNR = 10 nF, VOUT = 3 V f = 10 Hz–100 kHz, CL = 10 µF IL = 200 mA, CNR = 0 nF, VOUT = 3 V 47 µV rms 95 µV rms LINE REGULATION LOAD REGULATION DROPOUT VOLTAGE PEAK LOAD CURRENT OUTPUT NOISE 3 SHUTDOWN THRESHOLD VDROP VTHSD ON OFF 2.0 0.4 V V SHUTDOWN PIN INPUT CURRENT ISD VIN = 12 V, 0 < SD, ≤ 12 V 0 < SD, ≤ 5 V 1.9 1.4 9 6 µA µA GROUND CURRENT IN SHUTDOWN MODE IGNDSD SD = 0 V, VIN = 12 V 0.01 2 µA OUTPUT CURRENT IN SHUTDOWN MODE IOSD TA = +25°C @ VIN = 12 V TA = +85°C @ VIN = 12 V 1 2 µA µA ERROR PIN OUTPUT LEAKAGE IEL VEO = 5 V 1 µA ERROR PIN OUTPUT “LOW” VOLTAGE VEOL ISINK = 400 µA 0.40 V NOTES 1 Ambient temperature of +85°C corresponds to a junction temperature of +125°C under typical full load test conditions. 2 Application stable with no load. 3 See detail in Figure 19 and Application section of data sheet. Specifications subject to change without notice. REV. A –3– 0.19 ADP3330 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS* Input Supply Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . . –0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . . –40°C to +85°C Operating Junction Temperature Range . . . . –40°C to +125°C θJA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . +165°C/W θJA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . +190°C/W Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Pin Name Function 1 OUT 2 3 IN ERR 4 5 GND NR 6 SD Output of the Regulator. Bypass to ground with a 0.47 µF or larger capacitor. Regulator Input. Open Collector Output that goes low to indicate that the output is about to go out of regulation. Ground Pin. Noise Reduction Pin. Used for further reduction of output noise (see text for detail). No connection if not used. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ORDERING GUIDE Model Voltage Output Package Option* Marking Code ADP3330ART-2.5 ADP3330ART-2.75 ADP3330ART-2.85 ADP3330ART-3 ADP3330ART-3.3 ADP3330ART-3.6 ADP3330ART-5 2.5 V 2.75 V 2.85 V 3.0 V 3.3 V 3.6 V 5.0 V RT-6 (SOT-23-6) RT-6 (SOT-23-6) RT-6 (SOT-23-6) RT-6 (SOT-23-6) RT-6 (SOT-23-6) RT-6 (SOT-23-6) RT-6 (SOT-23-6) L1B L2B L3B L4B L5B L6B L8B PIN CONFIGURATION OUT 1 IN 2 ADP3330 6 SD 5 NR TOP VIEW ERR 3 (Not to Scale) 4 GND *Contact the factory for the availability of other output voltage options. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3330 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A Typical Performance Characteristics–ADP3330 3.010 IL = 0mA 3.004 IL = 10mA 3.002 IL = 50mA 3.000 IL = 100mA 2.998 IL = 150mA 2.996 2.994 3.003 40 IL = 100mA GROUND CURRENT – mA 3.006 VOUT = 3V VOUT = 3.0V VIN = 7V 3.004 OUTPUT VOLTAGE – Volts OUTPUT VOLTAGE – Volts 3.008 45 3.005 VOUT = 3.0V 3.002 3.001 3.000 2.999 2.998 2.997 2.992 6 7 8 9 10 INPUT VOLTAGE – Volts 11 12 Figure 2. Line Regulation Output Voltage vs. Supply Voltage 0 25 Figure 3. Output Voltage vs. Load Current IL = 0mA 1.0 0.8 0.6 0.4 IL = 50mA 0.2 IL = 150mA 0.1 IL = 200mA 0.0 GROUND CURRENT – mA 0.3 OUTPUT VOLTAGE – % GROUND CURRENT – mA 1.4 0.2 50 100 150 OUTPUT LOAD – mA –0.1 –45 –25 –5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE – 8C 200 Figure 5. Ground Current vs. Load Current Figure 6. Output Voltage Variation % vs. Junction Temperature 0 2 4 6 8 10 INPUT VOLTAGE – Volts 12 3.0 VIN = 7V 2.8 IL = 200mA 2.6 2.4 2.2 IL = 150mA 2.0 1.8 IL = 100mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 IL = 50mA 0.2 IL = 0mA 0 –45 –25 –5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE – 8C Figure 7. Ground Current vs. Junction Temperature 3.5 150 100 50 0 25 50 75 100 125 150 175 200 OUTPUT LOAD – mA Figure 8. Dropout Voltage vs. Output Current REV. A CL = 0.47mF VOUT – Volts 200 VOUT = 3V SD = VIN RL = 15V 3.0 2.5 2.0 3 2 0 1.0 10 0.5 0 0 1.0 2.0 3.0 TIME – Sec 4.0 5.0 Figure 9. Power-Up/Power-Down –5– CL = 10mF 1 1.5 VIN – Volts INPUT/OUTPUT VOLTAGE – Volts 250 INPUT/OUTPUT VOLTAGE – mV 10 Figure 4. Ground Current vs. Supply Voltage 0.4 1.2 0 15 50 75 100 125 150 175 200 OUTPUT LOAD – mA VIN = 7V 0 20 0 2.994 1.6 0 25 5 2.995 5 IL = 0mA 30 2.996 IL = 200mA 2.990 3.25 4 35 VIN = 7V VOUT = 3V SD = VIN RL = 15V 5 0 0 100 200 300 TIME – ms 400 500 Figure 10. Power-Up Response ADP3330 3.100 3.020 VOUT = 3V RL = 15V CL = 0.47mF 2.980 3.000 VOUT = 3V RL = 15V CL = 10mF 2.980 3.000 2.940 2.940 200 7.0 100 200 300 TIME – ms 400 3.050 20mA 0 100 200 300 TIME – ms 400 500 3 0 0 2 400 IOUT mA 200 0 VERR 3 0 2 100 100 20mA VSD VIN = 7V 0 0 0 200 400 600 800 0 1000 TIME – ms Figure 14. Load Transient Response 400 600 TIME – ms RMS NOISE – mV –60 CL = 0.47mF CNR = 0 CL = 10mF IL = 200mA –70 IL = 200mA 100 80 60 IL = 0mA IL = 200mA WITH NOISE REDUCTION 40 –80 CL = 10mF IL = 0.1mA –90 100 1k 10k 100k FREQUENCY – Hz 20 1M 10M Figure 17. Power Supply Ripple Rejection 0 0 1000 1 120 CL = 0.47mF IL = 200mA 800 Figure 16. Turn On–Turn Off Response VOLTAGE NOISE SPECTRAL DENSITY – mV/ Hz CL = 0.47mF IL = 0.1mA –30 –100 10 200 140 –20 –50 0 160 VOUT = 3.0V –10 –40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME – Sec Figure 15. Short Circuit Current 0 1000 1 300 200 800 VIN = 7V VOUT = 3V CL = 10mF RL = 15V 3 VOUT 2.900 0 600 VOUT Volts 2.950 400 Figure 13. Load Transient Response 500 VIN = 7V VOUT = 3V CL = 10mF 200 TIME – ms Figure 12. Line Transient Response 3.000 RIPPLE REJECTION – dB 100 7.0 0 Volts 3.100 mA 7.5 500 Figure 11. Line Transient Response mA 2.900 VIN – Volts 2.960 7.5 VIN = 7V VOUT = 3V CL = 0.47mF 2.950 2.960 0 Volts 3.050 Volts VOUT – Volts 3.000 VIN – Volts VOUT – Volts 3.020 CL = 10mF CNR = 0 CL = 0.47mF CNR = 10nF 0.1 CL = 10mF CNR = 10nF VOUT = 3.0V IL = 200mA IL = 0mA WITH NOISE REDUCTION 10 20 30 CL – mF 40 Figure 18. RMS Noise vs. CL (10 Hz–100 kHz) –6– 50 0.01 10 100 1k 10k FREQUENCY – Hz 100k 1M Figure 19. Output Noise Density REV. A ADP3330 THEORY OF OPERATION The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitance. The new anyCAP LDO ADP3330 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 which is varied to provide the available output voltage options. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. INPUT Most LDOs place strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. OUTPUT COMPENSATION ATTENUATION R1 CAPACITOR (VBANDGAP/VOUT) Q1 NONINVERTING WIDEBAND DRIVER gm R3 PTAT VOS D1 (a) R4 PTAT CURRENT CLOAD RLOAD R2 With the ADP3330 anyCAP LDO, this is no longer true. It can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. The innovative design allows the circuit to be stable with just a small 0.47 µF capacitor on the output. Additional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain which leads to excellent line and load regulation. An impressive ± 1.4% accuracy is guaranteed over line, load and temperature. ADP3330 GND Figure 20.␣ Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature-proportional input “offset voltage” that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the tradeoff of noise sources that leads to a low noise design. Additional features of the circuit include current limit, thermal shutdown and noise reduction. Compared to standard solutions that give warning after the output has lost regulation, the ADP3330 provides improved system performance by enabling the ERR pin to give warning just before the device loses regulation. As the chip’s temperature rises above +165°C, the circuit activates a soft thermal shutdown, indicated by a signal low on the ERR pin, to reduce the current to a safe level. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1, and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. REV. A –7– ADP3330 APPLICATION INFORMATION Capacitor Selection Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3330 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3330 is stable with extremely low ESR capacitors (ESR ≈ 0), such as Multilayer Ceramic Capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum at cold temperature. Ensure that the capacitor provides more than 0.47 µF at minimum temperature. SILICON DIE a. Normal SOT-23-6 Package SILICON DIE WITH ELECTRICALLY ISOLATED DIE ATTACH Input Bypass Capacitor: an input bypass capacitor is not strictly required but it is advisable in any application involving long input wires or high source impedance. Connecting a 0.47 µF capacitor from IN to ground reduces the circuit’s sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended. b. Thermally Enhanced Chip-on-Lead Package Figure 22. Thermal Overload Protection Noise Reduction The ADP3330 is protected against damage due to excessive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of +165°C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above +165°C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. A noise reduction capacitor (CNR) can be used to further reduce the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in 10 pF–500 pF range provide the best performance. Since the noise reduction pin (NR) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible and long PC board traces are not recommended. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed +125°C. When adding a noise reduction capacitor, use the following guidelines: • Maintain a minimum load current of 1 mA when not in shutdown. Calculating Junction Temperature • For CNR values greater than 500 pF, add a 100 kΩ series resistor (RNR). Device power dissipation is calculated as follows: It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values greater than 1 nF, this delay may be on the order of several milliseconds. Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. PD = (V IN – VOUT) ILOAD +(VIN) IGND Assuming ILOAD = 200 mA, IGND = 4 mA, VIN = 4.2 V and VOUT = 3.0 V, device power dissipation is: NR VIN IN C1 + 0.47mF – OUT R1 ERR SD PD = (4.2 – 3) 200 mA + 4.2 (4 mA) = 257 mW CNR RNR ADP3330-3 330kV The proprietary package used in the ADP3330 has a thermal resistance of 165°C/W, significantly lower than a standard 6-lead SOT-23 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to: VOUT = +3.3V + C2 – 0.47mF GND ∆TJA = 0.257 W × 165°C/W = 42.4°C Figure 21.␣ Noise Reduction Circuit To limit the maximum junction temperature to +125°C, maximum allowable ambient temperature will be: Chip-on-Lead Package The ADP3330 uses a patented Chip-on-Lead package design to ensure the best thermal performance in an SOT-23 footprint. In a standard SOT-23, the majority of the heat flows out of the ground pin. This new package uses an electrically isolated die attach that allows all pins to contribute to heat conduction. This technique reduces the thermal resistance to 190°C/W on a 2-layer board as compared to >230°C/W for a standard SOT-23 leadframe. Figure 22 shows the difference between the standard SOT-23 and the Chip-on-Lead leadframes. TA MAX = 125°C – 42.4°C = 82.6°C –8– REV. A ADP3330 Printed Circuit Board Layout Considerations Low Power, Low Dropout Applications All surface mount packages rely on the traces of the PC board to conduct heat away from the package. ADP3330 is well suited for applications such as cellular phone handsets that require low quiescent current and low dropout voltage features. ADP3330 draws 34 µA typical under light load situations (i.e., load current = 100 µA), which results in low power consumption when the cell phone is in standby mode. In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages one or more of the leads are fused to the die attach pad, significantly decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be attached to these fused pins. Figure 23 shows an application in which the ADP3330 is used in a handset to provide 2.75 V nominal output voltage. The cell phone is powered from 3 cell NiCd or 1 cell Li-Ion battery. ADP3330 guarantees an accuracy of 1.4%, even when the input/ output differential is merely 250 mV (worst case). This implies that the output is regulated and within specification even when the battery voltage has reached its end-of-discharge voltage of 3 V. The output voltage never falls below 2.7 V, even under worst case load and temperature conditions. The low dropout feature coupled with the high accuracy of the ADP3330 ensures that the system is reliably powered until the end of the life of the battery, which results in increased system talk time. The patented chip-on-lead frame design of the ADP3330 uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 165°C/W thermal resistance for an SOT-23-6 package, without any special board layout requirements, just relying on the normal traces connected to the leads. This yields a 17% improvement in heat dissipation capability as compared to a standard SOT-23-6 package. The thermal resistance can be decreased by, approximately, an additional 10% by attaching a few square cm of copper area to the VIN pin of the ADP3303 package. MINIMUM BATTERY VOLTAGE 3.0V It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3330’s pins since it will increase the junction to ambient thermal resistance of the package. 250mV MAXIMUM INPUT-OUTPUT OVERHEAD FOR 200mA OUTPUT CURRENT Error Flag Dropout Detector NOMINAL OUTPUT VOLTAGE 2.75V The ADP3330 will maintain its output voltage over a wide range of load, input voltage and temperature conditions. If the output is about to lose regulation by reducing the supply voltage below the combined regulated output and dropout voltages, the ERR flag will be activated. The ERR output is an open collector, which will be driven low. –1.4% OUTPUT VOLTAGE ACCURACY 2.712V ABSOLUTE MINIMUM OUTPUT VOLTAGE 2.700V Once set, the ERR flag’s hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load. 12mV TRANSIENT, LINE AND LOAD RESPECTIVE MARGIN Figure 23.␣ LDO Budgeting for a 3 Cell NiCd/1 Cell Li-Ion Supply Shutdown Mode Applying a TTL high signal to the shutdown (SD) pin, or tying it to the input pin, will turn the output ON. Pulling SD down to 0.4 V or below, or tying it to ground, will turn the output OFF. In shutdown mode, quiescent current is reduced to much less than 1 µA. REV. A END OF DISCHARGE VOLTAGE OF 3 CELL NiCd OR 1 CELL Li-Ion BATTERY –9– ADP3330 APPLICATION CIRCUITS Crossover Switch Higher Output Current The circuit in Figure 24 shows how two ADP3330s can be used to form a mixed supply voltage system. The output switches between two different levels selected by an external digital input. Output voltages can be any combination of voltages from the Ordering Guide of the data sheet. The ADP3330 can source up to 200 mA at room temperature without any heatsink or pass transistor. If higher current is needed, an appropriate pass transistor can be used, as in Figure 25, to increase the output current to 1 A. C1 100mF VIN = 3.85V TO 12V IN VOUT = 3.6V/2.5V OUT MJE253* VIN = 4.5V TO 8V IN ADP3330-3.6 OUTPUT SELECT 3V 0V VOUT = 3V@1A R1 50V OUT + SD ADP3330-3 GND SD C2 100mF ERR GND C1+ 1.0mF OUT IN ADP3330-2.5 + C2 0.47mF *AAVID531002 HEAT SINK IS USED Figure 25.␣ High Output Current Linear Regulator LOGIC SUPPLY SD GND Figure 24.␣ Crossover Switch –10– REV. A ADP3330 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3455a–0–8/99 6-Lead Surface Mount RT-6 (SOT-23-6) 0.122 (3.10) 0.106 (2.70) 0.071 (1.80) 0.059 (1.50) 6 5 4 1 2 3 0.118 (3.00) 0.098 (2.50) PIN 1 0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 10° 0.009 (0.23) 0° 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) PRINTED IN U.S.A. 0.059 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) REV. A –11– –12– PRINTED IN U.S.A. C3455a–0–8/99