Dual 350 MHz Low Power Amplifier AD8012* FEATURES Low Power 1.7 mA/Amplifier Supply Current Fully Specified for 5 V and +5 V Supplies High Output Current, 125 mA High Speed 350 MHz, –3 dB Bandwidth (G = +1) 150 MHz, –3 dB Bandwidth (G = +2) 2,250 V/s Slew Rate 20 ns Settling Time to 0.1% Low Distortion –72 dBc Worst Harmonic @ 500 kHz, RL = 100 –66 dBc Worst Harmonic @ 5 MHz, RL = 1 k Good Video Specifications (RL = 1 k, G = +2) 0.02% Differential Gain Error 0.06 Differential Phase Error Gain Flatness 0.1 dB to 40 MHz 60 ns Overdrive Recovery Low Offset Voltage, 1.5 mV Low Voltage Noise, 2.5 nV/√Hz Available in 8-Lead SOIC and 8-Lead MSOP FUNCTIONAL BLOCK DIAGRAM OUT1 1 8 +VS –IN1 2 7 OUT2 +IN1 3 6 –IN2 –VS 4 5 +IN2 AD8012 –40 G = +2 VOUT = 2V p-p RF = 750 –50 DISTORTION – dBc APPLICATIONS XDSL, HDSL Line Drivers ADC Buffers Professional Cameras CCD Imaging Systems Ultrasound Equipment Digital Cameras –60 THIRD –70 –80 SECOND PRODUCT DESCRIPTION The AD8012 is a dual, low power, current feedback amplifier capable of providing 350 MHz bandwidth while using only 1.7 mA per amplifier. It is intended for use in high frequency, wide dynamic range systems where low distortion and high speed are essential and low power is critical. With only 1.7 mA of supply current, the AD8012 also offers exceptional ac specifications such as 20 ns settling time and 2,250 V/µs slew rate. The video specifications are 0.02% differential gain and 0.06 degree differential phase, excellent for such a low power amplifier. In addition, the AD8012 has a low offset of 1.5 mV. –90 10 100 RL – Figure 1. Distortion vs. Load Resistance, VS = ± 5 V, Frequency = 500 kHz +VS + R1 + AMP 1 RL = 100 OR 135 VREF VIN The AD8012 is well suited for any application that requires high performance with minimal power. The product is available in standard 8-lead SOIC or MSOP packages and operates over the industrial temperature range –40°C to +85°C. 1k R2 VOUT LINE POWER IN dB – Np:Ns TRANSFORMER – –VS Figure 2. Differential Drive Circuit for XDSL Applications *Protected under U.S. Patent Number 5,537,079. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD8012–SPECIFICATIONS DUAL SUPPLY (@ T = 25C, V = 5 V, G = +2, R = 100 , R = R A S Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time Overdrive Recovery NOISE/HARMONIC PERFORMANCE Distortion Second Harmonic Third Harmonic Output IP3 IMD Crosstalk Input Voltage Noise Input Current Noise Differential Gain Differential Phase L F G = 750 , unless otherwise noted.) Conditions Min Typ G = +1, VOUT < 0.4 V p-p, RL = 1 kΩ G = +2, VOUT < 0.4 V p-p, RL = 1 kΩ G = +2, VOUT < 0.4 V p-p, RL = 100 Ω VOUT < 0.4 V p-p, RL = 1 kΩ/100 Ω VOUT = 4 V p-p VOUT = 4 V p-p VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p 0.02%, VOUT = 2 V p-p 2⫻ Overdrive 270 95 350 150 90 40/23 75 2,250 3 20 35 60 MHz MHz MHz MHz MHz V/µs ns ns ns ns –89/–73 –78/–62 –84/–72 –66/–52 30/40 –79/–77 –70 2.5 15 0.02/0.02 0.3/0.06 dBc dBc dBc dBc dBm dBc dB nV/√Hz pA/√Hz % Degrees VOUT = 2 V p-p, G = +2 500 kHz, RL = 1 kΩ/100 Ω 5 MHz, RL = 1 kΩ/100 Ω 500 kHz, RL = 1 kΩ/100 Ω 5 MHz, RL = 1 kΩ/100 Ω 500 kHz, ∆f = 10 kHz, RL = 1 kΩ/100 Ω 500 kHz, ∆f = 10 kHz, RL = 1 kΩ/100 Ω 5 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz, +Input, –Input f = 3.58 MHz, RL = 150 Ω/1 kΩ, G = +2 f = 3.58 MHz, RL = 150 Ω/1 kΩ, G = +2 DC PERFORMANCE Input Offset Voltage Open-Loop Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Bias Current Common-Mode Rejection Ratio Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short-Circuit Current ± 1.5 TMIN–TMAX VOUT = ± 2 V, RL = 100 Ω TMIN–TMAX +Input +Input +Input, –Input +Input, –Input, TMIN–TMAX VCM = ± 2.5 V 240 200 Operating Range Power Supply Rejection Ratio Unit mV mV kΩ kΩ –56 ± 3.8 –60 ± 4.1 kΩ pF µA µA dB V ± 3.85 70 0.1 ±4 125 500 Ω V mA mA POWER SUPPLY Supply Current/Amp 1.7 TMIN–TMAX Dual Supply ±4 ±5 500 450 2.3 ±3 G = +2 TMIN–TMAX Max ± 1.5 –58 –60 ± 12 ± 15 1.8 1.9 ± 6.0 mA mA V dB Specifications subject to change without notice. –2– REV. B AD8012 SINGLE SUPPLY (@ T = 25C, V = +5 V, G = +2, R = 100 , R = R A S Parameter DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time Overdrive Recovery NOISE/HARMONIC PERFORMANCE Distortion Second Harmonic Third Harmonic Output IP3 IMD Crosstalk Input Voltage Noise Input Current Noise Differential Gain Differential Phase L F G = 750 , unless otherwise noted.) Conditions Min Typ G = +1, VOUT < 0.4 V p-p, RL = 1 kΩ G = +2, VOUT < 0.4 V p-p, RL = 1 kΩ G = +2, VOUT < 0.4 V p-p, RL = 100 Ω VOUT < 0.4 V p-p, RL = 1 kΩ/100 Ω VOUT = 2 V p-p VOUT = 3 V p-p VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p 0.02%, VOUT = 2 V p-p 2⫻ Overdrive 220 90 300 140 85 43/24 60 1,200 2 25 40 60 MHz MHz MHz MHz MHz V/µs ns ns ns ns –87/–71 –77/–61 –89/–72 –78/–52 30/40 –77/–80 –70 2.5 15 dBc dBc dBc dBc dBm dBc dB nV/√Hz pA/√Hz 0.03/0.03 0.4/0.08 % Degrees VOUT = 2 V p-p, G = +2 500 kHz, RL = 1 kΩ/100 Ω 5 MHz, RL = 1 kΩ/100 Ω 500 kHz, RL = 1 kΩ/100 Ω 5 MHz, RL = 1 kΩ/100 Ω 500 kHz, RL = 1 kΩ/100 Ω 500 kHz, RL = 1 kΩ/100 Ω 5 MHz, RL = 100 Ω f = 10 kHz f = 10 kHz, +Input, –Input Black Level Clamped to +2 V, f = 3.58 MHz RL = 150 Ω/1 kΩ RL = 150 Ω/1 kΩ DC PERFORMANCE Input Offset Voltage Open-Loop Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Bias Current Common-Mode Rejection Ratio Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short-Circuit Current ±1 TMIN–TMAX VOUT = 2 V p-p, RL = 100 Ω TMIN–TMAX +Input +Input +Input, –Input +Input, –Input, TMIN–TMAX VCM = 1.5 V to 3.5 V 200 150 Operating Range Power Supply Rejection Ratio REV. B –60 1.2 to 3.8 1 to 4 50 0.1 0.9 to 4.2 100 500 Ω V mA mA 3 –58 –3– mV mV kΩ kΩ –56 1.5 to 3.5 1.55 Specifications subject to change without notice. Unit kΩ pF µA µA dB V POWER SUPPLY Supply Current/Amp TMIN–TMAX Single Supply ±3 ±4 400 450 2.3 ±3 G = +2 TMIN–TMAX Max –60 ± 12 ± 15 1.75 1.85 12 mA mA V dB AD8012 2.0 MAXIMUM POWER DISSIPATION MAXIMUM POWER DISSIPATION – W The maximum power that can be safely dissipated by the AD8012 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. The output stage of the AD8012 is designed for maximum load current capability. As a result, shorting the output to common can cause the AD8012 to source or sink 500 mA. To ensure proper operation, it is necessary to observe the maximum power derating curves. Direct connection of the output to either power supply rail can destroy the device. TJ = 150C 1.5 8-LEAD SOIC PACKAGE 1.0 0.5 8-LEAD MSOP 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – C 80 90 Figure 3. Plot of Maximum Power Dissipation vs. Temperature for AD8012 Test Circuits 750 750 750 VOUT RL VIN 49.9 0.1F 0.1F + + 750 VIN VOUT RL 53.6 +VS 0.1F 10F 10F 0.1F + + +VS 10F 10F –VS –VS Test Circuit 1. Gain = +2 Test Circuit 2. Gain = –1 –4– REV. B AD8012 ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air at +25°C. 8-Lead SOIC Package: JA = 155°C/W 8-Lead MSOP Package: JA = 200°C/W Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 SOIC Package (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range RM, R . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8012 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Range Package Description Package Options Branding AD8012AR AD8012AR-REEL AD8012AR-REEL7 AD8012ARM AD8012ARM-REEL AD8012ARM-REEL7 AD8012ARMZ* AD8012ARMZ-REEL* AD8012ARMZ-REEL7* –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 8-Lead SOIC 13” Tape and Reel 7” Tape and Reel 8-Lead MSOP 13” Tape and Reel 7” Tape and Reel 8-Lead MSOP 13” Tape and Reel 7” Tape and Reel R-8 R-8 R-8 RM-08 RM-08 RM-08 RM-08 RM-08 RM-08 H6A H6A H6A H6A H6A H6A *Z = Pb-free product. REV. B –5– AD8012–Typical Performance Characteristics 20mV 1V 5ns TPC 1. 100 mV Step Response; G = +2, VS = ±2.5 V or ±5 V, RL = 1 kΩ* 1V TPC 4. 4 V Step Response; G = –1, VS = ± 5 V, RL = 1 kΩ 20mV 10ns TPC 2. 4 V Step Response; G = +2, VS = ± 5 V, RL = 1 kΩ 20mV 10ns 5ns TPC 5. 100 mV Step Response; G = +2, VS = ±2.5 V or ±5 V, RL = 100 Ω* 500mV 5ns TPC 3. 100 mV Step Response; G = –1, VS = ± 2.5 V or ±5 V, RL = 1 kΩ* 10ns TPC 6. 2 V Step Response; G = +2, VS = ± 2.5 V, RL = 100 Ω *VS = ± 2.5 V operation is identical to VS = +5 V single-supply operation. –6– REV. B AD8012 1V 1V 10ns TPC 7. 4 V Step Response; G = +2, VS = ± 5 V, RL = 100 Ω 10ns TPC 10. 4 V Step Response; G = –1, VS = ± 5 V, RL = 100 Ω –40 G = +2 VOUT = 2V p-p RF = 750 DISTORTION – dBc –50 –60 THIRD –70 –80 SECOND 20mV 5ns –90 TPC 8. 100 mV Step Response; G = –1, VS = ±2.5 V or ±5 V, RL = 100 Ω* 10 100 RL – 1k TPC 11. Distortion vs. Load Resistance; VS = ± 5 V, Frequency = 500 kHz –40 DISTORTION dBc THIRD RL = 100 SECOND RL = 100 –60 THIRD RL = 1k –80 SECOND RL = 1k 500mV 10ns –100 1 FREQUENCY MHz TPC 9. 2 V Step Response; G = –1, VS = ± 2.5 V, RL = 100 Ω REV. B G = +2 VOUT = 2V p-p RF = 750 10 20 TPC 12. Distortion vs. Frequency; VS = ± 5 V –7– AD8012 0.5 0.5 G = +2 VO = 0.3V p-p RF = 750 RL = 100 VS = 5V NORMALIZED GAIN dB 0.3 0.2 G = +2 VO = 0.3V p-p RF = 750 RL = 100 VS = +5V 0.4 0.3 NORMALIZED GAIN dB 0.4 0.1 0 –0.1 –0.2 0.2 0.1 0 –0.1 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0.1 1 10 FREQUENCY MHz 100 0.1 TPC 13. Gain Flatness; VS = ± 5 V 100 TPC 16. Gain Flatness; VS = +5 V –40 5 G = +2 VOUT = 2V p-p RF = 750 VO = 0.3V p-p RF = 750 RL = 100 VS = 5V 4 3 NORMALIZED GAIN dB –50 SECOND DISTORTION – dBc 1 10 FREQUENCY MHz –60 –70 THIRD –80 2 1 0 –1 G = +10 –2 G = +1 G = +2 –3 –4 –90 10 100 RL – –5 1k 1 10 FREQUENCY MHz 500 TPC 17. Frequency Response; VS = ± 5 V TPC 14. Distortion vs. Load Resistance; VS = +5 V, Frequency = 500 kHz 9 –40 THIRD RL = 100 G = +2 RF = 750 RL = 100 VS = 5V 6 OUTPUT VOLTAGE dBV 3 DISTORTION – dBc 100 –60 SECOND RL = 1k SECOND RL = 100 –80 THIRD RL = 1k G = +2 VOUT = 2V p-p RF = 750 1V RMS 0 –3 –6 –9 –12 –15 –18 –21 –100 1 10 1 20 FREQUENCY – MHz 10 FREQUENCY MHz 100 500 TPC 18. Output Voltage vs. Frequency; VS = ± 5 V, G = +2, RL = 100 Ω TPC 15. Distortion vs. Frequency; VS = +5 V –8– REV. B AD8012 0 0 VIN = 0.2V p-p VS = 5V, +5V –10 –20 –20 –30 –30 –40 –40 –50 –60 –PSRR –50 –60 –70 –70 –80 –80 –90 –90 –100 0.03 0.1 –100 10 1 FREQUENCY – MHz 100 500 100k TPC 19. CMRR vs. Frequency; VS = ± 5 V, +5 V 1M 10M FREQUENCY – Hz 100M 500M TPC 22. PSRR vs. Frequency; VS = ± 5 V, +5 V 5 1k VO = 0.3V p-p RF = 750 RL = 100 VS = +5V 3 2 1 0 –1 G = +1 G = +10 –2 G = +2 –3 G = +2 RF = 750 100 OUTPUT RESISTANCE 4 NORMALIZED GAIN dB VS = +5V OR 5V G = +2 RF = 750 +PSRR PSRR – dB CMRR dB –10 10 VS = +5V VS = 5V 1 0.1 –4 –5 10 FREQUENCY – MHz 100 0.01 0.03 500 TPC 20. Frequency Response; VS = +5 V G = +2 RF = 750 RL = 100 VS = +5V 0 100 500 135 0 115 –40 95 –6 –9 TZ dB OUTPUT VOLTAGE dBV –3 10 1 FREQUENCY – MHz TPC 23. Output Resistance vs. Frequency 3 1VRMS 0.1 –12 –15 –18 PHASE –80 –120 75 55 –160 TZ(s) 35 –200 15 –240 –21 –24 –27 1 10 FREQUENCY MHz 100 –5 500 1k TPC 21. Output Voltage vs. Frequency; VS = +5 V, G = +2, RL = 100 Ω REV. B 10k 100k 1M 10M FREQUENCY Hz 100M –280 1G TPC 24. Open-Loop Transimpedance and Phase vs. Frequency –9– PHASE – Degrees 1 AD8012 9 7 SWING – V p-p G = +2 RF = 750 RL = 100 2V STEP OUTPUT VOLTAGE ERROR – 0.1%/DIV 5V 8 6 5 +5V 4 3 2 1 0.1% 0 10 100 LOAD – 1k 10k t=0 TPC 28. Settling Time, VS = ± 5 V 30 5 3.8 28 4 3.6 26 3.4 24 22 3.0 20 2.8 18 CURRENT NOISE +IN/–IN 16 14 2.4 2.2 VOLTAGE NOISE 2.0 100 1k 10k FREQUENCY – Hz 2 1 0 G = +1 –1 G = +10 –2 G = +2 –3 12 –4 10 100k –5 1 10 FREQUENCY – MHz 100 500 TPC 29. Frequency Response; VS = ± 5 V TPC 26. Noise vs. Frequency 9 0.5 RL = 1k f = 5MHz G = 2 R F = 750 0.3 NORMALIZED GAIN – dB 7 VO = 0.3V p-p G = +2 RF = 750 RL = 1k 0.4 8 6 RL = 100 5 4 3 2 0.2 0.1 0 –0.1 –0.2 –0.3 1 0 VO = 0.3V p-p RF = 750 RL = 1k 3 NORMALIZED GAIN dB 3.2 INPUT CURRENT NOISE – pA/ Hz 4.0 PEAK-TO-PEAK OUTPUT AT 5MHz (ⱕ1% THD) V INPUT VOLTAGE NOISE – nV/ Hz TPC 25. Output Swing vs. Load 2.6 5ns –0.4 3 4 5 6 7 8 9 TOTAL SUPPLY VOLTAGE V 10 –0.5 11 0.1 1 10 FREQUENCY – MHz 100 TPC 30. Gain Flatness; VS = ± 5 V TPC 27. Output Swing vs. Supply –10– REV. B AD8012 0.5 –20 DRIVER VO = 2V p-p RL = 100 –40 0.3 –50 –60 SIDE 1 –70 –80 SIDE 2 –90 0.2 0.1 0 –0.1 –0.2 –100 –0.3 –110 –0.4 –120 0.03 VO = 0.3V p-p RF = 750 RL = 1k 0.4 NORMALIZED GAIN – dB INPUT REFERRED ERROR – dB –30 –0.5 0.1 10 1 FREQUENCY – MHz 100 0.1 500 1 10 FREQUENCY – MHz 100 TPC 33. Gain Flatness; VS = +5 V TPC 31. Crosstalk vs. Frequency 5 VO = 0.3V p-p RF = 750 RL = 1k 4 NORMALIZED GAIN dB 3 +3V VOUT 0V 2 VIN 1 0V 0 0V G = +1 VIN –1 0V G = +10 –2 VOUT G = +2 –3 –3V –4 VOUT, 2V/DIV 20ns –5 1 10 FREQUENCY – MHz 100 500 TPC 34. Overdrive Recovery; VS = ± 5 V, G = +2, RF = 750 Ω, RL = 100 Ω, VIN = 3 V p-p (T = 1 µ s) TPC 32. Frequency Response; VS = +5 V REV. B –11– AD8012 THEORY OF OPERATION The AD8012 is a dual, high speed CF amplifier that attains new levels of bandwidth (BW), power, distortion, and signal swing capability. Its wide dynamic performance (including noise) is the result of both a new complementary high speed bipolar process and a new and unique architectural design. The AD8012 uses a two-gain stage complementary design approach versus the traditional single-stage complementary mirror structure sometimes referred to as the Nelson amplifier. Though twin stages have been tried before, they typically consumed high power since they were of a folded cascade design, similar to that of the AD9617. This design allows for the standing or quiescent current to add to the high signal or slew current-induced stages. In the time domain, the large signal output rise/fall time and slew rate is typically controlled by the small signal BW of the amplifier and the input signal step amplitude, respectively, and not the dc quiescent current of the gain stages (with the exception of input level shift diodes Q1/Q2). Using two stages versus one also allows for a higher overall gain bandwidth product (GBWP) for the same power, resulting in lower signal distortion and the ability to drive heavier external loads. In addition, the second-gain stage also isolates (divides down) A3’s input reflected load drive and the nonlinearities created, resulting in relatively lower distortion and higher open-loop gain. Overall, when high external load drive and low ac distortion is a requirement, a twin-gain stage integrating amplifier like the AD8012 will provide excellent results for lower power over the A1 IPN IPP traditional single stage complementary devices. In addition, because the AD8012 is a CF amplifier, closed-loop BW variations versus external gain variations (varying RN) will be much lower compared to a VF op amp, where the BW varies inversely with gain. Another key attribute of this amplifier is its ability to run on a single 5 V supply partially because of its wide common-mode input and output voltage range capability. For 5 V supply operation, the device consumes half the quiescent power (vs. 10 V supply) with little degradation in its ac and dc performance characteristics. See data sheet comparisons. DC GAIN CHARACTERISTICS Gain stages A1/A1B and A2/A2B combined provide negative feedforward transresistance gain as shown in Figure 4. Stage A3 is a unity-gain buffer that provides external load isolation to A2. Each stage uses a symmetrical complementary design (A3 is also complementary though not explicitly shown). This is done to reduce both second-order signal distortion and overall quiescent power as previously described. In the quasi dc to low frequency region, the closed-loop gain relationship can be approximated as: noninverting operation G = –RF /RN inverting operation These basic relationships are common to all traditional operational amplifiers. CD Z1 = R1 || C1 Z1 –VI IQ1 G = 1+ RF /RN A2 C P1 C P2 Q3 ICQ + IO IR + IFC Q1 VN Ð VP + VOI ZI A3 Z2 Q2 RF IE IR – IFC Q4 VO RL CL RN ICQ – IO Z1 IQ1 –VI INP IPN A2 C P1 AD8012 A1 CD Figure 4. Simplified Block Diagram –12– REV. B AD8012 APPLICATIONS Line Driving for HDSL TO RECEIVER CIRCUITRY High bitrate digital subscriber line (HDSL) is becoming popular as a means of providing full duplex data communication at rates up to 1.544 MBPS or 2.048 MBPS over moderate distances via conventional telephone twisted pair wires. Traditional T1 (E1 in Europe) requires repeaters every 3,000 feet to 6,000 feet to boost the signal strength and allow transmission over distances of up to 12,000 feet. In order to achieve repeaterless transmission over this distance, an HDSL modem requires a transmitted power level of 13.5 dBm (assuming a line impedance of 135 Ω). +3 0.88V –1 –0.88V –3 –2.64V +1 11 –3 00 –3 00 +1 11 +3 10 –3 00 –1 01 –1 01 +1 11 –1 01 RG 1.5k 66.5 RF 12V p-p 750 6V p-p 135 66.5 0.1F 1:1 1:1 –5V GAIN = +2 The immediate effect of back-termination is that the signal from the amplifier is halved before being applied to the line. This doubles the power the amplifier must deliver. However, the back-termination resistors also play an important second role. Full-duplex data transmission systems like HDSL simultaneously transmit data in both directions. As a result, the signal on the line and across the back termination resistors is the composite of the transmitted and received signal. The termination resistors are used to tap off this signal and feed it to the receive circuitry. Because the receive circuitry “knows” what is being transmitted, the transmitted data can be subtracted from the digitized composite signal to reveal the received data. Driving a line with a differential signal offers a number of advantages compared to a single-ended drive. Because the two outputs are always 180 degrees out of phase relative to one another, the differential signal output is double the output amplitude of either of the op amps. As a result, the differential amplifier can have a peak-to-peak swing of 16 V (each op amp can swing to ± 4 V), even though the power supply is ± 5 V. –3 00 Figure 5. Time Domain Representation of an HDSL Signal Many of the elements of a classic differential line driver are shown in the HDSL line driver in Figure 6. A 6 V peak-to-peak differential signal is applied to the input. The differential gain of the amplifier (1+2 RF/RG) is set to +2, so the resulting differential output signal is 12 V p-p. As is normal in telephony applications, a transformer galvanically isolates the differential amplifier from the line. In this case, a 1:1 turns ratio is used. In order to correctly terminate the line, it is necessary to set the output impedance of the amplifier to be equal to the impedance of the line being driven (135 Ω in this case). Because the transformer has a turns ratio of 1:1, the impedance reflected from the line is equal to the line impedance of 135 Ω (RREFL = RLINE/Turns Ratio2). As a result, two 66.5 Ω resistors correctly terminate the line. REV. B 6V p-p UP TO 12,000 FEET Figure 6. Differential for HDSL Applications DAC OUTPUT +3 10 RF 750 TO RECEIVER CIRCUITRY FILTERED OUTPUT TO LINE DRIVER –1 01 0.1F 1/2 AD8012 2.64V +1 + – HDSL uses the two binary/one quaternary line code (2B1Q). A sample 2B1Q waveform is shown in Figure 5. The digital bit stream is broken up into groups of two bits. Four analog voltages (called quaternary symbols) are used to represent the four possible combinations of two bits. These symbols are assigned the arbitrary names +3, +1, –1, and –3. The corresponding voltage levels are produced by a DAC that is usually part of an analog front end circuit (AFEC). Before being applied to the line, the DAC output is low-pass filtered and acquires the sinusoidal form shown in Figure 5. Finally, the filtered signal is applied to the line driver. The line voltages that correspond to the quaternary symbols +3, +1, –1, and –3 are 2.64 V, 0.88 V, –0.88 V, and –2.64 V. This gives a peak-to-peak line voltage of 5.28 V. SYMBOL NAME VOLTAGE +5V 1/2 AD8012 In addition, even-order harmonics (second, fourth, sixth, and so on.) of the two single-ended outputs tend to cancel out one another, so the total harmonic distortion (quadratic sum of all harmonics) decreases compared to the single-ended case, even as the signal amplitude is doubled. This is particularly advantageous in the case of the second harmonic. Because it is very close to the fundamental, filtering becomes difficult. In this application, the THD is dominated by the third harmonic, which is 65 dB below the carrier (i.e., spurious-free dynamic range = –65 dBc). Differential line driving also helps to preserve the integrity of the transmitted signal in the presence of electromagnetic interference (EMI). EMI tends to induce itself equally onto both the positive and negative signal lines. As a result, a receiver with good common-mode rejection will amplify the original signal while rejecting induced (common-mode) EMI. –13– AD8012 Choosing the Appropriate Turns Ratio for the Transformer Increasing the peak-to-peak output signal of the amplifier in the previous example and adding a variation in the turns ratio of the transformer can yield further enhancements to the circuit. The output signal swing of the AD8012 can be increased to about ± 3.9 V before clipping occurs. This increases the peak-to-peak output of the differential amplifier to 15.6 V. Because the signal applied to the primary winding is now bigger, the transformer turns ratio of 1:1 can be replaced with a (step-down) turns ratio of about 1.3:1 (from amplifier to line). This steps the 7.8 V peak-to-peak primary voltage down to 6 V. This is the same secondary voltage of the earlier examples, so the resulting power delivered to the line is the same. The received signal, which is small relative to the transmitted signal, will, however, be stepped up by a factor of 1.3. Amplifying the received signal in this manner enhances its signal-to-noise ratio and is useful when the received signal is small compared to the to-be-transmitted signal. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 7). One end should be connected to the ground plane and the other within 1/8 inch of each power pin. An additional (4.7 µF to 10 µF) tantalum electrolytic capacitor should be connected in parallel. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1.5 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains. Stripline design techniques should be used for long signal traces (greater than about 1 inch). They should be designed with the proper system characteristic impedance and be properly terminated at each end. The impedance reflected from the 135 Ω line now becomes 228 Ω (1.32 ⫻ 135 Ω). With a correctly terminated line, the amplifier must now drive a total load of 456 Ω (114 Ω + 114 Ω + 228 Ω), considerably more than the original 270 Ω load. This reduces the drive current from the op amps by about 40%. INVERTING CONFIGURATION RF RG RO* VIN VOUT +VS RT 10F + 0.1F More significant, however, is the reduction in dynamic power consumption—that is, the power the amplifier must consume in order to deliver the load power. Increasing the output signal so that it is as close as possible to the power rails minimizes the power consumed in the amplifier. There is, however, a price to pay in terms of increased signal distortion. Increasing the output signal of each op amp from the original ± 3 V to ± 3.9 V reduces the spurious-free dynamic range (SFDR) from –65 dB to –50 dB (measured at 500 kHz), even though the overall load impedance has increased from 270 Ω to 456 Ω. *RO CHOSEN FOR CHARACTERISTIC IMPEDANCE. RG NONINVERTING CONFIGURATION RF RO* VOUT LAYOUT CONSIDERATIONS VIN The specified high speed performance of the AD8012 requires careful attention to board layout and component selection. Table I shows recommended component values for the AD8012 and Figures 8–13 show recommended layouts for the 8-lead SOIC and MSOP packages for a positive gain. Proper RF design techniques and low parasitic component selections are mandatory. 0.1F RT 10F + –VS *RO CHOSEN FOR CHARACTERISTIC IMPEDANCE. Figure 7. Inverting and Noninverting Configurations Table I. Typical Bandwidth vs. Gain Setting Resistors Gain RF RG RT Small Signal –3 dB BW (MHz), VS = 5 V, RL = 1 k –1 +1 +2 +10 750 Ω 750 Ω 750 Ω 750 Ω 750 Ω 53.6 Ω 49.9 Ω 49.9 Ω 49.9 Ω 110 350 150 40 750 Ω 82.5 Ω RT chosen for 50 Ω characteristic input impedance. –14– REV. B AD8012 Figure 8. Universal SOIC Noninverter Top Silkscreen Figure 11. Universal MSOP Noninverter Top Silkscreen Figure 9. Universal SOIC Noninverter Top Figure 12. Universal MSOP Noninverter Top Figure 10. Universal SOIC Noninverter Bottom Figure 13. Universal MSOP Noninverter Bottom REV. B –15– AD8012 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) C01049–0–12/03(B) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY SEATING 0.10 PLANE 0.50 (0.0196) 45 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.00 BSC 8 5 4.90 BSC 3.00 BSC 1 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8 0 0.80 0.60 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Revision History Location Page 12/03—Data Sheet changed from REV. A to REV. B. Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 –16– REV. B