ETC AHA3520A

Product Specification
AHA3520
20 MBytes/sec ALDC Data
Compression Coprocessor IC
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
[email protected]
www.aha.com
advancedhardwarearchitectures
PS3520-1098
advancedhardwarearchitectures
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4.1 Port A and Port B Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4.2 FIFO Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4.3 Data Expansion During Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.0 Compression Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Compression Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.0 Decompression Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Decompression Pass Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Decompression Output Disabled Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.0 Microprocessor Interface and Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.1.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.1.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3 Pausing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.0 Port A and Port B Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.0 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.1 Status 0 (STAT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Port A Configuration 0 (ACNF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.3 Port A Configuration 1 (ACNF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.4 Port B Configuration 0 (BCNF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.5 Port B Configuration 1 (BCNF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.6 Identification (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.7 Port A Polarity (APOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.8 Port B Polarity (BPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.9 Port A Transfer Count (ATC0, ATC1, ATC2, ATC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.10 Port B Transfer Count (BTC0, BTC1, BTC2, BTC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.11 Error Status (ERRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.12 Interrupt Status (INTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.13 Command (CMND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.14 Transfer Size (TS0, TS1, TS2, TS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.15 Data Disabled Count (DDC0, DDC1, DDC2, DDC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.16 error mask (EMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.17 Interrupt Mask (IMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 Port A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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10.0 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.0 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12.0 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.0 AHA Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Figures
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Figure 18:
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Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Almost Full/Almost Empty Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Processor Read Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Processor Write Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Processor Read Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Processor Write Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Port A/B Timing, Four Edge, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port A/B Timing, Four Edge, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Port A/B Timing, Burst, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port A/B Timing, Burst, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Peripheral Access Read Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Peripheral Access Write Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Peripheral Access Read Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Peripheral Access Write Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AHA3520 PQFP Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Tables
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Table 19:
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Microprocessor Interface Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Port A Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Port B Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Almost Full/Almost Empty Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Processor Read Timing, MMODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Processor Write Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Processor Read Timing, MMODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Processor Write Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Port A/B Timing, Four Edge, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Port A/B Timing, Four Edge, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Port A/B Timing, Burst, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Port A/B Timing, Burst, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Peripheral Access Read Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Peripheral Access Write Timing, MMODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Peripheral Access Read Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Peripheral Access Write Timing, MMODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PQFP (Plastic Quad Flat Pack) 14 mm × 20 mm Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 34
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1.0
INTRODUCTION
AHA3520 is a single chip lossless compression
and decompression integrated circuit implementing
the industry standard adaptive lossless data
compression algorithm, also known as ALDC. The
device compresses, decompresses or passes
through data unchanged depending on the operating
mode selected. This device achieves an average
compression ratio of 2:1 on typical computer files.
The flexible hardware interface makes this part
suitable for many applications.
AHA 3520 is algorithm and pinout compatible
to the IBM ALDC device. Compressed files
between AHA and IBM’s implementation of the
algorithm do not always produce the same
compressed code stream. However, the
decompressed results are always the same. Files
compressed on either device can be interchanged
and decompressed on either device.
Content Addressable Memory (CAM) within
the compression/decompression engine eliminates
the need for external SRAMS. This part connects
directly to industry standard peripheral chips.
Included in this specification is a functional
overview, operation modes, register descriptions,
DC and AC Electrical characteristics, ordering
information, and a listing of related technical
publications. It is intended for hardware and
software engineers designing a compression system
using AHA3520.
AHA designs and develops lossless
compression, forward error correction and data
storage formatter/controller ICs. Other ALDC
product offering includes AHA3521. This is a pin
and firmware compatible device that includes
additional features. Technical publications are
available upon request.
1.1
CONVENTIONS, NOTATIONS AND
DEFINITIONS
- Active low signals have an “N” appended to the
end of the signal name. For example, CSN and
WRITEN.
- “Signal assertion” means the output signal is
logically true.
- Hex values are represented with a prefix of “0x”,
such as Register “0x00”. Binary values do not
contain a prefix, for example, MMODE = 1.
- A prefix or suffix of “x” indicates a letter missing
in a register name or signal name. For example,
xCNF0 refers to the ACNF0 or BCNF0 register.
- A range of signal names or register bits is denoted
by a set of colons between the numbers. Most
significant bit is always shown first, followed by
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least significant bit. For example, MDATA[7:0]
indicates signal names MDATA7 through
MDATA0.
- Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
- Reserved bits in registers are referred as “res”.
1.2
FEATURES
PERFORMANCE:
• 20 MB/s data compression, decompression or
pass-through rate with a single 40 MHz clock
• 2:1 average compression ratio
• A four byte Transfer Size register allows block
transfers up to 4 gigabytes
• Error checking in decompression mode
reportable via an interrupt
FLEXIBILITY:
• In-line and Look-aside architectures supported
• Polled or interrupt driven I/O
• Two independent DMA ports programmable for 8
or 16-bit transfers, handshaking modes and
master or slave operation
• Programmable polarity for DMA control signals
SYSTEM INTERFACE:
• Single chip data compression solution
• Two selectable microprocessor interfaces
• Programmable Interrupts
• Interfaces directly with the AHA5140 tape
formatter and industry standard SCSI chips
OTHERS:
• Open standard ALDC adaptive lossless
compression algorithm
• Complies to QIC-154, ECMA 222, ANSI
X3.280-1996 and ISO 15200 standard
specifications
• Compatible to IBM ALDC1-20S-HA
specification
• 100 pin package in 14 × 20 mm PQFP
1.3
APPLICATIONS
• QIC or 8 mm tape drives
1.4
FUNCTIONAL DESCRIPTION
AHA3520 is a compression/decompression
device residing between the host interface, usually
SCSI, and the buffer manager ASIC. Major blocks
in this device are the Microprocessor Interface, Port
A Interface, Port B Interface, and the Compression/
Decompression Engine. The Microprocessor
Interface provides status and control information by
register access. Port A and Port B Interfaces are
DMA ports configurable for bus width, polarity,
handshaking modes, and other options. The
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operating mode establishes the direction of both the
Port A and Port B Interfaces. Compression or
Compression Pass Through sets the Port A Interface
as an input and the Port B Interface as an output.
Conversely Decompression or Decompression Pass
Through sets the Port A Interface as an output and
the Port B Interface as an input. Decompression
Output Disabled mode allows the device to
decompress a block of data up to a predetermined
point while dumping the uncompressed data, then
automatically begin outputting the remaining
uncompressed data in that block or record.
A four byte Transfer Size counter allows the user
to partition the data into blocks of four gigabytes or
less to process. Compression Pass Through mode and
Decompression Pass Through modes allow data
transfers through the device without changing the
data. Both the Port A Interface and Port B Interface
have a 16-byte FIFO with Almost Empty and Almost
Full signal pins and programmable thresholds. Both
DMA interfaces, Port A and Port B, have
programmable wait states in addition to four
selectable DMA transfer modes: asynchronous
request/acknowledge pair, asynchronous burst mode,
and two peripheral access modes that correlate with
the two microprocessor modes.
1.4.1
PORT A AND PORT B INTERFACES
Both Port A and Port B Interfaces are
independently configurable via the Port A
Configuration registers (ACNFx), the Port A
Polarity register (APOL), the Port B Configuration
registers (BCNFx), and the Port B Polarity register
(BPOL). Both operate in four DMA modes.
Four-edge mode is an asynchronous data transfer
requiring a request and acknowledge pulse for each
transfer of one or two bytes, depending on the width
configuration of the Interface. A four edge transfer
begins by asserting the request signal, followed by
the acknowledge in response to the request, which
causes the request to deassert, and finally this causes
the acknowledge to deassert. Data is transferred on
the trailing edge of the acknowledge signal.
Burst mode is similar to four-edge mode except
there may be many acknowledges while the request
is held asserted. The advantage of this mode is that
it requires fewer clocks per transfer.
Two peripheral access modes exist and are
selected via the MMODE pin. Peripheral access
allows the microprocessor to write to and read from
a peripheral device connected to the Port A
Interface or Port B Interface. This mode is a
relatively slow, asynchronous transfer. This mode is
not allowed during a data transfer operation.
Page 2 of 35
1.4.2
FIFO OPERATION
Port A and Port B Interfaces both contain
sixteen-byte FIFOs with programmable thresholds.
AHA3520 has an Almost Full and an Almost Empty
signal pin associated with each of the Data
Interfaces. The FIFO thresholds are programmed in
the configuration registers (ACNF0 and BCNF0). If
the Data Interface is configured for either four-edge
or burst mode of operation the FIFO threshold
determines when request gets asserted and
deasserted. During an output transfer the request
signal asserts when the number of bytes in the FIFO
is greater than or equal to the programmed FIFO
threshold. The interface continues to request data
transfers until the FIFO becomes empty.
When transferring data into either the Port A or
Port B Interfaces, the request signal asserts when
the number of empty byte locations in the FIFO is
greater than or equal to the programmed FIFO
threshold. The interface continues to request data
transfers until the FIFO is full.
The almost full (xAF) and almost empty (xAE)
signals are always available to the user. Almost Full
can be used as an early warning indicator to stop
transferring data into the Port B Interface or Port A
Interface. The xAE signal can be used to stop
transfers out of the Port A Interface or Port B
Interface
The xAF signal deasserts when a transfer
operation begins. It asserts the clock after the
number of empty byte locations in the FIFO is less
than or equal to the FIFO threshold. The xAF signal
deasserts the clock after the number of empty byte
locations in the FIFO is greater than the FIFO
threshold.
The xAE signal asserts when a transfer
operation begins. It deasserts the clock after the
number of available bytes in the FIFO is greater than
the FIFO threshold. The xAE signal asserts after the
clock when the number of available bytes in the
FIFO is less than or equal to the FIFO threshold.
1.4.3
DATA EXPANSION DURING
COMPRESSION
Data expansion occurs when the size of the data
increases during a compression operation. This
typically occurs when the data is compressed prior to
input into the chip.The EXPAND status bit is set if
the Port B Transfer Count is larger than the Transfer
Size register. If data expansion caused the Port B
Transfer Count to exceed its maximum 4-byte value
then the BTC Overflow Error status gets set. Worst
case expansion allowable by the algorithm is 12.5%
or (9/8 times the uncompressed transfer size).
PS3520-1098
advancedhardwarearchitectures
Figure 1:
Functional Block Diagram
AHA3520 Compression Chip
ADATA[15:0]
APARITY[1:0]
ACOUT
AWR
ARD
APCS
ACIN
AAF
PORT A
INTERFACE
PORT B
INTERFACE
PORT A
DMA
STATE
MACHINE
PORT B
DMA
STATE
MACHINE
ALDC
ENGINE
PORT A
TRANSFER
COUNTER
PORT B
TRANSFER
COUNTER
BDATA[15:0]
BPARITY[1:0]
BCOUT
BWR
BRD
BPCS
BCIN
BAF
BAE
AAE
PASS THROUGH
CONTROLLER
CLOCK
GENERATION
2.0
COMPRESSION OPERATION
2.1
COMPRESSION PASS THROUGH
Compression Pass Through mode allows data to
enter the Port A Interface, transfer through the device
unchanged and exit through the Port B Interface. Pass
through mode uses the Port A Transfer counter, Port
B Transfer counter and Transfer Size register. The
DONE status bit and interrupt (if not masked) are set
when the transfer completes.
2.2
COMPRESSION
During compression operation, uncompressed
data flows into the Port A Interface, is compressed
by the compression engine and the compressed data
transferred out of the Port B Interface.
The device contains a Content Addressable
Memory (CAM). The CAM is the history buffer
during compression operation. The compressor
appends an end marker control code to the end of the
compressed data. It also pads the end of a transfer to a
byte boundary with zeroes. End marker control
PS3520-1098
INTERRUPT
LOGIC
IREQ
IREQN
RESETN
MMODE
ADDR[4:0]
PROCESSOR INTERFACE
STATE MACHINE
WAITN
MDATA[7:0]
PROCESSOR
INTERFACE
MCIN[1:0]
CLOCK
codewords are monitored during decompression, to
determine Decompression End errors.
The compression engine constantly monitors
the performance of compression for expansion
during compression operation. The EXPAND bit is
set if the Port B Transfer Count is larger than the
transfer size at the end of a compression operation.
When the Port B Transfer Count is higher than the
Port A Transfer Count the EXPAND bit in the
Status 0 register is set indicating data expansion
during compression operation.
Port A Interface count increments with each
byte received and when this count equals the
transfer size, all bytes in this transfer have been
received into Port A.
A compression operation is complete when the
last byte transfers out of the Port B Interface and the
Port B Interface count is zero, thus setting the
DONE status bit and generating a Done Interrupt if
it is not masked.
Page 3 of 35
Advanced
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3.0
DECOMPRESSION OPERATION
3.1
DECOMPRESSION PASS THROUGH
Decompression Pass Through mode allows data
to enter the Port B Interface, transfer through the
device unchanged and exit through the Port A
Interface. Pass through mode uses the Port A Transfer
counter, Port B Transfer counter and Transfer Size
register. The DONE status bit and interrupt (if not
masked) are set when the transfer completes.
3.2
4.0
MICROPROCESSOR INTERFACE AND REGISTER ACCESS
4.1
MICROPROCESSOR INTERFACE
DECOMPRESSION
During Decompression mode, compressed data
flows into the Port B Interface and is decompressed.
The resulting uncompressed data is transferred out of
the Port A Interface.
The number of compressed bytes in the transfer
is programmed into the four byte Transfer Size
register. A decompression operation is complete
when the last byte transfers out of the Port A
Interface, thus setting the DONE status bit and
generating a Done Interrupt if it is not masked.
Two types of errors are detected and reported
during decompression. Decoder Control Coder
Errors are caused by detection of invalid control
codes in the compressed data stream. Decoder End
Errors are detected when either the decompressor
encountered an end control code before the
expected end of record indicated by the Transfer
Size register, or the end of record was reached
according to the Transfer Size register but no end
control code was detected. These errors are reported
in the Error Status register.
3.3
reached where the user wants the data (Port A
Transfer Count is equal or greater than the Data
Disable Count), the device switches to normal
decompression mode and the remainder of that file
is decompressed and transferred out of the Port A
Interface. Removal of CBG headers also applies to
this mode.
DECOMPRESSION OUTPUT
DISABLED MODE
Decompressed output disabled mode allows the
user to decompress to a point in the record or block
and rebuild the history buffer while discarding the
uncompressed data. After the point in the file is
Table 1:
4.1.1
INTERRUPTS
IREQ and IREQN are two hardware interrupt
signals. IREQN is a negative active open-drain
output that requires a pull-up resistor if it is used.
IREQ is a standard TTL output. When active they
indicate an interrupt is set in the device. The
microprocessor can determine the cause of the
interrupt by reading the Interrupt Status register.
Masking individual interrupts with the
Interrupt Mask register disables particular
interrupts from causing the interrupt signal pins to
assert (IREQ and IREQN). They do not disable bits
in the Interrupt Status register.
The interrupt signals are reset to their inactive
state when either a hardware or software reset
occurs, when a data transfer operation resumes, or
when a data transfer operation begins. In addition,
disabling Interrupt Mask bits after the Interrupt pin
is asserted, clears the interrupt and deasserts the
Interrupt pin.
Microprocessor Interface Control Signals
PIN NAME
MCIN[0]
MCIN[1]
WAITN
ADDR[0]
Page 4 of 35
Microprocessor Interface configuration is
determined by the MMODE pin. If MMODE is tied
high transfers are controlled by a chip select signal
(CSN) and a read/write signal (RWN), otherwise
transfers are controlled by separate read (READN),
write (WRITEN) signals. Refer to Section 10.0
Timing Specifications for timing diagrams.
MMODE TIED LOW
MMODE TIED HIGH
READN
WRITEN
WAITN
ADDR[0] = 0 selects register bits 7:0
ADDR[0] = 1 selects register bits 15:8
CSN
RWN
WAITN
ADDR[0] = 0 selects register bits 15:8
ADDR[0] = 1 selects register bits 7:0
PS3520-1098
advancedhardwarearchitectures
4.1.2
4.3
RESETS
The AHA3520 has one hardware reset signal
and a software reset. When the RESETN signal is
asserted all registers except the Identification
registers are reset, current operations are cancelled,
and the history buffer is cleared. The software reset
via the Command register does not affect the
Configuration registers (ACNFx or BCNFx),
Identification registers (IDx), either of the Polarity
registers (APOL or BPOL), or the Command
register (CMND). All other registers are reset,
current operations cancelled and the history buffer
cleared.
4.2
When a Pause command is issued, the device
pauses at the next break in the DMA handshaking.
When a port is in slave mode, it pauses after
xCOUT (DACKx) deasserts. When a port is in
master mode and xCOUT (DREQx) is asserted, the
port does not pause until xCIN (DACKx) is
recieved from the external DMA device. The
AHA3520 waits until both ports are paused, at
which time the BUSY status bit clears and the
PAUSED status bit and interrupt are set.
5.0
REGISTER ACCESS
MMODE determines whether ADDR[0]
selects even or odd addressed registers. When
MMODE is high and ADDR[0]=0, odd addressed
registers are accessible. MMODE=1 causes
ADDR[0] input signal to be inverted.
The following registers may not be stable if
BUSY is set: Status 0, Status 1, Port A Transfer
Count, Port B Transfer Count, Error Status,
Interrupt Status and FIFO Access.
Table 2:
ACIN
ACOUT
AWR
ARD
APCS
AAF
AAE
Port A and Port B operate identically. They
both are 16-bit bidirectional data ports with parity
checking and generation. There are three
configuration registers associated with each port
and a polarity register that determines the polarity
of all of the control signals for that port.
The function of the control pin is determined by
either xCNF0[13, 12] bits or Command register
programmed for peripheral access. The polarity of
control signals are controlled by specific bits in the
Polarity registers.
MASTER
SLAVE
SLAVE=0
DACKA
DREQA
deasserted
deasserted
APCS
AAF
AAE
SLAVE=1
DREQA
DACKA
AWR
ARD
APCS
AAF
AAE
APOL
bit
DIRECTION
7
5
4
3
2
1
0
I
O
O
O
O
O
O
BPOL
bit
DIRECTION
7
5
4
3
2
1
0
I
O
O
O
O
O
O
Port B Interface Signals
SIGNAL
NAME
BCIN
BCOUT
BWR
BRD
BPCS
BAF
BAE
PS3520-1098
PORT A AND PORT B
CONFIGURATION
Port A Interface Signals
SIGNAL
NAME
Table 3:
PAUSING
MASTER
SLAVE
SLAVE=0
DACKB
DREQB
deasserted
deasserted
BPCS
BAF
BAE
SLAVE=1
DREQB
DACKB
BWR
BRD
BPCS
BAF
BAE
Page 5 of 35
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6.0
REGISTER DESCRIPTION
ADDR[4:0]
MMODE=0 MMODE=1
0x00
0x01
0x00
0x01
0x00
0x01
0x02
0x03
0x02
0x03
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x01
0x00
0x01
0x00
0x01
0x00
0x03
0x02
0x03
0x02
0x03
0x02
0x05
0x04
0x07
0x06
0x09
0x08
0x0B
0x0A
0x0D
0x0C
0x0F
0x0E
0x11
0x10
0x13
0x12
0x15
0x14
0x17
0x16
0x19
0x18
0x1B
0x1A
0x1D
0x1C
0x1F
0x1E
REGISTER RESET VALUE
MNEMONIC
REGISTER NAME
R
1
0x00
NEW
RESET
TRANSFER
COMMAND COMMAND
0x00
0x80
R/W
R/W
R/W
R/W
R
2
2
3
3
1
0x00
0x00
0x00
0x00
0xC1
unchanged
unchanged
unchanged
unchanged
0xC1
R/W
2
0xFF
unchanged unchanged
R/W
3
0xFF
unchanged unchanged
R
R
R
R
R
R
R
R
R
4
4
4
4
5
5
5
5
1
1
1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
unchanged
R/W
0x00
0x00
unchanged
R/W NOTES HARDWARE
RESET
STAT0
res
ACNF0
ACNF1
BCNF0
BCNF1
ID
res
APOL
res
BPOL
res
ATC2
ATC3
ATC0
ATC1
BTC2
BTC3
BTC0
BTC1
ERRS
res
INTS
res
res
CMND
res
res
TS2
TS3
TS0
TS1
DDC2
DDC3
DDC0
DDC1
EMSK
res
IMSK
res
Status 0
Reserved
Port A Configuration 0
Port A Configuration 1
Port B Configuration 0
Port B Configuration 1
Identification
Reserved
Port A Polarity
Reserved
Port B Polarity
Reserved
Port A Transfer Count, Byte 2
Port A Transfer Count, Byte 3
Port A Transfer Count, Byte 0
Port A Transfer Count, Byte 1
Port B Transfer Count, Byte 2
Port B Transfer Count, Byte 3
Port B Transfer Count, Byte 0
Port B Transfer Count, Byte 1
Error Status
Reserved
Interrupt Status
Reserved
Reserved
Command
Reserved
Reserved
Transfer Size, Byte 2
Transfer Size, Byte 3
Transfer Size, Byte 0
Transfer Size, Byte 1
Data Disabled Count, Byte 2
Data Disabled Count, Byte 3
Data Disabled Count, Byte 0
Data Disabled Count, Byte 1
Error Mask
Reserved
Interrupt Mask
Reserved
R
unchanged
unchanged
unchanged
unchanged
0xC1
Notes:
1) When CMND is not a Selection Command.
2) When CMND is a Select Port A Configuration Command.
3) When CMND is a Select Port B Configuration Command.
4) When CMND is any Transfer Command or Select Port A Configuration Command.
5) When CMND is any Transfer Command or Select Port B Configuration Command.
Page 6 of 35
PS3520-1098
advancedhardwarearchitectures
6.1
STATUS 0 (STAT0)
Read Only
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
1
0x00 0x01
BUSY -
bit7
BUSY
bit6
bit5
bit4
bit3
bit2
bit1
PAUSED OUTDIS BYPASS EXPAND ANYINT ANYERR
bit0
DONE
Busy. This bit is set when a data transfer operation begins. It is cleared when the data transfer
operation completes successfully, when an unmasked error occurs, when a reset occurs, or
when a paused command is issued by the microprocessor.
PAUSED - Paused. This bit is set when a data transfer operation is currently paused. It is cleared when a
paused data transfer operation is resumed or when a reset occurs.
OUTDIS - Output Disabled. This bit is set when Port A Interface output is disabled. It is cleared when Port
A Interface output is re-enabled or when a reset occurs.
BYPASS - Bypass. This bit is set after a Start Compression Bypass or a Start Decompression Bypass
command is written to the Command register. It is cleared after a Start Compression, Start
Decompression or when a reset occurs.
EXPAND - Expansion. This bit is set when the Port B Transfer Count register is larger than the Transfer
Size register at the end of a compression operation. It is cleared when another data transfer
operation begins or when a reset occurs.
ANYINT - Any Interrupt. This bit is set while an unmasked interrupt is active. This signal mirrors the
Interrupt signal pin.
ANYERR - Any Error. This bit is set when an unmasked error occurs. It is cleared when a data transfer
operation begins or when a reset occurs.
DONE -
6.2
Done. This bit is set when the current data transfer operation is complete. It is cleared when a
data transfer operation begins or when a reset occurs.
PORT A CONFIGURATION 0 (ACNF0)
Read/Write
Reset Value = 0x00
Software Reset Value = unchanged
MMODE =
0
1
bit7
0x00 0x01 reserved
bit6
bit5
WAITST[2:0]
bit4
bit3
bit2
bit1
bit0
FIFOTH[3:0]
WAITST[2:0]-Wait State. These bits configure the number of wait states used during a Port A Interface
peripheral access. The values 011 through 111 are valid.
FIFOTH[3:0]-FIFO Threshold. These bits configure the Port A FIFO threshold value. Values from 0000
through 1111 are valid.
PS3520-1098
Page 7 of 35
Advanced
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6.3
PORT A CONFIGURATION 1 (ACNF1)
Read/Write
Reset Value = 0x00
Software Reset Value = unchanged
MMODE =
0
1
bit7
0x01 0x00 PARITY
bit6
bit5
ODD
SLAVE
bit4
bit3
MODE[1:0]
bit2
bit1
WIDE
bit0
reserved
PARITY - Parity. When set, parity checking is enabled for the ADATA[15:0] data bus. When cleared,
parity checking is disabled for the ADATA[15:0] bus.
ODD -
Odd. Setting this bit along with PARITY enables odd parity checking and generation on the
ADATA[15:0] data bus. When cleared with PARITY set even parity checking and generation is
enabled on the ADATA[15:0] data bus.
SLAVE -
Slave. When set, the Port B Interface acts as a slave device and generates acknowledges in
response to requests. When cleared, the Port B Interface acts as a DMA master, and generates
requests and expects acknowledges.
MODE[1:0]-DMA Mode. These bits configure the interface DMA mode of the Port A Interface with values
as defined below.
WIDE -
6.4
MODE[1:0]
DMA TYPE
00
01
10
11
Four Edge
Burst
reserved
reserved
Two Byte. When set, ADATA[15:0] and PARITY[1:0] are used. When cleared, AD[7:0] and
PARITY[0] are used.
PORT B CONFIGURATION 0 (BCNF0)
Read/Write
Reset Value = 0x00
Software Reset Value = unchanged
MMODE =
0
1
bit7
0x00 0x01 reserved
bit6
bit5
WAITST[2:0]
bit4
bit3
bit2
bit1
bit0
FIFOTH[3:0]
WAITST[2:0]-Wait State. These bits configure the number of wait states used during Port A Interface
peripheral access. The values 001 through 111 are valid. Values 000, 001, 010 result in two wait
states.
FIFOTH[3:0]-FIFO Threshold. These bits configure the Port A FIFO threshold value. Values from 0001
through 1111 are valid. A value of 0000 results in the same operation as 0001.
Page 8 of 35
PS3520-1098
advancedhardwarearchitectures
6.5
PORT B CONFIGURATION 1 (BCNF1)
Read/Write
Reset Value = 0x00
Software Reset Value = unchanged
MMODE =
0
1
bit7
0x01 0x00 PARITY
bit6
bit5
ODD
SLAVE
bit4
bit3
MODE[1:0]
bit2
WIDE
bit1
bit0
reserved
PARITY - Parity. When set, parity checking is enabled for the BDATA[15:0] data bus. When cleared,
parity checking is disabled for the BDATA[15:0] bus.
ODD -
Odd. When set, odd parity checking and generation is used on the BDATA[15:0] data bus.
When cleared, even parity checking and generation is used on the BDATA[15:0] data bus.
SLAVE -
Slave. When set, the Port B Interface acts as a slave device and generates acknowledges in
response to requests. When cleared, the Port B Interface acts as a DMA master, and generates
requests and expects acknowledges.
MODE[1:0]-DMA Mode. These bits configure the interface DMA mode of the Port B Interface with values
as defined below.
WIDE -
6.6
MODE[1:0]
DMA TYPE
00
01
10
11
Four Edge
Burst
reserved
reserved
Two Byte. When set, BDATA[15:0] and PARITY[1:0] are used. When cleared, BD[7:0] and
PARITY[0] are used.
IDENTIFICATION (ID)
Read Only
Value = Contact AHA Applications Engineering
MMODE =
0
1
bit7
bit6
bit5
bit4
0x02 0x03
ID[7:0]-
6.7
bit3
bit2
bit1
bit0
ID[7:0]
The bits of this register correspond to the identification code of the chip. This register is
accessible when CMND is not a Selection Command.
PORT A POLARITY (APOL)
Read/Write
Reset Value = 0xFF
Software Reset Value = unchanged
MMODE =
0
1
0x02 0x03
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ACIN
reserved
ACOUT
AWR
ARD
APCS
AAF
AAE
The bits of this register correspond to Port A Interface signals. A set bit programs the corresponding
signal to be active low. A cleared bit programs the corresponding signal to be active high. This register is
only accessible when CMND is Select Port A Configuration.
PS3520-1098
Page 9 of 35
Advanced
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6.8
PORT B POLARITY (BPOL)
Read/Write
Reset Value = 0xFF
Software Reset Value = unchanged
MMODE =
0
1
0x02 0x03
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BCIN
reserved
BCOUT
BWR
BRD
BPCS
BAF
BAE
The bits of this register correspond to Port B Interface signals. A set bit programs the corresponding
signal to be active low. A cleared bit programs the corresponding signal to be active high.This register is
only accessible when CMND is Select Port B Configuration.
6.9
PORT A TRANSFER COUNT (ATC0, ATC1, ATC2, ATC3)
Read Only
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
1
0x06
0x07
0x04
0x05
0x07
0x06
0x05
0x04
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ATC[7:0]
ATC[15:8]
ATC[23:16]
ATC[31:24]
ATC[31:0]- Port A Transfer Count. These registers provide status information on the number of bytes
transferred for a current data transfer operation. During a compression operation, ATC is
incremented as each original data byte is received by the Port A Interface. When ATC equals TS
during compression, all bytes in the compression operation have been received by the AHA3520.
During a decompression operation, ATC is incremented as each decompressed data byte is sent by
the Port A Interface. This register is only accessible when CMND is not a Selection Command.
6.10 PORT B TRANSFER COUNT (BTC0, BTC1, BTC2, BTC3)
Read Only
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
1
0x00
0x01
0x00
0x01
0x01
0x00
0x01
0x00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BTC[7:0]
BTC[15:8]
BTC[23:16]
BTC[31:24]
BTC[31:0] -Port B Transfer Count. These registers provide status information on the number of bytes
transferred for a current data transfer operation. During a compression operation, BTC is
incremented as each compressed data byte is sent by the Port B Interface. During a
decompression operation, BTC is incremented as each compressed data byte is received by the
Port B Interface. When BTC equals TS during decompression, all bytes in the decompression
operation have been received by the AHA3520 host interface.This register is only accessible
when CMND is not a Selection Command.
Page 10 of 35
PS3520-1098
advancedhardwarearchitectures
6.11 ERROR STATUS (ERRS)
Read Only
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
bit7
1
bit6
0x0C 0x0D reserved APERR
bit5
bit4
bit3
bit2
bit1
bit0
BPERR
reserved
BTCO
ATCO
ADCC
ADE
The Error Status register provides error status bits to the microprocessor. This register should only be read
when CMND is not a Selection Command. These bits are set regardless of the error mask settings.
APERR - Port A Interface Parity Error. This bit is set when a parity error is detected during a transfer into
ADATA[15:0] and the Port A Interface Parity bit is set. It is cleared when a data transfer
operation begins or when a reset occurs.
BPERR -
Port B Interface Parity Error. This bit is set when a parity error is detected during a transfer into
BDATA[15:0] and the Port B Interface Parity bit is set. It is cleared when a data transfer
operation begins or when a reset occurs.
BTCO -
Port B Transfer Count Overflow Error. This bit is set when a carry out is detected on the Port B
Transfer Count register. It is cleared when a data transfer operation begins or when a reset occurs.
ATCO -
Port A Transfer Count Overflow Error. This bit is set when a carry out is detected on the Port A
Transfer Count register. It is cleared when a data transfer operation begins or when a reset occurs.
ADCC -
ALDC Decoder Control Code Error. This bit is set during decompression when an invalid
control code is detected in the compressed data stream. It is cleared when a data transfer
operation begins or when a reset occurs.
ADE -
ALDC Decoder End Error. This bit is set during decompression when an End control code is
detected while Port B Transfer Count is less than Transfer Size or when BTC equals TS and no
End control code is detected in the compressed data stream. It is cleared when a data transfer
operation begins or when a reset occurs.
6.12 INTERRUPT STATUS (INTS)
Read Only
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
bit7
1
0x0E 0x0F
DONE -
bit6
DONE PAUSED
bit5
bit4
bit3
reserved
bit2
bit1
bit0
ERROR
Done Interrupt. This bit is set when data transfer has completed on the Port B Interface during
compression and when data transfer has completed on the Port A Interface during
decompression. It is cleared when a data transfer operation begins or when a reset occurs.
PAUSED - Paused Interrupt. This bit is set when the current transfer step after the microprocessor issues a
Pause command is completed. It is cleared when the microprocessor issues a Resume
command, when a data transfer operation begins, or when a reset occurs.
ERROR - Error Interrupt. This bit is set when an error occurs. It is cleared when a data transfer operation
begins or when a reset occurs. The Error Status register is used to determine the cause of the error.
PS3520-1098
Page 11 of 35
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6.13 COMMAND (CMND)
Read/Write
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
1
bit7
0x11 0x10
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMND[7:0]
The Command register is used to program the operation of the compression subsystem.
CMND[7:0]-Command.This register provides for operation as described in the following table.
CMND[7:0]
0xC1
0xC2
0xC4
0xC8
ACTION
SELECTION COMMANDS
Select Port A Configuration. The Port A Configuration and Port A Polarity
registers are enabled for reads and writes.
Select Port B Configuration. The Port B Configuration and Port B Polarity
registers are enabled for reads and writes.
Select Port A Interface Peripheral Access. All peripheral access addresses are
enabled for reads and writes to a Port A Interface attached peripheral.
Select Port B Interface Peripheral Access. All peripheral access addresses are
enabled for reads and writes to a Port B Interface attached peripheral.
TRANSFER COMMANDS
(Described in Sections 2.0 and 3.0)
0x50
0x58
0x60
0x68
0x6C
Start Compression Bypass.
Start Compression.
Start Decompression Bypass.
Start Decompression.
Start Decompression Output Disabled.
CONTROL COMMANDS
0x42
0x44
0xA0
Pause. When a data transfer operation is in progress, any current operation
steps are completed and the Port A Interface and Port B Interface data busses
are placed into a high impedance state. The Paused Interrupt and Paused
Status bits are then set. All data currently being processed by the data transfer
operation is preserved.
Resume. A previously paused data transfer operation resumes processing. The
Paused Interrupt and Paused status bits are cleared and the Busy status bit is
set.
Software Reset. The Port A Configuration, Port B Configuration,
Identification, Port A Polarity, Port B Polarity, and Command registers are
not affected by this command. All other registers are reset, current operations
are cancelled, and the history buffer is cleared.
MISCELLANEOUS COMMANDS
0x00
Page 12 of 35
NOP, no operation is performed.
PS3520-1098
advancedhardwarearchitectures
6.14 TRANSFER SIZE (TS0, TS1, TS2, TS3)
Read/Write
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
bit7
0
1
0x16
0x17
0x14
0x15
0x17
0x16
0x15
0x14
TS[31:0]-
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TS[7:0]
TS[15:8]
TS[23:16]
TS[31:24]
Transfer Size. The Transfer Size register provides the microprocessor control of the number of
bytes transferred during a data transfer operation. The direction of the data transfer operation
specifies whether the Port A Transfer Count register or the Port B Transfer Count register is
used to determine when all data bytes have been received for the data transfer operation.
During compression, ATC is used. During decompression, BTC is used. When the appropriate
Transfer Count register (ATC or BTC) equals TS, all bytes in the current data transfer operation
have been received by the compression module.
6.15 DATA DISABLED COUNT (DDC0, DDC1, DDC2, DDC3)
Read/Write
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
1
0x1A
0x1B
0x18
0x19
0x1B
0x1A
0x19
0x18
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DDC[7:0]
DDC[15:8]
DDC[23:16]
DDC[31:24]
DDC[31:0]- Data Disabled Count.The Data Disabled Count register provides the microprocessor control of
the number of bytes skipped during a Start Decompression Output Disabled operation. If the
Data Disabled Count is set to 0x00 during a Start Decompression Output Disabled operation or
the DDC is greater than the Transfer Size (TS) during a Start Decompression Output Disabled
operation, then the Port A Interface output is disabled for the entire transfer.
PS3520-1098
Page 13 of 35
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6.16 ERROR MASK (EMSK)
Read/Write
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
bit7
1
bit6
bit5
bit4
0x1C 0x1D reserved APERRM BPERRM reserved
bit3
BTCOM
bit2
bit1
ATCOM ADCOM
bit0
ADEM
The Error Mask register provides error reporting configuration to the microprocessor. If an unmasked error
status bit is active, ANYERR status and ERROR interrupts are set.
APERRM -Port A Interface Parity Error Mask.
BPERRM - Port B Interface Parity Error Mask.
BTCOM - Port B Transfer Count Overflow Error Mask.
ATCOM - Port A Transfer Count Overflow Error Mask.
ADCOM - ALDC Decoder Control Code Error Mask.
ADEM -
ALDC Decoder End Error Mask.
6.17 INTERRUPT MASK (IMSK)
Read/Write
Reset Value = 0x00
Software Reset Value = 0x00
MMODE =
0
1
bit7
bit6
0x1E 0x1F DONEM PAUSEDM
bit5
bit4
bit3
reserved
bit2
bit1
bit0
ERRORM
The Interrupt Mask register masks the individual interrupts allowing the user to control which ones may
cause the Interrupt signal pins (IREQ or IREQN) to assert. For example, if DONE and PAUSED are set with
ERROR cleared, only an ERROR interrupt will cause the Interrupt signal pins to assert.
DONEM - Done Interrupt Mask.
PAUSEDM -Paused Interrupt Mask.
ERRORM -Error Interrupt Mask.
Page 14 of 35
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advancedhardwarearchitectures
7.0
SIGNAL DESCRIPTIONS
This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.
TYPE CODE
I
O
I/O
7.1
DESCRIPTION
Input only pin
Output only pin
Input/Output pin
MICROPROCESSOR INTERFACE
MICROPROCESSOR INTERFACE
SIGNAL
MDATA[7:0]
TYPE
DESCRIPTION
I/O
Microprocessor data bus
Microprocessor interface control pin [0]. If MMODE is high
this pin is CSN. If MMODE is low this pin is READN.
Microprocessor interface control pin [1]. If MMODE is high
this pin is RWN. If MMODE is low this pin is WRITEN.
Microprocessor output signal. WAITN is driven during CSN
and then goes to tristate with a resistive pullup.
Microprocessor Interface address bus, used to select internal
registers.
Microprocessor Interface mode selector pin.
Hardware reset signal, resets all registers except the
Identification register.
Interrupt request output signal, open drain output. This signal
requires a pull-up resistor if used by the system.
Interrupt request output signal, active high.
Clock input
Active low test pins. These pins must be tied high in the system.
Active low testpin. Tristates all pads
MCIN[0]
I
MCIN[1]
I
WAITN
O
ADDR[4:0]
I
MMODE
I
RESETN
I
IREQN
O
IREQ
CLOCK
TESTN[6:0]
TRISTATEN
O
I
I
I
PS3520-1098
DEFAULT
AFTER RESET
Hi-Z
Input
Input
High (internal
pullup)
Input
Input
Input
Hi-Z
Low
Input
Input
Input
Page 15 of 35
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7.2
PORT A INTERFACE
PORT A INTERFACE
SIGNAL
TYPE
ACIN
I
ACOUT
O
AWR
O
ARD
O
APCS
O
AAF
O
AAE
O
APARITY[1:0]
I/O
ADATA[15:0]
I/O
Note:
DESCRIPTION
Port A Interface Control Input signal. This signal functions as
DACKA or DREQA. Polarity is programmed by APOL[7].
Port A Interface Control Output signal. This signal functions as
DACKA or DREQA. Polarity is programmed by APOL[5].
Port A Interface Control Output signal. Polarity is controlled by
APOL[4].
Port A Interface Control Output signal. Polarity is controlled by
APOL[3].
Port A Interface Control Output signal. Polarity is controlled by
APOL[2].
Port A Interface Output signal. Port A FIFO almost full signal.
Polarity is programmed by APOL[1]. Exactly when this flag
gets set depends on the threshold bits in the Port A
Configuration 0 register.
Port A Interface Output signal. Port A almost empty signal.
Polarity is programmed by APOL[0]. Exactly when this flag
gets set depends on the threshold bits in the Port A
Configuration 0 register.
When enabled, this pin checks parity on input and generates
parity for output for the AD bus. APARITY[0] is used for
AD[7:0], and APARITY[1] is used for AD[15:8]. Setting
ACNF[15]=1 enables APARITY[0]. Setting ACNF[15]=1 and
ACNF[10]=1 enables APARITY[1]. When disabled these pins
may be tied high, tied low or not connected.
Port A Interface Data bus. The upper eight bits [15:8] are
enabled by setting ACNF[10]=1. When the upper eight bits are
disabled they may be tied high, tied low, or not connected.
DEFAULT
AFTER RESET
Input
High
High
High
High
High
Low
Hi-Z
Hi-Z
Refer to Section 5.0 Port A and Port B Configuration and Table 2 for configuration of Port A control signals.
Page 16 of 35
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advancedhardwarearchitectures
7.3
PORT B INTERFACE
PORT B INTERFACE
SIGNAL
TYPE
BCIN
I
BCOUT
O
BWR
O
BRD
O
BPCS
O
BAF
O
BAE
O
BPARITY[1:0]
I/O
BDATA[15:0]
I/O
Note:
DESCRIPTION
Port B Interface Control Input signal. This signal functions as
DACKB or DREQB. Polarity is programmed by BPOL[7].
Port B Interface Control Output signal. This signal functions as
DACKB or DREQB. Polarity is programmed by BPOL[5].
Port B Interface Control Output signal. Polarity is controlled by
BPOL[4].
Port B Interface Control Output signal. Polarity is controlled by
BPOL[3].
Port B Interface Control Output signal. Polarity is controlled by
BPOL[2].
Port B Interface Output signal. Port B FIFO almost full signal.
Polarity is programmed by BPOL[1]. Exactly when this flag
gets set depends on the threshold bits in the Port B
Configuration 0 register.
Port B Interface Output signal. Port B almost empty signal.
Polarity is programmed by BPOL[0]. Exactly when this flag
gets set depends on the threshold bits in the Port B
Configuration 0 register.
When enabled, this pin checks parity on input and generates
parity for output for the BD bus. BPARITY[0] is used for
BD[7:0], and BPARITY[1] is used for BD[15:8]. Setting
BCNF[15]=1 enables BPARITY[0]. Setting BCNF[15]=1 and
BCNF[10]=1 enables BPARITY[1]. When disabled these pins
may be tied high, tied low or not connected.
Port B Interface Data bus. The upper eight bits [15:8] are
enabled by setting BCNF[10]=1. When the upper eight bits are
disabled they may be tied high, tied low, or not connected.
DEFAULT
AFTER RESET
Input
High
High
High
High
High
Low
Hi-Z
Hi-Z
Refer to Section 5.0 Port A and Port B Configuration and Table 3 for configuration of Port B control signals.
PS3520-1098
Page 17 of 35
Advanced
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8.0
PINOUT
Page 18 of 35
PIN
SIGNAL
PIN
SIGNAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AAE
VDD
GND
BDATA[7]
BDATA[6]
BDATA[5]
BDATA[4]
BDATA[3]
BDATA[2]
VDD
GND
BDATA[1]
BAF
BAE
BDATA[0]
BDATA[15]
BDATA[14]
BDATA[13]
BDATA[12]
VDD
GND
BDATA[11]
BDATA[10]
BDATA[9]
BDATA[8]
BPARITY[0]
BPARITY[1]
VDD
GND
IREQN
IREQ
BPCS
WAITN
BRD
BWR
BCOUT
RESETN
TRISTATEN
CLK
GND
VDD
ADDR[4]
ADDR[3]
TESTN[0]
BCIN
GND
TESTN[1]
ADDR[2]
ADDR[1]
ADDR[0]
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
ACIN
VDD
GND
ADATA[7]
ADATA[6]
TESTN[2]
ADATA[5]
ADATA[4]
ADATA[3]
VDD
GND
ADATA[2]
ARD
APCS
ADATA[1]
ADATA[0]
ADATA[15]
ADATA[14]
ADATA[13]
VDD
GND
ADATA[12]
ADATA[11]
ADATA[10]
ADATA[9]
ADATA[8]
APARITY[0]
VDD
GND
APARITY[1]
MDATA[7]
TESTN[3]
TESTN[4]
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[3]
ACOUT
AWR
GND
VDD
MCIN[0]
MCIN[1]
MDATA[2]
MDATA[1]
MDATA[0]
AAF
MMODE
TESTN[5]
TESTN[6]
PS3520-1098
AAE
VDD
GND
BDATA[7]
BDATA[6]
BDATA[5]
BDATA[4]
BDATA[3]
BDATA[2]
VDD
GND
BDATA[1]
BAF
BAE
BDATA[0]
BDATA[15]
BDATA[14]
BDATA[13]
BDATA[12]
VDD
GND
BDATA[11]
BDATA[10]
BDATA[9]
BDATA[8]
BPARITY[0]
BPARITY[1]
VDD
GND
IREQN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
APARITY[1]
GND
VDD
APARITY[0]
ADATA[8]
ADATA[9]
ADATA[10]
ADATA[11]
ADATA[12]
GND
VDD
ADATA[13]
ADATA[14]
ADATA[15]
ADATA[0]
ADATA[1]
APCS
ARD
ADATA[2]
GND
VDD
ADATA[3]
ADATA[4]
ADATA[5]
TESTN[2]
ADATA[6]
ADATA[7]
GND
VDD
ACIN
advancedhardwarearchitectures
Figure 2:
MDATA[7]
TESTN[3]
TESTN[4]
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[3]
ACOUT
AWR
GND
VDD
MCIN[0]
MCIN[1]
MDATA[2]
MDATA[1]
MDATA[0]
AAF
MMODE
TESTN[5]
TESTN[6]
PS3520-1098
Pinout
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AHA3520A-040 PQC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
ADDR[0]
ADDR[1]
ADDR[2]
TESTN[1]
GND
BCIN
TESTN[0]
ADDR[3]
ADDR[4]
VDD
GND
CLK
TRISTATEN
RESETN
BCOUT
BWR
BRD
WAITN
BPCS
IREQ
Page 19 of 35
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9.0
ELECTRICAL SPECIFICATIONS
9.1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vdd
Vpin
9.2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
MIN
MAX
Power supply voltage
Voltage applied to any pin
UNITS
7.0
7.0
-0.5
NOTES
Volts
Volts
RECOMMENDED OPERATING CONDITIONS
SYMBOL
Vdd
Ta
9.3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
MAX
Power supply voltage
Operating temperature
4.75
0
UNITS
5.25
70
NOTES
Volts
°C
DC SPECIFICATIONS
SYMBOL
Vil
Vih
Vol
Voh
Iil
Iih
Iozl
Iozh
IddA
Idd
Iol
Ioh
Cin
Cout
CI/O
CL
PARAMETER
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input low current
Input high current
Output tristate low current
Output tristate high current
Active Idd current
Supply current (static)
Low level output current
(except IREQN)
IREQN (open drain)
High level output current
Input capacitance
Output capacitance
I/O capacitance
Load Capacitance
DC SPECIFICATIONS
CONDITIONS
MIN
MAX
UNITS
0.8
Volts
Volts
Volts
Volts
µAmps
µAmps
µAmps
µAmps
mAmps
mAmps
2.0
Iol = 4.0 mAmps
Ioh = -0.4 mAmps
Vin = 0 Volts
Vin = Vdd Volts
Vout = 0 Volts
Vout = Vdd Volts
Vdd = 5.25 Volts
0.4
2.4
-10
10
10
-10
250
1
4
NOTES
1
mAmps
8
-4
5
5
5
50
mAmps
pF
pF
pF
pF
Notes:
1) Test Conditions: worst case compression current; 0mA loads.
Page 20 of 35
PS3520-1098
advancedhardwarearchitectures
10.0 TIMING SPECIFICATIONS
Notes:
1) All AC timings are referenced to 1.4 Volts.
Figure 3:
Clock Timing
1
3
2
CLOCK
4
Table 4:
Clock Timing
NUMBER
1
2
3
4
5
5
PARAMETER
MIN
CLK period
CLK low pulsewidth
CLK high pulsewidth
CLK rise time
CLK fall time
MAX
25
10
10
3
3
UNITS NOTES
ns
ns
ns
ns
ns
1
1
1
2
2
Notes:
1) All AC Timings are referenced to 1.4 Volts
2) Rise and fall times are between 0.8 Volts and 2.0 Volts.
Figure 4:
Reset Timing
RESETN
1
2
MCIN[0] or MCIN[1]
(CSN, READN or WRITEN)
Table 5:
NUMBER
1
2
Figure 5:
Reset Timing
PARAMETER
MIN
RESETN pulsewidth
RESETN delay to CSN, READN or
WRITEN
MAX
UNITS NOTES
5
clocks
2
clocks
Almost Full/Almost Empty Timing
CLOCK (input)
1
2
xAF
1
2
xAE
Table 6:
NUMBER
1
2
Almost Full/Almost Empty Timing
PARAMETER
xAF or xAE asserted from CLOCK rise
xAF or xAE deasserted from CLOCK rise
MIN
MAX
3
3
26
26
UNITS NOTES
ns
ns
Notes:
1) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
PS3520-1098
Page 21 of 35
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Figure 6:
Processor Read Timing, MMODE = 1
MCIN[1] (RWN)
1
2
3
4
MCIN[0] (CSN)
5
6
WAITN
(Note 3)
7
8
14
9
Valid
ADDR
11
12
10
MDATA
Tristate
Tristate
Valid
13
Table 7:
Processor Read Timing, MMODE = 1
NUMBER
PARAMETER
MIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RWN setup to CSN asserted
RWN hold from CSN asserted
CSN pulsewidth
Delay from CSN deasserted until next CSN
CSN asserted to WAITN asserted
CSN hold from WAITN deasserted
WAITN deasserted from CSN asserted
ADDR setup to CSN asserted
ADDR hold from CSN asserted
MDATA valid from CSN asserted
MDATA tristate from CSN deasserted
MDATA hold from CSN deasserted
CSN asserted to MDATA driven
CSN deasserted to WAITN tristate
4
4
3
1 clock+5 ns
MAX
18
0
2 clocks
2
6
3
3
1 clock
UNITS NOTES
ns
ns
clocks
1
ns
ns
1
ns
ns
2
2
3 clocks+18 ns
2 clocks+24 ns
20
20
ns
ns
10
ns
Note:
1) When WAITN causes CSN to deassert, ignore number 3, otherwise ignore number 6.
2) The device latches ADDR on the falling edge of CSN. The user should latch MDATA on the rising edge of CSN.
3) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
Page 22 of 35
PS3520-1098
advancedhardwarearchitectures
Figure 7:
Processor Write Timing, MMODE = 1
1
2
MCIN[1] (RWN)
3
4
MCIN[0] (CSN)
5
6
WAITN
(Note 4)
7
8
ADDR
12
9
Valid
10
Table 8:
11
Valid
MDATA
Processor Write Timing, MMODE = 1
NUMBER
PARAMETER
MIN
1
2
3
4
5
6
7
8
9
10
11
12
RWN setup to CSN asserted
RWN hold from CSN asserted
CSN pulsewidth
Delay from CSN deasserted until next CSN
CSN asserted to WAITN asserted
CSN hold from WAITN deasserted
WAITN deasserted from CSN asserted
ADDR setup to CSN asserted
ADDR hold from CSN asserted
MDATA valid before CSN deasserted
MDATA hold from CSN deasserted
CSN deasserted to WAITN tristate
4
4
2
1 clock+5 ns
MAX
ns
ns
clocks
18
0
1 clock
2
6
4
4
UNITS NOTES
ns
ns
1
2
1
2 clocks+18 ns
10
ns
ns
ns
ns
ns
3
3
Notes:
1) When WAITN causes CSN to deassert, ignore number 3, otherwise ignore number 6.
2) When a read to a register immediately follows a write to that same register or to the command register, CSN must
deassert for a minimum of 3 clocks after the write.
3) The device latches ADDR on the falling edge of CSN.
4) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
PS3520-1098
Page 23 of 35
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
Figure 8:
Processor Read Timing, MMODE = 0
MCIN[0] (READN)
(Note 3)
1
3
2
4
WAITN
(Note 4)
5
6
12
7
Valid
ADDR
9
8
10
MDATA
Tristate
Tristate
Valid
11
Table 9:
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
Processor Read Timing, MMODE = 0
PARAMETER
READN pulsewidth
Delay from READN deasserted until next
READN
READN asserted to WAITN asserted
READN hold from WAITN deasserted
WAITN deasserted from READN asserted
ADDR setup to READN asserted
ADDR hold from READN asserted
MDATA valid from READN asserted
MDATA tristate from READN deasserted
MDATA hold from READN deasserted
MDATA asserted from READN asserted
READN deasserted to WAITN tristate
MIN
MAX
UNITS NOTES
3
clocks
2
clocks
18
0
2 clocks
2
6
1
ns
ns
1
ns
ns
2
2
3 clocks+18 ns
2 clocks+24 ns
20
3
1 clock
10
ns
ns
ns
Notes:
1) When WAITN causes READN to deassert ignore number 1, otherwise ignore number 4.
2) The device latches ADDR on the falling edge of READN. The user should latch MDATA on the rising edge of
READN.
3) WRITEN must be deasserted during register reads.
4) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
Page 24 of 35
PS3520-1098
advancedhardwarearchitectures
Figure 9:
Processor Write Timing, MMODE = 0
MCIN[1] (WRITEN)
(Note 3)
1
3
2
4
WAITN
(Note 4)
5
6
ADDR
10
7
Valid
8
Valid
MDATA
Table 10:
9
Processor Write Timing, MMODE = 0
NUMBER
PARAMETER
MIN
1
WRITEN pulsewidth
Delay from WRITEN deasserted until next
WRITEN
WRITEN asserted to WAITN asserted
WRITEN hold from WAITN deasserted
WAITN deasserted from WRITEN asserted
ADDR setup to WRITEN asserted
ADDR hold from WRITEN asserted
MDATA valid before WRITEN deasserted
MDATA hold from WRITEN deasserted
WRITEN deasserted to WAITN tristate
2
clocks
3
clocks
2
3
4
5
6
7
8
9
10
MAX
18
0
1 clock
2
6
4
4
UNITS NOTES
ns
ns
1
1
2 clocks+18 ns
10
ns
ns
ns
ns
ns
2
2
Notes:
1) When WAITN causes WRITEN to deassert ignore number 1, otherwise ignore number 4.
2) The device latches ADDR on the falling edge of WRITEN.
3) READN must be deasserted during register writes.
4) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
PS3520-1098
Page 25 of 35
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
Figure 10: Port A/B Timing, Four Edge, Master Mode
1
2
xCOUT (DREQx output)
3
4
5
xCIN (DACKx input)
10
7
6
xDATA (output)
Tristate
Tristate
Valid
9
8
xDATA (input)
Tristate
Table 11:
Port A/B Timing, Four Edge, Master Mode
NUMBER
PARAMETER
1
2
3
4
5
6
7
8
9
10
Tristate
Valid
MIN
DACKx asserted to DREQx deasserted
Delay from DREQx deasserted to next
2 clocks−5 ns
DREQx
DREQx asserted to DACKx asserted
1
DACKx pulsewidth
2
Delay from DACKx deasserted to next
1
DREQx
xDATA (output) driven from DACKx
2
asserted
xDATA (output) hold from DACKx deasserted
2
xDATA (input) valid before DACKx
4
deasserted
xDATA (input) hold from DACKx deasserted
8
xDATA (output) valid from DACKx asserted
MAX
20
UNITS NOTES
ns
1
1
23
23
clocks
clocks
1
1
clocks
1
ns
1
ns
1, 2
ns
1
ns
ns
1
1
Notes:
1) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
2) Internal bus keepers hold the xDATA until overdriven.
Page 26 of 35
PS3520-1098
advancedhardwarearchitectures
Figure 11: Port A/B Timing, Four Edge, Slave Mode
1
2
3
xCIN (DREQx input)
4
5
xCOUT (DACKx output)
xWR or xRD (output)
10
7
6
xDATA (output)
Tristate
9
8
xDATA (input)
Tristate
Table 12:
Port A/B Timing, Four Edge, Slave Mode
NUMBER
PARAMETER
1
2
3
4
5
6
7
8
9
10
Tristate
Valid
Tristate
Valid
MIN
MAX
UNITS NOTES
DREQx pulsewidth
2
clocks
DACKx deasserted from DREQx deasserted
1 clock
2 clocks+22 ns
Delay from DACKx deasserted to next
0
ns
DREQx
DREQx asserted to DACKx asserted
1
clocks
DACKx pulsewidth
2 clocks−8 ns
xDATA (output) driven from DACKx
1 clock−5 ns
asserted
xDATA (output) hold from DACKx deasserted 1 clock−10 ns 1 clock+5 ns
xDATA (input) valid after DREQx
1 clock−5 ns
deasserted
xDATA (input) hold from DACKx deasserted
0
ns
xDATA (output) valid from DACKx asserted
1 clock+10 ns
1
1
1
1
1
1
1, 2
1
1
1
Notes:
1) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
2) Internal bus keepers hold the xDATA until overdriven.
PS3520-1098
Page 27 of 35
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
Figure 12: Port A/B Timing, Burst, Master Mode
1
xCOUT (DREQx output)
2
3
4
5
10
xCIN (DACKx input)
11
6
xDATA (output)
7
Tristate
Valid
Valid
Valid
Tristate
8
9
xDATA (input)
Table 13:
NUMBER
1
2
3
4
5
6
7
8
9
10
11
Tristate
Valid
Valid
Valid
Tristate
Port A/B Timing, Burst, Master Mode
PARAMETER
MIN
Last DACKx asserted to DREQx deasserted,
end of burst
DREQx asserted to first DACKx asserted,
1
start of burst
DACKx pulsewidth
2 clocks−10 ns
DACKx deasserted to DACKx asserted
2 clocks−10 ns
Last DACKx deasserted to next DREQx
2
asserted, next burst
xDATA (output) driven from DACKx
2
asserted
xDATA (output) hold from DACKx deasserted
2
xDATA (input) valid before DACKx
4
deasserted
xDATA (input) hold from DACKx deasserted
8
DACKx cycle time
4
xDATA (output) valid from DACKx asserted
MAX
20
UNITS NOTES
ns
1
clocks
1
1
1
23
23
clocks
1
ns
1
ns
1, 2
ns
1
ns
clocks
ns
1
1
1
Notes:
1) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
2) Internal bus keepers hold the xDATA until overdriven.
Page 28 of 35
PS3520-1098
advancedhardwarearchitectures
Figure 13: Port A/B Timing, Burst, Slave Mode
1
xCIN (DREQx input)
2
3
5
4
xCOUT (DACKx output)
xWR or xRD (output)
10
6
xDATA (output)
Tristate
Valid
8
xDATA (input)
Table 14:
NUMBER
1
2
3
4
5
6
7
8
9
10
7
Tristate
Valid
Valid
Tristate
9
Valid
Valid
Valid
Tristate
Port A/B Timing, Burst, Slave Mode
PARAMETER
Last DACKx asserted to DREQx deasserted,
end of burst
DREQx asserted to first DACKx asserted,
start of burst
DACKx pulsewidth
DACKx deasserted to DACKx asserted
Last DACKx deasserted to next DREQx
asserted, next burst
xDATA (output) driven from DACKx
asserted
xDATA (output) hold from DACKx deasserted
xDATA (input) valid after DACKx asserted
xDATA (input) hold from DACKx deasserted
xDATA (output) valid from DACKx asserted
MIN
MAX
0 ns
3 clocks−22 ns
1
UNITS NOTES
1
clocks
2 clocks−8 ns 2 clocks+8 ns
2 clocks−8 ns
2
1
1
clocks
1 clock−5 ns
1 clock−10 ns 1 clock+5 ns
2 clocks−18 ns
0
1 clock+10 ns
1
1
1
ns
ns
1, 2
1
1
1
Notes:
1) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
2) Internal bus keepers hold the xDATA until overdriven.
PS3520-1098
Page 29 of 35
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
Figure 14: Peripheral Access Read Timing, MMODE = 1
MCIN[1] (RWN)
1
2
3
4
MCIN[0] (CSN)
5
6
WAITN
(Note 5)
7
8
16
9
Valid
ADDR
10
MDATA (output)
Tristate
Tristate
Valid
12
11
13
xRDN
14
15
xPCSN
xDATA (input)
Table 15:
Valid
Peripheral Access Read Timing, MMODE = 1
NUMBER
PARAMETER
MIN
1
2
3
4
5
6
RWN setup to CSN asserted
RWN hold from CSN asserted
CSN pulsewidth
Delay from CSN deasserted until next CSN
CSN asserted to WAITN asserted
CSN hold from WAITN deasserted
4
4
(n+1)
2
5
0
7
WAITN deasserted from CSN asserted
8
9
10
ADDR setup to CSN asserted
ADDR hold from CSN asserted
MDATA (output) hold from CSN deasserted
MDATA (output) valid from xDATA (input)
valid
xRDN asserted from CSN asserted
xRDN deasserted from CSN deasserted
xPCSN asserted from CSN asserted
xPCSN deasserted from CSN deasserted
CSN deasserted to WAITN tristate
11
12
13
14
15
16
n clocks
4
4
3
1 clock
1 clock
1 clock
1 clock
0
MAX
18
UNITS NOTES
ns
ns
clocks
clocks
ns
ns
(n+1) clocks
+18 ns
1, 2
1
2
3
3
20
ns
ns
ns
19
ns
4
2 clocks+21 ns
2 clocks+21 ns
2 clocks+21 ns
2 clocks+21 ns
10
4
4
4
4
ns
Notes:
1) When WAITN causes CSN to deassert ignore number 3, otherwise ignore number 6.
2) “n” is the number of wait states programmed into the xCNF registers.
3) The device latches ADDR on the falling edge of CSN. The user should latch MDATA on the rising edge of CSN.
4) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
5) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
Page 30 of 35
PS3520-1098
advancedhardwarearchitectures
Figure 15: Peripheral Access Write Timing, MMODE = 1
1
2
MCIN[1] (RWN)
3
4
MCIN[0] (CSN)
5
6
WAITN
(Note 5)
7
8
19
9
Valid
ADDR
10
MDATA
Tristate
11
Tristate
Valid
12
13
14
15
xWRN
xPCSN
16
17
xDATA (output) Tristate
Tristate
Valid
18
Table 16: Peripheral Access Write Timing, MMODE = 1
NUMBER
PARAMETER
MIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RWN setup to CSN asserted
RWN hold from CSN asserted
CSN pulsewidth
Delay from CSN deasserted until next CSN
CSN asserted to WAITN asserted
CSN hold from WAITN deasserted
WAITN deasserted from CSN asserted
ADDR setup to CSN asserted
ADDR hold from CSN asserted
MDATA valid before CSN deasserted
MDATA hold from CSN deasserted
xWRN asserted from CSN asserted
xWRN deasserted from CSN deasserted
xPCSN asserted from CSN asserted
xPCSN deasserted from CSN deasserted
xDATA (output) tristated from CSN
deasserted
xDATA valid from CSN deasserted
CSN asserted to xDATA driven
MCIN[0] inactive to WAITN tristate
4
4
(n+1)
3
5
0
n clocks
4
4
4
4
1 clock
1 clock
1 clock
1 clock
2 clocks
1 clock
0
MAX
18
UNITS NOTES
ns
ns
clocks
clocks
ns
ns
(n+1) clocks+18 ns
ns
ns
ns
ns
1, 2
6
1
2
3
3
2 clocks+21 ns
2 clocks+21 ns
2 clocks+21 ns
2 clocks+21 ns
4
4
4
4
3 clocks+17 ns
4
19
ns
10
ns
4
Notes:
1) When WAITN causes CSN to deassert ignore number 3, otherwise ignore number 6.
2) “n” is the number of wait states programmed into the xCNF registers.
3) The device latches ADDR on the falling edge of CSN.
4) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
5) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
6) This timing applies to before a write access as well as after.
PS3520-1098
Page 31 of 35
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
Figure 16: Peripheral Access Read Timing, MMODE = 0
1
2
MCIN[0] (READN)
3
4
WAITN
(Note 6)
5
6
14
7
Valid
ADDR
8
MDATA (output)
Tristate
Tristate
Valid
10
9
11
xRDN
12
13
xPCSN
xDATA (input)
Table 17:
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Valid
Peripheral Access Read Timing, MMODE = 0
PARAMETER
MIN
MAX
UNITS NOTES
READN pulsewidth
(n+1)
clocks
Delay from READN deasserted until next
2
clocks
READN
READN asserted to WAITN asserted
5
18
ns
READN hold from WAITN deasserted
0
ns
WAITN deasserted from READN asserted
n clocks (n+1) clocks+18 ns
ADDR setup from READN asserted
4
ns
ADDR hold from READN asserted
4
ns
MDATA (output) hold from READN
3
20
ns
deasserted
MDATA (output) valid from xDATA (input)
19
ns
valid
xRDN asserted from READN asserted
1 clock
2 clocks+21 ns
xRDN deasserted from READN deasserted
1 clock
2 clocks+21 ns
xPCSN asserted from READN asserted
1 clock
2 clocks+21 ns
xPCSN deasserted from READN deasserted 1 clock
2 clocks+21 ns
READN deasserted to WAITN tristate
0
10
ns
1, 2
1
2
2
2
5
5
5
5
5
Notes:
1) When WAITN causes READN to deassert ignore number 1, otherwise ignore number 4.
2) The device latches ADDR on the falling edge of READN. The user should latch MDATA on the rising edge of READN.
3) WRITEN must be deasserted during register reads.
4) “n” is the number of wait states programmed into the xCNF registers.
5) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
6) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
Page 32 of 35
PS3520-1098
advancedhardwarearchitectures
Figure 17: Peripheral Access Write Timing, MMODE = 0
1
2
MCIN[1] (WRITEN)
3
4
WAITN
(Note 6)
5
6
17
7
Valid
ADDR
8
MDATA (input)
Tristate
9
Tristate
Valid
10
11
12
13
xWRN
xPCSN
14
15
xDATA (output)
Tristate
Tristate
Valid
16
Table 18:
Peripheral Access Write Timing, MMODE = 0
NUMBER
PARAMETER
MIN
1
WRITEN pulsewidth
Delay from WRITEN deasserted until next
WRITEN
WRITEN asserted to WAITN asserted
WRITEN hold from WAITN deasserted
WAITN deasserted from WRITEN asserted
ADDR setup from WRITEN asserted
ADDR hold from WRITEN asserted
MDATA valid before WRITEN deasserted
MDATA hold from WRITEN deasserted
xWRN asserted from WRITEN asserted
xWRN deasserted from WRITEN deasserted
xPCSN asserted from WRITEN asserted
xPCSN deasserted from WRITEN deasserted
xDATA (output) tristated from WRITEN deasserted
xDATA valid from WRITEN deasserted
WRITEN asserted to xDATA driven
WRITEN inactive to WAITN tristate
(n+1)
clocks
3
clocks
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
5
0
n clocks
4
4
4
4
1 clock
1 clock
1 clock
1 clock
2 clocks
1 clock
0
MAX
18
UNITS NOTES
ns
ns
(n+1) clocks+18 ns
ns
ns
ns
ns
2 clocks+21 ns
2 clocks+21 ns
2 clocks+21 ns
2 clocks+21 ns
3 clocks+17 ns
19
ns
10
ns
1, 2
1
2
2
2
5
5
5
5
5
5
5
Notes:
1) When WAITN causes WRITEN to deassert ignore number 1, otherwise ignore number 4.
2) The device latches ADDR on the falling edge of WRITEN.
3) READN must be deasserted during register writes.
4) “n” is the number of wait states programmed into the xCNF registers.
5) These timings are valid for both Port A and Port B and inverted signal polarities. Replace “x” with “A” for Port
A signals and “B” for Port B signals.
6) WAITN is pulled up internally with a 10K resistor when not active and not driven low.
PS3520-1098
Page 33 of 35
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
11.0 PACKAGING
Figure 18: AHA3520 PQFP Package Specifications
D
D1
P
81
82
83
84
85
B
AHA3520A-040 PQC
(LCA)
E1 E
96
97
98
99
P
100
26 27 28 29 30
(LCB)
A2 A
L
Table 19:
A1
PQFP (Plastic Quad Flat Pack) 14 mm × 20 mm Package Dimensions
(All dimensions are in mm)
NUMBER OF PIN AND SPECIFICATION DIMENSION
SYMBOL
MIN
(LCA)
(LCB)
A
A1
A2
D
D1
E
E1
L
P
B
0.1
2.57
23.65
19.9
17.65
13.9
0.73
0.22
100
RB
NOM
20
30
0.23
2.71
23.9
20
17.9
14
0.88
0.65
0.3
MAX
3.1
0.36
2.87
24.15
20.1
18.15
14.1
1.03
0.33
JEDEC Outline MO-112
Page 34 of 35
PS3520-1098
advancedhardwarearchitectures
12.0 ORDERING INFORMATION
12.1 AVAILABLE PARTS
PART NUMBER
DESCRIPTION
AHA3520A-040 PQC
20 MBytes/sec ALDC Data Compression Coprocessor IC
with Enhanced Features, PQFP
12.2 PART NUMBERING
AHA
3520
A-
040
P
Q
C
Manufacturer
Device
Number
Revision
Level
Speed
Designation
Package
Material
Package
Type
Test
Specification
Device Number:
3520
Revision Letter:
A
Package Material Codes:
P
Plastic
Package Type Codes:
Q Q - Quad Flat Pack
Test Specifications:
C Commercial 0°C to +70°C
13.0 AHA RELATED TECHNICAL PUBLICATIONS
DOCUMENT #
PB3520
PB3521
PS3521
ANDC18
ANDC19
PS3520-1098
DESCRIPTION
AHA Product Brief – AHA3520 20 MBytes/sec ALDC Data Compression
Coprocessor IC
AHA Product Brief – AHA3521 20 MBytes/sec ALDC Data Compression
Coprocessor IC with Enhanced Features
AHA Product Specification – AHA3521 20 MBytes/sec ALDC Data
Compression Coprocessor IC with Enhanced Features
AHA Application Note – Differences between AHA and IBM Devices
AHA Application Note – Designer’s Guide for ALDC Compression/
Decompression Devices: AHA3520 and AHA3521
Page 35 of 35