NSC MM54HCT190

MM54HCT190/MM74HCT190 Synchronous Decade Up/
Down Counters with Mode Control. MM54HCT191/
MM74HCT191 Synchronous Binary Up/Down Counters
with Mode Control
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology. They possess the high noise
immunity and low power consumption of CMOS technology,
along with the speeds of low power Schottky TTL. These
circuits are synchronous, reversible, up/down counters. The
MM54HCT191/MM74HCT191 are 4-bit binary counters and
the MM54HCT190/MM74HCT190 are BCD counters.
Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic. This mode
of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting. The direction of the count is determined by the level of
the down/up input. When low, the counter counts up and
when high, it counts down.
These counters are fully programmable; that is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input. This feature allows the counters to be used as divide by
N dividers by simply modifying the count length with the
preset inputs.
Two outputs have been made available to perform the cascading function; ripple clock and maximum/minimum count.
The latter output produces a high level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low level output pulse equal in
width to the low level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high speed operation.
MM54HCT/MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices can be used to reduce power consumption in
existing designs.
Features
Y
Y
Y
Y
Connection Diagram
Level changes on Enable or Down/Up can be made
regardless of the level of the clock.
Low quiescent supply current: 80 mA maximum
(74HCT Series)
Low input current: 1 mA maximum
TTL compatible inputs
Truth Table
Dual-In-Line Package
Load
Enable
G
Down/
Up
H
H
L
H
L
L
X
H
L
H
X
X
Clock
Function
u
u
Count Up
Count Down
Load
No Change
X
X
Order Number MM54HCT190/191
or MM74HCT190/191
TL/F/5744 – 1
C1995 National Semiconductor Corporation
TL/F/5744
RRD-B30M105/Printed in U. S. A.
MM54HCT190/MM74HCT190 Synchronous Decade Up/Down Counters with Mode Control.
MM54HCT191/MM74HCT191 Synchronous Binary Up/Down Counters with Mode Control
January 1988
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr, tf)
b 0.5V to a 7.0V
Supply Voltage (VCC)
b 1.5V to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5V to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per Pin (IOUT)
g 50 mA
DC VCC or GND Current, per Pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
Min
4.5
Max
5.5
Units
V
0
VCC
V
b 40
b 55
a 85
a 125
§C
§C
500
ns
260§ C
DC Electrical Characteristics VCC e 5V g 10% unless otherwise specified
Symbol
Parameter
Conditions
TA e 25§ C
74HCT
54HCT
TA eb40§ C to 85§ C TA eb55§ C to 125§ C Units
Typ
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level VIN e VIH or VIL
Output Voltage
VCC VCCb0.1
lIOUTl e 20 mA
lIOUTl e 4.0 mA, VCC e 4.5V 4.2 3.98
lIOUTl e 4.8 mA, VCC e 5.5V 5.2 4.98
VCCb0.1
3.84
4.84
VCCb0.1
3.7
4.7
V
V
V
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
g 0.1
g 1.0
g 1.0
mA
8
80
160
mA
1.0
1.2
1.3
mA
VOL
Maximum Low Level VIN e VIH or VIL
Voltage
lIOUTl e 20 mA
lIOUTl e 4.0 mA, VCC e 4.5V
lIOUTl e 4.8 mA, VCC e 5.5V
IIN
Maximum Input
Current
ICC
Maximum Quiescent VIN e VCC or GND
Supply Current
IOUT e 0 mA
0
0.2
0.2
VIN e VCC or GND,
VIH or VIL
VIN e 2.4V or 0.5V (Note 4)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power dissipation temperature deratingÐplastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: Measured per pin, all other inputs held at VCC or GND.
2
AC Electrical Characteristics
Symbol
Parameter
TA e 25§ C, VCC e 5.0V, tr e tf e 6 ns, CL e 15 pF unless otherwise specified
From
Input
To
Output
Conditions
Typ
Guaranteed
Limits
Units
fMAX
Maximum Clock Frequency
40
MHz
tPLH, tPHL
Maximum Propagation
Delay Time
Load
QA, QB
QC, QD
30
ns
tPLH, tPHL
Maximum Propagation
Delay Time
Data A,
B, C, D
QA, QB
QC, QD
27
ns
tPLH, tPHL
Maximum Propagation
Delay Time
Clock
Ripple Clock
16
ns
tPLH, tPHL
Maximum Propagation
Delay Time
Clock
QA, QB
QC, QD
24
ns
tPLH, tPHL
Maximum Propagation
Delay Time
Clock
Max/Min
30
ns
tPLH, tPHL
Maximum Propagation
Delay Time
Down/Up
Ripple Clock
29
ns
tPLH, tPHL
Maximum Propagation
Delay Time
Down/Up
Max/Min
22
ns
tPHL, tPLH
Maximum Propagation
Delay Time
Enable
Ripple Clock
22
ns
tW
Minimum Clock or Load
Input Pulse Width
10
ns
3
AC Electrical Characteristics VCC e 5V g 10%, CL e 50 pF, tr e tf e 6 ns unless otherwise specified
Symbol
fMAX
Parameter
From
Input
74HCT
54HCT
To
T e 25§ C
Conditions A
TA eb40§ C to 85§ C TA eb55§ C to 125§ C Units
Output
Typ
Guaranteed Limits
Maximum Clock
Frequency
28
20
16
13
MHz
tPLH, tPHL Maximum Propagation Delay Time
Load
QA, QB
QC, QD
31
44
55
66
ns
tPLH, tPHL Maximum Propagation Delay Time
Data A,
B, C, D
QA, QB
QC, QD
30
40
50
60
ns
tPLH, tPHL Maximum Propagation Delay Time
Clock
Ripple
Clock
24
30
38
45
ns
tPLH, tPHL Maximum Propagation Delay Time
Clock
QA, QB
QC, QD
32
43
54
65
ns
tPLH, tPHL Maximum Propagation Delay Time
Clock
Max/Min
45
55
69
83
ns
tPLH, tPHL Maximum Propagation Delay Time
Down/Up
Ripple
Clock
42
50
63
75
ns
tPLH, tPHL Maximum Propagation Delay Time
Down/Up Max/Min
30
45
56
68
ns
26
33
41
50
ns
15
25
31
38
ns
tPHL, tPLH Propagation Delay
Time
Enable
Ripple
Clock
tW
Minimum Clock
Pulse Width
tS
Minimum Set-Up Time
Data
Load
10
20
25
30
ns
tH
Minimum Hold Time
Load
Data
b3
5
6
8
ns
tS
Minimum Set-Up Time
Down/Up
Clock
23
30
38
45
ns
tH
Minimum Hold Time
Clock
Down/Up
b7
0
0
0
ns
tS
Minimum Set-Up Time
Enable
Clock
13
20
25
30
ns
tH
Minimum Hold Time
Clock
Enable
b5
0
0
0
ns
10
15
19
22
ns
tTHL, tTLH Maximum Output
Rise and Fall Time
CIN
Maximum Input Capacitance
5
pF
CPD
Power Dissipation
Capacitance (Note 5)
35
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
4
Timing Diagrams
’HCT190 Synchronous Decade Counters
Typical Load, Count, and Inhibit Sequences
TL/F/5744 – 5
Sequence:
(1) Load (preset) to BCD seven
(2) Count up to eight, nine, zero, one and two
(3) Inhibit
(4) Count down to one, zero, nine, eight and seven
’HCT191 Synchronous Binary Counters
Typical Load, Count, and Inhibit Sequence
TL/F/5744 – 6
Sequence:
(1) Load (preset) to binary thirteen
(2) Count up to fourteen, fifteen, zero, one and two
(3) Inhibit
(4) Count down to one, zero, fifteen, fourteen and thirteen
5
Logic Diagram
’HCT191
TL/F/5744 – 3
6
Logic Diagram (Continued)
’HCT190 Decade Counters
TL/F/5744 – 7
7
MM54HCT190/MM74HCT190 Synchronous Decade Up/Down Counters with Mode Control.
MM54HCT191/MM74HCT191 Synchronous Binary Up/Down Counters with Mode Control
Physical Dimensions inches (millimeters)
Order Number MM54HCT191J or MM74HCT191J
NS Package J16A
Order Number MM74HCT191N
NS Package N16E
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