MM54HC190/MM74HC190 Synchronous Decade Up/Down Counters with Mode Control MM54HC191/MM74HC191 Synchronous Binary Up/Down Counters with Mode Control General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of CMOS technology, along with the speeds of low power Schottky TTL. These circuits are synchronous, reversible, up/down counters. The MM54HC191/MM74HC191 are 4-bit binary counters and the MM54HC190/MM74HC190 are BCD counters. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input, if the enable input is low. A high at the enable input inhibits counting. The direction of the count is determined by the level of the down/up input. When low, the counter counts up and when high, it counts down. These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo- N dividers by simply modifying the count length with the preset inputs. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. Features Y Y Y Y Level changes on Enable or Down/Up can be made regardless of the level of the clock input Wide power supply range: 2 – 6V Low quiescent supply current: 80 mA maximum (74HC Series) Low input current: 1 mA maximum Connection Diagram Dual-In-Line Package Load Enable G Down/ Up H H L H L L X H L H X X Clock Function u u Count Up Count Down Load No Change X X Asynchronous inputs Low input to load sets QA e A, QB e B, QC e C, and QD e D Order Number MM54HC190/191 or MM74HC190/191 TL/F/5322 – 1 Top View C1995 National Semiconductor Corporation TL/F/5322 RRD-B30M105/Printed in U. S. A. MM54HC190/MM74HC190/MM54HC191/MM74HC191 January 1988 Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics TA e 25§ C, VCC e 5.0V, tr e tf e 6 ns, CL e 15 pF (unless otherwise specified) Symbol From (Input) Parameter To (Output) Typ Units 40 MHz fMAX Maximum Clock Frequency tPLH, tPHL Maximum Propagation Delay Time Load QA, QB QC, QD 30 ns tPLH, tPHL Maximum Propagation Delay Time Data A, B, C, D QA, QB QC, QD 27 ns tPLH, tPHL Maximum Propagation Delay Time Clock Ripple Clock 16 ns tPLH, tPHL Maximum Propagation Delay Time Clock QA, QB QC, QD 24 ns tPLH, tPHL Maximum Propagation Delay Time Clock Max/Min 30 ns tPLH, tPHL Maximum Propagation Delay Time Down/Up Ripple Clock 29 ns tPLH, tPHL Maximum Propagation Delay Time Down/Up Max/Min 22 ns tPHL, tPLH Maximum Propagation Delay Time Enable Ripple Clock 22 ns tW Minimum Clock, Clear or Load Input Pulse Width 10 ns AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter From (Input) To (Output) TA e 25§ C VCC Typ fMAX Maximum Clock Frequency tPLH, tPHL Maximum Propagation Delay Time Load tPLH, tPHL Maximum Propagation Delay Time tPLH, tPHL tPLH, tPHL 74HC TA e b40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits 2.0V 4.5V 6.0V 9 30 36 4.0 20 24 3.5 16 19 2.6 13 15 MHz MHz MHz QA, QB QC, QD 2.0V 4.5V 6.0V 80 27 21 220 44 37 275 55 47 330 66 56 ns ns ns Data A, B, C, D QA, QB QC, QD 2.0V 4.5V 6.0V 71 25 19 200 40 34 250 50 43 300 60 51 ns ns ns Maximum Propagation Delay Time Clock Ripple Clock 2.0V 4.5V 6.0V 44 25 14 125 25 21 155 31 26 190 38 32 ns ns ns Maximum Propagation Delay Time Clock QA, QB QC, QD 2.0V 4.5V 6.0V 83 29 22 215 43 37 270 54 46 325 65 55 ns ns ns 3 AC Electrical Characteristics (Continued) Symbol Parameter From (Input) 74HC 54HC TA e 25§ C To Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units (Output) Typ Guaranteed Limits tPLH, tPHL Maximum Propagation Delay Time Clock Max/Min tPLH, tPHL Maximum Propagation Delay Time Down/Up Ripple Clock tPLH,tPHL Maximum Propagation Delay Time Down/Up Max/Min tPHL, tPLH Maximum Propagation Delay Time Enable Ripple Clock 2.0V 125 4.5V 41 6.0V 31 255 51 43 320 64 54 385 77 65 ns ns ns 2.0V 4.5V 6.0V 90 30 24 210 42 36 265 53 45 315 63 54 ns ns ns 2.0V 4.5V 6.0V 88 30 23 190 38 32 240 48 41 285 57 48 ns ns ns 2.0V 4.5V 6.0V 50 18 14 125 25 21 155 31 26 190 38 32 ns ns ns 2.0V 4.5V 6.0V 36 12 9 125 25 21 155 31 26 190 38 32 ns ns ns 50 14 10 100 20 17 125 25 21 150 30 26 ns ns ns tW Minimum Clock, Load or Clear Input Pulse Width tS Minimum Setup Time Data Load 2.0V 4.5V 6.0V tH Data Hold Time Load Data 2.0V b16 4.5V b3 6.0V b2 25 5 5 30 6 6 40 8 7 ns ns ns tS Minimum Setup Time Down/Up Clock 2.0V 4.5V 6.0V 150 30 26 190 38 33 225 48 38 ns ns ns tH Minimum Hold Time Clock Down/Up 0 0 0 0 0 0 0 0 0 ns ns ns tS Minimum Setup Time Enable Clock 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 26 ns ns ns tH Minimum Hold Time Clock Enable 2.0V b11 4.5V b5 6.0V b3 0 0 0 0 0 0 0 0 0 ns ns ns trem Minimum Removal Time Load Clock 2.0V 4.5V 6.0V 1 1 0 25 5 5 30 6 6 40 8 7 ns ns ns tTHL, tTLH Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 30 10 9 75 15 13 95 19 16 110 22 19 s ns ns tW Minimum Load Pulse Width 2.0V 4.5V 6.0V 53 15 12 100 20 17 125 25 21 150 30 26 ns ns ns CIN Input Capacitance 5 10 10 10 pF CPD Power Dissipation Capacitance (Note 5) 35 62 18 14 2.0V b23 4.5V b5 6.0V b4 28 10 7 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 4 Logic Diagrams ’HC190 Decade Counters TL/F/5322 – 2 Pin (16) e VCC, Pin (8) e GND 5 Logic Diagrams (Continued) ’HC191 Binary Counters TL/F/5322 – 3 Pin (16) e VCC, Pin (8) e GND 6 Timing Diagrams ’HC190 Synchronous Decade Counters Typical Load, Count, and Inhibit Sequences TL/F/5322 – 4 Sequence: (1) Load (preset) to BCD seven (2) Count up to eight, nine, zero, one and two (3) Inhibit (4) Count down to one, zero, nine, eight, and seven ’HC191 Synchronous Binary Counters Typical Load, Count, and Inhibit Sequence TL/F/5322 – 5 Sequence: (1) Load (preset) to binary thirteen (2) Count up to fourteen, fifteen, zero, one, and two (3) Inhibit (4) Count down to one, zero, fifteen, fourteen, and thirteen 7 MM54HC190/MM74HC190/MM54HC191/MM74HC191 Physical Dimensions inches (millimeters) Order Number MM54HC190J, MM54HC191J, MM74HC190J, or MM74HC191J NS Package J16A Order Number MM74HC190N or MM74HC191N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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