NSC MM54HC193

MM54HC192/MM74HC192
Synchronous Decade Up/Down Counters
MM54HC193/MM74HC193
Synchronous Binary Up/Down Counters
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of CMOS technology,
along with the speeds of low power Schottky TTL. The
MM54HC192/MM74HC192 is a decade counter, and the
MM54HC193/MM74HC193 is a binary counter. Both counters have two separate clock inputs, an UP COUNT input
and a DOWN COUNT input. All outputs of the flip-flops are
simultaneously triggered on the low to high transition of either clock while the other input is held high. The direction of
counting is determined by which input is clocked.
These counters may be preset by entering the desired data
on the DATA A, DATA B, DATA C, and DATA D inputs.
When the LOAD input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as divide-by-n counters by modifying the
count length with the preset inputs.
In addition both counters can also be cleared. This is accomplished by inputting a high on the CLEAR input. All 4
internal stages are set to a low level independently of either
COUNT input.
Connection Diagram
Both a BORROW and CARRY output are provided to enable cascading of both up and down counting functions. The
BORROW output produces a negative going pulse when the
counter underflows and the CARRY outputs a pulse when
the counter overflows. The counters can be cascaded by
connecting the CARRY and BORROW outputs of one device to the COUNT UP and COUNT DOWN inputs, respectively, of the next device.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
Y
Y
Y
Y
Y
Y
Typical propagation delay,
Count up to Q: 28 ns
Typical operating frequency: 27 MHz
Wide power supply range: 2 – 6V
Low quiescent supply current: 80 mA maximum
(74HC Series)
Low input current: 1 mA maximum
4 mA output drive
Truth Table
Count
Dual-In-Line Package
Up
Clear
Load
Function
L
L
H
L
H
H
X
L
Count Up
Count Down
Clear
Load
Down
u
H
H
X
X
u
X
X
H e high level
L e low level
u e transition from low-to-high
X e don’t care
TL/F/5011 – 1
Order Number MM54HC192/193 or MM74HC192/193
C1995 National Semiconductor Corporation
TL/F/5011
RRD-B30M115/Printed in U. S. A.
MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters
MM54HC193/MM74HC193 Synchronous Binary Up/Down Counters
January 1988
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics TA e 25§ C, VCC e 5.0V, tr e tf e 6 ns, CL e 15 pF (unless otherwise specified)
Symbol
Parameter
Conditions
fMAX
Maximum Clock Frequency
tPLH
Maximum Propagation Delay
Low to High
tPHL
Maximum Propagation Delay
High to Low
tPLH
Maximum Propagation Delay
Low to High
tPHL
Maximum Propagation Delay
High to Low
tPLH
Maximum Propagation Delay
Low to High
tPHL
Maximum Propagation Delay
High to Low
tPLH
Maximum Propagation Delay
Low to High
tPHL
Maximum Propagation Delay
High to Low
tPHL
Maximum Propagation Delay
High to Low
tW
Minimum Pulse Width
tSD
Minimum Setup time
tHD
Minimum Hold Time
tREM
Minimum Removal Time
Typ
Guaranteed
Limit
Units
Count Up
27
20
MHz
Count Down
31
24
MHz
17
26
ns
18
24
ns
16
24
ns
15
24
ns
28
40
ns
36
52
ns
30
42
ns
40
55
ns
35
47
ns
Count Up to Carry
Count Down to
Borrow
Count Up Or
Down to Q
Data or
Load to Q
Clear to Q
Clear
’HC192
’HC193
40
20
52
26
ns
ns
Load
’HC192
’HC193
40
10
52
20
ns
ns
15
22
ns
10
20
ns
b3
0
ns
10
ns
Count Up/Down
Data to Load
Clear Inactive
to Clock
AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
fMAX
tPLH
tPHL
74HC
54HC
TA eb40 to 85§ C TA eb55 to 125§ C Units
Guaranteed Limits
Count Up
2.0V
4.5V
6.0V
5
25
29
3
18
20
2.5
14
16
2
12
13
MHz
MHz
MHz
Count Down
2.0V
4.5V
6.0V
5
27
31
4
20
23
3
16
18
2
11
12
MHz
MHz
MHz
2.0V
4.5V
6.0V
30
13
11
140
28
24
175
35
30
210
42
36
ns
ns
ns
2.0V
4.5V
6.0V
39
16
14
130
26
22
163
33
28
195
39
33
ns
ns
ns
Maximum Clock Frequency
Maximum Propagation Delay
Low to High
Count Up
Maximum Propagation Delay to Carry
High to Low
3
AC Electrical Characteristics (Continued) VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
tPLH, tPHL Maximum Propagation Delay
Guaranteed Limits
2.0V
4.5V
6.0V
39
16
14
130
26
22
163
33
28
195
39
33
ns
ns
ns
tTLH, tTHL Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tPLH
Maximum Propagation Delay
Low to High
2.0V
4.5V
6.0V
77
35
30
215
43
37
269
54
46
323
65
55
ns
ns
ns
tPHL
Maximum Propagation Delay
High to Low
2.0V
4.5V
6.0V
95
45
38
275
55
47
344
69
59
413
83
71
ns
ns
ns
tPLH
Maximum Propagation Delay
Low to High
2.0V
4.5V
6.0V
85
37
30
230
46
39
288
58
49
345
69
59
ns
ns
ns
tPHL
Maximum Propagation Delay
High to Low
2.0V 102
4.5V 47
6.0V 39
290
58
49
363
73
61
435
87
74
ns
ns
ns
tPHL
Maximum Propagation Delay
High to Low
2.0V
4.5V
6.0V
85
42
38
265
53
45
331
66
56
398
80
68
ns
ns
ns
Clear
or
Load
2.0V 119
’HC192 4.5V 42
6.0V 38
260
52
45
325
65
56
390
78
68
ns
ns
ns
Load
2.0V
’HC193 4.5V
6.0V
31
10
9
100
20
17
125
25
21
150
30
26
ns
ns
ns
2.0V
Count Up/Down 4.5V
6.0V
43
17
15
110
22
19
138
28
24
165
33
29
ns
ns
ns
2.0V
’HC193 4.5V
6.0V
70
21
19
130
26
22
163
33
28
195
39
33
ns
ns
ns
2.0V
4.5V
6.0V
30
10
9
100
20
17
125
25
22
150
30
25
ns
ns
ns
2.0V b30
4.5V b3
6.0V b3
0
0
0
0
0
0
0
0
0
ns
ns
ns
2.0V b20
4.5V b3
6.0V b2
10
10
10
10
10
10
10
10
10
ns
ns
ns
2.0V
4.5V
6.0V
500
300
200
500
300
200
500
300
200
ns
ns
ns
10
10
10
pF
tW
Count Down
to Borrow
74HC
54HC
TA eb40 to 85§ C TA eb55 to 125§ C Units
Count Up Or
Down to Q
Data or
Load to Q
Clear to Q
Minimum Pulse Width
Clear
tSD
Minimum Setup Time
tHD
Minimum Hold Time
tREM
Minimum Removal Time
tr, tf
Maximum Count Up or Down
Input Rise & Fall Time
CIN
Input Capacitance
CPD
Power Dissipation Capacitance (Note 5)
Data
To
Load
Clear Inactive
to Clock
5
100
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
4
MM54HC192 Synchronous 4-Bit Up/Down Decade Counter
TL/F/5011 – 2
Logic Diagrams
5
MM54HC193 Synchronous 4-Bit Up/Down Binary Counter
TL/F/5011 – 3
Logic Diagrams (Continued)
6
Logic Waveforms
’HC192 Synchronous Decade Counters
Typical Clear, Load, and Count Sequences
TL/F/5011 – 4
Sequences:
(1) Clear outputs to zero
(2) Load (preset) to BCD seven.
(3) Count up to eight, nine, carry, zero, one and two.
(4) Count down to one, zero, borrow, nine, eight, and seven.
’HC193 Synchronous Binary Counters
Typical Clear, Load, and Count Sequences
TL/F/5011 – 5
Sequence:
(1) Clear outputs to zero.
(2) Load (preset) to binary thirteen
(3) Count up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Note A: Clear overrides load data, and count inputs.
Note B: When counting up, count-down input must be high; when counting down, count-up input must be high.
7
MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters
MM54HC193/MM74HC193 Synchronous Binary Up/Down Counters
Physical Dimensions inches (millimeters)
Order Number MM54HC192J, MM54HC193J, MM74HC192J or MM74HC193J
NS Package J16A
Order Number MM74HC192N or MM74HC193N
NS Package N16E
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