May 21, 2009 Stereo Class AB Audio Subsystem with a True Ground Headphone Amplifier General Description RL = 8Ω speaker 520W (typ) The LM49200 is a fully integrated audio subsystem with a stereo power amplifier capable of delivering 500mW of continuous average power per channel into 8Ω with 1% THD+N using a 3.3V supply. The LM49200 includes a separate stereo headphone amplifier that can deliver 35mW per channel into 32Ω. The LM49200 has three input channels. A pair of single-ended inputs and a fully differential input channel. The LM49200 features a 32-step digital volume control on the input stage and an 8-step digital volume control on the headphone output stage. The digital volume control and output modes are programmed through a two-wire I2C compatible interface that allows flexibility in routing and mixing audio channels. The LM49200 is designed for cellular phone, PDA, and other portable handheld applications. The high level of integration minimizes external components. The True Ground headphone amplifier eliminates the physically large DC blocking output capacitors reducing required board space and reducing cost. RL = 32Ω headphone 38mW (typ) Key Specifications ■ Supply Voltage (VDD) ■ I2C Supply Voltage 2.7V ≤ VDD ≤ 5.5V 1.7V ≤ I2CVDD ≤ 5.5V ■ Output power at VDD = 5V, 1% THD+N ■ PSRR: VDD = 3.3V, 217Hz ripple, Mono In ■ Shutdown power supply current 95dB (typ) 0.02μA (typ) Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Differential mono input and stereo single-ended input 32-step digital volume control (-80 to +18dB) Three independent volume channels (Left, Right, Mono) Separate headphone volume control Flexible output for speaker and headphone output True Ground headphone amplifier eliminates large DC blocking capacitors reducing PCB space and cost Receiver pass-through capability Soft enable function RF immunity topology “Click and Pop” suppression circuitry Thermal shutdown protection Micro-power shutdown I2C control interface Available in space-saving microSMD package Applications RL = 8Ω speaker 1.25W (typ) RL = 32Ω headphone 38mW (typ) ■ Portable electronic devices ■ Mobile Phones ■ PDAs ■ Output power at VDD = 3.3V, 1% THD+N Boomer® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 300627 www.national.com LM49200 Stereo Class AB Audio Subsystem with a True Ground Headphone Amplifier LM49200 LM49200 Typical Application 30062752 FIGURE 1. Typical Audio Application Circuit www.national.com 2 LM49200 Connection Diagrams 20 Bump micro SMD Package micro SMD Markings 30062751 Top View XY - Date Code TT - Die Traceability G- Boomer Family L3 - LM49200TL 30062750 Top View (Bump Side Down) Order Number LM49200TL, LM49200TLX See NS Package Number TLA20BBA Ordering Information Order Number Package Package DWG # LM49200TL 20 Bump micro SMD LM49200TLX 20 Bump micro SMD Transport Media MSL Level Green Status TLA20BBA 250 units on tape and reel 1 RoHS and no sB/Br TLA20BBA 3000 units on tape and reel 1 RoHS and no sB/Br 3 www.national.com LM49200 Bump Descriptions Bump Name Pin Function Type A1 ROUT- Right Loudspeaker Negative Output Analog Output A2 VDD Power Supply Power Input A3 MIN+ Differential Mono Positive Input Analog Input A4 MIN- Differential Mono Negative Input Analog Input B1 ROUT+ Right Loudspeaker Positive Output Analog Output B2 I2CVDD I2C power supply Power Input B3 LIN Single-ended Left Input Analog Input Analog Input B4 RIN Single-ended Right Input C1 GND Power Ground Ground C2 SCL I2C Clock Digital Input C3 BIAS Half-Supply Bias point, capacitor bypassed Analog Output C4 VSSCP Negative Charge Pump Power Supply Analog Output D1 LOUT+ Left Loudspeaker Negative Output Analog Output I2C Data D2 SDA D3 CIN Negative Terminal Charge Pump Flying Capacitor Analog Output D4 CIP Positive Terminal Charge Pump Flying Capacitor Analog Output E1 LOUT- Left Loudspeaker Positive Output Analog Output E2 HPR Right Headphone Output Analog Output E3 HPL Left Headphone Output Analog Output E4 CPGND Charge Pump Ground Ground www.national.com 4 Digital Input If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (Note 1) Storage Temperature Voltage at Any Input Pin Power Dissipation (Note 3) ESD Rating (Note 4) ESD Rating (Note 5) Junction Temperature (TJMAX) Soldering Information Vapor Phase (60sec.) θJA 6.0V −65°C to +150°C GND − 0.3 to VDD + 0.3V Internally Limited 2000V 200V 150°C 45.1°C/W Operating Ratings Temperature Range TMIN ≤ TA ≤ TMAX Supply Voltage (VDD) −40°C ≤ TA ≤ 85°C 2.7V ≤ VDD ≤ 5.5V 1.7V ≤ I2CVDD ≤ 5.5V Supply Voltage (I2CVDD) I2CVDD ≤ VDD 215°C Electrical Characteristics VDD = 3.3V (Notes 1, 2) The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified. LS = Loudspeaker, HP = Headphone. LM49200 Symbol Parameter Conditions Units (Limits) Typical (Note 6) Limits (Note 7) 1.2 1.7 mA (max) Stereo LS only (Mode 2) 4 5.5 mA (max) Stereo HP only (Mode 8) 4.5 6.4 mA (max) VIN = 0, No Loads IDD Quiescent Power Supply Current EP Receiver (Output Mode Bit D4 = 1) Stereo LS + Stereo HP (Mode 10) ISD Shutdown Current VOS Output Offset Voltage 7.0 9.8 mA (max) 0.02 1 µA (max) 2.5 1.4 15 5 mV (max) mV (max) LS output, Mode 2, RL = 8Ω BTL THD+N = 1%, f = 1kHz 520 450 mW (min) HP output, Mode 8, RL = 32Ω SE THD+N = 1%, f = 1kHz 38 35 mW (min) LS output, f = 1kHz, RL = 8Ω BTL PO = 250mW, Mode 2 0.05 % HP output, f = 1kHz, RL = 32Ω SE PO = 12mW, Mode 8 0.02 % LS output, f = 1kHz, VREF = VOUT (1%THD+N) Gain = 0dB, A-weighted LIN & RIN AC terminated 105 dB HP output, f = 1kHz, VREF = VOUT (1%THD+N) Gain = 0dB, A-weighted LIN & RIN AC terminated 101 dB VIN = 0V, Mode 10 LS output, RL = 8Ω BTL HP output, RL = 32Ω SE PO THD+N SNR Output Power Total Harmonic Distortion + Noise Signal-to-Noise Ratio 5 www.national.com LM49200 Infrared (15sec.) 220°C See AN-1112 “Micro SMD Wafer Level Chip Scale Package” Thermal Resistance Absolute Maximum Ratings (Notes 1, 2) LM49200 LM49200 Symbol Parameter Conditions Typical (Note 6) Limits (Note 7) Units (Limits) A-weighted, Inputs terminated to AC GND, Output Referred εOUT Output Noise Right LS only, Mode 1 8 µV LS: Mode 1 8 µV LS: Mode 2 11 µV LS: Mode 3 14 µV HP: Mode 4 8 µV HP: Mode 8 9 µV HP: Mode 12 11 µV LS: Mode 1, RL = 8Ω BTL 95 dB LS: Mode 2, RL = 8Ω BTL 75 dB HP: Mode 4, RL = 32Ω SE 90 dB HP: Mode 8, RL = 32Ω SE 80 dB HP: RL = 32Ω SE, Mode 4 60 66 dB dB LS: PO = 400mW, f = 1kHz, Mode 2 80 dB HP: PO = 12mW, f = 1kHz, Mode 8 70 dB VRIPPLE = 200mVPP, fRIPPLE = 217Hz, CB = 2.2μF All inputs AC terminated to GND, output referred PSRR Power Supply Rejection Ratio f = 217Hz, VCM = 1VP-P CMRR XTALK ZIN Common-Mode Rejection Ratio Crosstalk LS: RL = 8Ω BTL, Mode 1 Maximum Gain setting 12.5 10 15 kΩ (min) kΩ (max) Maximum Attenuation setting 110 90 130 kΩ (min) kΩ (max) Maximum Gain Maximum Attenuation 18 –80 dB dB 0.2 dB CB = 2.2μF, HP, Normal Turn-On Mode 29 ms CB = 2.2μF, HP, Fast Turn-On Mode 16 ms MIN, LIN, and RIN Input Impedance VOL Digital Volume Control Range VOL Volume Control Step Size Error TWU Wake-Up Time from Shutdown Electrical Characteristics VDD = 5.0V (Notes 1, 2) The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified. LS = Loudspeaker, HP = Headphone. LM49200 Symbol Parameter Conditions Units (Limits) Typical (Note 6) Limits (Note 7) EP Receiver (Output Mode Bit D4 = 1) 1.3 1.8 mA (max) Stereo LS only (Mode 2) 4.2 5.9 mA (max) Stereo HP only (Mode 8) 4.7 6.5 mA (max) Stereo LS + Stereo HP (Mode 10) 7.3 10.1 mA (max) 0.02 1 µA (max) 2.5 1.4 15 5 mV (max) mV (max) VIN = 0, No Loads IDD Quiescent Power Supply Current ISD Shutdown Current VOS Output Offset Voltage VIN = 0V, Mode 10 LS output, RL = 8Ω BTL HP output, RL = 32Ω SE www.national.com 6 PO THD+N SNR Parameter Output Power Total Harmonic Distortion + Noise Signal-to-Noise Ratio Conditions Typical (Note 6) Limits (Note 7) Units (Limits) LS output, Mode 2, RL = 8Ω BTL THD+N = 1%, f = 1kHz 1.25 W HP output, Mode 8, RL = 32Ω SE THD+N = 1%, f = 1kHz 38 mW LS output, f = 1kHz, RL = 8Ω BTL PO = 400mW, Mode 2 0.05 % HP output, f = 1kHz, RL = 32Ω SE PO = 12mW, Mode 8 0.02 % LS output, f = 1kHz, VREF = VOUT (1%THD+N) Gain = 0dB, A-weighted LIN & RIN AC terminated 109 dB HP output, f = 1kHz, VREF = VOUT (1%THD+N) Gain = 0dB, A-weighted LIN & RIN AC terminated 101 dB A-weighted, Inputs terminated to AC GND, Output Referred εOUT Output Noise Right LS only, Mode 1 8 µV LS: Mode 1 8 µV LS: Mode 2 11 µV LS: Mode 3 14 µV HP: Mode 4 8 µV HP: Mode 8 9 µV HP: Mode 12 11 µV VRIPPLE = 200mVP-P, fRIPPLE = 217Hz, CB = 2.2μF All inputs AC terminated to GND, output referred PSRR Power Supply Rejection Ratio LS: Mode 1, RL = 8Ω BTL 90 dB LS: Mode 2, RL = 8Ω BTL 70 dB HP: Mode 4, RL = 32Ω SE 87 dB HP: Mode 8, RL = 32Ω SE 77 dB HP: RL = 32Ω SE, Mode 4 60 66 dB dB LS: PO = 1W, f = 1kHz, Mode 2 80 dB HP: PO = 12mW, f = 1kHz, Mode 8 70 dB Maximum Gain setting 12.5 kΩ Maximum Attenuation setting 110 kΩ Maximum Gain Maximum Attenuation 18 –80 dB dB 0.2 dB CB = 2.2μF, HP, Normal Turn-On Mode 29 ms CB = 2.2μF, HP, Fast Turn-On Mode 16 ms f = 217Hz, VCM = 1VP-P CMRR Common-Mode Rejection Ratio XTALK Crosstalk ZIN MIN, LIN, and RIN Input Impedance VOL Digital Volume Control Range VOL Volume Control Step Size Error TWU Wake-Up Time from Shutdown LS: RL = 8Ω BTL, Mode 1 7 www.national.com LM49200 LM49200 Symbol LM49200 I2C Interface (Notes 1, 2) The following specifications apply for VDD = 5.0V and 3.3V, 2.2V ≤ I2C_VDD ≤ 5.5V, TA = 25°C, unless otherwise specified. LM49200 Conditions Units (Limits) Symbol Parameter t1 I2C Clock Period 2.5 µs (min) t2 I2C Data Setup Time 100 ns (min) t3 I2C 0 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) t6 I2C Data Hold Time 100 ns (min) Typical (Note 4) Data Stable Time VIH I2C VIL I2C Input Voltage Low Input Voltage High I2C Interface Limits (Notes 7, 8) 0.7xI2CV DD V (min) 0.3xI2CVDD V (max) (Notes 1, 2) The following specifications apply for VDD = 5.0V and 3.3V, 1.7V ≤ I2C_VDD ≤ 2.2V, TA = 25°C, unless otherwise specified. LM49200 Conditions Units (Limits) Symbol Parameter t1 I2C Clock Period 2.5 µs (min) t2 I2C Data Setup Time 250 ns (min) t3 I2C 0 ns (min) t4 Start Condition Time 250 ns (min) t5 Stop Condition Time 250 ns (min) t6 I2C Data Hold Time 250 ns (min) Data Stable Time VIH I2C VIL I2C Input Voltage Low Input Voltage High Typical (Note 6) Limits (Notes 7, 8) 0.7xI2CV DD V (min) 0.3xI2CVDD V (max) Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, applicable std. JESD22-A114C. Note 5: Machine model, applicable std. JESD22-A115-A. Note 6: Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis. Note 8: Refer to the I2C timing diagram, Figure 2. www.national.com 8 LM49200 Typical Performance Characteristics For all performance graphs, the Output Gains are set to 0dB, unless otherwise noted. THD+N vs Frequency VDD = 3.3V, RL = 8Ω, PO = 250mW Mode 1, 80kHz BW THD+N vs Frequency VDD = 3.3V, RL = 8Ω, PO = 250mW Mode 2, 80kHz BW 30062762 30062763 THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW/Ch Mode 4, 80kHz BW THD+N vs Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW/Ch Mode 8, 80kHz BW 30062765 30062764 THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 600mW Mode 1, 80kHz BW THD+N vs Frequency VDD = 5V, RL = 8Ω, PO = 600mW Mode 2, 80kHz BW 30062766 30062767 9 www.national.com LM49200 THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 12mW/Ch Mode 4, 80kHz BW THD+N vs Frequency VDD = 5V, RL = 32Ω, PO = 12mW/Ch Mode 8, 80kHz BW 30062769 30062768 THD+N vs Output Power VDD = 3.3V & 5V, RL = 8Ω BTL, f = 1kHz Mode 1, 80kHz BW THD+N vs Output Power VDD = 3.3V & 5V, RL = 8Ω BTL, f = 1kHz Mode 2, 80kHz BW 30062772 30062773 THD+N vs Output Power VDD = 3.3V & 5V, RL = 8Ω, f = 1kHz Mode 5, 80kHz BW THD+N vs Output Power VDD = 3.3V & 5V, RL = 32Ω, f = 1kHz Mode 4, 80kHz BW 30062770 www.national.com 30062774 10 THD+N vs Output Power VDD = 3.3V & 5V, RL = 8Ω BTL, f = 1kHz Mode 10, 80kHz BW 30062771 30062775 PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8Ω Mode 1, 80kHz BW PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8Ω Mode 2, 80kHz BW 30062754 30062755 PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 32Ω Mode 8, 80kHz BW PSRR vs Frequency VDD = 3.3V, VRIPPLE = 200mVP-P, RL =32Ω Mode 4, 80kHz BW 30062756 30062757 11 www.national.com LM49200 THD+N vs Output Power VDD = 3.3V & 5V, RL = 32Ω, f = 1kHz Mode 8, 80kHz BW LM49200 PSRR vs Frequency VDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω Mode 1, 80kHz BW PSRR vs Frequency VDD = 5V, VRIPPLE = 200mVP-P, RL = 32Ω Mode 4, 80kHz BW 30062759 30062760 PSRR vs Frequency VDD = 5V, VRIPPLE = 200mVP-P, RL = 32Ω Mode 8, 80kHz BW Power Dissipation vs Output Power VDD = 3.3V & 5V, RL = 8Ω BTL Mode 3, 80kHz BW 30062761 30062788 Power Dissipation vs Output Power VDD = 3.3V & 5V, RL = 32Ω SE Mode 12, 80kHz BW Crosstalk vs Frequency VDD = 5.0V, VIN = 1VP-P, RL = 8Ω Mode 2, 80kHz BW 30062789 www.national.com 30062784 12 LM49200 Crosstalk vs Frequency VDD = 5.0V, VIN = 1VP-P, RL = 32Ω Mode 8, 80kHz BW Supply Current vs Supply Voltage No Load, Mode 3 (2 plots, output gain amps on/off) 30062790 30062785 Supply Current vs Supply Voltage No Load, Mode 12 (2 plots, output gain amps on/off) Output Power vs Supply Voltage f = 1kHz, RL = 8Ω BTL Mode 2, 80kHz BW 30062791 30062786 Output Power vs Supply Voltage f = 1kHz, RL = 32Ω SE Mode 8, 80kHz BW 30062787 13 www.national.com LM49200 Application Information I2C BUS FORMAT The I2C bus format is shown in Figure 4. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the slave device. Set R/W = 0; the LM49200 is a WRITE-ONLY device and will not respond to the R/W = 1. The data is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM49200 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. After the 8-bit register data word is sent, the LM49200 sends another ACK bit. Following the acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is high. I2C COMPATIBLE INTERFACE The LM49200 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49200 and the master can communicate at clock rates up to 400kHz. Figure 2 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM49200 is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 3). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 4). The LM49200 device address is 11111000. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM49200's I2C interface is powered up through the I2CVDD pin. The LM49200's I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system 300627s0 FIGURE 2. I2C Timing Diagram 30062782 FIGURE 3. Start and Stop Diagram www.national.com 14 LM49200 30062783 FIGURE 4. Start and Stop Diagram TABLE 1. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 0 0 0 Chip Address TABLE 2. Control Registers Register D7 D6 D5 D4 D3 D2 D1 D0 I2CVDD_SD(2) Turn_On _Time (3) Power_On (4) Shutdown Control 0 0 0 HPR_SD (1) Output Mode Control 0 1 0 EP_Mode(5) Headphone Output Gain Control 1 0 0 0 Mono Input Volume Control 1 0 1 Mono_Vol (8) Left Input Volume Control 1 1 0 Left_Vol (8) Right Input Volume Control 1 1 1 Right_Vol (8) 0 Mode_Control (6) HP_Gain (7) 0 5. EP_Mode: EP (Receiver) Mode control. Right loudspeaker channel can be used as earpiece path. See Table 4. 6. Mode_Control: Sets the output mode. See Tables 4. 7. HP_Gain: Sets the headphone amplifier output gain. See Table 5 8. Mono_Vol/Left_Vol/Right_Vol: Sets the input volume for Mono, Left and Right inputs. See Table 6. Notes: All registers default to 0 on initial power-up. 1. HPR_SD: Right channel shutdown control. See Table 3. 2. I2CVDD_SD: Control Enable Function. I2CVDD can be used to act as a hardware reset input. See Table 3. 3. Turn_On_Time: Reduces the turn on time for faster activation. See Table 3. 4. Power_On: Master Power on bit. See Table 3. 15 www.national.com LM49200 TABLE 3. Shutdown Control Register Bit Name Value Description This bit is a master shutdown control bit and sets the device to be on or off. 0 Value Power_On Status 0 Master power off, device disable. 1 Master power on, device enable. This bit sets the turn on time of the device. 1 Value Turn_On_Time Status 0 Normal Turn-on time 1 Fast Turn-on time This bit allows the I2C supply voltage to be used as a reset signal. Value I2CVDD_SD 2 Status I2CV 0 acts as an active low reset input. If I2CVDD drops below 1.1V, the device resets and the I2C registers are restored to their default state. 1 Normal Operation. I2CVDD voltage does not reset the device. DD This bit is used when only one channel of the headphone amplifier is needed. 4 HPR_SD 0 Normal headphone operation. 1 Mono headphone output at left channel, right headphone in shutdown. TABLE 4. Output Mode Control Register (see key below table) Bits 3:0 Field Description Mode_Control These bits determine how the input signals are mixed and routed to the outputs. Value 4 EP Mode Mode Left Loudspeaker Right Loudspeaker Right Headphone 0000 0 SD SD SD SD 0001 1 GM x M GM x M Mute Mute 0010 2 GL x L GL x L Mute Mute GL x L + GM x M GR x R + GM x M 011 3 Mute Mute 0100 4 SD SD GM x M/2 GM x M/2 0101 5 GM x M GM x M GM x M/2 GM x M/2 0110 6 GL x L GR x R GM x M/2 GM x M/2 0111 7 GM x M/2 GM x M/2 1000 8 SD SD GL x L GR x R 1001 9 GM x M GM x M GL x L GR x R 1010 10 GL x L GR x R GL x L GR x R 1011 11 GL x L GR x R 1100 12 SD SD GL x L + GM x M/2 GR x R + GM x M/2 1101 13 GM x M GM x M GL x L + GM x M/2 GR x R + GM x M/2 1110 14 GL x L GR x R GL x L + GM x M/2 GR x R + GM x M/2 1111 15 GL x L + GM x M/2 GR x R + GM x M/2 GL x L + GM x M GL x L + GM x M GL x L + GM x M GR x R + GM x M GL x L + GM x M GR x R + GM x M This bit sets the loudspeaker amplifiers for earpiece mode. Value Status 0 Normal loudspeaker operation, control determined by bits 3:0. 1 Bit overrides bits 3:0. Right loudspeaker amplifier bias current reduced for low power operation. Left loudspeaker amplifier shutdown. Mono input path active and signal routed to right loudspeaker output. Left & right input gain amplifiers shutdown for reduced power consumption. M : MIN, Mono differential input www.national.com Left Headphone 16 LM49200 L : LIN, Left single-ended input R : RIN, Right single-ended input SD : Shutdown GM : Mono_Vol setting determined by the Mono Input Volume Control register, See Table 6. GL : Left_Vol setting determined by the Left Input Volume Control register, See Table 6. GR : Right_Vol setting determined by the Right Input Volume Control register, See Table 6. TABLE 5. Output Gain Control Register Bits Field 2:0 HP_GAIN Description These bits set the gain of the headphone output amplifiers. Value Gain (dB) 000 0 001 –1.2 010 –2.5 011 –4.0 100 –6.0 101 –8.5 110 –12 111 –18 17 www.national.com LM49200 TABLE 6. Input Volume Control Registers Bits Fields 4:0 Mono_Vol Right_Vol Left_Vol www.national.com Description These bits set the input volume for each input volume register listed. Volume Step Value Gain (dB) 1 00000 –80.0 2 00001 –46.5 3 00010 –40.5 4 00011 –34.5 5 00100 –30.0 6 00101 –27.0 7 00110 –24.0 8 00111 –21.0 9 01000 –18.0 10 01001 –15.0 11 01010 –13.5 12 01011 –12.0 13 01100 –10.5 14 01101 –9.0 15 01110 –7.5 16 01111 –6.0 17 10000 –4.5 18 10001 –3.0 19 10010 –1.5 20 10011 0.0 21 10100 1.5 22 10101 3.0 23 10110 4.5 24 10111 6.0 25 11000 7.5 26 11001 9.0 27 11010 10.5 28 11011 12.0 29 11100 13.5 30 11101 15.0 31 11110 16.5 32 11111 18.0 18 POWER_ON BIT The Power_On bit is the master control bit to activate or deactivate the LM49200. All registers can be loaded independent of the Power_On bit setting as long as the IC is powered correctly. Cycling the Power_On bit does not change the values of any registers nor return all bits to the default power on value of zero. The Power_On bit only determines whether the IC is on or off. DIFFERENTIAL AMPLIFIER EXPLANATION The LM49200 features a differential input stage, which offers improved noise rejection compared to a single-ended input amplifier. Because a differential input amplifier amplifies the difference between the two input signals, any component common to both signals is cancelled. An additional benefit of the differential input structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to both inputs, and thus cancelled by the amplifier, the LM49200 can be used without input coupling capacitors when configured with a differential input signal. HPR_SD BIT The HPR_SD bit will deactivate the right headphone output amplifier. This bit is provided to reduce power consumption when only one headphone output is needed. BRIDGE CONFIGURATION EXPLAINED By driving the load differentially through the MONO outputs, an amplifier configuration commonly referred to as “bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier configuration where one side of the load is connected to ground. A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. A bridge configuration, such as the one used in LM49200, also creates a second advantage over single-ended amplifiers. Since the differential outputs are biased at half-supply, no net DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, single-ended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both increased internal IC power dissipation and also possible loudspeaker damage. MODE_CONTROL BITS In the LM49200 OUTPUT MODE CONTROL register (Table 4), Bit B5 (EP Bypass) controls the operation of the Earpiece Bypass path. If EP Bypass = 0, it would act under normal output mode operation set by bits B3, B2, B1, and B0. If EP Bypass = 1, it overrides the B3, B2, B1, and B0 Bits and enables the Receiver Bypass path, a class AB amplifier, to the speaker output. Bit B4 (HPR_SD) of the OUPUT MODE CONTROL register controls the right headphone shutdown. If HPR_SD = 1, the right headphone output is disabled. The LM49200 includes a comprehensive mixer multiplexer controlled through the I2C interface. The mixer/multiplexer allows any input combination to appear on any output of LM49200. Multiple input paths can be selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the selected channel. Table 5 shows how the input signals are mixed together for each possible input selection. HP_GAIN BITS The headphone outputs have an additional, single volume control set by the three HP_Gain bits in the Output Gain Control register. The HP_Gain volume setting controls the output level for both the left and the right headphone outputs. POWER DISSIPATION Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or singleended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. The power dissipation of the LM49200 varies with the mode selected. The maximum power dissipation occurs in modes where all inputs and outputs are active (Modes 6, 7, 8, 9, 10, 11, 13, 14, 15). The power dissipation is dominated by the Class AB amplifier. The maximum power dissipation for a given application can be derived from the power dissipation graphs or from Equation 1. LS (EP_MODE) BIT The LS (EP_Mode) bit selects the amount of bias current in the loudspeaker amplifier. Setting the LS (EP_Mode) bit to a '1' will reduce the amount of current from the VDDLS supply by approximately 0.5mA. The THD performance of the loudspeaker amplifier will be reduced as a result of lower bias current. See the performance graphs in the Typical Performance Characteristics section above. VOLUME CONTROL BITS The LM49200 has three independent 32-step volume controls, one for each of the inputs. The five bits of the Volume Control registers sets the volume for the specified input channel. PDMAX = 4*(VDD)2 / (2π2RL) (1) It is critical that the maximum junction temperature (TJMAX) of 150°C is not exceeded. TJMAX can be determined from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the thermal resistance SHUTDOWN FUNCTION The LM49200 features the following shutdown controls. 19 www.national.com LM49200 Bit B4 (GAMP_SD) of the SHUTDOWN CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized. Bit B0 (PWR_On) of the SHUTDOWN CONTROL register is the global shutdown control for the entire device. Set PWR_On = 0 for normal operation. PWR_On = 1 overrides any other shutdown control bit. TURN_ON_TIME BIT The Turn_On_Time bit determines the delay time from the Power_On bit set to '1' and the internal circuits ready. For input capacitor values up to 0.47μF the Turn_On_Time bit can be set to fast mode by setting the bit to a '1'. When the input capacitor values are larger than 0.47μF then the Turn_On_Time bit should be set to '0' for normal turn-on time and higher delay. This allows sufficient time to charge the input capacitors to the ½ VDDLS bias voltage. LM49200 of the application can be reduced from the free air value, resulting in higher PDMAX. Additional copper foil can be added to any of the leads connected to the LM49200. It is especially effective when connected to VDD, GND, and the output pins. Refer to the application information on the LM49200 reference design board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power. Refer to the Typical Performance Characteristics curves for power dissipation information for different output powers and output loading. headphone amplifiers when compared to a traditional headphone amplifier operating from the same supply voltage. INPUT CAPACITOR SELECTION Input capacitors may be required for some applications, or when the audio source is single-ended. Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM49200. The input capacitors create a highpass filter with the input resistors RIN. The -3dB point of the high-pass filter is found using equation below. f = 1 / 2πRINCIN POWER SUPPLY BYPASSING As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. Typical applications employ a 5V regulator with 10µF tantalum or electrolytic capacitor and a ceramic bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of the LM49200. The selection of a bypass capacitor, especially CB, is dependent upon PSRR requirements, click and pop performance, system cost, and size constraints. (2) Where the value of RIN is given in the Electrical Characteristics Table. High-pass filtering the audio signal helps protect the speakers. When the LM49200 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. GROUND REFERENCED HEADPHONE AMPLIFIER The LM49200 features a low noise inverting charge pump that generates an internal negative supply voltage. This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220μF) are not necessary. The coupling capacitors are replaced by two small ceramic charge pump capacitors, saving board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone amplifiers, the headphone impedance and the output capacitor from a high-pass filter that not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass response. Because the LM49200 does not require the output coupling capacitors, the low frequency response of the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the available dynamic range of the LM49200 www.national.com (Hz) CHARGE PUMP FLYING CAPACITOR (C1) The flying capacitor (C1), see Figure 1, affects the load regulation and output impedance of the charge pump. A C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2μF, the RDS(ON) of the charge pump switches and the ESR of C1 and Cs5 dominate the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. CHARGE PUMP HOLD CAPACITOR (CS3) The value and ESR of the hold capacitor (Cs5) directly affects the ripple on CPVSS. Increasing the value of Cs5 reduces output ripple. Decreasing the ESR of Cs5 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. 20 LM49200 Demo Board Circuit 30062753 FIGURE 5. Demo Board Circuit to 5V. Jumper headers J13 and J12 must be set accordingly. If a single power supply for I2CVDD and VDD is desired then header J5 should be used with a jumper added to header J11 to connect I2CVDD to the external supply voltage connected to J5. Connection headers J1 and J2 are provided along with the stereo headphone jack J4 for easily connection and monitoring of the headphone outputs. Demonstration Board The demonstration board (see Figure 5) has connection and jumper options to be powered from the USB bus, from external power supplies or a combination of both. Additional options are to power I2CVDD and VDD from a single power supply or separate power supplies, as long as the voltage limits for each power supply are not exceeded. See the Operating Ratings for each supply's limit range. When powered from the USB bus the I2CVDD will be set to 3.3V and the VDD will be set 21 www.national.com LM49200 LM49200 microSMD Demo Board Views 30062780 30062777 Silk Screen Composite View 30062781 30062778 Top Layer Internal Layer 1 30062779 30062776 Internal Layer 2 www.national.com Bottom Layer 22 LM49200 LM49200 Reference Demo Board Bill Of Materials TABLE 7. Bill Of Materials Designator Vlaue Tolerance Part Description R1, R2 5.1kΩ 5% 1/10W, 0603 Resistors CIN1, CIN2 CIN3, CIN4 1μF 10% 1206, X7R Ceramic Capacitor CS1, CB 2.2μF 10% Size A, Tantalum Capacitor CS2 0.1μF 10% 0805, 16V, X7R Ceramic Capacitor CS3, C1 2.2μF 10% 0603, 10V, X7R Ceramic Capacitor Comment U2 LM49200TL J1, J2, J3 J4, J5, J8 J9, J10 0.100" 1x2 header, vertical mount Input, Output, VDD, GND J11, J12, J13 0.100" 1x3 header, vertical mount VDD Selects, VDD, I2CVDD, GND J6 16 pin header I2C Connector U1 Headphone Jack log and digital sections. It is further recommended to put digital and analog power traces over the corresponding digital and analog ground traces to minimize noise coupling. PCB Layout Guidelines This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual results will depend heavily on the final layout. PLACEMENT OF DIGITAL AND ANALOG COMPONENTS All digital components and high-speed digital signals traces should be located as far away as possible from analog components and circuit traces. General Mixed Signal Layout Recommendations AVOIDING TYPICAL DESIGN AND LAYOUT PROBLEMS Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90 degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise coupling and cross talk. SINGLE-POINT POWER AND GROUND CONNECTIONS The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can be helpful in minimizing high frequency noise coupling between the ana- 23 www.national.com LM49200 Revision History Rev Date 1.0 05/21/09 www.national.com Description Initial release. 24 LM49200 Physical Dimensions inches (millimeters) unless otherwise noted 20 Bump micro SMD Package NS Package Number TLA20BBA X1 = 2.022±0.030mm X2 = 2.517±0.030mm, X3 = 0.600±0.075mm 25 www.national.com LM49200 Stereo Class AB Audio Subsystem with a True Ground Headphone Amplifier Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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