ETC DP83265

February 1991
DP83265 BSI TM Device
(FDDI System Interface)
General Description
Features
The DP83265 BSI device implements an interface between
the National FDDI BMACTM device and a host system. It
provides a multi-frame, MAC-level interface to one or more
MAC Users.
The BSI device accepts MAC User requests to receive and
transmit multiple frames (Service Data Units). On reception
(Indicate), it receives the byte stream from the BMAC device, packs it into 32-bit words and writes it to memory. On
transmission (Request), it unpacks the 32-bit wide memory
data and sends it a byte at a time to the BMAC device. The
host software and the BSI device communicate via registers, descriptors, and an attention/notify scheme using clustered interrupts.
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32-bit wide Address/Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit
words
Interfaces to low-cost DRAMs or directly to system bus
2 Output and 3 Input Channels
Supports Header/Info splitting
Bridging support
Efficient data structures
Programmable Big or Little Endian alignment
Full Duplex data path allows transmission to self
Confirmation status batching services
Receive frame filtering services
Operates from 12.5 MHz to 25 MHz synchronously with
host system
TL/F/10791 – 1
FIGURE 1. FDDI Chip Set Block Diagram
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
BSITM , BMACTM , CDDTM , CRDTM and PLAYERTM are trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/10791
RRD-B30M105/Printed in U. S. A.
DP83265 BSI Device (FDDI System Interface)
PRELIMINARY
Table of Contents
5.0 CONTROL INFORMATION
1.0 FDDI CHIP SET OVERVIEW
5.1 Overview
2.0 ARCHITECTURE DESCRIPTION
5.2 Operation Registers
2.1 Interfaces
5.3 Control and Event Register Descriptions
2.2 Data Structures
5.4 Pointer RAM Registers
2.3 Map Engine
5.5 Limit RAM Registers
5.6 Descriptors
3.0 FEATURE OVERVIEW
3.1 32-Bit address/Data Path to Host Memory
5.7 Operating Rules
3.2 Multi-Channel Architecture
5.8 Pointer RAM Register Descriptions
3.3 Support for Header/Info Splitting
5.9 Limit RAM Register Descriptions
3.4 MAC Bridging Support
5.10 BSI Device Descriptors
3.5 Confirmation Status Batching Services
6.0 SIGNAL DESCRIPTIONS
3.6 Receive Frame Filtering Services
6.1 Pin Organization
3.7 Two Timing Domains
6.2 Control Interface
3.8 Clustered Interrupts
6.3 BMAC Device Indicate Interface
6.4 BMAC Device Request Interface
4.0 FUNCTIONAL DESCRIPTION
4.1 Overview
6.5 ABus Interface
4.2 Operation
6.6 Electrical Interface
4.3 Bus Interface Unit
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1.0 FDDI Chip Set Overview
National Semiconductor’s FDDI chip set consists of five
components as shown in Figure 1-1. For more information
about the other devices in the chip set, consult the appropriate data sheets and application notes.
DP83261 BMAC TM Device
Media Access Controller
The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FDDI X3T9.5
MAC Standard.
DP83231 CRD TM Device
Clock Recovery Device
Features
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream.
# All of the standard defined ring service options
# Full duplex operation with through parity
# Supports all FDDI Ring Scheduling Classes (Synchro-
Features
nous, Asynchronous, etc.)
# PHY Layer loopback test
# Crystal controlled
# Clock locks in less than 85 ms
# Supports Individual, Group, Short, Long and External
Addressing
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DP83241 CDD TM Device
Clock Distribution Device
From a 12.5 MHz reference, the Clock Distributon Device
synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clock required by the BSI, BMAC, and PLAYER devices.
Generates Beacon, Claim, and Void frames internally
Extensive ring and station statistics gathering
Extensions for MAC level bridging
Separate management port that is used to configure and
control operation
# Multi-frame streaming interface
DP83251/55 PLAYER TM Device
Physical Layer Controller
DP83265 BSI TM Device
System Interface
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9.5 Standard.
The BSI Device implements an interface between the
BMAC device and a host system.
Features
Features
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4B/5B encoders and decoders
Framing logic
Elasticity Buffer, Repeat Filter and Smoother
Line state detector/generator
Link error detector
Configuration switch
Full duplex operation
Separate management port that is used to configure and
control operation
In addition, the DP83255 contains an additional
PHYÐData.request and PHYÐData.indicate port required
for concentrators and dual attach stations.
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32-bit wide Address/Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit words
Interfaces to low-cost DRAMs or directly to system bus
Provides 2 Output and 3 Input Channels
Supports Header/Info splitting
Efficient data structures
Programmable Big or Little Endian alignment
Full duplex data path allows transmission to self
Confirmation status batching services
Receive frame filtering services
Operates from 12.5 MHz to 25 MHz synchronously with
host system
2.0 Architecture Description
The BSI device is composed of three interfaces and the
Map Engine.
The three interfaces are the BMAC device, the ABus, and
the Control Bus. They are used to connect the BSI device to
the BMAC device, Host System, and external Control Bus.
The Map Engine manages the operation of the BSI device.
The Control Bus Interface is separate from the BMAC device and ABus Interfaces to allow independent operation of
the Control Bus.
2.1 INTERFACES
The BSI device connects to external components via three
interfaces: the BMAC device Interface, the ABus Interface,
and the Control Bus Interface (see Figure 2-1).
2.2.1 Data Types
The architecture of the BSI device defines two basic kinds
of objects: Data Units and Descriptors. A Data Unit is a
group of contiguous bytes which forms all or part of a frame
(Service Data Unit). A Descriptor is a two-word (64-bit) control object that provides addressing information and control/
status information about BSI device operations.
Data and Descriptor objects may consist of one or more
parts, where each part is contiguous and wholly contained
within a 1k or 4k memory page. A single-part object consists
of one Only Part; a multiple-part object consists of one First
Part, zero or more Middle Parts, and one Last Part. In Descriptor names, the object part is denoted in a suffix, preceded by a dot. Thus an Input Data Unit Descriptor (IDUD),
which describes the last Data Unit of a frame received from
the ring, is called an IDUD.Last.
A single-part Data Unit is stored in contiguous locations
within a single 4k byte page in memory. Multiple-part Data
Units are stored in separate, and not necessarily contiguous
4k byte pages. Descriptors are stored in contiguous locations in Queues and Lists, where each Queue or List occupies a single 1k byte or 4k byte memory page, aligned on
the queue-size boundary. For both Queues and Lists, an
access to the next location after the end of a page will automatically wrap-around and access the first location in the
page.
The host uses the Control Bus to access the BSI device’s
internal registers, and to manage the attention/notify logic.
2.2 DATA STRUCTURES
2.1.1 BMAC Device Interface
The BSI device connects to the BMAC device via the
MAÐIndicate (receive) and MAÐRequest (transmit) Interfaces, as shown in Figure 2-1 .
Received Data is transferred from the BMAC device to
the BSI device via the MAÐIndicate Interface. The
MAÐIndicate Interface consists of a parity bit (odd parity)
and byte-wide data along with flag and control signals.
Transmit Data is transferred from the BSI device to
the BMAC device via the MAÐRequest Interface. The
MAÐRequest Interface consists of a parity bit (odd parity)
and byte-wide data along with flag and control signals.
2.1.2 ABus Interface
The BSI device connects to the Host System via the ABus
Interface. The ABus Interface consists of four bits of parity
(odd parity) and 32 bits of multiplexed address and data
along with transfer control and bus arbitration signals.
2.1.3 Control Bus Interface
The Control Bus Interface connects the BSI device to the
external Control Bus.
TL/F/10791 – 2
FIGURE 2-1. BSI Device Interfaces
4
2.0 Architecture Description (Continued)
Every Output Data Unit part is described by an Output Data
Unit Descriptor (ODUD). Output Data Unit Descriptors are
fetched from memory so that frame parts can be assembled
for transmission.
Every Input Data Unit part is described by an Input Data Unit
Descriptor (IDUD). Input Data Unit Descriptors are generated on Indicate Channels to describe where the BSI device
wrote each frame part and to report status for the frame.
Request Descriptors (REQs) are written by the user to specify the operational parameters for BSI device Request operations. Request Descriptors also contain the start address
of part of a stream of ODUDs and the number of frames
represented by the ODUD stream part (i.e., the number of
ODUD.Last descriptors). Typically, the user will define a single Request Object consisting of multiple frames of the
same request and service class, frame control, and expected status.
Confirmation Messages (CNFs) are created by the BSI device to record the result of a Request operation.
Pool Space Descriptors (PSPs) describe the location and
size of a region of memory space available for writing Input
Data Units.
Request (transmit) and Indicate (receive) data structures
are summarized in Figures 2-2 and 2-3 .
Data Units (MAC Service Data Units) are transferred between the BSI device and BMAC device via five simplex
Channels, three used for Indicate (receive) data and two for
Request (transmit) data. Parts of frames received from the
ring and copied to memory are called Input Data Units
(IDUs); parts of frames read from memory to be tansmitted
to the ring are called Output Data Units (ODUs).
Descriptors are transferred between the BSI device and
Host via the ABus, whose operation is for the most part
transparent to the user. There are five Descriptor types recognized by the BSI device: Input Data Unit Descriptors
(IDUDs), Output Data Unit Descriptors (ODUDs), Pool
Space Descriptors (PSPs), Request Descriptors (REQs),
and Confirmation Message Descriptors (CNFs).
Input and Output Data Unit Descriptors describe a single
Data Unit part, i.e., its address (page number and offset),
its size in bytes, and its part (Only, First, Middle, or
Last). Frames consisting of a single part are described by
a Descriptor.Only; frames consisting of multiple parts
are described by a Descriptor.First, zero or more Descriptor.Middles, and a Descriptor.Last.
TL/F/10791 – 3
FIGURE 2-2. BSI Device Request Data Structures
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2.0 Architecture Description (Continued)
TL/F/10791 – 4
FIGURE 2-3. BSI Device Indicate Data Structures
2.3 MAP ENGINE
The Map Engine, which manages the operation of the BSI,
is comprised of seven basic blocks: Indicate Machine, Request Machine, Status/Space State Machine, Operation
RAM, Pointer RAM, Limit RAM, and Bus Interface Unit. An
internal block diagram of the BSI device is shown in Figure
2-4 .
2.2.2 Descriptor Queues and Lists
The BSI device utilizes 10 Queues and two Lists. These
queues and lists are circular. There are six Queues for Indicate operations, and four Queues and two Lists for Request
operations. Each of the three Indicate Channels has a Data
Queue containing Pool Space Descriptors (PSPs), and a
Status Queue containing Input Data Unit Descriptors
(IDUDs). Each Request Channel has a Data Queue containing Request Descriptors (REQs), a Status Queue containing
Confirmation Messages (CNFs), and a List containing Output Data Unit Descriptors (ODUDs).
During Indicate and Request operations, Descriptor Queues
and Lists are read and written by the BSI device, using registers in the Pointer and Limit RAM Register files. The Pointer RAM Queue and List Pointer Registers point to a location
from which a Descriptor will be read (PSPs, REQs, and
ODUDs) or written (IDUDs and CNFs).
For each Queue Pointer Register there is a corresponding
Queue Limit Register in the Limit RAM Register file, which
holds the Queue’s limit as an offset value in units of 1 Descriptor (8 bytes). The address in the Queue Pointer is incremented before a Descriptor is read and after a Descriptor is
written, then compared with the value in the corresponding
Queue Limit Register. When a Descriptor is accessed from
the location defined by the Queue Limit Register, an attention is generated, informing the host that the Queue is empty. When a pointer value is incremented past the end of the
page, it wraps to the beginning of the page.
2.3.1 Indicate Machine
The Indicate Block accepts Service Data Units (frames)
from the BMAC device in the byte stream format (MAÐIndicate).
Upon receiving the data, the Indicate Block performs the
following functions:
# Decodes the Frame Control field to determine the frame
type
# Sorts the received frames onto Channels according to
the Sort Mode
# Filters identical MAC frames
# Copies the received frames to memory according to
Copy Criteria
# Writes status for the received frames to the Indicate
Status Queue
# Issues interrupts to the host at host-defined status breakpoints
2.3.2 Request Machine
The Request Machine presents Service Data Units (MAC
frames) to the BMAC device in the byte stream format
(MAÐRequest).
The Request Machine performs the following functions:
2.2.3 Storage Allocation
The maximum unit of contiguous storage allocation in external memory is a Page. All BSI device addresses consist of a
16-bit page number and a 12-bit offset.
The BSI device uses a page size of 1K or 4k bytes for storage of Descriptor Queues and Lists (as selected by the
user), and a page size of 4K bytes for storage of Data Units.
A single page may contain multiple Data Units, and multiplepart Data Units may span multiple disjoint or contiguous
pages.
# Reads frames from host memory and assembles them
onto Request Channels
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Prioritizes active requests
Transmits frames to the BMAC device
Writes status for transmitted and returning frames
Issues interrupts to the host on user-defined group
boundaries
2.0 Architecture Description (Continued)
TL/F/10791 – 5
FIGURE 2-4. BSI Device Internal Block Diagram
3. Confirmation Message Descriptor stream
4. Request Descriptor stream
The BIU arbitrates between the Subchannels and issues a
Bus Request when any Subchannel requests service. The
priority of Subchannel bus requests is generally as follows,
from highest priority to lowest priority:
1. Output Data Unit reads (highest priority)
2. Input Data Unit writes
3. Input Data Unit Descriptor writes
4. Confirmation Message Descriptor writes
5. Pool Space Descriptor reads
6. Mailbox reads/writes
7. Pointer RAM and Limit RAM Service functions (lowest
priority)
Addresses for Subchannel accesses are contained in the
Pointer RAM Registers.
2.3.3 Status/Space Machine
The Status/Space Machine is used by both the Indicate Machine and the Request Machine.
The Status/Space Machine manages all descriptor Queues
and writes status for received and transmitted frames.
2.3.4 Bus Interface Unit
The Bus Interface Unit (BIU) is used by both the Indicate
and Request Blocks. It manages the ABus Interface, providing the BSI device with a 32-bit data path to local or system
memory.
The Bus Interface Unit controls the transfer of Data Units
and Descriptors between the BSI device and Host memory
via the ABus.
Data and Descriptors are transferred between the BSI device and Host memory in streams, where a stream is a flow
of logically related information (i.e., a single type of data or
descriptor object) in one direction (either to or from host
memory). Each Channel supports a subset of object
streams, via Subchannels. The three Indicate Channels
each support three Subchannels:
1. Input Data Unit stream
2. Input Data Unit Descriptor stream
3. Pool Space Descriptor stream
The two Request Channels each support four Subchannels:
1. Output Data Unit stream
2. Output Data Unit Descriptor stream
2.3.5 Pointer RAM
The Pointer RAM Block is used by both the Indicate and
Request Machines. It contains pointers to all Data Units and
Descriptors manipulated by the BSI device, namely, Input
and Output Data Units, Input and Output Data Unit Descriptors, Request Descriptors, Confirmation Messages, and
Pool Space Descriptors.
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3.2 MULTI-CHANNEL ARCHITECTURE
2.0 Architecture Description
The BSI device provides three Input Channels and two Output Channels, which are designed to operate independently
and concurrently. They are separately configured by the
user to manage the reception or transmission of a particular
kind of frame (for example, synchronous frames only).
(Continued)
The Pointer RAM Block is accessed by clearing the PTOP
(Pointer RAM Operation) bit in the Service Attention Register, which causes the transfer of data between the Pointer
RAM Register and a mailbox location in memory.
3.3 SUPPORT FOR HEADER/INFO SPLITTING
In order to support high performance protocol processing,
the BSI device can be programmed to split the header and
information portions of (non-MAC/SMT) frames between
two Indicate Channels. Frame bytes from the Frame Control
field (FC) up to the user-defined header length are copied
onto Indicate Channel 1, and the remaining bytes (info) are
copied onto Indicate Channel 2.
2.3.6 Limit RAM
The Limit RAM Block is used by both the Indicate and Request Machines. It contains data values that define the limits of the ten Queues maintained by the BSI device.
Limit RAM Registers are accessed by clearing the LMOP
(Limit RAM Operation) bit in the Service Attention Register,
which causes the transfer of data between the Limit RAM
Register and the Limit Data and Limit Address Registers.
3.4 MAC BRIDGING SUPPORT
Support for bridging and monitoring applications is provided
by the Internal/External Sorting Mode. All frames matching
the external address (frames requiring bridging) are sorted
onto Indicate Channel 2, MAC and SMT frames matching
the internal (BMAC device) address are sorted onto Indicate
Channel 0, and all other frames matching the BMAC device’s internal address (short or long) are sorted onto Indicate Channel 1.
3.0 Feature Overview
The BSI device implements a system interface for the FDDI
BMAC Device. It is designed to provide a high-performance,
low-cost interface for a variety of hosts.
On the system side, the BSI device provides a simple yet
powerful bus interface and memory management scheme to
maximize system efficiency. It is capable of interfacing to a
variety of host busses/environments. The BSI device provides a 32-bit wide multiplexed address/data interface,
which can be configured to share a system bus to main
memory or communicate via external shared memory. The
system interface supports virtual addressing using fixed-size
pages.
On the network side, the BSI device performs many functions which greatly simplify the interface to the BMAC device, and provides many services which simplify network
management and increase system performance and reliability. The BSI device is capable of batching confirmation and
indication status, filtering out MAC frames with the same
information field, and performing network monitoring functions.
3.5 CONFIRMATION STATUS BATCHING SERVICES
The BSI device provides confirmation status for transmitted
and returning frames. Interrupts to the host are generated
only at status breakpoints, which are defined by the user on
a per Channel basis when the Channel is configured for
operation.
The BSI device further reduces host processing time by
separating received frame status from the received data.
This allows the CPU to quickly scan for errors when deciding whether to copy the data to memory. If the status were
embedded in the data stream, all the data would need to be
read contiguously to find the Status Indicator.
3.6 RECEIVE FRAME FILTERING SERVICES
To increase performance and reliability, the BSI device can
be programmed to filter out identical (same FC and Info
field) MAC or SMT frames received from the ring. Filtering
unnecessary frames reduces the fill rate of the Indicate
FIFO, reduces CPU frame processing time, and avoids unnecessary memory bus transactions.
3.1 32-BIT ADDRESS/DATA PATH TO HOST MEMORY
The BSI device provides a 32-bit wide synchronous multiplexed address/data interface, which permits interfacing to
a standard multi-master system bus operating from
12.5 MHz to 25 MHz, or to local memory, using Big or Little
Endian byte ordering. The memory may be static or dynamic. For maximum performance, the BSI device utilizes burst
mode transfers, with four or eight 32-bit words to a burst. To
assist the user with the burst transfer capability, the three
bits of the address which cycle during a burst are output
demultiplexed. Maximum burst speed is one 32-bit word per
clock, but slower speeds may be accommodated by inserting wait states.
The BSI device can operate within any combination of cached/non-cached, paged or non-paged memory environments. To provide this capability, all data structures are contained within a page, and bus transactions never cross a
page. The BSI device performs all bus transactions within
aligned blocks to ease the interface to a cached environment.
3.7 TWO TIMING DOMAINS
To provide maximum performance and system flexibility, the
BSI device utilizes two independent clocks, one for the MAC
(ring) Interface, and one for the system/memory bus. The
BSI device provides a fully synchronized interface between
these two timing domains.
3.8 CLUSTERED INTERRUPTS
The BSI device can be operated in a polled or interrupt-driven environment. The BSI device provides the ability to generate attentions (interrupts) at group boundaries. Some
boundaries are pre-defined in hardware; others are defined
by the user when the Channel is configured. This interrupt
scheme significantly reduces the number of interrupts to the
host, thus reducing host processing overhead.
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4.0 Functional Description (Continued)
whether they are synchronous or asynchronous, high-priority asynchronous or low-priority asynchronous, whether their
address matches an internal (BMAC device) or external address, or the header and Information fields of all non-MAC/
SMT frames.
The Synchronous/Asynchronous Sort Mode is intended for
use in end-stations or applications using synchronous transmission.
With High-priority/Low-priority sorting, high-priority asynchronous frames are sorted onto Indicate Channel 1 and
low-priority asynchronous frames are sorted onto Indicate
Channel 2. The most-significant bit of the three-bit priority
field within the FC field determines the priority. This Mode is
intended for end stations using two priority levels of asynchronous transmission.
With External/Internal sorting, frames matching the internal
address (in the BMAC device) are sorted onto Indicate
Channel 1 and frames matching an external address (when
the EA input is asserted) are sorted onto Indicate Channel
2. This mode is intended for bridges or ring monitors, which
would utilize the ECIP/EA/EM pins with external address
matching circuitry.
The proper use of the ECIP, EA, and EM pins is as follows.
External address matching circuitry must assert ECIP somewhere from the assertion of FCRCVD (from the BMAC device) up to the clock cycle before the assertion of
INFORCVD (from the BMAC device). Otherwise, the BSI device assumes that no external address comparison is taking
place. ECIP must be negated for at least one cycle to complete the external comparison. If it has not been deasserted
before EDRCVD (from the BMAC device) the frame is not
copied. EA and EM are sampled on the clock cycle after
ECIP is negated. ECIP is ignored after it is negated until
FCRCVD is asserted again.
Note that this design allows ECIP to be a positive or negative pulse. To confirm frames in this mode, (typically with
Source Address Transparency enabled), EM must be asserted within the same timeframe as EA.
With the Header/Info Sort Mode, Indicate Channels 1 and 2
receive all non-MAC/SMT frames that are to be copied, but
between them split the frame header (whose length is userdefined) and the remaining portions of the frame (Info). Indicate Channel 1 copies the initial bytes up until the host-defined header length is reached. The remainder of the
frame’s bytes are copied onto Indicate Channel 2. Only one
IDUD stream is produced (on Indicate Channel 1), but both
PSP Queues are used to determine where the IDUs will be
written. When a multi-part IDUD is produced, the Indicate
Status field is used to determine which parts point to the
header and which point to the Info. This Mode is intended
for high-performance protocol processing applications.
The Indicate Machine filters identical MAC and SMT frames
when the SKIP bit in the Indicate Mode Register is set, and
the Indicate Configuration Register’s Copy Control field (2
bits) for Indicate Channel 0 is set to 01 or 10.
Received frames are copied to memory based on the
AFLAG and MFLAG, ECIP, EA, and EM input signals from
external address matching logic, input signals from the
BMAC device, as well as the Indicate Channel’s Copy Control field. Received frames are written as a series of Input
Data Units to the current Indicate page. Each frame is
aligned to the start of a currently-defined, burst-size memory
block (16 or 32 bytes as programmed in the Mode Register’s SMLB bit). The first word contains the FC only, copied
The BSI device is composed of the Map Engine and Interfaces to the Control Bus (Control Bus Interface), the BMAC
device (BMAC Device Interface) and the ABus (Abus Interface).
In this section, the Map Engine is described in detail to provide an in-depth look at the operation of the BSI device.
4.1 OVERVIEW
The Map Engine consists of two major blocks, the Indicate
Machine and the Request Machine. These blocks share the
Bus Interface Unit, Status/Space Machine, Pointer RAM,
and Limit RAM blocks.
The Map Engine provides an interface between the BMAC
FDDI Protocol chip and a host system. The Map Engine
transfers FDDI frames (Service Data Units) between the
FDDI device and host memory.
4.1.1 Indicate Machine
On the Receive side (from the ring) the Indicate Machine
sequences through the incoming byte stream from the
BMAC device. Received frames are sorted onto Indicate
Channels and a decision is made whether or not to copy
them to host memory. The Indicate Machine uses the control signals provided by the BMAC device Receive State
Machine on the MAC Indicate Interface.
4.1.2 Request Machine
On the Transmit side (to the ring) the Request Machine prepares one or more frames from host memory for transmission to the BMAC device. The Request Machine provides all
the control signals to drive the BMAC device Request Interface.
4.2 OPERATION
4.2.1 Indicate Operation
The Indicate Block accepts data from the BMAC device as a
byte stream.
Upon receiving the data, the Indicate Block performs the
following functions:
# Decodes the Frame Control field to determine the frame
type
# Sorts the received frames onto Channels according to
the Sort Mode
# Filters identical MAC frames
# Copies the received frames to memory according to
Copy Criteria
# Writes status for the received frames to the Indicate
Status Queue
# Issues interrupts to the host on host-defined status
breakpoints
The Indicate Machine decodes the Frame Control (FC) field
to determine the type of frame. Ten types of frames are
recognized: Logical Link Control (LLC), Restricted Token,
Unrestricted Token, Reserved, Station Management (SMT),
SMT Next Station Addressing, MAC Beacon, MAC Claim,
Other MAC, and Implementer.
The Indicate Machine sorts incoming frames onto Indicate
Channels according to the frame’s FC field, the state of the
AFLAG signal from the BMAC device, and the host-defined
sorting mode programmed in the Sort Mode field of the Indicate Mode Register. SMT and MAC Service Data Units
(SDUs) are always sorted onto Indicate Channel 0. On Indicate Channels 1 and 2, frames can be sorted according to
9
4.0 Functional Description (Continued)
Breakpoint bits (Breakpoint on Burst End, Breakpoint on
Service Opportunity, and Breakpoint on Threshold) in the
Indicate Mode Register, and enabling the breakpoints to
generate an attention by setting the corresponding Breakpoint bit in the Indicate Notify Register.
When an Indicate exception occurs, the current frame is
marked complete, status is written into an IDUD.Last, and
the Channel’s Exception (EXC) bit in the Indicate Attention
Register is set.
When an Indicate error (other than a parity error) is detected, the Channel’s Error (ERR) bit in the State Attention Register is set. The host must reset the INSTOP Attention bit to
restart processing on the Indicate Channel.
When parity checking is enabled and a parity error is detected in a received frame, it is recorded in the Indicate Status
field of the IDUD, and the BMAC device Parity Error (PBE)
bit in the Status Attention Register is set.
into all bytes of the first word written, with the DA, SA and
INFO fields aligned to the first byte of the next word. The
format differs according to the setting of the Mode Register’s BIGEND (Big Endian) bit, as shown in Figure 4-1.
Byte 0
Bit 31
Byte 3
Bit 0
Big Endian Indicate Data Unit Format
FC
FC
FC
FC
DA0
DA1
SA0
SA1
Byte 3
Bit 31
Little Endian Indicate Data Unit Format
Byte 0
Bit 0
FC
FC
FC
FC
SA1
SA0
DA1
DA0
FIGURE 4-1. Indicate Data Unit Formats
(Short Addresses)
4.2.2 Request Operation
The Request Block transmits frames from host memory to
the BMAC device. Data is presented to the BMAC device as
a byte stream.
The Request Block performs the following functions:
For each Input Data Unit, the Indicate Machine creates an
Input Data Unit Descriptor (IDUD), which contains status information about the IDU, its size (byte count), and its location in memory. For IDUs that fit within the current Indicate
page, an IDUD.Only Descriptor is created. For IDUs that
span more than one page, a multi-part IDUD is created, i.e.,
when a frame crosses a page boundary, the BSI device
writes an IDUD.First; if another page is crossed, an
IDUD.Middle will be written; and at the frame end, an
IDUD.Last is written. IDUDs are written to consecutive locations in the Indicate Status Queue for the particular Indicate
Channel, up to the host-defined queue limit.
The Indicate Machine copies IDUs and IDUDs to memory as
long as there are no exceptions or errors, and the Channel
has data and status space. When a lack of either data or
status space is detected on a particular Channel, the Indicate Machine stops copying new frames for that Channel
(only). It will set the No Status Space attention bit in the No
Space Attention Register when it runs out of Status Space.
It will set the Low Data Space bit in the No Space Attention
Register when the last available PSP is prefetched from the
Indicate Channel PSP Queue. The host allocates more data
space by adding PSPs to the tail of the PSP Queue and then
updating the PSP Queue Limit Register, which causes the
BSI device to clear the Low Data Space attention bit and
resume copying (on the same Channel). The host allocates
more status space by updating the IDUD Queue Limit Register and then explicitly clearing the Channel’s No Status
Space bit, after which the Indicate Machine resumes copying.
The BSI device provides the ability to group incoming
frames and then generate interrupts (via attentions) at
group boundaries. To group incoming frames, the BSI device defines status breakpoints, which identify the end of a
group (burst) of related frames. Status breakpoints can be
enabled to generate an attention.
The breakpoints for Indicate Channels are defined by the
host in the Indicate Mode, Indicate Notify, and Indicate
Threshold registers. Status breakpoints include Channel
change, receipt of a token, SA change, DA change, MAC
Info change, and the fact that a user-specified number of
frames have been copied on a particular Indicate Channel.
Status breakpoint generation may be individually enabled
for Indicate Channels 1 and 2 by setting the corresponding
#
#
#
#
#
Prioritizes active requests to transmit frames
Requests the BMAC device to obtain a token
Transmits frames to the BMAC device
Writes status for transmitted and returning frames
Issues interrupts to the host on user-defined group
boundaries
The Request Machine processes requests by reading Request Descriptors from the REQ Queue, then assembling
frames of the specified service class, frame control and expected status for transmission to the BMAC device. Request and ODUD Descriptors are checked for consistency,
and the Request Class is checked for compatibility with the
current ring state. When an inconsistency or incompatibility
is detected, the request is aborted.
When a consistency failure occurs, the Request is terminated with appropriate status. The Request Machine then locates the end of the current object (REQ or ODUD). If the
current Descriptor is not the end (Last bit not set), the Request Machine will fetch subsequent Descriptors until it detects the end, then resume processing with the next Descriptor.First or Descriptor.Only.
Requests are processed on both Request Channels simultaneously. Their interaction is determined by their priorities
(Request Channel 0 has higher priority than Request Channel 1) and the Hold and Preempt/Prestage bits in the Request Channel’s Request Configuration Register. An active
Request Channel 0 is always serviced first, and may be programmed to preempt Request Channel 1, such that uncommitted Request Channel 1’s data already in the request
FIFO will be purged and then refetched after servicing Request Channel 0. When prestaging is enabled, the next
frame is staged before the token arrives. Prestaging is always enabled for Request Channel 0, and is a programmable option on Request Channel 1.
When a REQ.First is loaded, the Request Machine commands the BMAC device to capture a token of the type
specified in the REQ Descriptor, and concurrently fetches
the first ODUD. If prestaging is enabled, or a service opportunity exists for this Request Channel, data from the first
10
4.0 Functional Description (Continued)
frames are ignored by the BSI device. The frame count ends
when any of the following conditions occur:
ODU is loaded into the Request FIFO, and the BSI device
requests transmission from the BMAC device. When the
BMAC device has captured the appropriate token and the
frame is committed to transmission (the FIFO threshold has
been reached or the end of the frame is in the FIFO), transmission begins. The BSI device fetches the next ODUD and
starts loading the ODUs of the next frame into the FIFO.
This continues (across multiple service opportunities if required) until all frames for that Request have been transmitted (i.e., an REQ.ONLY or an REQ.LAST is detected), or an
exception or error occurs, which prematurely ends the Request.
The BSI device will load REQ Descriptors as long as the
RQSTOP bit in the State Attention Register is Zero, the
REQ Queue contains valid entries (the REQ Queue Pointer
Register does not exceed the REQ Queue Limit Register),
and there is space in the CNF Queue (the CNF Queue
Pointer Register is less than the CNF Queue Limit Register).
Request status is generated as a single confirmation object
(single- or multi-part) per Request object, with each confirmation object consisting of one or more CNF Descriptors.
The type of confirmation is specified by the host in the Confirmation Class field of the REQ Descriptor.
The BSI device can be programmed to generate CNF Descriptors at the end of the Request object (End Confirmation), or at the end of each token opportunity (Intermediate
Confirmation), as selected in the E and I bits of the Request
Class Field of the REQ Descriptor. A CNF Descriptor is always written when an exception or error occurs (regardless
of the value in the Confirmation Class field), when a Request completes (for End or Intermediate Confirmation
Class), or when an enabled breakpoint occurs (Intermediate
Confirmation Class only).
There are three basic types of confirmation: Transmitter,
Full, and None. With Transmitter Confirmation, the BSI device verifies that the Output Data Units were successfully
transmitted. With Full Confirmation, the Request Machine
verifies that the ODUs were successfully transmitted, that
the number of (returning) frames ‘‘matches’’ the number of
transmitted ODUs, and that the returning frames contain the
expected status. When the None Confirmation Class is selected, confirmation is written only if an exception or error
occurs.
For Full Confirmation, a matching frame must meet the following criteria:
1. The frame has a valid Ending Delimiter (ED).
2. The selected bits in the FC fields of the transmitted and
received frames are equal (the selected bits are specified
in the FCT bit of the Request Configuration Register).
3. The frame is MyÐSA (MFLAG or both SAT & EM asserted).
4. The frame matches the values in the Expected Frame
Status Register.
5. FCS checking is disabled or FCS checking is enabled and
the frame has a valid FCS.
6. All bytes from FC to ED have good parity (when the
FLOW bit in the Mode Register is set, i.e., parity checking
is enabled).
The confirmed frame count starts after the first Request
burst frame has been committed by the BMAC device, and
when a frame with MyÐSA is received. Void and MyÐVoid
1. All the frames have been transmitted, and the transmitted
and confirmed frame counts are equal.
2. There is a MACRST (MAC Reset).
3. The state of the ring-operation has changed.
4. A stripped frame or a frame with a parity error is received.
5. A non-matching frame is received.
6. A token is received.
When Source Address Transparency is selected (by setting
the SAT bit in the Request Configuration Register) and Full
confirmation is enabled, confirmation begins when a frame
end is detected with either MFLAG or EM asserted.
When a non-matching frame is received, the BSI device
ends the Request, and generates the Request Complete
(RCM), Exception (EXC), and Breakpoint (BRK) attentions.
Any remaining REQs in the Request object are fetched until
a REQ.Last or REQ.Only is encountered. Processing then
resumes on the next REQ.First or REQ.Only (any other type
of REQ would be a consistency failure).
Request errors and exceptions are reported in the State
Attention Register, Request Attention Register, and the
Confirmation Message Descriptor. When an exception or error occurs, the Request Machine generates a CNF and
ends the Request. The Unserviceable Request (USR) attention is set to block subsequent Requests once one becomes unserviceable.
4.2.3 State Machines
There are three state machines under control of the host:
the Request Machine, the Indicate Machine, and the
Status/Space Machine. Each Machine has two Modes:
Stop and Run. The Mode is determined by the setting of the
Machine’s corresponding STOP bit in the State Attention
Register. The STOP bits are set by the BSI device when an
error occurs or may be set by the user to place the Machine
in Stop Mode.
The BSI Control Registers may be programmed only when
all Machines are in Stop Mode. When the Status/Space
Machine is in Stop Mode, only the Pointer RAM and Limit
RAM Registers may be programmed.
When the Indicate and Request Machines are in Stop
Mode, all indicate and request operations are halted. When
the Status/Space Machine is in Stop Mode, only the PTOP
and LMOP service functions can be performed.
4.3 BUS INTERFACE UNIT
4.3.1 Overview
The ABus provides a 32-bit wide synchronous multiplexed
address/data bus for transfers between the host system
and the BSI device. The ABus uses a bus request/bus grant
protocol that allows multiple bus masters, supports burst
transfers of 16 and 32 bytes, and supports virtual and physical addressing using fixed-size pages. The BSI is capable of
operating directly on the system bus to main memory, or
connected to external shared memory.
All bus signals are synchronized to the master bus clock.
The maximum burst speed is one, 32-bit word per clock, but
slower speeds may be accommodated by inserting wait
states. The user may use separate clocks for the ring (FDDI
MAC) and system (ABus) interfaces. The only restriction is
that the ABus clock must be at least as fast as the ring clock
11
4.0 Functional Description (Continued)
Burst transfers are always word-aligned on a 16- or 32-byte
(burst-size) address boundary. Burst transfers will never
cross a burst-size boundary. If a 32-byte transfer size is chosen, the BSI device will perform both 16-byte and 32-byte
bursts, whichever is most efficient (least number of clocks
to load/store all required data).
The Bus Interface Unit can operate in either Big Endian or
Little Endian Mode. The bit and byte alignments for both
modes are shown in Figure 4-2 . Byte 0 is the first byte received from the ring or transmitted to the ring.
(LBC). It is important to note that all ABus outputs change
and all ABus inputs are sampled on the rising edge of
ABÐCLK.
Addressing Modes
The Bus Interface Unit has two Address Modes, as selected
by the user: Physical Address Mode and Virtual Address
Mode. In Physical Address Mode, the BSI device emits the
memory address and immediately begins transferring the
data. In Virtual Address Mode, the BSI device inserts two
clock cycles and TRI-STATETM s the address between emitting the virtual address and starting to transfer the data. This
allows virtual-to-physical address translation by an external
MMU.
The BSI device interfaces to byte-addressable memory, but
always transfers information in words. The BSI device uses
a word width of 32 data bits plus 4 (1 per byte) parity bits.
Parity may be ignored.
Bus Arbitration
The ABus is a multi-master bus, using a simple Bus Request/Bus Grant protocol that allows an external Bus Arbiter to support any number of bus masters, using any arbitration scheme (e.g., rotating or fixed priority). The protocol
provides for multiple transactions per tenure, and bus master preemption.
The BSI device asserts a Bus Request, and assumes mastership when Bus Grant is asserted. If the BSI device has
another transaction pending, it will keep Bus Request asserted, or reassert it before the completion of the current
transaction. If Bus Grant is (re)asserted before the end of
the current transaction, the BSI device retains mastership
and runs the next transaction. This process may be repeated indefinitely.
If the Bus Arbiter wishes to preempt the BSI device, it deasserts Bus Grant. The BSI device will complete the current
bus transaction, then release the bus. From preemption to
bus release is a maximum of (11 bus clocks a (8 times the
number of memory wait states)) bus clocks. For example, in
a 1 wait-state system, the BSI device will release the bus
within a maximum of 19 bus clocks.
Bus Transfers
The bus supports several types of transactions. Simple
reads and writes involve a single address and data transfer.
Burst reads and writes involve a single address transfer followed by multiple data transfers. The BSI device provides
the incrementing address bits during the burst transaction.
Burst sizes are selected dynamically by the BSI.
On Indicate Channels, when 8-word bursts are enabled, all
transactions will be 8 words until the end of the frame; the
last transfer will be 4 or 8 words, depending on the number
of remaining bytes. If only 4-word bursts are allowed, all
Indicate Data transfers are 4 words.
On Request Channels, the BSI will use 4- or 8-word bursts
to access all data up to the end of the ODU. If 8-word bursts
are enabled, the first access will be an 8-word burst if the
ODU begins less than 4 words from the start of an 8-word
burst boundary. If 8-word bursts are not allowed, or if the
ODU begins 4 or more words from the start of an 8-word
burst boundary, a 4-word burst will be used. The BSI will
ignore unused bytes if the ODU does not start on a burst
boundary. At the end of an ODU, the BSI will use the smallest transfer size (1, 4, or 8 words) which completes the ODU
read. To coexist in a system that assumes implicit wraparound for the addresses within a burst, the BSI device never emits a burst that will wrap the 4- or 8-word boundary.
A Function Code identifying the type of transaction is output
by the BSI device on the upper four address bits during the
address phase of a data transfer. This can be used for more
elaborate external addressing schemes, for example, to direct control information to one memory and data to another
(e.g., an external FIFO). To assist the user with the burst
transfer capability, the BSI device also outputs three demultiplexed address bits during a burst transfer. These indicate
the next word within a burst to be accessed.
Big-Endian Byte Order
D[31]
D[0]
Word
Halfword 0
Byte 0
Halfword 1
Byte 1
Byte 2
Byte 3
Little-Endian Byte Order
D[31]
D[0]
Word
Halfword 1
Byte 3
Byte 2
Halfword 0
Byte 1
Byte 0
FIGURE 4-2. ABus Byte Orders
Parity
There are two options for parity: one for systems using parity, the other for systems not using parity. Parity checking on
the ABus can be disabled by clearing the FLOW bit in the
Mode Register. When parity is enabled (FLOW bit is set), it
operates in flow-through mode on the main datapath, that
is, parity is not checked at the ABus but simply flows between the ABus and the BMAC device interface, and is
checked by the BMAC device as it is received. When the
FLOW bit is set, parity checking is also enabled on the Control Bus and MAC Indicate Interfaces.
The BSI device generates parity on all addresses output on
the ABus.
Byte Ordering
The basic addressable quantum is a byte, so request data
may be aligned to any byte boundary in memory. All information is accessed in 32-bit words, however, so the BSI
device ignores unused bytes when reading.
Descriptors must always be aligned to a word address
boundary. Input Data Units are always aligned to a burstsize boundary. Output Data Units may be any number of
bytes, aligned to any byte-address boundary, but operate
most efficiently when aligned to a burst-size boundary.
12
4.0 Functional Description (Continued)
two Burst FIFOs, each containing two banks of 32 bytes,
which provide ABus bursting capability.
Bandwidth
The ABus supports single reads and writes, and burst reads
and writes. With physical addressing, back-to-back single
reads/writes can take place every four clock cycles. Burst
transactions can transfer 8, 32-bit words (32 bytes) every 11
clock cycles. With a 25 MHz clock this yields a peak bandwidth of 72.7 Mbytes/sec.
To allow the bus to operate at high frequency, the protocol
defines all signals to be both asserted and deasserted by
the bus master and slaves. Having a bus device actively
deassert a signal guarantees a high-speed inactive transition. If this were not defined, external pull-up resistors
would not be able to deassert signals fast enough. The protocol also reduces contention by avoiding cases where two
bus devices simultaneously drive the same line.
The BSI device operates synchronously with the ABus
clock. In general, operations will be asynchronous to the
ring, since most applications will use a system bus clock
that is asynchronous to the ring. The BSI device is designed
to interface either directly to the host’s main system bus or
to external shared memory. When interfaced to the host’s
bus, there are two parameters of critical interest: latency
and bandwidth.
Data moves between the Request and Indicate Channels
and the ABus via four FIFOs, two in the receive path (Indicate) and two in the transmit path (Request). On the BMAC
Device Interface, there are two, 16 x 32 bit data FIFOs for
Indicate and Request data. On the ABus Interface, there are
The amount of latency covered by the Data FIFO plus one
of the banks of the Burst FIFO must meet the average and
maximum bus latency of the external memory. With a new
byte every 80 ns from the ring, a 64-byte FIFO provides
64 x 80 e 5.12 ms maximum latency.
To assist latency issues, the BSI device can completely
empty or fill the Burst FIFO in one bus tenure by asserting
Bus Request for multiple transactions. Since one bank of
the Burst FIFO is 8 words deep, if 8-word bursts are enabled, that half of the Burst FIFO can be emptied in one
transaction. If the second half of the burst FIFO is also full, it
can be emptied in the same bus tenure by again granting
the bus to the BSI device.
The BSI device may be preempted at any time by removing
Bus Grant, which causes the BSI device to complete the
current transaction and release the bus. There will be a
maximum of 11 clocks (plus any memory wait states) from
preemption to bus release (fewer if 8-word bursts are not
enabled).
4.3.2 Bus States
An ABus Master has eight states: idle (Ti), bus request
(Tbr), virtual address (Tva), MMU translate (Tmmu), physical
address (Tpa), data transfer (Td), wait (Tw) and recovery
(Tr). The ABus Master state diagram is shown in Figure 4-3 .
An ABus Slave has five states: idle (Ti), selected (Ts), data
transfer (Td), wait (Tw), and recovery (Tr).
13
14
Note 4: Timing for ABÐBR not shown.
FIGURE 4-3. BSI Device ABus Master State Machine (from the BSI Device)
Note 3: If (ABÐACK) lastÐdata negates ABÐAS, processes data.
Note 1: If (ABÐACK) nextÐdata decrements burstÐcount, processes data.
Note 2: BurstÐcount is pipelined 1 ahead, so is true in last Td state.
TL/F/10791 – 6
4.0 Functional Description (Continued)
4.0 Functional Description (Continued)
cle). If the slave can drive data at the rate of one word per
clock (in a burst), it keeps ABÐACK asserted.
Master States
The Ti state exists when no bus activity is required. The BIU
does not drive any of the bus signals when it is in this state
(all are released). If the BIU requires bus service, it may
assert Bus Request.
When a transaction is run, the BIU enters Tbr and asserts
Bus Request, then waits for Bus Grant to be asserted.
The state following Tbr is either Tva or Tpa. In Virtual Address Mode, the BIU enters Tva and drives the virtual address and size lines onto the bus. In Physical Address
Mode, Tpa occurs next (see Section 4.3.3).
Following a Tva state is a Tmmu state. During this cycle the
external MMU is performing a translation of the virtual address emitted during Tva.
Following a Tmmu state (when using virtual addressing) or a
Tbr state (when using physical addressing), is the Tpa state.
During the Tpa state, the BSI device drives the read/write
strobes and size signals. In physical address mode, it also
drives ABÐAD with address. In virtual address mode, the
BSI device TRI-STATEs ABÐBD so the host CPU or MMU
can drive the address.
Following the Tpa state, the BIU enters the Td state to
transfer data words. Each data transfer may be extended
indefinitely by inserting Tw states. A slave acknowledges by
asserting ABÐACK and transferring data in a Td state (cy-
Following the final Td/Tw state, the BIU enters a Tr state to
allow time to turn off or turn around bus transceivers.
A bus retry request is recognized in any Td/Tw state. The
BIU will go to a Tr state and then rerun the transaction when
it obtains a new Bus Grant. The whole transaction is retried,
i.e., all words of a burst. Additionally, no other transaction
will be attempted before the interrupted one is retried. The
BIU retries indefinitely until either the transaction completes
successfully, or a bus error is signaled.
Bus errors are recognized in Td/Tw states.
4.3.3 Physical Addressing Bus Transactions
Bus transactions in Physical Address Mode are shown in
Figure 4-4 through 4-7 . BSI device signals are defined in
Chapter 6.
Single Read
Tbr:
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG. Moves to
Tpa on the next clock.
Tpa:
BSI device drives ABÐA and ABÐAD with the address, asserts ABÐAS, drives ABÐRW and
ABÐSIZ[2:0], negates ABÐBR if another transaction is not required.
TL/F/10791 – 7
FIGURE 4-4. ABus Single Read, Physical Addressing, 0 W – S, 1 W – S, Bus Handover
15
4.0 Functional Description (Continued)
Td:
Tr:
BSI device negates ABÐAS, asserts ABÐDEN,
samples ABÐACK and ABÐERR. Slave asserts
ABÐACK, drives ABÐERR, drives ABÐAD (with
data) when ready. The BSI device samples a valid
ABÐACK, capturing the read data. Tw states may
occur after Td.
BSI
device
negates
ABÐRW,
ABÐDEN,
ABÐSIZ[2:0], releases ABÐA, and ABÐAS. Slave
deasserts ABÐACK and ABÐERR, releases
ABÐAD.
Tpa:
Td:
Tr:
Single Write
Tbr: BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG. Moves to
Tpa on the next clock.
BSI device drives ABÐA and ABÐAD with the address, asserts ABÐAS, drives ABÐRW and
ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
BSI device negates ABÐAS, asserts ABÐDEN,
drives ABÐAD with the write data and starts sampling ABÐACK and ABÐERR. Slave captures
ABÐAD data, asserts ABÐACK, drives ABÐERR.
Tw states may occur after Td if the slave deasserts
ABÐACK.
BSI
device
negates
ABÐRW,
ABÐDEN,
ABÐSIZ[2:0], releases ABÐA, ABÐAD, ABÐAS.
Slave deasserts ABÐACK and ABÐERR, and stops
driving ABÐAD with data.
TL/F/10791 – 8
FIGURE 4-5. ABus Single Write, Physical Addressing, 0 W – S, 1 W – S, Bus Handover
16
4.0 Functional Description (Continued)
Burst Read
Tbr:
Tpa:
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG. Moves to
Tpa on the next clock.
BSI device drives ABÐA and ABÐAD with the address, asserts ABÐAS, drives ABÐRW and
ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
Td:
BSI device asserts ABÐDEN, samples ABÐACK
and ABÐERR, increments the address on ABÐA.
Slave asserts ABÐACK, drives ABÐERR, and
drives ABÐAD (with data) when ready. BSI device
samples a valid ABÐACK, capturing the read data.
Tw states may occur after Td. Td state is repeated
four or eight times (according to the burst size). On
the last Td state, the BSI device negates ABÐAS.
Tr:
BSI
device
negates
ABÐRW,
ABÐDEN,
ABÐSIZ[2:0], and releases ABÐA and ABÐAS.
Slave deasserts ABÐACK and ABÐERR, and releases ABÐAD.
TL/F/10791 – 9
FIGURE 4-6. ABus Burst Read, Physical Addressing, 16 Bytes, 1 W – S
17
4.0 Functional Description (Continued)
Burst Write
Tbr:
Tpa:
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG. Moves to
Tpa on the next clock.
BSI device drives ABÐA and ABÐAD with the address, asserts ABÐAS, drives ABÐRW and
ABÐSIZ[2:0], and negates ABÐBR if another transaction is not required.
Td:
BSI device asserts ABÐDEN, drives ABÐAD with
the write data, samples ABÐACK and ABÐERR, increments the address on ABÐA. Slave captures
ABÐAD data, asserts ABÐACK, drives ABÐERR.
BSI device samples a valid ABÐACK. Tw states may
occur after Td. Td state is repeated as required for
the complete burst. On the last Td state, the BSI
device negates ABÐAS.
Tr:
BSI
device
negates
ABÐRW,
ABÐDEN,
ABÐSIZ[2:0], releases ABÐA and ABÐAS. Slave
deasserts ABÐACK and ABÐERR, and stops driving ABÐAD with data.
TL/F/10791 – 10
FIGURE 4-7. ABus Burst Write, Physical Addressing, 16 Bytes 1 W – S
18
4.0 Functional Description (Continued)
4.3.4 Virtual Addressing Bus Transactions
Burst Read
Single Read
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG, BSI
drives ABÐA and ABÐAD when ABÐBG is asserted. Moves to Tva on the next clock.
Tva:
BSI device drives ABÐA and ABÐAD with the virtual address for one clock, negates ABÐAS, asserts
ABÐRW, drives ABÐSIZ[2:0], and negates
ABÐBR if another transaction is not required.
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABÐAD with the translated (physical) address. BSI device drives ABÐA and asserts
ABÐAS.
Td:
BSI device asserts ABÐDEN, samples ABÐACK
and ABÐERR. Slave asserts ABÐACK, drives
ABÐERR, drives ABÐAD (with data) when ready.
BSI device samples a valid ABÐACK, capturing the
read data. Tw states may occur after Td. This state
is repeated four or eight times (according to burst
size). On the last Td state the BSI device negates
ABÐAS.
Tbr:
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG, and BSI
device drives ABÐA and ABÐAD when ABÐBG is
asserted. Moves to Tva on the next clock.
Tva:
BSI device drives ABÐA and ABÐAD with the virtual address for one clock, negates ABÐAS, asserts
ABÐRW, drives ABÐSIZ[2:0], and negates
ABÐBR if another transaction is not required.
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABÐAD with the translated (physical) address, BSI device drives ABÐA and asserts
ABÐAS.
Tbr:
Td:
Tr:
BSI device negates ABÐAS, asserts ABÐDEN,
samples ABÐACK and ABÐERR. Slave asserts
ABÐACK, drives ABÐERR, drives ABÐAD (with
data) when ready. BSI device samples a valid
ABÐACK, capturing the read data. Tw states may
occur after Td.
BSI device negates ABÐRW, ABÐDEN, and
ABÐSIZ[2:0], releases ABÐA and ABÐAS. Slave
deasserts ABÐACK and ABÐERR and releases
ABÐAD.
Tr:
Single Write
Tbr:
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG, BSI device drives ABÐA and ABÐAD when ABÐBG is
asserted. Moves to Tva on the next clock.
Tva:
BSI device drives ABÐA and ABÐAD with the virtual address for one clock, negates ABÐAS, negates
ABÐRW, and drives ABÐSIZ[2:0].
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABÐAD with the address, BSI device drives ABÐA asserts ABÐAS, and negates
ABÐBR if another transaction is not required.
Td:
BSI device negates ABÐAS, asserts ABÐDEN,
drives ABÐAD with the write data and starts sampling ABÐACK and ABÐERR. Slave captures
ABÐAD data, asserts ABÐACK, and drives
ABÐERR.
BSI
device
samples
a
valid
ABÐACK. Tw states may occur after Td.
ABÐDEN,
Tr:
BSI
device
negates
ABÐRW,
ABÐSIZ[2:0], releases ABÐA, ABÐAD, and
ABÐAS.
Slave
deasserts
ABÐACK
and
ABÐERR, and stops driving ABÐAD with data.
ABÐDEN,
BSI
device
negates
ABÐRW,
ABÐSIZ[2:0], releases ABÐA and ABÐAS. Slave
deasserts ABÐACK and ABÐERR, and releases
ABÐAD.
Burst Write
Tbr:
BSI device asserts ABÐBR to indicate it wishes to
perform a transfer. Host asserts ABÐBG, BSI device drives ABÐA and ABÐAD when ABÐBG is
asserted. Moves to Tva on the next clock.
Tva:
BSI device drives ABÐA and ABÐAD with the virtual address for one clock, negates ABÐAS, negates
ABÐRW, drives ABÐSIZ[2:0].
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABÐAD with the address, BSI device drives ABÐA asserts ABÐAS, and negates
ABÐBR if another transaction is not required.
Td:
BSI device asserts ABÐDEN, drives ABÐAD with
the write data and starts sampling ABÐACK and
ABÐERR. Slave captures ABÐAD data, asserts
ABÐACK and drives ABÐERR. BSI device samples a valid ABÐACK. Tw states may occur after
Td. This state is repeated as required for the complete burst. On the last Td state, the BSI device
negates ABÐAS.
Tr:
19
BSI
device
negates
ABÐRW,
ABÐDEN,
ABÐSIZ[2:0], releases ABÐA, ABÐAD, ABÐAS.
Slave deasserts ABÐACK and ABÐERR, stops
driving ABÐAD with data.
5.0 Control Information
# Limit Address Register (LAR) is used to program the
5.1 OVERVIEW
parameters and data used in the LMOP (Limit RAM Operation) service function.
Control information includes the parameters that are used
to manage and operate the BSI device.
Control information is divided into four basic groups: Operation Registers, Pointer RAM Registers, Limit RAM Registers, and Descriptors. The Control information Register Address Space is shown in Table 5-1.
Operation registers are accessed directly via the Control
Bus. Limit RAM Registers are accessed indirectly via the
Control Bus, using the Limit RAM Data and Limit RAM Address Registers. The Pointer RAM Registers are accessed
indirectly via the Control Bus and ABus using the Pointer
RAM Address and Control Register, the Mailbox Address
Register, and a mailbox location in ABus memory.
# Limit Data Register (LDR) is used to program the data
used in the LMOP service function.
# Request Channel 0 Configuration Register (R0CR) is
used to program the operational parameters for Request
Channel 0.
# Request Channel 1 Configuration Register (R1CR) is
used to program the operational parameters for Request
Channel 1.
# Request Channel 0 Expected Frame Status Register
(R0EFSR) defines the expected frame status for frames
being confirmed on Request Channel 0.
# Request Channel 1 Expected Frame Status Register
5.2 OPERATION REGISTERS
The Operation Registers are divided into two functional
groups: Control Registers and Event Registers. They are
shown in Table 5-2.
(R1EFSR) defines the expected frame status for frames
being confirmed on Request Channel 1.
# Indicate Threshold Register (ITR) is used to specify a
maximum number of frames that can be copied onto an
Indicate Channel before a breakpoint is generated.
Control Registers
The Control Registers are used to configure and control the
operation of the BSI device.
The Control Registers include the following registers:
# Indicate Mode Register (IMR) specifies how the incoming frames are sorted onto Indicate Channels, enables
frame filtering, and enables breakpoints on various burst
boundaries.
# Mode Register (MR) establishes major operating parameters for the BSI device.
# Indicate Configuration Register (ICR) is used to pro-
# Pointer RAM Control and Address Register (PCAR) is
gram the copy criteria for each of the Indicate Channels.
used to program the parameters for the PTOP (Pointer
RAM Operation) service function.
# Indicate Header Length Register (IHLR) defines the
length of the frame header for use with the Header/Info
Sort Mode.
# Mailbox Address Register (MBAR) is used to program
the memory address of the mailbox used in the data
transfer of the PTOP service function.
Table 5.1 Control Register Address Space
Address
Range
Description
Read
Conditions
Write
Conditions
00 – 1Fh
00 – 15h*
0 – 9h**
Operation Registers
Pointer RAM Registers
Limit RAM Registers
Always
Always
Always
Always (Conditional)
Always
Always
*Bits 0–4 of Pointer RAM Address and Control Register
**Bits 4–7 of Limit RAM Address Register
20
5.0 Control Information (Continued)
TABLE 5-2. Control and Event Registers
Access Rules
Register
Group
Address
C
00
Mode Register (MR)
Always
Always
C
01
Reserved
N/A
N/A
C
02
Pointer RAM Control and Address Register (PCAR)
Always
Always
Register Name
Read
Write
C
03
Mailbox Address Register (MBAR)
Always
Always
E
04
Master Attention Register (MAR)
Always
Data Ignored
E
05
Master Notify Register (MNR)
Always
Always
E
06
State Attention Register (STAR)
Always
Conditional
E
07
State Notify Register (STNR)
Always
Always
E
08
Service Attention Register (SAR)
Always
Conditional
E
09
Service Notify Register (SNR)
Always
Always
E
0A
No Space Attention Register (NSAR)
Always
Conditional
E
0B
No Space Notify Register (NSNR)
Always
Always
C
0C
Limit Address Register (LAR)
Always
Always
C
0D
Limit Data Register (LDR)
Always
Always
E
0E
Request Attention Register (RAR)
Always
Conditional
E
0F
Request Notify Register (RNR)
Always
Always
C
10
Request Channel 0 Configuration Register (R0CR)
Always
Always
C
11
Request Channel 1 Configuration Register (R1CR)
Always
Always
C
12
Request Channel 0 Expected Frame Status Register (R0EFSR)
Always
Always
C
13
Request Channel 1 Expected Frame Status Register (R1EFSR)
Always
Always
E
14
Indicate Attention Register (IAR)
Always
Conditional
E
15
Indicate Notify Register (INR)
Always
Always
C
16
Indicate Threshold Register (ITR)
Always
INSTOP Mode
or EXC e 1 Only
C
17
Indicate Mode Register (IMR)
Always
INSTOP Mode
Only
C
18
Indicate Configuration Register (ICR)
Always
Always
C
19
Indicate Header Length Register (IHLR)
Always
INSTOP Mode
or EXC e 1 Only
Reserved
N/A
N/A
Compare Register (CMP)
Always
Always
1A–C
E
1F
C e Control Register
E e Event Register
21
5.0 Control Information (Continued)
TABLE 5-3. Control and Event Registers Following Reset
Address
Register
Reset
00
Mode Register
00
02
Pointer RAM Control and Address Register
NA
03
Mailbox Address Register
*
04
Master Attention Register
00
05
Master Notify Registers
00
06
State Attention Register
07
07
State Notify Register
00
08
Service Attention Register
0F
09
Service Notify Register
00
0A
No Space Attention Register
FF
0B
No Space Notify Register
00
0C
Limit Address Register
NA
0D
Limit Data Register
NA
0E
Request Attention Register
00
0F
Request Notify Register
00
10
Request Channel 0 Configuration Register
NA
11
Request Channel 1 Configuration Register
NA
12
Request Channel 0 Expected Frame Status Register
NA
13
Request Channel 1 Expected Frame Status Register
NA
14
Indicate Attention Register
00
15
Indicate Notify Register
00
16
Indicate Threshold Register
NA
17
Indicate Mode Register
NA
18
Indicate Configuration Register
NA
19
Indicate Header Length Register
NA
1F
Compare Register
NA
* e Initialized to a silicon Revision code upon reset. The Revision code remains until it is overwritten by the host.
NA e Not altered upon reset.
22
5.0 Control Information (Continued)
Event Registers
The Event Registers record the occurrence of events or series of events. Events are recorded and contribute to generating the
Interrupt signal. There is a two-level hierarchy in generating this signal, as shown in Figure 5-1 .
At the first level of the hierarchy, events are recorded as bits in the Attention Registers (e.g., No Space Attention Register). Each
Attention Register has a corresponding Notify Register (e.g., No Space Notify Register). When a bit in the Attention Register is
set to One and its corresponding bit in the Notify Register is also set to One, the corresponding bit in the Master Attention
Register will be set to one.
At the second level of the hierarchy, if a bit in the Master Attention Register is set to One and the corresponding bit in the Master
Notify Register is set to One, the Interrupt signal is asserted.
Bits in Conditional Write Registers (e.g., No Space Attention Register) are only written when the corresponding bits in the
Compare Register are equal to the bits to be overwritten.
TL/F/10791 – 11
FIGURE 5-1. Event Registers Hierarchy
# Service Notify Register (SNR) is used to enable atten-
Events are recorded in Attention Registers and contribute to
the Interrupt when the bit in the corresponding Notify Register is set (see Table 5-2).
The Event Registers include the following registers:
tions in the Service Attention Register.
# No Space Attention Register (NSAR) presents attentions generated when the IDUD, PSP, or CNF Queues
run out of space or valid entries.
# Master Attention Register (MAR) collects enabled at-
# Request Attention Register (RAR) presents attentions
tentions from the State Attention Register, Service Attention Register, No Space Attention Register, Request Attention Register, and Indicate Attention Register.
generated by both Request Channels.
# Request Notify Register (RNR) is used to enable atten-
# Master Notify Register (NMR) is used to selectively en-
tions in the Request Attention Register.
able attention in the Master Attention Register.
# Indicate Attention Register (IAR) presents the atten-
# State Attention Register (STAR) presents attentions
tions generated by the Indicate Channels.
for major states within the BSI device and various error
conditions.
# Indicate Notify Register (INR) is used to enable atten-
# State Notify Register (STNR) is used to enable atten-
# Compare Register (CMP) is used for comparison with a
tions in the Indicate Attention Register.
tions in the State Attention Register.
write access of a conditional write (Attention) register.
# Service Attention Register (SAR) presents attentions
for the PTOP and LMOP service functions.
23
5.0 Control Information (Continued)
5.3 CONTROL AND EVENT REGISTER DESCRIPTIONS
Mode Register (MR)
The Mode Register (MR) is used to program the major operating parameters for the BSI device. This register should be
programmed only at power-on, or after a software Master Reset.
This register is cleared upon reset.
Access Rules
Address
Read
Write
00h
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
SMLB
SMLQ
VIRT
BIGEND
FLOW
MRST
FABCLK
TEST
Bit
Symbol
D0
TEST
Test Mode: Enables test logic, in which the transmitted frames counter will cause a
service loss after four frames, instead of 255 frames.
Description
D1
FABCLK
Fast ABus Clock: Determines the metastability delay period for synchronizing between
the ABus clock and the Ring clock (LBC). Upon reset this bit is cleared to Zero, which
selects one ABus clock period as the delay. When this bit is set to One, only (/2 of an ABus
clock delay is used. When ABÐCLK e LBC, (i.e., at 12.5 MHz and in phase), this bit
should be set. For any ABÐCLK greater then LBC, this bit must be Zero.
D2
MRST
Master Reset: When this bit is set, the Indicate, Request, and Status/Space Macines are
placed in Stop Mode,and BSI device registers are initialized to the values shown in Table
5-5. This bit is cleared after the reset is complete.
D3
FLOW
Flow Parity: When this bit is set, parity flows between the ABus and the BMAC device,
that is, incoming data is not checked at the ABus interface, but is checked (by the BMAC
device) as it is passed to the BMAC device. The parity check includes the frame’s FC
through ED fields. When this bit is set, Control Bus parity is also checked, and errors are
reported in the CPE bit of the State Attention Register. When this bit is Zero, no parity is
checked on the Control Bus or ABus.
D4
BIGEND
Big Endian Data Format: Selects between the Little Endian (BIGEND e 0) or Big Endian
(BIGEND e 1) data format. See Figure 4-2 .
D5
VIRT
Virtual Address Mode: Selects between virtual (VIRT e 1) or physical (VIRT e 0)
address mode on the ABus.
D6
SMLQ
Small Queue: Selects the size of all Descriptor queues and lists. When SMLQ e 0, the
size is 4k bytes; when SMLQ e 1, the size is 1k bytes. Note that data pages are always
4k bytes.
D7
SMLB
Small Bursts: Selects size of bursts on ABus. When SMLB e 0, the BSI device uses 1-,
4-, and 8-word transfers. When SMLB e 1, the BSI device uses 1- and 4-word transfers.
24
5.0 Control Information (Continued)
Pointer RAM Control and Address Register (PCAR)
The Pointer RAM Control and Address Register (PCAR) is used to program the parameters for the PTOP (Pointer RAM
Operation) service function, in which data is written to or read from a Pointer RAM Register.
This register is not altered upon reset.
Access Rules
Address
Read
Write
02h
Always
Always
Register Bits
Bit
D7
D6
D5
D4
D3
D2
D1
D0
BP1
BP0
PTRW
A4
A3
A2
A1
A0
Symbol
Description
D0 – 4
A0– 4
Pointer RAM Address: These five bits contain the Pointer RAM Register address for a
subsequent PTOP service function.
D5
PTRW
PTOP Read/Write: This bit determines whether a PTOP service function will be a read
from the Pointer RAM Register to the mailbox in memory (PTRW e 1), or a write to the
Pointer RAM Register from the mailbox (PTRW e 0).
D6 – 7
BP0– 1
Byte Pointer: These two bits are used to program an internal byte pointer for accesses to
the 32-bit Mailbox Address Register. They are normally set to Zero to initialize the byte
pointer for four successive writes (most-significant byte first) and are automatically
incremented after each write.
25
5.0 Control Information (Continued)
Mailbox Address Register (MBAR)
The Mailbox Address Register (MBAR) is used to program the word-aligned 28-bit memory address of the mailbox used in the
data transfer of the PTOP (Pointer RAM Operation) service function.
The address of this register is used as a window into four internal byte registers. The four byte registers are loaded by
successive writes to this address after first setting the BPR bits in the Pointer RAM Control and Address Register to Zero. The
bytes must be loaded most-significant byte first. The BSI device increments the byte pointer internally after each write or read.
Mailbox Address bits 0 and 1 forced internally to Zero.
This register is initialized to a silicon Revision code upon reset. The Revision code remains until it is overwritten by the host.
Access Rules
Address
Read
Write
03h
Always
Always
Register Bits
7
0
Mailbox Address [27:24]
Mailbox Address [23:16]
Mailbox Address [15:8]
Mailbox Address [7:0]
26
5.0 Control Information (Continued)
Master Attention Register (MAR)
The Master Attention Register (MAR) collects enabled attentions from the State Attention Register, Service Attention Register,
No Space Attention Register, Request Attention Register, and Indicate Attention Register. If the Notify bit in the Master Notify
Register and the corresponding bit in the MAR are set to One, the INT is forced to LOW and thus triggers an interrupt.
Writes to the Master Attention Register are permitted, but do not change the contents.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
04h
Always
Data Ignored
Register Bits
Bit
D7
D6
D5
D4
D3
D2
D1
D0
STA
NSA
SVA
RQA
INA
RES
RES
RES
Symbol
Description
D0 – 2
RES
Reserved
D3
INA
Indicate Attention Register: Is set if any bit in the Indicate Attention Register is set.
D4
RQA
Request Attention Register: Is set if any bit in the Request Attention Register is set.
D5
SVA
Service Attention Register: Is set if any bit in the Service Attention Register is set.
D6
NSA
No Space Attention Register: Is set if any bit in the No Space Attention Register is set.
D7
STA
State Attention Register: Is set if any bit in the State Attention Register is set.
27
5.0 Control Information (Continued)
Master Notify Register (MNR)
The Master Notify Register (MNR) is used to enable attentions in the Master Attention Register (MAR). If a bit in Register MNR
and the corresponding bit in Register MAR are set to One, the INT signal is deasserted and causes an interrupt.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
05h
Always
Always
Register Bits
Bit
D7
D6
D5
D4
D3
D2
D1
D0
STAN
NSAN
SVAN
RQAN
INAN
RES
RES
RES
Symbol
Description
D0 – 2
RES
Reserved
D3
INAN
Indicate Attention Register Notify: This bit is used to enable the INA bit in Register MNR.
D4
RQAN
Request Attention Register Notify: This bit is used to enable the RQA bit in Register MNR.
D5
SVAN
Service Attention Register Notify: This bit is used to enable the SVA bit in Register MNR.
D6
NSAN
No Space Attention Register Notify: This bit is used to enable the NSA bit in Register MNR.
D7
STAN
State Attention Register Notify: This bit is used to enable the STA bit in Register MNR.
28
5.0 Control Information (Continued)
State Attention Register (STAR)
The State Attention Register (STAR) controls the state of the Indicate, Request, and Status/Space Machines. It also records
parity, internal logic, and ABus transaction errors. Each bit may be enabled by setting the corresponding bit in the State Notify
Register.
Access Rules
Address
Read
Write
06h
Always
Conditional
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
ERR
BPE
CPE
CWI
CMDE
SPSTOP
RQSTOP
INSTOP
Bit
Symbol
Description
D0
INSTOP
Indicate Stop: This bit is set by the host to place the Indicate Machine in Stop Mode. This
bit is set by the BSI device when the Indicate state machine detects an internal error,
enters an invalid state, or when the host loads the Indicate Header Length Register with an
illegal value. This bit is set upon reset.
D1
RQSTOP
Request Stop: This bit is set by the host to place the Request Machine in Stop Mode. This
bit is set by the BSI device when the Request Machine detects an internal error or enters
an invalid state. It is also set when an ABus error occurs while storing a Confirmation
Status Message Descriptor (CNF). This bit is set upon reset.
D2
SPSTOP
Status/Space Stop: This bit is set by the host to place the Status/Space Machine in Stop
Mode. This bit is set by the BSI device when the Status/Space Machine has entered
STOP Mode because of an unrecoverable error. In STOP Mode, only PTOP or LMOP
service functions will be performed. This bit is set upon reset.
D3
CMDE
Command Error: Indicates that the host performed an invalid operation. This occurs when
an invalid value is loaded into the Indicate Header Length Register (which also sets the
INSTOP attention). This bit is cleared upon reset.
D4
CWI
Conditional Write Inhibit: Indicates that at least one bit of the previous conditional write
operation was not written. This bit is set unconditionally after each write to a conditional
write register. It is also set when the value of the Compare Register is not equal to the
value of the register that was accessed for a write before it was written. This may indicate
that the accessed register has changed since it was last read. This bit is cleared after a
successful conditional write. CWI bit does not contribute to setting the STA bit of the
Master Attention Register because its associated Notify bit is always 0. This bit is cleared
upon reset.
D5
CPE
Control Bus Parity Error: Indicates a parity error detected on CBD7 – 0. If there is a
Control Bus parity error during a host write, the write is suppressed. Control Bus parity
errors are reported when flow-through parity is enabled (the FLOW bit of the Mode
Register is set). This bit is cleared upon reset.
D6
BPE
BMAC Device Parity Error: Indicates parity error detected on MID7 – 0. BMAC device
parity is always checked during a frame. This bit is cleared upon reset.
D7
ERR
Error: This bit is set by the BSI device when a non-recoverable error occurs. These
include an ABus transaction error while writing confirmation status, an internal logic error,
or when any state machine enters an invalid state. This bit is cleared upon reset.
29
5.0 Control Information (Continued)
State Notify Register (STNR)
The State Notify Register (STNR) is used to enable bits in the State Attention Register (STAR). If a bit in Register STNR is set to
One, the corresponding bit in Register STAR will be applied to the Master Attention Register, which can be used to generate an
interrupt to the host.
All bits in this register are cleared to Zero upon reset.
Access Rules
Address
Read
Write
07h
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
ERRN
BPEN
CPEN
CWIN
CMDEN
SPSTOPN
RQSTOPN
INSTOPN
Bit
Symbol
D0
INSTOPN
Indicate Stop Notify: This bit is used to enable the INSTOP bit in Register STAR.
Description
D1
RQSTOPN
Request Stop Notify: This bit is used to enable the RQSTOP bit in Register STAR.
D2
SPSTOPN
Status/Space Stop Notify: This bit is used to enable the SPSTOP bit in Register STAR.
D3
CMDEN
Command Error Notify: This bit is used to enable the CMDE bit in Register STAR.
D4
CWIN
Conditional Write Inhibit Notify: This bit is used to enable the CWI bit in Register STAR.
D5
CPEN
Control Bus Parity Error Notify: This bit is used to enable the CPE bit in Register STAR.
D6
BPEN
BMAC Device Parity Error Notify: This bit is used to enable the BPE bit in Register STAR.
D7
ERRN
Error Notify: This bit is used to enable the ERR bit in Register STAR.
30
5.0 Control Information (Continued)
Service Attention Register (SAR)
The Service Attention Register (SAR) is used to present the attentions for the service functions. Each bit may be enabled by
setting the corresponding bit in the State Notify Register.
Access Rules
Address
Read
Write
08h
Always
Conditional
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
RES
RES
ABR0
ABR1
LMOP
PTOP
Bit
Symbol
D0
PTOP
Pointer RAM Operation: This bit is cleared by the host to cause the BSI device to transfer
data between a Pointer RAM Register and a mailbox location in memory. The Pointer RAM
Control and Address Register contains the Pointer RAM Register address and determines
the direction of the transfer (read or write). The memory address is in the Mailbox Address
Register. This bit is set by the BSI device after it performs the data transfer.
While PTOP e 0 , the host must not alter the Pointer RAM Address and Control Register
or the Mailbox Address Register.
D1
LMOP
Limit RAM Operation: This bit is cleared by the host to cause the BSI device to transfer
data between a Limit RAM Register and the Limit Data and Limit Address Registers. The
Limit Address Register contains the Pointer RAM Register address and determines the
direction of the transfer (read and write). This bit is set by the BSI device after it data
performs the transfer.
While LMOP e 0, the host must not alter either the Limit Address or Limit Data Registers.
D2
ABR1
Abort Request RCHN1: This bit is cleared by the host to abort a Request on RCHN1. This
bit is set by the BSI device when RQABORT ends a request on RCHN1. The host may
write a 1 to this bit, which may or may not prevent the request from being aborted. When
this bit is cleared by the host, the USR1 bit in the Request Attention Register is set and
further processing on RCHN1 is halted.
D3
ABR0
Abort Request RCHN0: This bit is cleared by the host to abort a Request on RCHN0. This
bit is set by the BSI device when RQABORT ends a request on RCHN0. The host may
write a 1 to this bit, which may or may not prevent the request from being aborted. When
this bit is cleared by the host, the USR0 bit in the Request Attention Register is set and
further processing on RCHN0 is halted.
RES
Reserved
D4 – 7
Description
31
5.0 Control Information (Continued)
Service Notify Register (SNR)
The Service Notify Register (SNR) is used to enable attentions in the Service Attention Register (SAR). If a bit in Register SNR is
set to One, the corresponding bit in Register SAR will be applied to the Master Attention Register, which can be used to
generate an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
09h
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
RES
RES
ABR0N
ABR1N
LMOPN
PTOPN
Bit
Symbol
D0
PTOPN
Pointer RAM Operation Notify: This bit is used to enable the PTOP bit in Register SAR.
D1
LMOPN
Limit RAM Operation Notify: This bit is used to enable the LMOP bit in Register SAR.
D2
ABR1N
Abort Request RCHN1 Notify: This bit is used to enable the ABR1 bit in Register SAR.
D3
ABR0N
Abort Request RCHN0 Notify: This bit is used to enable the ABR0 bit in Register SAR.
RES
Reserved
D4 – 7
Description
32
5.0 Control Information (Continued)
No Space Attention Register (NSAR)
The No Space Attention Register (NSAR) presents the attentions generated when the CNF, PSP, or IDUD Queues run out of
space. The host may set any attention bit to cause an attention for test purposes only, though this should not be done during
normal operation.
The No Data Space attentions are set and cleared by the BSI device automatically. The No Status Space attentions are set by
the BSI device, and must be cleared by the host.
Upon reset this register is set to 0xffh.
Access Rules
Address
Read
Write
0Ah
Always
Conditional
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
NSR0
NSR1
LDI0
NSI0
LDI1
NSI1
LDI2
NSI2
Bit
Symbol
D0
NSI2
No Status Space on ICHN2: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to
the next-to-last available entry in the Indicate Channel’s IDUD Status Queue. When this occurs, the BSI device
stops copying on ICHN2 and the last IDUD is written with special status. This bit (as well as the USR Attention bit)
must be cleared by the host before the BSI device will resume copying on this Channel.
Description
D1
LDI2
Low Data Space on ICHN2: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from
ICHN2’s last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning
is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI
device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in
this space. If SPS fetching was stopped because there were no more PSP entries, fetching will resume
automatically when the PSP Queue Limit Register is updated.
D2
NSI1
No Status Space on ICHN1: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to
the next-to-last available entry in the Indicate Channel’s IDUD Status Queue. When this occurs, the BSI device
stops copying on ICHN1 and the last IDUD is written with special status. This bit (as well as the USR Attention bit)
must be cleared by the host before the BSI device will resume copying on this Channel.
D3
LDI1
Low Data Space on ICHN1: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from
ICHN1’s last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning
is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI
device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in
this space. If PSP fetching was stopped because there were no more PSP entries, fetching will resume
automatically when the PSP Queue Limit Register is updated.
D4
NSI0
No Status Space on ICHN0: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to
the next-to-last available entry in the Indicate Channel’s IDUD Status Queue. When this occurs, the BSI device
stops copying on ICHN0 and the last IDUD is written with special status. This bit (as well as the USR Attention bit)
must be cleared by the host before the BSI device will resume copying on this Channel.
D5
LDI0
Low Data Space on ICHN0: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from
ICHN0’s last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning
is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI
device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in
this space. If PSP fetching was stopped because there were no more PSP entries, fetching will resume
automatically when the PSP Queue Limit Register is updated.
D6
NSR1
No Status Space on RCHN1: This bit is set by the BSI device upon a Reset, or when it has written a CNF
Descriptor to the next-to-last Queue location. Due to internal pipelining, the BSI device may write up to two more
CNFs to the Queue after this attention is generated. Thus the Host must set the CNF Queue Limit Register to be
one less than the available space in the Queue. This bit (as well as the USR attention bit) must be cleared by the
Host before the BSI device will continue to process requests on RCHN1.
D7
NSR0
No Status Space on RCHN0: This bit is set by the BSI device upon a Reset, or when it has written a CNF
Descriptor to the next-to-last Queue location. Due to internal pipelining, the BSI device may write up to two more
CNFs to the Queue after this attention is generated. Thus the Host must set the CNF Queue Limit Register to be
one less than the available space in the Queue. This bit (as well as the USR attention bit) must be cleared by the
Host before the BSI device will continue to process requests on RCHN0.
33
5.0 Control Information (Continued)
No Space Notify Register (NSNR)
The No Space Notify Register (NSNR) is used to enable attentions in the No Space Attention Register (NSAR). If a bit in
Register NSNR is set to One, the corresponding bit in Register NSAR will be applied to the Master Attention Register, which can
be used to generate an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
0Bh
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
NSR0N
NSR1N
LDI0N
NSI0N
LDI1N
NSI1N
LDI2N
NSI2N
Bit
Symbol
D0
NSI2N
No Status Space on ICHN2 Notify: This bit is used to enable the NSI2 in Register NSAR.
Description
D1
LDI2N
Low Data Space on ICHN2 Notify: This bit is used to enable the LDI2 in Register NSAR.
D2
NSI1N
No Status Space on ICHN1 Notify: This bit is used to enable the NSI1 in Register NSAR.
D3
LDI1N
Low Data Space on ICHN1 Notify: This bit is used to enable the LDI1 in Register NSAR.
D4
NSI0N
No Status Space on ICHN0 Notify: This bit is used to enable the NSI0 in Register NSAR.
D5
LDI0N
Low Data Space on ICHN0 Notify: This bit is used to enable the LDIO in Register NSAR.
D6
NSR1N
No Status Space on RCHN1 Notify: This bit is used to enable the NSR1 in Register NSAR.
D7
NSR0N
No Status Space on RCHN0 Notify: This bit is used to enable the NSR0 in Register NSAR.
34
5.0 Control Information (Continued)
Limit Address Register (LAR)
The Limit Address Register (LAR) is used to program the parameters for a LMOP (Limit RAM Operation) service function.
This register is not altered upon reset.
Access Rules
Address
Read
Write
0Ch
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
LRA3
LRA2
LRA1
LRA0
LMRW
RES
RES
LRD8
Bit
Symbol
D0
LRD8
Limit RAM Data Bit 8: This bit contains the most-significant data bit read or written from
the addressed Limit RAM Register.
D1 – 2
RES
Reserved
LMRW
LMOP Read/Write: This bit determines whether a LMOP service function will be a read
(LMRW e 1) or write (LMRW e 0).
LRA0– 3
Limit RAM Register Address: Used to program the Limit RAM Register address for a
subsequent LMOP service function.
D3
D4 – 7
Description
35
5.0 Control Information (Continued)
Limit Data Register (LDR)
The Limit Data Register (LDR) is used to contain the 8 least-significant Limit RAM data bits transferred in a LMOP service
function. (The most-significant data bit is in the Limit Address register.)
This register is not altered upon reset.
Access Rules
Address
Read
Write
0Dh
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
LRD7
LRD6
LRD5
LRD4
LRD3
LRD2
LRD1
LRD0
Bit
Symbol
D0 – 7
LRD0– 7
Description
Limit RAM Data Bits 0– 7: These bits contain the least-significant data bits read from or
written to a Limit RAM Register in a LMOP service function.
36
5.0 Control Information (Continued)
Request Attention Register (RAR)
The Request Attention Register (RAR) is used to present exception, breakpoint, request complete, and unserviceable request
attentions generated by each Request Channel. Each bit may be enabled by setting the corresponding bit in the Request Notify
Register.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
0Eh
Always
Conditional
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
USRR0
RCMR0
EXCR0
BRKR0
USRR1
RCMR1
EXCR1
BRKR1
Bit
Symbol
D0
BRKR1
Breakpoint on RCHN1: Is set by the BSI device when a CNF Descriptor is written on
RCHN1. No action is taken by the BSI device if the host sets this bit.
Description
D1
EXCR1
Exception on RCHN1: Is set by the BSI device when an exception occurs on RCHN1. No
action is taken by the BSI device if the host sets this bit.
D2
RCMR1
Request Complete on RCHN1: Is set by the BSI device when it has completed
processing a Request object on RCHN1, an error occurs, or a completion exception
occurs. No action is taken if the Host sets this bit.
D3
USRR1
Unserviceable Request on RCHN1: Is set by the BSI device when a Request cannot be
processed on RCHN1. This occurs when the Request Class is inappropriate for the current
ring state, or when there is no CNF status space, or when the host aborts a request by
clearing the ABR bit in the Service Attention Register. While this bit is set, no requests will
be processed on RCHN1. The host must clear this bit to resume request processing.
D4
BRKR0
Breakpoint on RCHN0: Is set by the BSI device when a CNF Descriptor is written on
RCHN0. No action is taken by the BSI device if the host sets this bit.
D5
EXCR0
Exception on RCHN0: Is set by the BSI device when an exception occurs on RCHN0. No
action is taken by the BSI device if the host sets this bit.
D6
RCMR0
Request Complete on RCHN0: Is set by the BSI device when it has completed
processing a Request object on RCHN0, an error occurs, or a completion exception
occurs. No action is taken if the Host sets this bit.
D7
USRR0
Unserviceable Request on RCHN0: Is set by the BSI device when a Request cannot be
processed on RCHN0. This occurs when the Request Class is inappropriate for the current
ring state, or when there is no CNF status space, or when the host aborts a request by
clearing the ABR bit in the Service Attention Register. While this bit is set, no requests will
be processed on RCHN0. The host must clear this bit to resume request processing.
37
5.0 Control Information (Continued)
Request Notify Register (RNR)
The Request Notify Register (RNR) is used to enable attentions in the Request Attention Register (RAR). If a bit in Register
RNR is set to One, the corresponding bit in Register RAR will be applied to the Master Attention Register, which can be used to
generate an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
0Fh
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
USRR0N
RCMR0N
EXCR0N
BRKR0N
USRR1N
RCMR1N
EXCR1N
BRKR1N
Bit
Symbol
D0
BRKR1N
Breakpoint on RCHN1 Notify: This bit is used to enable the BRKR1 bit in Register RAR.
Description
D1
EXCR1N
Exception on RCHN1 Notify: This bit is used to enable the EXCR1 bit in Register RAR.
D2
RCMR1N
Request Complete on RCHN1 Notify: This bit is used to enable the RCMR1 bit in
Register RAR.
D3
USRR1N
Unserviceable Request on RCHN1 Notify: This bit is used to enable the USRR1 bit in
Register RAR.
D4
BRKR0N
Breakpoint on RCHN0 Notify: This bit is used to enable the BRKR0 bit in Register RAR.
D5
EXCR0N
Exception on RCHN0 Notify: This bit is used to enable the EXCR0 bit in Register RAR.
D6
RCMR0N
Request Complete on RCHN0 Notify: This bit is used to enable the RCMR0 bit in
Register RAR.
D7
USRR0N
Unserviceable Request on RCHN0 Notify: This bit is used to enable the USRR0 bit in
Register RAR.
38
5.0 Control Information (Continued)
Request Channel 0 and 1 Configuration Registers (R0CR and R1CR)
The two Request Configuration Registers (R0CR and R1CR) are programmed with the operational parameters for each of the
Request Channels. These registers may only be altered between Requests, i.e., while the particular Request Channel does not
have a Request loaded.
These registers are not altered upon reset.
Access Rules
Address
Read
Write
10-11h
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
TT1
TT0
PRE
HLD
FCT
SAT
VST
FCS
Bit
Symbol
D0
FCS
Frame Check Sequence Disable: When this bit is set, the BSI device asserts the FCST
signal throughout the request. This may drive the BMAC device FCST pin, or also the SAT
or SAIGT pins, depending on the application. This bit is normally used to program the
BMAC device not to concatenate its generated FCS to the transmitted frame. The Valid
FCS bit in the Expected Frame Status Register independently determines whether a frame
needs a valid FCS to meet the matching frame criteria.
Description
D1
VST
Void Stripping: When this bit is set, the BSI device asserts the STRIP output signal out
throughout the request. This may drive the BMAC device STRIP (Void Strip) pin, or also
the SAT pin, depending on the application.
D2
SAT
Source Address Transparency: When this bit is set, the BSI device asserts the SAT
output signal throughout the request. This may drive the BMAC device’s SAT and/or
SAIGT pins, depending on the application. When SAT is set, Full Confirmation requires the
use of the EM (External SA Match) signal.
D3
FCT
Frame Control Transparency: When this bit is set, the FC will be sourced from the ODU
(not the REQ.First Descriptor). When Full Confirmation is enabled and FCT e 0, all bits of
the FC in returning frames must match the FC field in the REQ Descriptor; if FCT e 1, only
the C, L and r bits must match.
Note that since the BSI device decodes the REQ.F Descriptor FC field to determine
whether to assert RQCLM/RQBCN, FC transparency may be used to send Beacons or
Claims in any ring non-operational state, as long as the FC in the REQ Descriptor is not set
to Beacon or Claim. By programming a Beacon or Claim FC in the REQ Descriptor, then
using FC transparency, any type of frame may be transmitted in the Beacon or Claim state.
D4
HLD
Hold: When this bit is set, the BSI device will not end a service opportunity until the
Request is complete. When this bit is Zero, the BSI device ends the service opportunity on
the Request Channel when all of the following conditions are met:
1. There is no valid request active on the Request Channel.
2. The service class is non-immediate.
3. There is no data in the FIFO.
4. There is no valid REQ fetched by the BSI device.
This bit also affects Prestaging on RCHN1 (Request Channel 1). When HLD e 0,
prestaging is enabled on RCHN1, regardless of the state of the PRE bit (except for
Immediate service classes). When HLD e 1, prestaging is determined by the PRE bit. This
option can potentially waste ring bandwidth, but may be required (particularly on RCHN0,
Request Channel 0) if a small guaranteed service time is required.
When using the Repeat option, HLD is required for small frames. If HLD is not used, the
other Request Channel will be checked for service before releasing the token between
frames. This may not be the desired action, particularly if there is a request on RCHN1 that
needs servicing after the completion of RCHN0’s Repeated Request.
39
5.0 Control Information (Continued)
Request Channel 0 and 1 Configuration Registers (R0CR and R1CR) (Continued)
Symbol
Bit
Description
D5
PRE
Preempt/Prestage: When this bit is set, preemption is enabled for RCHN0, and prestaging is enabled for
RCHN1 (prestaging is always enabled for RCHN0). When this bit Zero, preemption is disabled and prestaging is
enabled only on RCHN0.
When preemption is enabled, RCHN0 preempts a (non-committed) frame of RCHN1 already in the FIFO,
causing it to be purged and refetched after RCHN0’s request has been serviced. When the Request Machine is
servicing a request on RCHN1 and a request on RCHN0 becomes active, if preemption is enabled on RCHN0,
the Request Machine will finish transmitting the current frame on RCHN1, then release the token and move
back to the start state. This has the effect of reprioritizing the Request Channels, thus ensuring that frames on
RCHN0 are transmitted at the next service opportunity. When RCHN0 has been serviced, transmission will
continue on RCHN1 with no loss of data.
When prestaging is enabled, the next frame for RCHN1 is staged (ODUs are loaded into the FIFO before the
token arrives). If prestaging is not enabled, the Request Machine waits until the token is captured before
staging the first frame. Once the token is captured, the Request Machine begins fetching data, and when the
FIFO threshold has been reached, transmits the data on that Request Channel. For requests with an Immediate
service class, prestaging is not applicable.
When this bit is Zero, preemption is disabled for RCHN0, and requests on RCHN1 will not be prestaged unless
the HLD bit is Zero, in which case RCHN1 will prestage data regardless of the setting of the PRE bit.
Note that when prestaging is not enabled on RCHN1, data is not staged until the token is captured. Since there
is no data in the FIFO (if there is no active request on RCHN0), the BSI device will immediately release the
token if the HLD option is not set.
D6 – 7
TT0 – 1
Transmit Threshold: Determines the threshold on the output data FIFO before the BSI device requests
transmission.
TT1
TT0
Threshold Value
0
0
8 Words
0
1
16 Words
1
0
Reserved
1
1
Reserved
40
5.0 Control Information (Continued)
Request Channel 0 and 1 Expected Frame Status Registers (R0EFSR and R1EFSR)
The Expected Frame Status Registers (R0EFSR and R1EFSR) define the matching criteria used for Full Confirmation of
returning frames on each Request Channel. A returning frame must meet the programmed criteria to be counted as a matching
frame.
These registers are not altered upon reset.
Access Rules
Address
Read
Write
12–13h
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
VDL
VFCS
EE1
EE0
EA1
EA0
EC1
EC0
Bit
Symbol
D0 – 1
EC0– 1
D2 – 3
D4 – 5
EA0– 1
EE0 – 1
Description
Expected C Indicator:
EC1
EC0
0
0
0
1
1
0
1
1
Value
Any
R
S
R or S
Expected A Indicator:
EA1
EA0
0
0
0
1
1
0
1
1
Value
Any
R
S
R or S
Expected E Indicator:
EE1
EE0
0
0
0
1
1
0
1
1
Value
Any
R
S
R or S
D6
VFCS
Valid FCS: When this bit is set, returning frames must have a valid FCS field to meet the confirmation criteria.
D7
VDL
Valid Data Length: When this bit is set, returning frames must have a valid VDL field to meet the confirmation
criteria.
41
5.0 Control Information (Continued)
Indicate Attention Register (IAR)
The Indicate Attention Register (IAR) is used to present exception and breakpoint attentions generated by each Indicate
Channel. An Attention bit is set by hardware when an exception or breakpoint occurs on the corresponding Indicate Channel.
Each bit may be enabled by setting the corresponding bit in the Indicate Notify Register.
Access Rules
Address
Read
Write
14h
Always
Conditional
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
EXCI0
BRKI0
EXCI1
BRKI1
EXCI2
BRKI2
Bit
Symbol
D0
BRKI2
Breakpoint on ICHN2: Is set when a breakpoint is detected on Indicate Channel 2. No
action is taken if the host sets this bit.
D1
EXCI2
Exception on ICHN2: Is set by the BSI device when an exception occurs on Indicate
Channel 2. May be set by the host to disable copying on ICHN2, which is convenient when
updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,
copying is disabled on ICHN2.
D2
BRKI1
Breakpoint on ICHN1: Is set when a breakpoint is detected on Indicate Channel 1. No
action is taken if the host sets this bit.
D3
EXCI1
Exception on ICHN1: Is set by the BSI device when an exception occurs on Indicate
Channel 1. May be set by the host to disable copying on ICHN1, which is convenient when
updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,
copying is disabled on ICHN1.
D4
BRKI0
Breakpoint on ICHN0: Is set when a breakpoint is detected on ICHN0. No action is taken
if the host sets this bit.
D5
EXCIO
Exception on ICHN0: Is set by the BSI device when an exception occurs on Indicate
Channel 0. May be set by the host to disable copying on ICHN0, which is convenient when
updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,
copying is disabled on ICHN0.
RES
Reserved
D6 – 7
Description
42
5.0 Control Information (Continued)
Indicate Notify Register (INR)
The Indicate Notify Register (INR) is used to enable attentions in the Indicate Attention Register (IAR). If a bit in Register INR is
set to One, the corresponding bit in Register IAR will be applied to the Master Attention Register, which can be used to generate
an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
15h
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
EXC0N
BRK0N
EXC1N
BRK1N
EXC2N
BRK2N
Bit
D0
Symbol
Description
BRK2N
Breakpoint on ICHN2 Notify: This bit is used to enable the BRK2 bit in Register IAR.
D1
EXC2N
Exception on ICHN2 Notify: This bit is used to enable the EXC2 bit in Register IAR.
D2
BRK1N
Breakpoint on ICHN1 Notify: This bit is used to enable the BRK1 bit in Register IAR.
D3
EXC1N
Exception on ICHN1 Notify: This bit is used to enable the EXC1 bit in Register IAR.
D4
BRK0N
Breakpoint on ICHN0 Notify: This bit is used to enable the BRK0 bit in Register IAR.
D5
EXC0N
Exception on ICHN0 Notify: This bit is used to enable the EXC0 bit in Register IAR.
D6 – 7
RES
Reserved
43
5.0 Control Information (Continued)
Indicate Threshold Register (ITR)
The Indicate Threshold Register (ITR) specifies the maximum number of frames that can be received on Indicate Channel 1 or
Indicate Channel 2 before an attention will be generated. This register may be written only when the INSTOP bit in the State
Attention Register is set, or when the Indicate Channel’s corresponding EXC bit in the Indicate Attention Register is set.
This register is not altered upon reset.
Access Rules
Address
Read
Write
16h
Always
INSTOP Mode or EXC e 1 Only
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
THR7
THR6
THR5
THR4
THR3
THR2
THR1
THR0
Bit
Symbol
Description
D0 – 7
THR0 – 7
Threshold Data Bits 0– 7: The value programmed in this register is loaded into an internal
counter every time the Indicate Channel changes. Each valid frame copied on the current
Channel decrements the counter. When the counter reaches Zero, a status breakpoint
attention is generated (i.e., the Channel’s BRK bit in the Indicate Attention Register is set)
if the Channel’s Breakpoint on Threshold (BOT) bit in the Indicate Mode Register is set.
Loading the Indicate Threshold Register with Zero generates a breakpoint after 256
consecutive frames are received on any one Indicate Channel.
44
5.0 Control Information (Continued)
Indicate Mode Register (IMR)
The Indicate Mode Register (IMR) defines configuration options for all three Indicate Channels, including the sort mode, frame
filtering, and status breakpoints.
This register may be written only when the INSTOP bit in the State Attention Register is set. It may be written with its current
value any time, which is useful for one-shot sampling.
This register is not altered upon reset.
Access Rules
Address
Read
Write
17h
Always
INSTOP Mode Only
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
SM1
SM0
SKIP
RES
BOT1
BOT2
BOB
BOS
Bit
Symbol
D0
BOS
Breakpoint on Service Opportunity: Enables the end of a service opportunity to
generate an Indicate breakpoint attention (i.e., set the Channel’s BRK bit in the Indicate
Attention Register). Service opportunities include receipt of a Token, a MAC Frame, or a
ring operational change following some copied frames.
Description
D1
BOB
Breakpoint on Burst: Enables the end of a burst to generate an Indicate breakpoint
attention (i.e., set the Channel’s BRK bit in the Indicate Attention Register). End of burst
includes Channel change, DA change, SA change, or MAC INFO change. A Channel
change is detected from the FC field of valid, copied frames. A DA change is detected
when a frame’s DA field changes from our address to any other. A SA change is detected
when a frame’s SA field is not the same as the previous one. A MAC INFO breakpoint
occurs when a MAC frame does not have the identical first four bytes of INFO as the
previous frame. This breakpoint always sets the BRK bit (i.e., this breakpoint is always
enabled).
D2
BOT2
Breakpoint on Threshold for ICHN2: Enables the value in the Indicate Threshold
Register to be used to generate an Indicate breakpoint attention on Indicate Channel 2,
(i.e., set the BRK2 bit in the Indicate Attention Register).
D3
BOT1
Breakpoint on Threshold for ICHN1: Enables the value in the Indicate Threshold
Register to be used to generate an Indicate breakpoint attention on ICHN1, (i.e., set the
BRK1 bit in the Indicate Attention Register.
D4
RES
Reserved
D5
SKIP
Skip Enable: Enables filtering on Indicate Channel 0 when the Copy Control field for
ICHN0 in the Indicate Configuration Register is set to 01 or 10. When this bit is set, only
the unique MAC and SMT frames received on Indicate Channel 0 will be copied to
memory, i.e., those having an FC field or first four bytes of the Information field that differs
from the previous frame.
A write to the Indicate Mode Register disables filtering.
45
5.0 Control Information (Continued)
Indicate Mode Register (IMR) (Continued)
Bit
Symbol
Description
SM0 – 1
D6 – 7
Sort Mode: These bits determine how the BSI device sorts Indicate data onto Indicate Channels 1 and 2.
(Indicate Channel 0 always receives SMT and MAC frames.)
SM1
SM0
ICHN2
ICHN1
0
0
Asynchronous
Synchronous
0
1
External
Internal
1
0
Info
Header
1
1
Low Priority
High Priority
The Synchronous/Asynchronous Sort Mode is intended for use in end-stations or applications using
synchronous transmission.
The Internal/External Sorting Mode is intended for bridging or monitoring applications. MAC/SMT frames
matching the internal (BMAC device) address are sorted onto ICHN0, and all other frames matching the
BMAC device’s internal address (short or long) are sorted onto ICHN1. All frames matching the external
address (frames requiring bridging) are sorted onto ICHN2 (including MAC/SMT). This sorting mode
utilizes the EM, EA, and ECIP input signals with external address matching circuitry. External address
circuitry must assert ECIP sometime from the assertion of FCRCVD up to the clock before the assertion of
INFORCVD. Otherwise, the BSI device assumes no external address comparison is taking place. ECIP
must be negated before EDRCVD; if not, the frame is not copied. EA and EM are sampled on the clock
after ECIP is negated. ECIP is ignored after it is negated, until FCRCVD is asserted again. To confirm
transmitted frames in this mode (typically using SAT), EM must be asserted within the same time frame as
EA. Note that internal matches have precedence over external matches.
The Header/Info Sort Mode is intended for high performance protocol processing. MAC/SMT frames are
sorted onto ICHN0, while all other frames are sorted onto ICHN1 and ICHN2. Frame bytes from the FC up
to the programmed header length are copied onto ICHN1. The remaining bytes (info) are copied onto
ICHN2. Only one stream of IDUDs is produced (on ICHN1), but both Indicate Channel’s PSP queues are
used for space (i.e., PSPs from ICHN1 for header space, and PSPs from ICHN2 for info space). Frames
may comprise a header only, or a header a info. For frames with info, multi-part IDUD objects are
produced. For multi-part IDUDs, the Indicate Status field in the IDUD is used to determine which part of
the IDUD object points to the end of the header. The remainder of the IDUD object points to the Info.
For example, if page crosses occur while writing the header and while writing out the Info, the BSI Device
will generate a four part IDUD object (IDUD.First, IDUD.Middle, IDUD.Middle, IDUD.Last). The IDUD.First
will have a status of ‘‘page cross’’. The first IDUD.Middle will have a status of ‘‘end of header’’. The next
IDUD.Middle will have a status of ‘‘page boundary crossed’’. The IDUD.Last will have an ‘‘end of frame’’
status.
The High Priority/Low Priority Sort Mode is intended for end stations using two priority levels of
asynchronous transmission. The priority is determined by the most-significant z-bit of the FC
(zzz e 0xx e low-priority; zzz e 1xx e high-priority).
46
5.0 Control Information (Continued)
Indicate Configuration Register (ICR)
The Indicate Configuration Register (ICR) is used to program the copy criteria for each of the Indicate Channels.
This register is not altered upon reset.
Access Rules
Address
Read
Write
18h
Always
Always
Register Bits
D7
D6
CC0
Bit
D0 – 1
D5
D4
RES
D3
CC1
Symbol
CC2
D2
RES
D1
D0
CC2
Description
Copy Control ICHN2:
CC1
CC0
0
0
0
1
1
0
1
1
D2
RES
Reserved
D3 – 4
CC1
Copy Control ICHN1:
CC4
CC3
0
0
0
1
1
0
1
1
D5
RES
Reserved
D6 – 7
CC0
Copy Control ICHN0:
CC7
CC6
0
0
0
1
1
0
1
1
47
Copy Mode
Do Not Copy
Copy if (AFLAG l ( E ECIP & EA)) & E MFLAG
Copy if (AFLAG l ( E ECIP & EA)) l MFLAG
Copy Promiscously.
Copy Mode
Do Not Copy
Copy if (AFLAG l ( E ECIP & EA)) & E MFLAG
Copy if (AFLAG l ( E ECIP & EA)) l MFLAG
Copy Promiscuously.
Copy Mode
Do Not Copy
Copy if (AFLAG l ( E ECIP & EA)) & E MFLAG
Copy if (AFLAG l ( E ECIP & EA)) l MFLAG
Copy Promiscuously.
5.0 Control Information (Continued)
Indicate Header Length Register (IHLR)
The Indicate Header Length Register (IHLR) defines the length (in words) of the frame header, for use with the Header/Info Sort
Mode.
The Indicate Header Length Register must be initialized before setting the Sort Mode to Header/Info. This register may be
changed while the INSTOP bit in the State Attention Register or the EXC bit in the Indicate Attention Register is set.
This register is not altered upon reset.
Access Rules
Address
Read
Write
19h
Always
INSTOP Mode or EXC e 1 Only
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
HL7
HL6
HL5
HL4
HL3
HL2
HL1
HL0
Bit
Symbol
D0 – 7
HL0– 7
Description
Header Length: Specifies the length (in words) of the frame header, for use with the
Header/Info Sort Mode. The frame FC is written as a separate word, and thus counts as
one word. For example, to split after four bytes of header data in a frame with long
addresses, this register is programmed with the value 05 (1 word FC, 1.5 DA, 1.5 SA,
1 HDRÐDATA). IHLR must not be loaded with a value less than 4. If it is, the BSI device
sets the Command Error (CMDE) and Indicate Stop (INSTOP) attentions.
48
5.0 Control Information (Continued)
Compare Register (CMP)
The Compare Register (CMP) is used in comparison with a write access of a conditional write register. The Compare Register is
loaded on a read of any of the conditional event Attention Registers or by directly writing to it.
All bits in this register are set to Zero upon reset.
Access Rules
Address
Read
Write
1Fh
Always
Always
Register Bits
D7
D6
D5
D4
D3
D2
D1
D0
CMP7
CMP6
CMP5
CMP4
CMP3
CMP2
CMP1
CMP0
Bit
Symbol
D0 – 7
CMP0– 7
Description
Compare: These bits are compared to bits D0 – 7 of the accessed register, and only the
bits in the Attention Register that have the same current value as the corresponding bit in
the Compare register will be updated with the new value.
49
5.0 Control Information (Continued)
Descriptors include the following:
5.4 POINTER RAM REGISTERS
Pointer RAM Registers contain pointers to all data and Descriptors manipulated by the BSI device, namely, Input and
Output Data Units, Input and Output Data Unit Descriptors,
Request Descriptors, Confirmation Messages, and Pool
Space Descriptors. Pointer RAM Registers are shown in Table 5-4.
# Input Data Unit Descriptors (IDUDs) specify the location, size, part, and status information for Input Data
Units.
# Output Data Unit Descriptors (ODUDs) specify the location and size of Output Data Units. For multi-ODUD
frames, they also specify which part of the frame is pointed to by the ODUD.
5.5 LIMIT RAM REGISTERS
The Limit RAM Registers are used by both the Indicate and
Request machines. Limit RAM Registers contain data values that define the limits of the ten queues maintained by
the BSI device. Limit RAM Registers are shown in Table
5-5.
# Pool Space Descriptors (PSPs) describe the location
and size of a region of memory space available for writing Indicate data.
# Request Descriptors (REQs) describe the location of a
stream of Output Data Unit Descriptors and contain operational parameters
5.6 DESCRIPTORS
Descriptors are used to observe and control the operation
of the BSI device. They contain address, status, and control
information about Indicate and Request operations. Descriptors are stored in lists and wrap-around queues in
memory external to the BSI device and accessed via the
ABus.
# Confirmation Status Messages (CNFs) describe the result of a Request operation.
5.7 OPERATING RULES
Multi-Byte Register Ordering
When referring to multi-byte fields, byte 0 is always the most
significant byte. When referring to bits within a byte, bit 7 is
the most significant bit and bit 0 is the least significant bit.
When referring to the contents of a byte, the most significant bit is always referred to first.
50
5.0 Control Information (Continued)
TABLE 5-4. Pointer RAM Registers
Group
P
O
I
N
T
E
R
R
A
M
Address
Register Name
Access Rules
Read
Write
00
ODU Pointer RCHN1 (OPR1)
Always
Always
01
ODUD List Pointer RCHN1 (OLPR1)
Always
Always
02
CNF Queue Pointer RCHN1 (CQPR1)
Always
Always
03
REQ Queue Pointer RCHN1 (RQPR1)
Always
Always
04
ODU Pointer RCHN0 (OPR0)
Always
Always
05
ODUD List Pointer RCHN0 (OLPR0)
Always
Always
06
CNF Queue Pointer RCHN0 (CQPR0)
Always
Always
07
REQ Queue Pointer RCHN0 (RQPR0)
Always
Always
08
IDU Pointer ICHN2 (IPI2)
Always
Always
09
IDUD Queue Pointer ICHN2 (IQPI2)
Always
Always
0A
PSP Queue Pointer ICHN2 (PQPI2)
Always
Always
0B
Next PSP ICHN2 (NPI2)
Always
Always
0C
IDU Pointer ICHN1 (IPI1)
Always
Always
0D
IDUD Queue Pointer ICHN1 (IPQI1)
Always
Always
0E
PSP Queue Pointer ICHN1 (PQPI1)
Always
Always
0F
Next PSP ICHN1 (NPI1)
Always
Always
10
IDU Pointer ICHN0 (IPI0)
Always
Always
11
IDUD Queue Pointer ICHN0 (IQPI0)
Always
Always
12
PSP Queue Pointer ICHN0 (PQPI0)
Always
Always
13
Next PSP ICHN0 (NPI0)
Always
Always
14
IDUD Shadow Register (ISR)
Always
Always
15
ODUD Shadow Register (OSR)
Always
Always
161F
Reserved
N/A
N/A
TABLE 5-5. Limit RAM Registers
Group
L
I
M
I
T
R
A
M
Address
Register Name
Access Rules
Read
Write
0
REQ Queue Limit RCHN1 (RQLR1)
Always
Always
1
CNF Queue Limit RCHN1 (CQLR1)
Always
Always
2
REQ Queue Limit RCHN0 (RQLR0)
Always
Always
3
CNF Queue Limit RCHN0 (CQLR0)
Always
Always
4
IDUD Queue Limit ICHN2 (IQLI2)
Always
Always
5
PSP Queue Limit ICHN2 (PQLI2)
Always
Always
6
IDUD Queue Limit ICHN1 (IQLI1)
Always
Always
7
PSP Queue Limit ICHN1 (PQLI1)
Always
Always
8
IDUD Queue Limit ICHN0 (IQLI0)
Always
Always
9
PSP Queue Limit ICHN0 (PQLI0)
Always
Always
N/A
N/A
A–F
Reserved
51
5.0 Control Information (Continued)
PSP Queue Pointer Register: Points to the next available
PSP. Initialized by the host with the start address of the PSP
Queue, after the Queue has been initialized with valid PSP
Descriptors. As each PSP is read from memory, this register
is loaded with the address in the Next PSP Register.
Next PSP Register: Written by the BSI device with the PSP
fetched from the PSP Queue.
Indicate Shadow Register: Written by the BSI device with
the start address of the last IDU copied to memory.
Request Shadow Register: Written by the BSI device with
the address of the current ODUD.
See Table 5-4 for Summary including address and access
rules.
5.8 POINTER RAM REGISTER DESCRIPTIONS
The Pointer RAM Register set contains 32, 28-bit registers.
Registers 23 through 31 are reserved, and user access of
these locations produces undefined results.
Pointer RAM Registers are read and written by the host
using the Pointer RAM Operation (PTOP) service function
and are accessed directly by BSI device hardware during
Indicate and Request operations.
During Indicate and Request operations, Pointer RAM registers are used as addresses for ABus accesses of data and
Descriptors, i.e., the subchannel addresses for loads
(reads) of streams of PSPs, ODUs, ODUDs, and REQs, and
for stores (writes) of streams of IDUs, IDUDs, and CNFs.
Pointer RAM Registers include the following:
ODU Pointer: Contains the address of an Output Data Unit.
During Request operations, this register is loaded by the BSI
device from the Location Field of its Output Data Unit Descriptor.
ODUD List Pointer: Loaded by the BSI device from the
Location Field of the REQ Descriptor when it is read from
memory. The address is incremented by the BSI device as
each ODUD is fetched from memory.
CNF Queue Pointer: Contains the current CNF Status
Queue address. This register is written by the user after he
has allocated space for the CNF Queue. During Request
operations, this register is incremented by the BSI device
after each CNF is written to the CNF Queue.
REQ Queue Pointer: Initialized by the host with the start
address of the REQ Descriptor Queue after the Queue has
been initialized. During Request operations, the address is
incremented by the BSI device as each REQ is fetched.
IDU Pointer: Written by the BSI device with the Location
Field of the PSP Descriptor when it is read from memory.
IDUD Queue Pointer: Points to the Queue location where
IDUDs will be stored. Written by the user after he has allocated space for the IDUD Status Queue. Incremented by
the BSI device as IDUDs are written to consecutive locations in the Queue.
5.9 LIMIT RAM REGISTER DESCRIPTIONS
The Limit RAM Register set contains 16, 9-bit registers.
Registers 11 through 15 are reserved, and used access of
these locations produces undefined results.
The Limit RAM registers contain data values that define the
limits of each of the ten queues maintained by the BSI device.
Limit RAM Registers are read and written by the host using
the Limit RAM Operation (LMOP) service function when the
Status/Space Machine is in STOP Mode, and are read directly by BSI device hardware during Indicate and Request
operations.
Limit RAM Registers include the following:
REQ Queue Limit: Defines the last valid REQ written by the
host.
CNF Queue Limit Register: Defines the last Queue location where a CNF may be written by the BSI device. Due to
pipelining, the BSI device may write up to two CNFs after it
detects a write to the next-to-last CNF entry (and generates
a No Status Space Attention). For this reason, the host must
always define the CNF queue limit to be one Descriptor less
than the available space.
IDUD Queue Limit Register: Defines the last Queue location where an IDUD may be written by the BSI device.
PSP Queue Limit: Defines the last valid PSP written by the
host.
See Table 5-5 for Summary including address and access
rules.
52
5.0 Control Information (Continued)
5.10 BSI DEVICE DESCRIPTORS
Input Data Unit Descriptor (IDUD)
Input Data Unit Descriptors (IDUDs) are generated on Indicate Channels to describe where the BSI device wrote each frame
part and to report status for the frame.
For multi-part IDUDs, intermediate status is written in each IDUD, and when a status event occurs, definitive status is written in
the last IDUD.
A detailed description of the encodings of the Indicate Status bits is given in Table 5-6.
31
30
29
28
27
IS
F–L
24
23
FRA
16
FRS
15
14
VC
RES
13
12
RES
LOC
0
CNT
Word 0
Word 1
Word 0
Bit
Symbol
Description
D0–12
CNT
Byte Count: Number of bytes in the SDU.
D13–14
RES
Reserved
VC
VCOPY: Reflects the state of the VCOPY signal sent to the BMAC device for this
frame.
0: VCOPY was negated.
1: VCOPY was asserted.
FRS
Frame Status: This field is valid only for Full Confirmation, and if the frame ended
with an ED.
D16– 17
C
C Indicator:
00: none
01: R
10: S
11: T
D18– 19
A
A Indicator:
00: none
01: R
10: S
11: T
D20– 21
E
E Indicator:
00: none
01: R
10: S
11: T
D22
VFCS
Valid FCS:
0: FCS field was invalid
1: FCS field was valid
D23
VDL
Valid Data Length:
0: Data length was invalid
1: Data length was valid
D15
D16–23
53
5.0 Control Information (Continued)
5.10 BSI DEVICE DESCRIPTORS (Continued)
Input Data Unit Descriptor (IDUD) (Continued)
Word 0 (Continued)
Bit
Symbol
D24 – 27
Description
FRA
Frame Attributes
D2425
TC
Termination Condition: This field is valid only for Full Confirmation.
00: Other (e.g., MAC Reset/token).
01: ED.
10: Format error.
11: Frame stripped.
D26
AFLAG
AFLAG: Reflects the state of the AFLAG input signal, which is sampled by the BSI device at
INFORCVD.This field is valid only for Full Confirmation.
0: External DA match.
1: Internal DA match.
D27
MFLAG
MFLAG: Reflects the state of the MFLG input signal, which is sampled by the BSI device at INFORCVD.
This field is valid only for Full Confirmation.
0: Frame sent by another station.
1: Frame sent by this station.
IS
Indicate Status: The values in this field are prioritized, with the highest number having the highest
priority. A detailed description of the encodings is given in Table 5-6.
IS3
IS2 IS1 IS0 Meaning
Non-end Frame Status
0
0
0
0
Last IDU of queue, page-cross.
0
0
0
1
Page boundary crossed.
0
0
1
0
End of header.
0
0
1
1
Page-cross with header-end.
Normal-end Frame Status
0
1
0
0
Intermediate (no breakpoints).
0
1
0
1
Burst boundary.
0
1
1
0
Threshold.
0
1
1
1
Service opportunity.
Copy Abort due to No Space
1
0
0
0
No data space.
1
0
0
1
No header space.
1
0
1
0
Good header, info not copied.
1
0
1
1
Not enough info space.
Error
1
1
0
0
FIFO overrun.
1
1
0
1
Bad frame (no VDL or no VFCS).
1
1
1
0
Parity error.
1
1
1
1
Internal error.
D28 – 31
Word 1
Bit
Symbol
Description
D0 – 27
LOC
Location: 28-bit memory address of the start of an IDU. For the first IDU of a frame, the address is of
the fourth FC byte of the burst-aligned frame (i.e., bits [1:0] e 11). For subsequent IDUs, the address
is of the first byte of the IDU (i.e, bits [1:0] e 00).
D28 – 29
RES
Reserved
D30 – 31
F–L
First/Last Tag: Identifies the IDU object part, i.e., Only, First, Middle, or Last.
54
5.0 Control Information (Continued)
TABLE 5-6. Indicate Status Field (IS) of IDU Descriptor
NON-END FRAME STATUS
[0000]
Last IDUD of Queue, with a Page Cross: The last available location of the ICHN’s IDUD queue was written. Since there
was a page cross, there was more data to be written. Since there was no more IDUD space, the remaining data was not
written. Note that this code will not be written in a IDU.Middle, so that a Zero IS field with Zero F – L tags can be utilized by
software as a null descriptor.
[0001]
Page Cross: Must be an IDUD.FIRST or IDUD.MIDDLE. This is part of a frame that filled up the remainder of the current
page, requiring a new page for the remainder of the data.
[0010]
Header End: This refers to the last IDU of the header portion of a frame.
[0011]
Page Cross and Header End: The occurrence of a page cross and header end.
NORMAL-END FRAME STATUS
[0100]
Intermediate: A frame ended normally, and there was no breakpoint.
[0101]
Burst Boundary: A frame ended normally, and there was a breakpoint because a burst boundary was detected.
[0110]
Threshold: The copied frame threshold counter was reached when this frame was copied, and the frame ended normally.
[0111]
Service Opportunity: This (normal end) frame was preceeded by a token or MACRST, a MAC frame was received, or there
was a ring-op change. Any of these events marks a burst boundary.
NO SPACE COPY ABORT
[1000]
Insufficient Data Space: Not all the frame was copied because there was insufficient data space. This code is only written
in non-Header/Info Sort Mode.
[1001]
Insufficient Header Space: The frame copy was aborted because there was insufficient header space (in Header/Info
Sort Mode).
[1010]
Successful Header Copy, Frame Info Not Copied: There was sufficient space to copy the header, but insufficient data
space to copy info, or insufficient IDU space (on ICHN2), or both. No info was copied.
[1011]
No Info Space: The frame’s header was copied. When copying the data, there was insufficient data and/or IDU space.
ERROR
[1100]
FIFO Overrun: The Indicate FIFO had an overrun while copying this frame.
[1101]
Bad Frame: The frame did not have a valid data length, or had invalid FCS, or both.
[1110]
Parity Error: There was a parity error during this frame.
[1111]
Internal Error: There was an internal logic error during this frame.
55
5.0 Control Information (Continued)
The BSI device checks for the following inconsistencies
when the REQ is loaded from memory:
REQ Descriptor (REQ)
Request Descriptors (REQs) contain the part, byte address,
and size of one or more Output Data Unit Descriptors. They
also contain parameters and commands to the BSI device
associated with Request operations.
Multiple REQ Descriptors (parts) may be grouped as one
Request Descriptor object by the host software, with the
REQ.First defining the parameters for the entire Request
object. Also, multiple Output Data Unit Descriptors may be
grouped contiguously, to be described by a single REQ Descriptor.
Each REQ part is fetched by the BSI device from the Request Channel’s REQ Descriptor Queue, using the REQ
Queue Pointer Register. Each Request Channel processes
one Request Descriptor, per service opportunity, until a
REQ.Last is encountered.
31
30
29
28
RES
27
UID
F–L
24
1. REQ.F with invalid Confirmation Class (as shown in the
Table 5-8).
2. REQ.First with Request Class e 0.
3. REQ.First, when the previous REQ was not a REQ.Last
or REQ.Only.
4. REQ which is not a REQ.First, when the previous REQ
was a REQ.Last or a REQ.Only.
When an inconsistency is detected, the BSI device aborts
the Request, and reports the exception in the Request
Status field of the CNF Descriptor.
The encodings of the RQCLS and CNFCLS bits are described in more detail in Tables 5-7 and 5-8 respectively.
23
16
SIZE
15
12
CNFCLS
RES
11
8
RQCLS
LOC
7
FC
0
Word 0
Word 1
Word 0
Bit
Symbol
Description
D0 – 7
FC
Frame Control: Frame control field to be used unless FC transparency is enabled. This field is
decoded to determine whether to assert RQCLM or RQBCN. This decoding is always active, i.e.,
regardless of frame control transparency. This field is also used for comparing received frames
when confirming (without FC transparency).
D8 – 11
RQCLS
Request/Release Class: This field encodes the Request Class for the entire Request object, and is
thus only sampled on a REQ.First or REQ.Only. The field is asserted on the RQRCLS output signals
to the BMAC device when requesting a token. If the Request Class is incompatible with the current
ring state, the BSI device sets the RCHN’s USR bit in the Request Attention Register. The encoding
of this field is shown in Table 5-7.
D12 – 15
CNFCLS
Confirmation Class: This field encodes the Confirmation Class for the entire Request object, and is
only sampled on a REQ.First or REQ.Only. The encoding of this field is shown in Table 5-8.
D12
E
End: Enables confirmation on completion of request.
0: CNFs on completion disabled.
1: CNFs on completion enabled.
D13
I
Intermediate: Enables Intermediate Confirmation.
0: Intermediate CNFs disabled.
1: Intermediate CNFs enabled.
D14
F
Full/Transmitter: Selects between Transmitter and Full Confirmation.
0: Transmitter confirm.
1: Full confirm.
D15
R
Repeat: Enables repeated transmission of the first frame of the request until the request is aborted.
This may be used when sending BEACON or CLAIM frames.
0: Fetch all frames of REQ.
1: Repeat transmission of first frame of REQ.
A Request may use Repeat on RCHN1, and have a Request loaded on RCHN0, but not vice-versa.
Specifically, when a Request with the Repeat option is loaded on RCHN0, RCHN1 must not have
any REQs active or visible to the BSI device. Thus REQs on RCHN1 may be queued externally but
the queue’s Limit Register must not be set at or after that point. Requests with the Repeat option
should only be used on one Request Channel at a time, and preferably on RCHN0.
56
5.0 Control Information (Continued)
REQ Descriptor (REQ) (Continued)
Word 0 (Continued)
Bit
Symbol
Description
D16 – 23
SIZE
Size: Count of number of frames represented by the ODUD stream pointed to by LOC. REQ Descriptors
with a frame count are permitted, and are typically used to end a Request, without having to send data.
For example, to end a restricted dialogue, a REQ.Last with SIZE e 0 will cause the Request Machine to
command the BMAC device to capture and release the specified classes of token. The response of the
BSI device to REQs with SIZE e 0 is as follows:
1. REQ.First: BSI device latches the REQ Descriptor fields, then fetches the next REQ. REQRCLS is
asserted, but RQRDY remains deasserted.
2. REQ.Middle: BSI device fetches the next REQ.
3. REQ.Only: BSI device requests the capture of the appropriate token. When it is captured, the BSI
asserts RQFINAL and ends the request.
4. REQ.Last: BSI device captures the token, asserts RQFINAL, then marks the request complete.
D24 – 29
UID
User Identification: Contains the UID field from the current REQ.First or REQ.Only.
D30 – 31
RES
Reserved
Word 1
Bit
Symbol
Description
D0 – 27
LOC
Location: Bits [27:2] are the memory word address of ODUD stream. Bits [1:0] are expected to be 00,
and are not checked.
D28 – 29
RES
Reserved
D30 – 31
F– L
First/Last Tag: Identifies the ODUD stream part, i.e., Only, First, Middle, or Last.
57
5.0 Control Information (Continued)
TABLE 5-7. REQ Descriptor Request Class Field Encodings
RQCLS
Value
RQCLS
Name
Class
Type
THT
Token
Capture
Token
Issue
None
Ð
none
non
E
non-r
non-r
Notes
0000
None
0001
Apr1
Async pri1
0010
Reserved
Reserved
0011
Reserved
Reserved
0100
Syn
Sync
D
any
capt
1
0101
Imm
Immed
D
none
none
4
0110
ImmN
Immed
D
none
non-r
4
0111
ImmR
Immed
D
none
restr
4
1000
Asyn
Async
E
non-r
non-r
1001
Rbeg
Restricted
E
non-r
restr
2, 3
1010
Rend
Restricted
E
restr
non-r
2
1011
Rcnt
Restricted
E
restr
restr
2
1100
AsynD
Async
D
non-r
non-r
1101
RbegD
Restricted
D
non-r
restr
2, 3
1110
RendD
Restricted
D
restr
non-r
2
1111
RcntD
Restricted
D
restr
restr
2
E e enabled, D e disabled, non-r e non-restricted, restr e restricted, capt e captured
Note 1: Synchronous Requests are not serviced when bit BCNR of the Ring Event Latch Register is set.
Note 2: Restricted Requests are not serviced when bit BCNR, CLMR, or OTRMAC of the Ring Event Latch Register is set.
Note 3: Restricted Dialogues only begin when a Non-Restricted token has been received and transmitted.
Note 4: Immediate Requests are serviced when the ring is Non-Operational. These requests are serviced from the Data state if neither signal RQCLM nor RQBCN
is asserted. If signal RQCLM is asserted, Immediate Requests are serviced from the Claim State. If signal RQBCN is asserted, Immediate Requests are serviced
from the Beacon State. RQCLM and RQBCN do not cause transitions to the Claim and Beacon States.
TABLE 5-8. REQ Descriptor Confirmation Class Field Encodings
[R]
[F]
[I]
[E]
Confirmation Class
x
x
0
0
0
0
x
x
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
Invalid (consistency failure)
Invalid (consistency failure)
None: Confirmation only on exception
Tend: Transmitter confirm, CNF on exception or completion
Tint: Transmitter confirm, CNF on exception,
completion or intermediate
Fend: Full Confirm, CNF on exception or completion
Fint: Full Confirm, CNF on exception,
completion or intermediate
NoneR: Confirmation only on exception, repeat frame
TendR: Transmitter confirm, CNF on exception
or completion, repeat frame
TintR: Transmitter confirm, CNF on exception, completion
or intermediate, repeat frame
FendR: Full confirmation, CNF on exception or
completion, repeat frame
FintR: Full Confirmation, CNF on exception,
completion, or intermediate, repeat frame
58
5.0 Control Information (Continued)
Output Data Unit Descriptor (ODUD)
An Output Data Unit Descriptor (ODUD) contains the part, byte address and size of an Output Data Unit. During Request
operations, ODUDs are fetched by the BSI device from a list in memory, using the address in the ODUD List Pointer Register (in
the Pointer RAM).
ODUDs may have a zero byte count, which is useful for fixed protocol stacks. One layer may be called, and if it has no data to
add to the frame, it may add an ODUD with a zero byte count to the list.
The BSI device checks for the following inconsistencies when an ODUD is loaded from memory:
1. ODUD.First, when the previous ODUD was not an ODUD.Last or ODUD.Only.
2. ODUD which is not an ODUD.First, when the previous ODUD was an ODUD.Last or ODUD.Only.
3. ODUD.First with zero byte count.
When an inconsistency is detected, the BSI device aborts the Request, and reports the exception in the Request Status field of
the CNF Descriptor.
ODUDs must contain at least 4 bytes (for short addresses).
31
30
29
28
27
13
12
RES
F–L
0
CNT
RES
LOC
Word 0
Word 1
Word 0
Bit
Symbol
Description
D0 – 12
CNT
Byte Count: Number of bytes in the ODU. The size may be Zero, which is useful for fixed
protocol stacks.
D13 – 31
RES
Reserved
Word 1
Bit
Symbol
Description
D0 – 27
LOC
Location: Memory byte address of SDU.
D28 – 29
RES
Reserved
D30 – 31
F– L
First/Last Tag: Identifies the Output Data Unit part, i.e., Only, First, Middle, or Last.
59
5.0 Control Information (Continued)
Confirmation Status Message Descriptor (CNF)
A Confirmation Status Message (CNF) describes the result of a Request operation.
A more detailed description of the encoding of the RS bits is given in Table 5-9.
31
30
29
28
27
RS
24
FRA
F–L
UID
23
16
15
8
7
0
FRS
TFC
CFC
Word 0
FC
CS
RES
Word 1
Word 0
Bit
Symbol
Description
D0 – 7
CFC
Confirmed Frame Count: Number of confirmed frames. Valid only for Full
Confirmation.
D8 – 15
TFC
Transmitted Frame Count: Number of frames successfully transmitted by the
BSI device and BMAC device. Valid for all confirmation classes.
D16 – 23
FRS
Frame Status: This field is valid only for Full Confirmation, and if the frame
ended with an ED.
D16– 17
C
C Indicator:
00: None
01: R
10: S
11: T
D18– 19
A
A Indicator:
00: None
01: R
10: S
11: T
D20– 21
E
E Indicator:
00: None
01: R
10: S
11: T
D22
VFCS
Valid FSC:
0: FSC Field was Invalid.
1: FSC Field was Valid.
D23
VDL
Valid Data Length:
0: Data Length was Invalid.
1: Data Length was Valid.
D24 – 27
FRA
Frame Attributes: This field is valid only for Full Confirmation.
TC
Terminating Condition:
00: Other (e.g., MAC Reset/token).
01: Ed.
10: Format Error.
11: Frame Stripped.
D26
AFLAG
AFLAG: Reflects the state of the AFLAG input signal, which is sampled by the
BSI device at INFORCVD.
0: No DA Match.
1: DA Match.
D27
MFLAG
MFLAG: Reflects the state of the MFLAG input signal, which is sampled by the
BSI device at INFORCVD.
0: Frame Sent by another Station.
1: Frame Sent by this Station.
D24– 25
60
5.0 Control Information (Continued)
Confirmation Status Message Descriptor (CNF) (Continued)
Word 0 (Continued)
Bit
Symbol
D28 – 31 RS
Description
Request Status: This field represents a priority encoded status value, with the highest number having the
highest priority. This field is described in Table 5 – 9.
RS3
RS2
RS1
RS0
Meaning
Intermediate
0
0
0
0
None
0
0
0
1
Preempted
0
0
1
0
Part Done
Breakpoints
0
0
1
1
Service Loss
0
1
0
0
Reserved
Completion
0
1
0
1
Completed BEACON
0
1
1
0
Completed OK
Exception Completion
0
1
1
1
Bad Confirmation
1
0
0
0
Underrun
1
0
0
1
Host Abort
1
0
1
0
Bad Ringop
1
0
1
1
MAC Abort
1
1
0
0
Timeout
1
1
0
1
MAC Reset
1
1
1
0
Consistency Failure
Error
1
1
1
1
Internal or Fatal ABus Error
61
5.0 Control Information (Continued)
Confirmation Status Message Descriptor (CNF) (Continued)
Word 1
Bit
Symbol
Description
D0 – 7
RES
Reserved
D8 – 15
CS
Confirmation Status
FT
Frame Type: This field reflects the type of frame that ended Full Confirmation.
00: Any Other.
01: Token.
10: Other Void.
00: My Void.
D10
F
Full Confirm: This bit is set when the Request was for Full Confirmation.
D11
U
Unexpected Frame Status: This bit is set when the frame status does not
match the value programmed in the Request Expected Frame Status Register.
This applies only to Full Confirmation.
D12
P
Parity: This bit is set when a parity error is detected in a received frame. Parity is
checked from FC to ED inclusive if the FLOW bit in the Mode Register is set.
D13
E
Exception: This bit is set when an exception occurs. The RCHN’s EXC bit in the
Request Attention Register is also set.
D14
R
Ring-Op: This bit is set when the ring enters a bad operational state after
transmission but before all returning frames have been confirmed.
D15
T
Transmit Class:
0: Restricted.
1: Non-Restricted.
D16 – 23
FC
Frame Control: Frame Control field of the last frame of the last confirmed burst.
Valid only for Full Confirmation.
D24 – 29
UID
User Identification: Contains the UID field copied from the current REQ.FIRST
or REQ.ONLY.
D30 – 31
F– L
First/Last Tag: Identifies the CNF part, i.e., Only, First, Middle, or Last.
D8 – 9
62
5.0 Control Information (Continued)
TABLE 5–9. Request Status (RS) Field of CNF Descriptor
INTERMEDIATE
[0000]
None: Non status is written. This may be used by software to identify a NULL or invalid CNF.
[0001]
[0010]
Preempted: RCHN1 was preempted by RCHN0. RCHN1 will be serviced following RCHN0.
Part None: The BSI device is servicing a Request, but it cannot hold onto a token, and the last frame of a
Request.part has been transmitted.
BREAKPOINTS
[0011]
Service Loss: The THT expired during a Request with THT enabled. Only occurs for Intermediate Confirmation.
[0100]
Reserved
COMPLETION
[0101]
Completed BEACON: When transmitting from the BEACON state, this status is returned when the BMAC device
receives a MyÐBeacon. When transmitting from the CLAIM state, this status is returned when the BMAC device
wins the CLAIM process.
[0110]
Completed OK: Normal completion with good status.
EXCEPTION COMPLETION
[0111]
Bad Confirmation: There was an error during confirmation, causing the Request to complete with this status, or one
of higher priority. Confirmation errors include MACRST, ring-operational change, receiving an OtherÐVoid or MyÐ
Void or token, receiving a bad frame, or receiving a frame that did not match the programmed expected frame status.
[1000]
Underrun: There was no data in the request data FIFO when it was required to be presented to the BMAC device.
[1001]
Host Abort: The host aborted the Request on this Request Channel, either directly by clearing the ABT bit in the
Service Attention Register or indirectly by having insufficient entries in the CNF queue.
[1010]
Bad Ringop: A Request was loaded with a Request Class inappropriate for the current ring operational state.
[1011]
MAC Device Abort: The BMAC device aborted the Request and asserted TXABORT. This could be from an
interface parity error, or because the transmitted frame failed the FC check, or because the BMAC device received a
MAC frame while transmitting in the BEACON state. This status is also returned when the BMAC device receives an
OtherÐBeacon while the BSI device is transmitting in the BEACON state, or when the CLAIM process is lost while
the BSI device is transmitting in the CLAIM state.
[1100]
Timeout: The TRT expired during a Request with THT disabled. The Request is aborted.
[1101]
MAC Reset: The BMAC device asserted MACRST.
[1110]
Consistency Failure: There was an inconsistency within the REQ or ODUD stream.
ERROR
[1111]
Internal or Fatal ABus Error: There was an internal logic error or a fatal ABus error while writing a CNF.
63
5.0 Control Information (Continued)
Pool Space Descriptor (PSP)
Pool Space Descriptors (PSPs) contain the address and size (in bytes) of a free space in host memory available for writing Input
Data Units. When PSPs are read by the BSI device, the address field of the PSP is loaded into the Indicate Channel’s IDU
Pointer Register, and is used as the subchannel address for the IDU memory write.
31
30
29
28
27
13
12
0
RES
F–L
CNT
RES
LOC
Word 0
Word 1
Word 0
Bit
Symbol
Description
D0 – 12
CNT
Byte Count: Number of bytes in the available memory area (up to 4k bytes).
D13 – 31
RES
Reserved
Word 1
Bit
Symbol
Description
D0 – 27
LOC
Location: Memory byte address of memory area available for writing IDUs. Normally the
page offset will be Zero to simplify space management.
D30 – 31
RES
Reserved
64
6.0 Signal Descriptions
6.1 PIN ORGANIZATION
The BSI device pinout is organized into five groups:
Control Interface: Used for host microprocessor access to the BSI device.
BMAC Device Indicate Interface: Pins for receiving and processing incoming frames from the DP82361 BMAC device.
BMAC Device Request Interface: Pins for transmitting frames to the BMAC device.
ABus Interface: Pins for transferring data and data information between system memory and the BSI device.
Electrical Interface: Pins associated with power supply, clocking, and scan test.
TL/F/10791 – 12
FIGURE 6-1. DP83265 160-Pin Pinout
Order Number DP83265VF
See NS Package Number VF160A
65
6.0 Signal Descriptions (Continued)
DP83265 Pinout Description
Pin
I/O
Pin
Description
I/O
Pin
Description
I/O
Pin
Description
1
ABÐACK
Description
I
41
LBC1
I
81
VCC
Core
121
ABÐAD7
I/O
I/O
2
ABÐERR
I
42
LBC3
I
82
GND
Core
122
ABÐBP1
I/O
3
ABÐA4
O
43
LBC5
I
83
RQBCN
O
123
ABÐAD8
I/O
4
ABÐA3
O
44
GND
84
RQCLM
O
124
GND
5
ABÐA2
O
45
NC
85
FCST
O
125
VCC
6
ABÐRW
O
46
NC
86
VCC
126
ABÐAD9
I/O
7
ABÐDEN
O
47
GND
87
GND
127
ABÐAD10
I/O
8
VCC
48
NC
88
STRIP
O
128
ABÐAD11
I/O
9
GND
49
ECIP
I
89
SAT
O
129
ABÐAD12
I/O
10
ABÐSIZ2
O
50
EA
I
90
RST
I
130
ABÐAD13
I/O
11
ABÐSIZ1
O
51
EM
I
91
RW
I
131
ABÐAD14
I/O
12
ABÐSIZ0
O
52
MRQ0
O
92
CE
I
132
ABÐAD15
I/O
13
ABÐBR
O
53
MRQ1
O
93
INT
OD
133
ABÐBP2
I/O
14
ABÐBG
I
54
MRQ2
O
94
ACK
OD
134
GND
15
FCRCVD
I
55
MRQ3
O
95
CBA0
I
135
VCC
16
MIDS
I
56
VCC
96
CBA1
I
136
ABÐAD16
I/O
17
AFLAG
I
57
GND
97
CBA2
I
137
ABÐAD17
I/O
18
MFLAG
I
58
MRQ4
O
98
CBA3
I
138
ABÐAD18
I/O
19
SAMESA
I
59
MRQ5
O
99
CBA4
I
139
ABÐAD19
20
INFORCVD
I
60
MRQ6
O
100
CBD0
I/O
140
GND
Core
21
SAMEINFO
I
61
MRQ7
O
101
CBD1
I/O
141
VCC
Core
22
EDRCVD
I
62
MRP
O
102
CBD2
I/O
142
ABÐAD20
I/O
23
VFCS
I
63
TXRINGOP
I
103
CBD3
I/O
143
ABÐAD21
I/O
24
VDL
I
64
TXCLASS
I
104
VCC
144
ABÐAD22
I/O
25
TKRCVD
I
65
TXABORT
I
105
GND
145
ABÐAD23
I/O
26
FOERROR
I
66
TXED
I
106
CBD4
I/O
146
GND
27
FRSTRP
I
67
MRDS
I
107
CBD5
I/O
147
VCC
28
VCOPY
O
68
TXRDY
I
108
CBD6
I/O
148
ABÐBP3
I/O
29
MACRST
I
69
TXPASS
I
109
CBD7
I/O
149
ABÐAD24
I/O
30
MIP
I
70
RQABORT
O
110
CBP
I/O
150
ABÐAD25
I/O
31
MID7
I
71
RQFINAL
O
111
ABÐBP0
I/O
151
ABÐAD26
I/O
32
MID6
I
72
RQEOF
O
112
ABÐAD0
I/O
152
ABÐAD27
I/O
33
MID5
I
73
RQSEND
O
113
ABÐAD1
I/O
153
ABÐAD28
I/O
34
MID4
I
74
VCC
114
VCC
154
ABÐAD29
I/O
35
MID3
I
75
GND
115
GND
155
ABÐAD30
I/O
36
MID2
I
76
RQRDY
O
116
ABÐAD2
I/O
156
GND
37
MID1
I
77
RQRCLS0
O
117
ABÐAD3
I/O
157
VCC
38
MID0
I
78
RQRCLS1
O
118
ABÐAD4
I/O
158
ABÐAD31
I/O
39
VCC
Core
79
RQRCLS2
O
119
ABÐAD5
I/O
159
ABÐAB
I/O
40
GND
Core
80
RQRCLS3
O
120
ABÐAD6
I/O
160
ABÐCLK
I/O
66
I/O
6.0 Signal Descriptions (Continued)
6.2 CONTROL INTERFACE
The Control Interface operates asynchronously to the operation of the BMAC device and ABus interfaces.
The ACK and INT signals are open drain to allow wire ORing.
Symbol
CBP
Pin Ý
I/O
Description
110
I/O
Control Bus Parity: Odd parity on CBD7 – 0.
CBD7 – 0
109-106,
103–100
I/O
Control Bus Data: Bidirectional Data bus.
CBA4 – 0
99– 95
I
Control Bus Address: Address of a particular BSI device register.
CE
92
I
Control Bus Enable: Handshake signal used to begin a Control
Interface access. Active low signal.
R/W
91
I
Read/Write: Determines current direction of a Control Interface
access.
ACK
94
OD
Acknowledge: Acknowledges that the Control Interface access has
been performed. Active low, open drain signal.
INT
93
OD
Interrupt: Indicates presence of one or more enabled conditions.
Active low, open drain signal.
RST
90
I
Reset: Causes a reset of BSI device state machines and registers.
67
6.0 Signal Descriptions (Continued)
6.3 BMAC Device Indicate Interface
The BMAC Device Indicate Interface signals provide data and control bytes as received from the BMAC device. Each Indicate
Data byte is also provided with odd parity.
MID7 – 0 signals are valid on the rising edge of the Local Byte Clock signal (provided by the Clock Recovery Device).
Data:
Symbol
MIP
MID7 – 0
Pin Ý
I/O
Description
30
I
MAC Indicate Parity: This is connected directly to the corresponding BMAC device
pin of similar name. Odd parity on MID7 – 0. Only valid with Data and Status
indicators.
31– 38
I
MAC Indicate Data: This is connected directly to the corresponding BMAC device
pin of similar name.
Data: The BMAC device indicates data is being presented on MID7 – 0 during the
time when RCSTART is asserted until one of the following signals is asserted:
EDRCVD, TKRCVD, FOERROR, or MACRST.
Status: The BMAC device indicates Status Indicators are being presented on
MID7–0 when EDRCVD or TKRCVD is asserted.
Frame Sequencing:
The Frame Sequencing signals apply to the data available at the MAC Indicate Interface (MIP and MID7 – 0). The Frame
Sequencing signals can be used to control the latching of appropriate Frame Status.
PinÝ
I/O
Description
FCRCVD
Symbol
15
I
Frame Control Received: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the Frame Control Field
has been received.
INFORCVD
20
I
Information Field Received: This is connected directly to the corresponding
BMAC device pin of similar name. The BMAC device indicates that four bytes of the
Information Field have been received. It is asserted by the BMAC device on the
fourth byte of the INFO field and remains active until the next JK symbol pair is
received.
EDRCVD
22
I
EDFS Received: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the End of Frame Sequence has
been received.
MIDS
16
I
MAC Indicate Data Strobe: Asserted by BMAC device to indicate valid data. This
signal should be tied to VCC for FDDI-I, and used for FDDI-II.
Pin Ý
I/O
AFLAG
17
I
My Destination Address Recognized: This is connected directly to the
corresponding BMAC device pin of similar name. The BMAC device indicates that
an internal address match occurred on the Destination Address field. It is reset
when the next JK symbol pair is received.
MFLAG
18
I
My Source Address Recognized: This is connected directly to the corresponding
BMAC device pin of similar name. The BMAC device indicates that the received
Source Address field matched the MLA or MSA BMAC device registers. It is reset
when the next JK symbol pair is received.
SAMESA
19
I
Same Source Address: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the SA of the current
frame is the same as the previous frame, that the frames were not MAC frames, and
that the frames are the same size. It is reset when the next KJ symbol pair is
received.
SAMEINFO
21
I
Same MAC Information: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the first four bytes of
the IF of the current frame are the same as the previous frame, that the frames were
MAC frames, and that their address lengths are the same. SAMEINFO is asserted
along with INFORCVD. It is reset when the next JK symbol pair is received.
Frame Information:
Symbol
Description
68
6.0 Signal Descriptions (Continued)
Frame Status:
Pin Ý
I/O
VDL
Symbol
24
I
Valid Data Length: The BMAC device indicates a valid data length for the current
frame.
Description
VFCS
23
I
Valid Frame Check Sequence: The BMAC device indicates a valid FCS for the
current frame.
TKRCVD
25
I
Token Received: The BMAC device indicates that a complete token was received.
FRSTRP
27
I
Frame Stripped: The BMAC device indicates that the current frame was stripped.
FOERROR
26
I
Format Error: The BMAC device indicates a standard-defined format error.
MACRST
29
I
MAC Reset: The BMAC device indicates an internal error, MAC frame, MAC reset,
or hardware or software reset.
EA
50
I
External AFlag: This signal is used by external address matching to signal that a
Destination Address (DA) match has occurred. Assuming that the proper timing of
EA and ECIP are met, the assertion of EA will cause the BSI device to copy this
frame. EA is sampled on the cycle after ECIP is deasserted. The sample window is
from FCRCVD to EDRCVD.
EM
51
I
External MFlag: This signal is used by external address matching logic to signal a
Source Address (SA) match. It is sampled on the clock cycle after ECIP is
deasserted.
VCOPY
28
O
Valid Copy: Affects the setting of the transmitted Cx (Copied Indicator).
The value of VCOPY is used to determine the value of the transmitted Cx. VCOPY
must be asserted one byte time before EDRCVD is asserted.
ECIP
49
I
External Compare in Progress: This signal is asserted to indicate that external
address comparison has begun. It is deasserted to indicate that the comparison has
completed. EA and EM are sampled upon the deassertion of ECIP. ECIP must be
asserted during the period from the assertion of FCRVCD (by the BMAC device) to
the assertion of INFORCVD (by the BMAC device) in order for the BSI to recognize
an external comparison. It must be deasserted for at least one cycle for the external
comparison to complete. If ECIP has not been deasserted before EDRCVD (from
the BMAC device), the BSI device will not copy this frame. ECIP may be
implemented as a positive or negative pulse.
69
6.0 Signal Descriptions (Continued)
6.4 BMAC Device Request Interface
The BMAC Device Request Interface signals provide data and control bytes to the BMAC device as received from the Host
System. Each Request Data byte is also provided with odd parity.
Symbol
MRP
MRD7 – 0
Pin Ý
I/O
Description
62
O
MAC Request Parity: This is connected directly to the corresponding BMAC device
pin of similar name. Odd parity on MRD7 – 0.
61–58,
O
MAC Request Data: This is connected directly to the corresponding BMAC device
pin of similar name. The BMAC device indicates data is being presented on
MRD7–0.
55– 52
Service Parameters:
Symbol
Pin Ý
I/O
Description
RQRCLS3 – 0
80–77
O
Request Class: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates the service class parameters for this
request. When RQRCLS l 0, the BMAC device Transmitter will capture a usable
token for non-immediate requests) and assert TXRDY. The service opportunity
continues as long as the token is usable with the current service parameters, even if
RQRDY is not asserted. When RQRCLS e 0, the service opportunity will terminate
after the current frame (even if RQRCLS subsequently becomes non-Zero).
RQCLM
84
O
Request CLAIM: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that this request is to be serviced in the
Transmit CLAIM state. Ignored for non-immediate requests.
RQCBN
83
O
Request BEACON: This is connected directly to the corresponding BMAC device
pin of similar name. The BMAC device indicates that this request is to be serviced in
the Transmit BEACON state. Ignored for non-immediate requests.
70
6.0 Signal Descriptions (Continued)
Frame Options:
Pin Ý
I/O
STRIP
Symbol
88
O
Void Strip: Connected to STRIP and possibly SAT on the BMAC device.
Description
SAT
89
O
Source Address Transparency: Connected to SAIGT on the BMAC device and to
SAT on the BMAC device if STRIP is not.
FCST
85
O
Frame Check Sequence Transparency: This is connected directly to the
corresponding BMAC device pin of similar name. When selected, the BMAC device
will not append FCS to the end of the Information field.
Request Handshake:
Symbol
Pin Ý
I/O
Description
TXPASS
69
I
Transmit Pass: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates the absence of a service opportunity. This
could result from an unusable request class, waiting for a token, timer expiration, or
MAC Reset. TXPASS is always asserted between service opportunities. It is
deasserted when TXRDY is asserted at the beginning of a service opportunity.
TXRDY
68
I
Transmit Ready: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the BMAC device transmitter is
ready for another frame. For a non-immediate request, a useable token must be
held in order to transmit frames.
TXRDY is asserted by the BMAC device when:
a. a usable token is being held, or
b. an immediate request becomes serviceable, or
c. after frame transmission if the current service opportunity is still usable for
another frame.
TXRDY is deasserted when TXPASS or TXACK is asserted.
RQRDY
76
O
Request Ready: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the BMAC device transmitter
should attempt to use a service opportunity.
If RQRDY is asserted within 6 byte times after TXRDY is asserted, the BMAC device
transmitter will wait at least LÐMax plus one Void frame (4.16 ms b 4.80 ms) for
RQSEND to be asserted before releasing the token.
RQSEND
73
O
Request Send: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that the BMAC device transmitter should
send the next frame. The MRD7 – 0 signals convey the FC byte when this signal is
asserted.
If RQSEND is asserted within 6 byte times after TXRDY is asserted, the BMAC
device transmitter will send the frame with a minimum length preamble. If RQSEND
is not asserted within LÐMax plus one Void frame after RQRDY has been asserted
(4.16 ms b 4.60 ms), the token may become unusable due to timer expiration.
RQSEND may only be asserted when TXRDY and RQRDY are asserted and
RQFINAL is deasserted.
RQSEND must be deasserted not later than one byte time after TXRDY is
deasserted
MRDS
67
I
MAC Request Data Strobe: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that data on MRD7 – 0 is
valid. This signal should be connected to the TXACK on the BMAC device.
RQEOF
72
O
Request EOF: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that MRD7 – 0 conveys the last data byte
when asserted. Normally, this is the last byte of the INFO field of the frame
(exceptions: FCS transparency, invalid frame length).
RQEOF causes TXACK to be deasserted and is ignored when TXACK is not
asserted.
71
6.0 Signal Descriptions (Continued)
Request Handshake: (Continued)
Symbol
Pin Ý
I/O
Description
RQABORT
70
O
Request Abort: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that the current frame should be aborted.
Normally this causes the BMAC device transmitter to generate a Void, CLAIM, or
BEACON frame.
RQABORT causes TXACK to be deasserted and is ignored when TXACK is not
asserted.
RQFINAL
71
O
Request Final: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that the final frame of the request has
been presented to the BMAC device Interface.
When asserted, the Issue Token Class (as opposed to the Capture Token Class)
becomes the new Token Class (TXCLASS). RQFINAL may only be asserted when
RQRDY is asserted and RQSEND is deasserted. RQFINAL is ignored unless
RQRDY has been asserted for at least one byte time and the service parameters
have been valid for at least three byte times.
RQFINAL must be deasserted not later than two byte times after TXPASS is
deasserted.
TXED
66
I
Transmit End Delimiter: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the ED is being
transmitted.
TXABORT
65
I
Transmit Abort: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the MAC Transmitter aborted the
current frame.
Symbol
Pin Ý
I/O
Description
TXRINGOP
63
I
Transmit Ring Operational: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates the state of the MAC
Transmitter.
TXCLASS
64
I
Transmit Token Class: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates the class of the current
token.
Transmit Status:
72
6.0 Signal Descriptions (Continued)
6.5 ABus Interface
The ABus Interface signals provide a 32-bit multiplexed address/data bus for transfers between the host system and the BSI
device. The ABus uses a bus request/bus grant protocol that allows for multiple bus masters, supports burst transfers of 4 or 8
32-bit words, and permits both physical and virtual addressing using fixed-size pages.
Address and Data:
Pin Ý
I/O
ABÐBP3 –0
Symbol
148, 133,
122, 111
I/O
ABus Byte Parity: These TRI-STATE signals contain the BSI device-generated parity
for each address byte of ABÐAD, such that ABÐBP0 is the parity for ABÐAD7 –0,
ABÐBP1 is the parity for ABÐAD15 – 8, etc.
ABÐAD31–0
158,
155–149,
145–142,
139–136,
132–126,
123,
121–116,
113–112
I/O
ABus Address and Data: These TRI-STATE signals are the multiplexed ABus address
and data lines. During the address phase of a cycle, ABÐAD27 – 0 contain the 28-bit
address, and ABÐAD31 – 28 contain a 4-bit function code identifying the type of
transaction, encoded as follows:
ABÐAD[31:28]
Transaction Type
0
RSAP1 ODU Load
1
RSAP1 ODUD Load/CNF Store
2
RSAP1 REQ Load
3
RSAP0 ODU Load
4
RSAP0 ODUD Load/CNF Store
5
RSAP0 REQ Load
6
ISAP2 IDU Store
7
ISAP2 IDUD Store
8
ISAP2 PSP Load
9
ISAP1 IDU Store
A
ISAP1 IDUD Store
B
ISAP1 PSP Load
C
ISAP0 IDU Store
D
ISAP0 IDUD Store
E
ISAP0 PSP Load
F
PTR RAM Load/Store
3–5
O
ABus Burst Address: These TRI-STATE signals contain the word address during burstmode accesses. They are driven from Tpa to the last Td state, negated in the following
Tr state, then released. Note that the address presented allows external pipelining for
optimum memory timing.
ABÐA4 – 2
Description
73
6.0 Signal Descriptions (Continued)
Bus Control:
Symbol
Pin Ý I/O
Description
ABÐAS
159
O ABus Address Strobe: When asserted, This TRI-STATE signal indicates that data on ABÐAD is valid.
When this signal is inactive and ABÐACK is asserted, the next cycle is a Tr state, in which the bus arbiter
can sample all bus requests, then issue a bus grant in the following cycle.
ABÐRW
6
O ABus Read/Write: This TRI-STATE signal determines the current direction of an ABus access.
ABÐDEN
7
O ABus Data Enable: This TRI-STATE signal indicates that data on ABÐAD31 – 0 is valid.
ABÐSIZ2 – 0 10 – 12 O ABus Size: These TRI-STATE signals indicate the size of the transfer on ABÐAD31 – 0, encoded as
follows:
Transfer
ABÐSIZ2
ABÐSIZ1
ABÐSIZ0
Size
0
0
0
4 Bytes
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
16 Bytes
1
0
1
32 Bytes
1
1
0
Reserved
1
1
1
Reserved
ABÐACK
1
I
ABus Acknowledge: Indicates a bus slave’s response to a bus master. The meaning of this signal
depends on the state of ABus Error (ABÐERR), as described below.
ABÐERR
2
I
ABus Error: This signal is asserted by a bus slave to cause a transaction retry or transaction abort.
Together with ABÐACK, the encoding is as follows:
ABÐACK
ABÐERR
Definition
1
1
Insert Wait States
1
0
Bus Error
0
0
Transaction Retry
0
1
Acknowledge
Bus Arbitration:
Symbol
Pin Ý
I/O
Description
ABÐBR
13
O
ABus Bus Request: This signal is used by a bus master to request use of the ABus.
ABÐBG
14
I
ABus Bus Grant: This signal is asserted by external bus arbitration logic to grant
use of the ABus to the BSI device. When ABÐBG is deasserted, the BSI device
completes the current transaction and releases the bus. If ABÐBG is asserted at
the start of a transaction (Tbr), the BSI device will run a transaction.
ABÐCLK
160
I
ABus Clock: All ABus operations are synchronized to the rising edge of ABÐCLK.
74
6.0 Signal Descriptions (Continued)
6.6 ELECTRICAL INTERFACE
Symbol
Pin Ý
I/O
LBC5, 3, 1
43–41
I
Description
Local Byte Clock: 12.5 MHz clock with a 60/40 duty-cycle. Generated by CDD.
VCC [13]
8, 39, 56
74, 81, 86,
104, 114,
125, 135,
141, 147, 157
Positive Power Supply: 5V, g 10% relative to GND.
GND[13]
9, 40, 57
75, 82, 87,
105, 115, 124,
134, 140, 146,
156
Power Supply Return.
GND
NC
44, 47
45, 46, 48
Must be grounded.
No Connect: Must be left unconnected.
75
DP83265 BSI Device (FDDI System Interface)
Physical Dimensions inches (millimeters)
Order Number DP83265VF
NS Package Number VF160A
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