DP83290EB FDDI Physical Layer Evaluation Board 1.0 Introduction This document is intended to provide the user with an overview concerning the design, operation, and installation of the National Semiconductor DP83290EB FDDI Physical Layer Evaluation Board, hereafter referred to as the Link Card. Appendix A.1 is included in this document. All other appendices can be found in the DP83290EB FDDI Physical Layer Evaluation Board User’s Guide. They are listed here for reference only. Table of Contents 4.0 APPENDICES 1.0 INTRODUCTION 2.0 EVALUATION BOARDS AND ENVIRONMENT 2.1 Link Card Description 2.2 Link Card Features 2.3 BMAC Card Description 2.4 Station Environment (PC-AT Platform) 3.0 SYSTEM DESCRIPTION A. Board Specifics 1. Installation 2. Layout Considerations 3. Pinouts D. Point to Point Applications E. Configuration Diagrams F. Board Schematics 3.1 Block Diagram Description 3.2 At Interface Block 1. Circuit Schematics 2. Layout Plots 3.3 Clock Bus Block G. At Interface GAL Equations 3.4 CDD Device Block H. Component Inventory 3.5 CRD Device Block 3.6 Link Bus Block 3.7 PLAYERTM Device Block 3.8 Transceiver Block PLAYERTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10826 RRD-B30M105/Printed in U. S. A. DP83290EB FDDI Physical Layer Evaluation Board April 1990 2.0 Evaluation Boards and Environment 2.1 Link Card Description 2.3 BMAC Card Description The Link Card is intended for evaluation of the following three National Semiconductor devices which implement the FDDI Physical Layer and clock distribution. DP83255 Physical Layer Controller (PLAYER device) DP83241 Clock Distribution Device (CDD device) DP83231 Clock Recovery Device (CRD device) The design goal of the Link Card was to allow the user to exercise the Physical Layer devices and CDD device. The Link Card can be used in tandem with the DP83291EB MAC Card (see Section 2.3). A Link Card connected to a single MAC Card implements a single attachment station. Dual attachment stations require two Link Cards. The Link Card requires a PC-AT compatible machine which is a readily available platform capable of supporting an FDDI application. The National Semiconductor DP83291EB BMAC Evaluation Board, hereafter referred to as the BMAC Card, is intended for evaluation of the DP83261 Basic Media Access Controller (BMAC device). The design goal of the BMAC Card is to allow the user to exercise BMAC functions. The BMAC Card requires a PC-AT compatible environment. This environment is a readily available evaluation platform capable of supporting a FDDI application. 2.4 Station Environment (PC-AT Platform) A PC-AT compatible environment was chosen for the National Semiconductor evaluation platform because of the availability of PC-AT compatible machines. Although the PC-AT does not have the performance of a workstation, the PC-AT does provide a relatively simple bus interface and an abundance of user applications that can be used to support an evaluation platform. 2.2 Link Card Features The Link Card offers many features to provide a flexible and convenient evaluation platform: 3.0 System Description 3.1 Block Diagram Description The Link Card block diagram is composed of the following seven blocks: 1. AT Bus Interface 2. Clock Bus Interface 3. Clock Distribution Device (CDD device) 4. Clock Recovery Device (CRD device) 5. Link Bus Interface 6. Physical Layer Controller (PLAYER device) 7. Transceiver Interface Figure 1 is a detailed representation of the block diagram. # Utilizes the National FDDI Chip Set DP83255 PLAYER Device DP83241 CDD Device DP83231 CRD Device # System modularity supports single attachment or dual attachment configurations. # # # # Utilizes a PC-AT compatible form factor Built-in diagnostic capability for fault detection Supports an external optical bypass switch Power consumption is 1.5 amps typical per Link Card 2 3.0 System Description (Continued) TL/F/10826 – 5 FIGURE 1. Link Card Block Diagram 3 3.0 System Description (Continued) 3.2 AT Interface Block 3.5 CRD Device Block The function of the AT Interface Block is to interface the Link Card with the AT host. This block features a full 24-bit address bus for flexible Link Card memory map placement. The data bus is 8 bits wide which is adequate for this demo platform. Bits 8 through 15 are not used on the base Link Card, but they have been tapped to test points on the board. The test points are included in the event that an application requires a 16-bit data bus. In addition to the address and data buses, seven AT bus interrupts and the necessary control signals are included. All address and data signal lines are buffered with independent parity generation supplied for the data bus. The AT bus block is the sole power supply for the Link Card. The Clock Recovery Device has been designed for used in this FDDI implementation. The device receives serial data from a Fiber Optic Receiver (FORX) in differential ECL NRZI 4B/5B group code format and outputs resynchronized NRZI received data and a 125 MHz received clock in differential ECL format for use by the PLAYER device. 3.6 Link Bus Block The function of the Link Bus is to provide a data path between the Link and MAC Cards that form an FDDI station. Each connection contains two 10-bit data buses (Indicate and Request) and station configuration signals. The pinout of the Link Bus has been designed to allow the user to build Single Attachment and Dual Attachment/Single MAC configurations. To build one of these configurations, the user must simply connect the cabling in the manner shown in Appendix E of the User’s Guide. Every other wire in the Link Bus is grounded to insure data integrity. This cabling scheme has been tested for resistance to data corruption induced by crosstalk. The address decoding scheme is accomplished with generic array logic devices (GALs). Equations for each of the four GAL devices are included in Appendix G of the DP83290EB FDDI Physical Layer Evaluation Board User’s Guide. Beyond these basic functions, the AT Interface offers a number of modes such as autoconfiguration, base register area select, and memory map configuration. 3.7 Player Device Block The Physical Layer Controller is a part of National Semiconductor’s FDDI Chip Set. It implements one Physical Layer entity as defined by the ANSI X3T9.5 PHY standard. The PLAYER device performs the 4B/5B encoding and decoding, serialization and deserialization of data, repeat filter, and line state control and detection. It also contains a configuration switch. The PLAYER device supports many types of station configurations as allowed by the standard. Although tailored to the FDDI specification, the PLAYER device is also well suited for use in high speed point-to-point communication links over optical fibers and coaxial cable. 3.3 Clock Bus Block The Clock Bus Block is included in the Link Card design to provide a physical bus among all Link and MAC Cards that form a station. The construction of the bus is a twenty pin ribbon cable capable of supporting 9 signals. Each signal is surrounded on either side by a ground line to reduce crosstalk. 3.4 CDD Device Block The Clock Distribution Device is a clock generation and distribution device intended for use in FDDI networks. The device provides the complete set of clocks required to convert byte wide data to serial format for fiber medium transmission and to move byte wide data between the PLAYER and BMAC devices in various station configurations. 12.5 MHz and 125 MHz differential ECL clocks are generated for the conversion of data to serial format and 12.5 MHz and 125 MHz TTL clocks are generated for the byte wide data transfers. 3.8 Transceiver Block The transceiver block consists of two parts: fiber optic receiver and fiber optic transmitter. The Link Card supports the following FDDI optical transceiver modules: AT&T ODL 125 Lightwave Data Links Sumitomo DM-742 1300nm Data Link Any transceiver pair which supports the AT&T footprint 2.1.8.1.1 pin format composed of 2 independent 16-pin DIP (footprints) See Appendix A. of the User’s Guide for a detailed footprint description. 4 4.0 Appendices A. Board Specifics 1. Installation A.1.1 Setup TL/F/10826 – 2 5 DP83290EB FDDI Physical Layer Evaluation Board 4.0 Appendices (Continued) A.1.1 Setup (Continued) TL/F/10826 – 3 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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