ETC DP83200EB

DP83200EB
FDDI AT Evaluation Kit
General Description
The DP83200EB FDDI is a complete design/evaluation kit
(using an AT or compatible platform), that includes hardware, software and application documentation, to implement a single node compliant with an ANSI X3T9.5 FDDI
network. The kit has been designed to demonstrate the capabilities of National Semiconductor’s FDDI chip set.
It contains a Link card and MAC card, that together implement one FDDI Single Attach node.
The Evaluation Boards allow evaluation of the many capabilities of the chip set and serve as an educational tool for
customers designing products with the FDDI chip set. High
performance as a goal was sacrificed at the expense of
simplicity and accessibility. There are many laboratories
around the world with a spare IBMÉ PCÉ or compatible.
These boards allow users to experiment and gain experience with the FDDI chip set in order to unleash its capabilities in their own products.
The DP83200EB can be combined with a DP83200EK Kit to
create a dual attach station. The DP83200EK Kit contains
the additional Link card (PHY Layer) and appropriate cables.
Features
Y
Y
Y
Y
Y
Y
Y
Y
System modularity supports single attachment or dual
attachment
Utilizes a PC-ATÉ compatible form factor
Built-in diagnostic capability for fault detection
Supports an external optical bypass switch
Supports asynchronous and synchronous transmission
classes
PAL based buffer management
Supported by demonstration and diagnostic software
Board schematics
TL/F/11122 – 1
BMACTM , CDDTM , CRDTM and PLAYERTM are trademarks of National Semiconductor Corporation.
PALÉ is a registered trademark of Advanced Micro Devices, Inc.
IBMÉ, PCÉ, PC-ATÉ are registered trademarks of International Business Machines Corporation.
C1995 National Semiconductor Corporation
TL/F/11122
RRD-B30M105/Printed in U. S. A.
DP83200EB FDDI AT Evaluation Kit
February 1991
TL/F/11122 – 2
SAS Configuration
TL/F/11122 – 3
DAS Configuration
FIGURE 1. Single attach and optional dual attach configuration
2
1.0 Link Card
# System modularity supports single attachment or dual
1.1 Link Card Description
#
#
#
#
The Link Card is intended for evaluation of the following
three National Semiconductor devices which implement the
FDDI Physical Layer and clock distribution.
DP83255 Physical Layer Controller (PLAYERTM device)
DP83241 Clock Distribution Device (CDD TM device)
DP83231 Clock Recovery Device (CRD TM device)
The design goal of the Link Card was to allow the user to
exercise the Physical Layer devices and CDD device. The
Link Card can be used in tandem with the DP83291EB MAC
Card (see Section 2.3). A Link Card connected to a single
MAC Card inplements a single attachment station. Dual attachment stations require two Link Cards. The Link Card
requires a PC-AT compatible machine which is a readily
available platform capable of supporting an FDDI application.
attachment configurations.
Utilizes a PC-AT compatible form factor
Built-in diagnostic capability for fault detection
Supports an external optical bypass switch
Power consumption is 1.5 amps typical per Link Card
2.0 Link Card System Description
2.1 Block Diagram Description
The Link Card block diagram is composed of the following
seven blocks:
1. AT Bus Interface
2. Clock Bus Interface
3. Clock Distribution Device (CDD device)
4. Clock Recovery Device (CRD device)
5. Link Bus Interface
6. Physical Layer Controller (PLAYER device)
7. Transceiver Interface
1.2 Link Card Features
The Link Card offers many features to provide a flexible and
convenient evaluation platform:
# Utilizes the National FDDI Chip Set
DP83255 PLAYER Device
DP83241 CDD Device
DP83231 CRD Device
Figure 2 is a detailed representation of the block diagram.
3
2.0 Link Card System Description (Continued)
TL/F/11122 – 4
FIGURE 2. Link Card Block Diagram
4
2.0 Link Card System Description (Continued)
2.2 AT Interface Block
The function of the AT Interface Block is to interface the
Link Card with the AT host. This block features a full 24-bit
address bus for flexible Link Card memory map placement.
The data bus is 8 bits wide which is adequate for this demo
platform. Bits 8 through 15 are not used on the base Link
Card, but they have been tapped to test points on the board.
The test points are included in the event that an application
requires a 16-bit data bus. In addition to the address and
data buses, seven AT bus interrupts and the necessary control signals are included. All address and data signal lines
are buffered with independent parity generation supplied for
the data bus.
The AT bus block is the sole power supply for the Link Card.
2.5 CRD Device Block
The Clock Recovery Device has been designed for use in
this FDDI implementation. The device receives serial data
from a Fiber Optic Receiver (FORX) in differential ECL NRZI
4B/5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the PLAYER device.
2.6 Link Bus Block
The function of the Link Bus is to provide a data path between the Link and MAC Cards that form an FDDI station.
Each connection contains two 10-bit data buses (Indicate
and Request) and station configuration signals. The pinout
of the Link Bus has been designed to allow the user to build
Single Attachment and Dual Attachment/Single MAC configurations. To build one of these configurations, the user
must simply connect the cabling in the manner shown in
Appendix E of the User’s Guide.
Every other write in the LInk Bus is grounded to insure data
integrity. This cabling scheme has been tested for resistance to data corruption induced by crosstalk.
The address decoding scheme is accomplished with generic array logic devices (GALs). Equations for each of the four
GAL devices are included in Appendix G of the DP83290EB
FDDI Physical Layer Evaluation Board User’s Guide.
Beyond these basic functions, the AT Interface offers a
number of modes such as autoconfiguration, base register
area select, and memory map configuration.
2.3 Clock Bus Block
The Clock Bus Block is included in the Link Card design to
provide a physical bus among all Link and MAC Cards that
form a station. The consruction of the bus is a twenty pin
ribbon cable capable of supporting 9 signals. Each signal is
surrounded on either side by a ground line to reduce crosstalk.
2.7 PLAYER Device Block
The Physical Layer Controller is a part of National Semiconductor’s FDDI Chip Set. It implements one Physical Layer
entity as defined by the ANSI X3T9.5 PHY standard. The
PLAYER device performs the 4B/5B encoding and decoding, serialization and deserialization of data, repeat filter,
and line state control and detection. It also contains a configuration switch. The PLAYER device supports many types
of station configurations as allowed by the standard.
Although tailored to the FDDI specification, the PLAYER device is also well suited for use in high speed point-to-point
communication links over optical fibers and coaxial cable.
2.4 CDD Device Block
The Clock Distribution Device is a clock generation and distribution device intended for use in FDDI networks. The device provides the complete set of clocks required to convert
byte wide data to serial format for fiber medium transmission and to move byte wide data between the PLAYER and
BMAC devices in various station configurations. 12.5 MHz
and 125 MHz differential ECL clocks are generated for the
conversion of data to serial format and 12.5 MHz and
125 MHz TTL clocks are generated for the byte wide data
transfers.
2.8 Transceiver Block
The transceiver block consists of two parts: fiber optic receiver and fiber optic transmitter. The Link Card supports
the following FDDI optical transceiver modules:
AT&T ODL 125 Lightwave Data Links
Sumitomo DM-742 1300nm Data Link
Any Transceiver pair which supports the
AT&T footprint 2.1.8.1 pin format
composed of 2 independent 16-pin DIP (footprints)
See Appendix A of the User’s Guide for a detailed footprint
description.
5
2.0 Link Card System Description (Continued)
2.9 Installation
A.1.1 Setup
TL/F/11122 – 5
6
2.0 Link Card System Description (Continued)
A.1.1 Setup (Continued)
TL/F/11122 – 6
7
3.0 MAC Card
3.1 MAC CARD DESCRIPTION
3.3 MAC CARD SYSTEM DESCRIPTION
The DP83291EB FDDI MAC Layer Evaluation Board is a
PC-AT compatible board that implements the MAC Layer
functions of the FDDI standard. The Board utilizes the National Semiconductor DP83261 BMACTM device along with
PALÉ-based Buffer Management Logic to implement a simple MAC Layer.
The MAC Evaluation Board is designed to perform simple
transmission and reception scenarios. One 8k and 8 Static
RAM is used for Transmission and another is used for Reception and Status. See Figure 3 for a detailed block diagram.
On Transmission, the Transmission Counter is used to address the TxÐRAM where the frames to be transmitted are
written. The Transmit Sequencer controls the sequencing of
frames across the BMAC device’s MAC Request Interface.
On Reception, the Receive Sequencer controls the sequencing of frames across the BMAC device’s MAC indicate interface. Transmit and Receive Status is stored and
multiplexed into the RxÐRAM between frames. The Receive Counter is used to address the RxÐRAM. The Receive Counter is under the control of the Receive Sequencer. The Copy PAL monitors the addressing information
across the BMAC device and determines whether to continue to copy frames. This is signaled to the Receive Sequencer which then adjusts the Receive Counter accordingly.
3.2 MAC CARD FEATURES
The MAC card offers many features on a convenient platform:
# PC-AT compatible full size card
# Dual ported memory interfaceÐfull duplex data path
# Interfaces to link cards for DAS or SAS configurations
# Supported by demonstration software
# Utilizes DP83261 BMAC device
# Full network statistics
# Supports asynchronous and synchronous transmission
classes
# PAL based buffer management
TL/F/11122 – 7
FIGURE 3. MAC Card Block Diagram
8
3.0 MAC Card (Continued)
The TxÐRAM contains either one maximum size frame or
up to 16 frames of 512 bytes or less. The RxÐRAM may be
filled with up to 8 frames.
0400 – 0FFF reserved for future use
1000 – 3FFF reserved for future use
See Figure 4 .
The DP8570A is used as a timer on this board and provides
support for Station Management. Its registers are accessed
via the PC interface and is memory mapped.
The PC interface provides access to the Transmit and Receive RAM in addition to the Board Registers and BMAC
device. The Board Registers include a Mode, Function and
Status Register.
MAC Registers
0000 – 00FF BMAC Device Registers
0100 – 01FF Board Registers
BMAC Device Registers
The BMAC Device Registers are mapped directly into the
64k segment of the address space as defined in the BMAC
Device Datasheet.
3.4 ADDRESS MAPPING
PC BUS INTERFACE
MAC Evaluation Board Registers
The board registers are mapped into the 64k segment of the
address space as:
0100 Mode Register
0140 Function Register
0180 Status Register
01A0 Timer Registers
01C0 Board Reset
Board Address Mapping
The Evaluation Board Control Bus is mapped into a 64k
segment within the lowest 1M of the PC address space. The
64k offset is selected (by a jumper) as shown below:
Sel e 0
offset is C0000
Sel e 1
offset is D0000
64k Segment Mapping
The 64k segment reserved for the evaluation board is divided as shown below:
0000 – 3FFF Used for control registers (See Figure 3 )
Note: For MAC1 add 200th to each address.
4000 – 7FFF reserved
8000 – 9FFF used to access 8k TxÐRAM
A000 – BFFF shadow to TxÐRAM
C000 – DFFF used to access 8k RxÐRAM
E000 – FFFF shadow of RxÐRAM
Board Register Address Mapping
The address space used for control registers is divided into
512 byte pages for each PHY or MAC. The MAC is selectable as either MAC 0 or MAC 1.
0000 – 01FF MAC0
0200 – 03FF MAC1
BMAC 0 REGISTERS
0000 – 00FF
BOARD 0 REGISTERS
00FF – 01FF
BMAC 1 REGISTERS
0200 – 02FF
BOARD 1 REGISTERS
0300 – 03FF
RESERVED
0400 – 0FFF
RESERVED
1000 – 3FFF
RESERVED
4000 – 7FFF
TX RAM
8000 – 9FFF
SHADOW TX RAM
A000 – BFFF
RX RAM
C000 – DFFF
SHADOW RX RAM
E000 – FFFF
FIGURE 4. Board Address Map
9
3.0 MAC Card (Continued)
Interrupts
3.5 MAC Board Installation
The MAC Card requires a full length slot. It can be installed
in either an AT or XT slot. There are several options that
can be programmed via jumpers provided on the MAC Card.
The position of the jumpers on the board are shown in
Figure 5 .
JUMPER SETTINGS
J1: Base Address, MAC Select, Interrupt and Option Selection
J1 is used to select the Base Address of the MAC Card,
MAC Number, interrupt to be used for the interconnected
MAC and Link Cards and Option Selections on the BMAC
device. The possible settings and factory defaults follow.
TL/F/11122–8
Factory Default Shown
TL/F/11122 – 9
Factory Default e IRQ4
MAC Select
TL/F/11122 – 10
Factory Default e MAC0
TL/F/11122 – 11
FIGURE 5. MAC Card Jumper Locations
10
3.0 MAC Card (Continued)
Base Address Select
TL/F/11122 – 12
Factory Default e D000
Options Selection
TL/F/11122 – 13
Factory Default e Options Controlled by SAT Option in Board Mode Register
11
3.0 MAC Card (Continued)
J2: Latch Clock Select
J5: Master Clock Select
J2 is used to select which phase of the LBC to transfer data
between the Link and MAC Cards. This is used to optimize
set up and hold time on data transfers between the BMAC
and PLAYER devices when using a bus. This jumper
should always be left at the default setting (LBC5).
J2: Latch Clock Select
J5 programs whether or not this board provides the master
clock for the node. Typically in a DAS or SAS configuration,
only a single MAC is used. The MAC card will provide the
clock for the entire system. If two MACs are present in the
node, only one of the MAC Boards should provide a clock.
This jumper should only be programmed when configuring Dual MAC systems.
J5: Master Clock Select
TL/F/11122 – 14
J3: CDD Device Feedback Select
J3 is used to select which phase of the LBC that the CDD
device will use in its feedback loop This jumper should be
left at the default setting (LBC1).
J3: CDD Device Feedback Select
TL/F/11122 – 17
INSTALLING THE BOARD WITH A LINK CARD
The MAC Card should be inserted into the PC-AT or XT slot
along with the Link Card. Make sure that the board is inserted into the connectors accurately. The next step is to connect the cabling between the MAC Card and the Link Card.
Two configurations are possible, Single Attach Station
(SAS) and a Dual Attach Station (DAS).
SAS Configuration
To implement a SAS Configuration a MAC Card and a Link
Card are inserted into two slots on the AT. Two cables are
required. First connect the 20-Pin Clock Cable into the 20
Pin header on the top of both the Link Card and MAC Card.
Then connect the 50-Pin Cable between the two ‘‘A’’ port
connectors on the Cards. This is the connector farthest
from the back of the AT chassis (see Figure 5 ). Make sure
the cables are properly engaged with the pins by pressing
down on the top of the cable with your thumbs. Once the
cables have been attached inspect the cards to make sure
that they are straight in the connectors. Pressing in the cables has a tendancy to skew the cards in the slots.
TL/F/11122 – 15
J4: Reference Select
J4 is used to select either the clock on the clock bus or the
local crystal oscillator as a reference. In order to provide
less skew between the Link and the MAC Cards, the CDD
device is locked to the Clock Bus signal. This jumper
should be left at he default setting.
J4 Reference Select
DAS Configuration
To implement a DAS Configuration an additional Link Card
is required. (Two Link Cards a 1 MAC Card implements a
DAS). Insert a MAC Card and two Link Cards adjacent to
each other as shown in Figure 1. Connect the Cable between the Link Cards as shown, then connect the Clock Bus
Cable and the final Data Cable between the Link and MAC
Cards as shown. Note that the clock cable must attach to all
three boards. Make sure the cables are properly engaged
with the pins on the cards. Also confirm that the cards are
straight in the card cage after connecting the cables.
TL/F/11122 – 16
12
13
DP83200EB FDDI AT Evaluation Kit
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