Serially Controlled, ±15 V/+12 V/±5 V, 8-Channel/ 4-Channel, iCMOS Multiplexers/Matrix Switches ADG1438/ADG1439 FEATURES FUNCTIONAL BLOCK DIAGRAM ADG1438 ADG1439 S1 S1A DA S4A D S1B DB S4B APPLICATIONS INPUT SHIFT REGISTER Relay replacement Audio and video routing Automatic test equipment Data acquisition systems Temperature measurement systems Avionics Battery-powered systems Communication systems Medical equipment INPUT SHIFT REGISTER SDO SCLK SYNC DIN RESET Figure 1. SDO SCLK SYNC DIN RESET 08496-002 S8 08496-001 Serial interface up to 50 MHz SDO daisy-chaining option 9.5 Ω on resistance @ 25°C 1.6 Ω on-resistance flatness Fully specified at ±15 V/+12 V/±5 V 3 V logic-compatible inputs Rail-to-rail operation 20-lead TSSOP and 20-lead ,4 mm × 4 mm LFCSP packages Figure 2. GENERAL DESCRIPTION The ADG1438 and ADG1439 are CMOS analog matrix switches with a serially controlled 3-wire interface. The ADG1438 is an 8-channel matrix switch, and the ADG1439 is a dual 4-channel matrix switch. The ADG1438/ADG1439 use a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The output of the shift register, SDO, enables a number of the ADG1438/ADG1439 parts to be daisy-chained. On power-up, the internal shift register contains all zeros, and all switches are in the off state. Each switch conducts equally well in both directions when on, making these parts suitable for both multiplexing and demultiplexing applications. Because each switch is turned on or off by a separate bit, these parts can also be configured as a type of switch array, where any, all, or none of the eight switches can be closed at any time. The input signal range extends to the supply rails. All channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. iCMOS® construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 50 MHz serial interface. 9.5 Ω on resistance. 1.6 Ω on-resistance flatness. 3 V logic-compatible digital input, VINH = 2.0 V, VINL = 0.8 V. Table 1. Related Devices Part No. ADG1408/ADG1409 Description Low on resistance, parallel interface, 4-/8-channel ±15 V multiplexers Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADG1438/ADG1439 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 10 Applications ....................................................................................... 1 ESD Caution................................................................................ 10 Functional Block Diagram .............................................................. 1 Pin Configurations and Function Descriptions ......................... 11 General Description ......................................................................... 1 Typical Performance Characteristics ........................................... 13 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 16 Revision History ............................................................................... 2 Terminology .................................................................................... 18 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 19 ±15 V Dual Supply ....................................................................... 3 Serial Interface ............................................................................ 19 12 V Single Supply ........................................................................ 5 Input Shift Register .................................................................... 19 ±5 V Dual Supply ......................................................................... 7 Power-On Reset .......................................................................... 19 Continuous Current per Channel .............................................. 8 Daisy-Chaining ........................................................................... 19 Timing Characteristics ................................................................ 9 Outline Dimensions ....................................................................... 20 Timing Diagram ........................................................................... 9 Ordering Guide .......................................................................... 20 Absolute Maximum Ratings.......................................................... 10 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG1438/ADG1439 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = –15 V ± 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) ADG1438 ADG1439 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current +25°C −40°C to +85°C −40°C to +125°C VSS to VDD 9.5 11.5 0.55 14 1 1.6 1.5 1.9 2.15 ±0.05 ±0.15 ±0.05 ±0.25 ±0.25 ±0.01 ±0.3 16 1.7 2.3 ±1 ±2 ±3 ±1.5 ±12 ±6 ±3 ±12 2.0 0.8 ±0.001 ±0.1 Digital Input Capacitance, CIN LOGIC OUTPUTS (SDO) Output Low Voltage, VOL 1 High Impedance Leakage Current 4 0.4 0.6 Ω max Ω typ Ω max Ω typ VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS = −10 mA; see Figure 27. VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS = −10 mA. VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS = −10 mA. Ω max nA typ nA max nA typ nA max nA max nA typ nA max V min V max μA typ μA max pF typ VDD = +16.5 V, VSS = −16.5 V. VS = ±10 V, VD = ט10 V; see Figure 28. VS = ±10 V, VD = ט10 V; see Figure 28. VS = VD = ±10 V; see Figure 29. VIN = VGND or VL. ISINK = 3 mA. ISINK = 6 mA. 4 55 ns typ RL = 100 Ω, CL = 35 pF. ns min ns typ ns max pC typ VS1 = VS2 = 10 V; see Figure 31. RL = 100 Ω, CL = 35 pF. VS = 10 V; see Figure 30. VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34. RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 36. 0.001 30 Transition Time, tTRANSITION V Ω typ Test Conditions/Comments V max V max μA typ μA max pF typ ±1 High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 Break-Before-Make Time Delay, tBBM Unit Charge Injection 80 100 4 Off Isolation −70 dB typ Channel-to-Channel Crosstalk −70 dB typ Total Harmonic Distortion (THD + N) 0.057 % typ 120 130 Rev. 0 | Page 3 of 20 ADG1438/ADG1439 Parameter −3 dB Bandwidth ADG1438 ADG1439 Insertion Loss CS (Off ) CD (Off ) ADG1438 ADG1439 CD, CS (On) ADG1438 ADG1439 POWER REQUIREMENTS IDD +25°C −40°C to +85°C −40°C to +125°C MHz typ MHz typ dB typ 9 pF typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35. f = 1 MHz. 58 28 pF typ pF typ f = 1 MHz. f = 1 MHz. 286 139 pF typ pF typ f = 1 MHz. f = 1 MHz. VDD = +16.5 V, VSS = −16.5 V. Digital inputs = 0 V or VL. 0.001 0.3 1 IL Active – 30 MHz 0.26 IL Active – 50 MHz 0.42 ISS 0.001 0.3 0.5 VDD/VSS 1 Test Conditions/Comments RL = 50 Ω, CL = 5 pF; see Figure 35. 82 130 0.7 1 IL Inactive Unit 0.35 0.55 1 ±4.5/±16.5 Guaranteed by design, not subject to production test. Rev. 0 | Page 4 of 20 μA typ μA max μA typ μA max mA typ mA max mA typ mA max μA typ μA max V min/Vmax Digital inputs = 0 V or VL. Digital inputs toggle between 0 V and VL. Digital inputs toggle between 0 V and VL. Digital inputs = 0 V or VL. ADG1438/ADG1439 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) +25°C −40°C to +85°C −40°C to +125°C Unit 0 to VDD V Ω typ 18 21.5 0.55 26 1.2 1.6 28.5 1.8 5 6 6.9 7.3 ±0.02 ±0.15 ±0.02 ±1 Drain Off Leakage, ID (Off ) ±0.25 ±0.25 ±0.05 ±0.3 ±3 ±1.5 ±12 ±6 ±3 ±12 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current 2.0 0.8 ±0.001 ±0.1 Digital Input Capacitance, CIN LOGIC OUTPUTS (SDO) Output Low Voltage, VOL 1 High Impedance Leakage Current 4 0.4 0.6 V min V max μA typ μA max pF typ 115 ns typ 60 Transition Time, tTRANSITION nA max nA max nA typ nA max 4 ±1 High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 Break-Before-Make Time Delay, tBBM nA max nA typ V max V max μA typ μA max pF typ 0.001 ns min ns typ ns max pC typ Charge Injection 155 195 7 Off Isolation −70 dB typ Channel-to-Channel Crosstalk −70 dB typ −3 dB Bandwidth ADG1438 ADG1439 58 105 MHz typ MHz typ 235 260 Rev. 0 | Page 5 of 20 VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = −10 mA. VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = −10 mA. Ω max nA typ ±2 VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = −10 mA; see Figure 27. Ω max Ω typ LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ADG1438 ADG1439 Channel On Leakage, ID, IS (On) Ω max Ω typ Test Conditions/Comments VDD = 10.8 V. VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28. VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28. VS = VD = 1 V or 10 V; see Figure 29. VIN = VGND or VL. ISINK = 3 mA. ISINK = 6 mA. RL = 100 Ω, CL = 35 pF. VS1 = VS2 = 8 V; see Figure 31. RL = 100 Ω, CL = 35 pF. VS = 8 V; see Figure 30. VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34. RL = 50 Ω, CL = 5 pF; see Figure 35. ADG1438/ADG1439 −40°C to +85°C Parameter Insertion Loss +25°C 1.3 −40°C to +125°C CS (Off ) CD (Off ) ADG1438 ADG1439 CD, CS (On) ADG1438 ADG1439 POWER REQUIREMENTS IDD 14 pF typ Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35. f = 1 MHz. 86 42 pF typ pF typ f = 1 MHz. f = 1 MHz. 295 145 pF typ pF typ f = 1 MHz. f = 1 MHz. VDD = 13.2 V. Digital inputs = 0 V or VL. 0.001 1 IL Inactive 0.3 1 IL Active – 30 MHz 0.26 IL Active – 50 MHz 0.42 ISS 0.001 0.3 0.5 VDD 1 0.35 0.55 1 5/16.5 Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 20 Unit dB typ μA typ μA max μA typ μA max mA typ mA max mA typ mA max μA typ μA max V min/Vmax Digital inputs = 0 V or VL. Digital inputs toggle between 0 V and VL. Digital inputs toggle between 0 V and VL. Digital inputs = 0 V or VL. ADG1438/ADG1439 ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to VDD, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (ΔRON) On-Resistance Flatness (RFLAT(ON)) +25°C −40°C to +85°C −40°C to +125°C VSS to VDD 21 25 0.6 29 1.3 1.7 32 1.9 5.2 6.4 7.3 7.6 Unit V Ω typ Ω max Ω typ Ω max Ω typ Drain Off Leakage, ID (Off ) ADG1438 ADG1439 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current High Impedance Leakage Current ±0.02 ±0.15 ±0.02 ±0.25 ±0.25 ±0.05 ±0.3 ±1 ±2 ±3 ±1.5 ±12 ±6 ±3 ±12 2.0 0.8 ±0.001 4 0.4 0.6 0.001 ±1 High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 Break-Before-Make Time Delay, tBBM 4 150 80 Transition Time, tTRANSITION VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5V, IS = −10 mA. VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V, IS = −10 mA. VDD = +5.5 V, VSS = −5.5 V. ±0.1 Digital Input Capacitance, CIN LOGIC OUTPUTS (SDO) Output Low Voltage, VOL 1 VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V, IS = −10 mA; see Figure 27. Ω max LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Test Conditions/Comments Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion (THD + N) 200 230 5 −70 −70 0.14 −3 dB Bandwidth ADG1438 ADG1439 Insertion Loss CS (Off ) 62 116 1.2 12 315 350 nA typ nA max nA typ nA max nA max nA typ nA max V min V max μA typ μA max pF typ VS = ±4.5 V, VD = ט4.5 V; see Figure 28. VS = VD = ±4.5 V; see Figure 29. VIN = VGND or VL. V max V max μA typ μA max pF typ ISINK = 3 mA. ISINK = 6 mA. ns typ ns min ns typ ns max pC typ dB typ dB typ % typ RL = 100 Ω, CL = 35 pF. VS1 = VS2 = 3 V; see Figure 31. RL = 100 Ω, CL = 35 pF. VS = 3 V; see Figure 30. VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34. RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36. RL = 50 Ω, CL = 5 pF; see Figure 35. MHz typ MHz typ dB typ pF typ Rev. 0 | Page 7 of 20 VS = ±4.5 V, VD = ט4.5 V; see Figure 28. RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35. f = 1 MHz. ADG1438/ADG1439 Parameter CD (Off ) ADG1438 ADG1439 CD, CS (On) ADG1438 ADG1439 POWER REQUIREMENTS IDD +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments 76 38 pF typ pF typ f = 1 MHz. f = 1 MHz. 311 151 pF typ pF typ f = 1 MHz. f = 1 MHz. VDD = +5.5 V, VSS = −5.5 V. Digital inputs = 0 V or VL. 0.001 1 IL Inactive 0.3 1 IL Active – 30 MHz IL Active – 50 MHz ISS 0.26 0.3 0.35 0.5 0.55 0.42 0.001 1 ±4.5/±16.5 VDD/VSS 1 μA typ μA max μA typ μA max mA typ mA max mA typ mA max μA typ μA max V min/Vmax Digital inputs = 0 V or VL. Digital inputs toggle between 0 V and VL. Digital inputs toggle between 0 V and VL. Digital inputs = 0 V or VL. Guaranteed by design, not subject to production test. CONTINUOUS CURRENT PER CHANNEL Table 5. ADG1438, One Channel On Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 20-Lead TSSOP (θJA = 112.6°C/W) 20-Lead LFCSP (θJA = 30.4°C/W) 12 V Single Supply 20-Lead TSSOP (θJA = 112.6°C/W) 20-Lead LFCSP (θJA = 30.4°C/W) 5 V Dual Supply 20-Lead TSSOP (θJA = 112.6°C/W) 20-Lead LFCSP (θJA = 30.4°C/W) 1 25°C 85°C 125°C Unit 169 295 97 139 48 55 mA max mA max 161 281 93 135 47 54 mA max mA max Test Conditions/Comments VDD = +13.5 V, VSS = −13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = −4.5 V 122 214 76 114 43 51 mA max mA max 25°C 85°C 125°C Unit 125 220 77 116 43 52 mA max mA max 119 210 74 112 42 51 mA max mA max 159 90 93 59 47 37 mA max mA max Guaranteed by design, not subject to production test. Table 6. ADG1439, One Channel On Per Multiplexer Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 20-Lead TSSOP (θJA = 112.6°C/W) 20-Lead LFCSP (θJA = 30.4°C/W) 12 V Single Supply 20-Lead TSSOP (θJA = 112.6°C/W) 20-Lead LFCSP (θJA = 30.4°C/W) 5 V Dual Supply 20-Lead TSSOP (θJA = 112.6°C/W) 20-Lead LFCSP (θJA = 30.4°C/W) 1 Test Conditions/Comments VDD = +13.5 V, VSS = −13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = −4.5 V Guaranteed by design, not subject to production test. Rev. 0 | Page 8 of 20 ADG1438/ADG1439 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 3). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 7. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 3 t12 Limit at TMIN, TMAX 20 9 9 5 5 5 5 15 5 5 40 15 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK active edge setup time Data setup time Data hold time SCLK active edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK active edge ignored SCLK active edge to SYNC falling edge ignored SCLK rising edge to SDO valid Minimum RESET pulse width 1 Guaranteed by design and characterization, not production tested. Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 3 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode. 2 TIMING DIAGRAM t10 t1 t9 SCLK t8 t2 t3 t4 t7 SYNC t5 DIN t6 DB7 DB0 08496-003 RESET t12 Figure 3. Serial Write Operation t1 SCLK 8 t8 t3 t4 16 t9 t2 t7 SYNC t5 DIN t6 DB7 DB0 DB0 DB7 INPUT WORD FOR DEVICE N + 1 INPUT WORD FOR DEVICE N t11 DB0 DB7 UNDEFINED INPUT WORD FOR DEVICE N 08496-004 SDO Figure 4. Daisy-Chain Timing Diagram Rev. 0 | Page 9 of 20 ADG1438/ADG1439 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 8. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs 1 Digital Inputs1 Continuous Current, Sx or Dx Pins Peak Current, Sx or Dx Pins (Pulsed at 1 ms, 10% Duty Cycle Max) TSSOP LFCSP Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature (Pb-Free) Time at Peak Temperature 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V −0.3 V to +7 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VL + 0.3 V or 30 mA, whichever occurs first Table 5 and Table 6 specifications + 15% 300 mA 400 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. THERMAL RESISTANCE Table 9. Thermal Resistance Package Type 20 Lead TSSOP (4-Layer Board) 20-Lead LFCSP (4-Layer Board and Exposed Paddle Soldered to VSS) ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 260(+0/−5)°C 10 sec to 40 sec Overvoltages at the analog and digital inputs are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. 0 | Page 10 of 20 θJA 112.6 30.4 θJC 50 N/A Unit °C/W °C/W ADG1438/ADG1439 19 VL DIN 3 18 SDO ADG1438 GND 4 20 19 18 17 16 20 SYNC VDD 2 DIN GND S1 S2 S3 15 S5 S2 7 14 S6 S3 8 13 S7 S4 9 12 S8 D 10 11 NC NC = NO CONNECT PIN 1 INDICATOR ADG1438 TOP VIEW (Not to Scale) 15 RESET 14 VSS 13 S5 12 S6 11 S7 S4 NC D NC S8 S1 6 08496-005 NC 5 1 2 3 4 5 6 7 8 9 10 17 RESET TOP VIEW (Not to Scale) 16 VSS 08496-106 SCLK 1 VDD SCLK SYNC VL SDO PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS. Figure 5. ADG1438 Pin Configuration (TSSOP) Figure 6. ADG1438 Pin Configuration (LFCSP) Table 10. ADG1438 Pin Function Descriptions Pin No. TSSOP LFCSP 1 19 Mnemonic SCLK 2 3 20 1 VDD DIN 4 5 6 7 8 9 10 11 12 13 14 15 16 2 7 3 4 5 6 8 9 10 11 12 13 14 GND NC S1 S2 S3 S4 D NC S8 S7 S6 S5 VSS 17 15 RESET 18 16 SDO 19 20 17 18 VL SYNC EPAD Description Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Most Positive Power Supply Potential. Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground (0 V) Reference. No Connect. Source Terminal 1. Can be an input or an output. Source Terminal 2. Can be an input or an output. Source Terminal 3. Can be an input or an output. Source Terminal 4. Can be an input or an output. Drain Terminal. Can be an input or an output. No Connect. Source Terminal 8. Can be an input or an output. Source Terminal 7. Can be an input or an output. Source Terminal 6. Can be an input or an output. Source Terminal 5. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. Active Low Logic Input. When this pin is low, all switches are open, and the appropriate registers are cleared to 0. Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. This is an open-drain output that should be pulled to the VL supply with an external 1 kΩ resistor. Logic Power Supply Input. Operates from 2.7 V to 5.5 V. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch condition. The exposed pad is tied to the substrate, VSS. Rev. 0 | Page 11 of 20 19 VL DIN 3 18 SDO ADG1439 20 19 18 17 16 20 SYNC VDD 2 DIN GND S1A S2A S3A 15 S1B S2A 7 14 S2B S3A 8 13 S3B S4A 9 12 S4B DA 10 11 DB NC = NO CONNECT ADG1439 TOP VIEW (Not to Scale) 15 14 13 12 11 RESET VSS S1B S2B S3B NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS. 08496-107 NC 5 S1A 6 PIN 1 INDICATOR S4A 6 DA 7 NC 8 DB 9 S4B 10 17 RESET TOP VIEW (Not to Scale) 16 VSS GND 4 1 2 3 4 5 08496-108 SCLK 1 VDD SCLK SYNC VL SDO ADG1438/ADG1439 Figure 7. ADG1439 Pin Configuration (TSSOP) Figure 8. ADG1439 Pin Configuration (LFCSP) Table 11. ADG1439 Pin Function Descriptions Pin No. TSSOP LFCSP 1 19 Mnemonic SCLK 2 3 20 1 VDD DIN 4 5 6 7 8 9 10 11 12 13 14 15 16 2 8 3 4 5 6 7 9 10 11 12 13 14 GND NC S1A S2A S3A S4A DA DB S4B S3B S2B S1B VSS 17 15 RESET 18 16 SDO 19 20 17 18 VL SYNC EPAD Description Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Most Positive Power Supply Potential. Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground (0 V) Reference. No Connect. Source Terminal 1A. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Source Terminal 3A. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Drain Terminal A. Can be an input or an output. Drain Terminal B. Can be an input or an output. Source Terminal 4B. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0. Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. This is an open-drain output that should be pulled to the VL supply with an external 1 kΩ resistor. Logic Power Supply Input. Operates from 2.7 V to 5.5 V. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch condition. The exposed pad is tied to the substrate, VSS. Rev. 0 | Page 12 of 20 ADG1438/ADG1439 TYPICAL PERFORMANCE CHARACTERISTICS 16 18 VDD = +10V VSS = –10V 14 VDD = +13.5V VSS = –13.5V 15 ON RESISTANCE (Ω) VDD = +12V VSS = –12V 10 8 6 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V 4 12 TA = +125°C TA = +85°C 9 TA = +25°C 6 TA = –40°C 3 VDD = +15V VSS = –15V TA = 25°C IS = –10mA 0 –16.5 –13.5 –10.5 –7.5 –4.5 –1.5 4.5 1.5 7.5 10.5 13.5 16.5 VS, VD (V) 0 –15 0 5 10 15 Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply 35 30 VDD = +3.V VSS = –3.V 30 25 VDD = +5.0V VSS = –5.0V 20 15 VDD = +5.5V VSS = –5.5V 10 VDD = +7V VSS = –7V 5 TA = +25°C 10 TA = –40°C 5 VDD = +5V VSS = –5V TA = 25°C IS = –10mA –5 TA = +85°C 15 –3 1 –1 3 5 7 VS, VD (V) 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 08496-010 0 –7 TA = +125°C 20 12 08496-011 25 ON RESISTANCE (Ω) VDD = +4.5V VSS = –4.5V 08496-007 ON RESISTANCE (Ω) –5 VS, VD (V) Figure 9. On Resistance as a Function of VD (VS), Dual Supply VS, VD (V) Figure 10. On Resistance as a Function of VD (Vs), Dual Supply Figure 13. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Dual Supply 40 25 VDD = +5V VSS = 0V 35 20 30 25 20 VDD = +10.8V VSS = 0V 15 ON RESISTANCE (Ω) VDD = +8V VSS = 0V VDD = +12V VSS = 0V TA = +125°C 15 TA = +85°C TA = +25°C 10 TA = –40°C 10 5 0 VDD = +15V VSS = 0V TA = 25°C IS = –10mA 0 1.5 3.0 4.5 6.0 7.5 9.0 5 VDD = +13.2V VSS = 0V 10.5 12.0 13.5 VDD = +12V VSS = 0V 15.0 VS, VD (V) 0 08496-008 ON RESISTANCE (Ω) –10 08496-009 2 08496-006 ON RESISTANCE (Ω) 12 0 2 4 6 8 10 VS, VD (V) Figure 11. On Resistance as a Function of VD (VS), Single Supply Figure 14. On Resistance as a Function of VD (VS) for Different Temperatures, 12 V Single Supply Rev. 0 | Page 13 of 20 ADG1438/ADG1439 500 1.0 VDD = +15V VSS = –15V VBIAS = +10V/–10V VL = 5.5V ID (OFF) –+ 400 IS (OFF) +– IDD (µA) 0 IS (OFF) –+ –0.5 300 200 ID, IS (ON) – – 100 ID (OFF) +– –1.5 0 20 40 60 80 100 120 TEMPERATURE (°C) VL = 2.7V 0 0 0.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 18. IDD vs. Logic Level 50 10 TA = 25°C 40 6 CHARGE INJECTION (pC) ID, IS (ON) ++ ID (OFF) –+ 4 IS (OFF) +– 2 0 IS (OFF) –+ ID, IS (ON) –– ID (OFF) +– –4 0 20 40 60 80 TEMPERATURE (°C) 100 120 20 VDD = +12V VSS = 0V 10 0 VDD = +15V VSS = –15V –10 –20 –30 –15 08496-016 –2 VDD = +5V VSS = –5V 30 –10 –5 0 5 10 15 VS (V) 08496-019 VDD = +5V VSS = –5V VBIAS = +4.5V/–4.5V 8 Figure 19. Charge Injection vs. Source Voltage Figure 16. Leakage Current as a Function of Temperature, 5 V Dual Supply 300 10 VDD = 12V VSS = 0V VBIAS = 1V/10V 8 ID, IS (ON) ++ 250 6 200 4 TIME (ns) ID (OFF) –+ IS (OFF) +– 2 IS (OFF) –+ VDD = +5V, VSS = –5V 150 100 VDD = +12V, VSS = 0V 0 –2 50 ID, IS (ON) –– ID (OFF) +– 0 20 40 60 80 TEMPERATURE (°C) 100 120 0 08496-017 –4 VDD = +15V, VSS = –15V –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 20. Transition Time vs. Temperature Figure 17. Leakage Current as a Function of Temperature, 12 V Single Supply Rev. 0 | Page 14 of 20 120 08496-120 LEAKAGE CURRENT (nA) 2.0 LOGIC LEVEL (V) Figure 15. Leakage Current as a Function of Temperature, 15 V Dual Supply LEAKAGE CURRENT (nA) 1.5 08496-018 –1.0 08496-015 LEAKAGE CURRENT (nA) 0.5 IDD PER LOGIC INPUT TA= 25°C ID, IS (ON) ++ ADG1438/ADG1439 0 0 TA = 25°C VDD = +15V VSS = –15V –0.5 INSERTION LOSS (dB) –40 –60 –80 –100 –1.0 TA = 25°C VDD = +15V VSS = –15V –1.5 –2.0 –2.5 –3.0 –3.5 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) –4.0 08496-121 –120 1k 1M 10M 100M Figure 24. ADG1438 On Response vs. Frequency 0 0.20 TA = 25°C VDD = +15V VSS = –15V LOAD = 110Ω TA = 25°C 0.18 0.16 VDD = 5V, VSS = –5V, VS = 5V p-p 0.14 –40 THD + N (%) CROSSTALK (dB) 100k FREQUENCY (Hz) Figure 21. Off Isolation vs. Frequency –20 10k 08496-124 OFF ISOLATION (dB) –20 –60 –80 0.12 0.10 0.08 VDD = 15V, VSS = –15V, VS = 10V p-p 0.06 0.04 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 08496-122 0 20 0 TA = 25°C VDD = +15V VSS = –15V TA = 25°C VDD = +15V VSS = –15V –20 NO DECOUPLING CAPACITORS –40 ACPSRR (dB) –40 –60 –60 DECOUPLING CAPACITORS –80 –80 –100 –100 100k 1M 10M 100M FREQUENCY (Hz) 1G 08496-123 CROSSTALK (dB) 15 Figure 25. THD + N vs. Frequency 0 –120 10k 10 FREQUENCY (kHz) Figure 22. ADG1438 Crosstalk vs. Frequency –20 5 Figure 23. ADG1439 Crosstalk vs. Frequency –120 1k 10k 100k 1M FREQUENCY (Hz) Figure 26. ACPSRR vs. Frequency Rev. 0 | Page 15 of 20 10M 08496-127 –120 10k 08496-026 0.02 ADG1438/ADG1439 TEST CIRCUITS V A IDS D A VD Figure 27. On Resistance ID (ON) ID (OFF) VS 08496-020 VS S S NC NC = NO CONNECT Figure 28. Off Leakage VDD VSS VDD VSS SYNC S1 50% VS1 S2 TO S7 D GND VS1 VS8 RL 300Ω CL 35pF VOUT 90% VOUT 90% tOFF * SIMILAR CONNECTION FOR ADG1439 08496-023 S8 tON Figure 30. Switching Times, tON/tOFF 3V VDD VSS VDD VSS SYNC S1 0V S2 TO S7 VS S8 80% ADG14381 80% OUTPUT D OUTPUT GND 100Ω tBBM 1SIMILAR CONNECTION FOR ADG1439. Figure 31. Break-Before-Make Delay, tBBM Rev. 0 | Page 16 of 20 35pF 08496-024 VS1 = VS8 A VD Figure 29. On Leakage 50% ADG1438* D 08496-022 IS (OFF) D 08496-021 S ADG1438/ADG1439 VDD VSS VDD VSS 3V SYNC ADG1438 1 RS VOUT S D VOUT ΔVOUT SWITCH OFF INPUT LOGIC GND VS SWITCH ON CL 1nF 08496-025 QINJ = CL × ΔVOUT 1SIMILAR CONNECTION FOR ADG1439. Figure 32. Charge Injection VSS VDD 0.1µF NETWORK ANALYZER VSS S 0.1µF VDD 50Ω 50Ω S VS 50Ω VS D RL 50Ω ADG1438 GND D VOUT VOUT VS 08496-027 GND INSERTION LOSS = 20 log Figure 33. Off Isolation VDD RL 50Ω VOUT WITH SWITCH VOUT WITHOUT SWITCH VSS 0.1µF VDD VDD VSS VSS 0.1µF 0.1µF S1 D S2 VS VOUT Figure 35. Insertion Loss 0.1µF VOUT RL 50Ω ADG1438 OFF ISOLATION = 20 log NETWORK ANALYZER NETWORK ANALYZER VSS 08496-029 VDD VSS 0.1µF VDD R 50Ω RS S ADG1438 IN GND ADG1438 GND 08496-028 VOUT VS VS V p-p D VIN CHANNEL-TO-CHANNEL CROSSTALK = 20 log AUDIO PRECISION VSS Figure 34. Channel-to-Channel Crosstalk RL 10kΩ Figure 36. THD + Noise Rev. 0 | Page 17 of 20 VOUT 08496-030 VDD 0.1µF ADG1438/ADG1439 TERMINOLOGY tBBM Off time measured between the 80% point of both switches when switching from one address state to another. RON Ohmic resistance between Terminal D and Terminal S. ΔRON Difference between the RON of any two channels. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum values of on resistance as measured over the specified analog signal range.. IS (Off) Source leakage current when the switch is off. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ID (Off) Drain leakage current when the switch is off. ISS Negative supply current. ID, IS (On) Channel leakage current when the switch is on. VD (VS) Analog voltage on Terminal D (drain terminal) and Terminal S (source terminals, S1 to S8). CS (Off) Channel input capacitance for off condition. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth Frequency at which the output is attenuated by 3 dB. CD (Off) Channel output capacitance for off condition. On Response Frequency response of the on switch. CD, CS (On) On switch capacitance. Total Harmonic Distortion (THD + N) Ratio of the harmonic amplitude plus noise of the signal to the fundamental. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and the switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and the switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital input and the switch on condition when switching from one address state to another. AC Power Supply Rejection Ratio (ACPSRR) A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Insertion Loss The loss due to the on resistance of the switch. Rev. 0 | Page 18 of 20 ADG1438/ADG1439 THEORY OF OPERATION The ADG1438 and ADG1439 are serially controlled, 8-channel and dual 4-channel matrix switches, respectively. While providing the normal multiplexing and demultiplexing functions, these devices also provide the user with more flexibility as to where a signal can be routed. Each of the eight bits of the 8-bit write corresponds to one switch of the device. Logic 1 in a particular bit position turns the switch on, whereas Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches on. This feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). Care must be taken, however, in the multiplexing situation where a number of inputs may be shorted together (separated only by the small on resistance of the switch). SERIAL INTERFACE The ADG1438/ADG1439 has a 3-wire serial interface (SYNC, SCLK, and DIN pins) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs (see Figure 3 for a timing diagram of a typical write sequence). The write sequence begins by bringing the SYNC line low. This enables the input shift register. Data from the DIN line is clocked into the 8-bit input shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the ADG1438/ADG1439 compatible with high speed DSPs. Data can be written to the shift register in more or fewer than eight bits. In each case, the shift register retains the last eight bits that are written. When all eight bits are written into the shift register, the SYNC line is brought high again. The switches are updated with the new configuration, and the input shift register is disabled. With SYNC held high, the input shift register is disabled so that further data or noise on the DIN line has no effect on the shift register. Data appears on the SDO pin on the rising edge of SCLK, suitable for daisy-chaining or readback, delayed by eight bits. INPUT SHIFT REGISTER The input shift register is eight bits wide, as shown in Table 12 and Table 13. Each bit controls one switch. These data bits are transferred to the switch register on the rising edge of SYNC. Table 12. ADG1438 Input Shift Register Bit Map1 MSB DB7 S8 1 DB6 S7 DB5 S6 DB4 S5 DB3 S4 DB2 S3 DB1 S2 LSB DB0 S1 Logic 0 = switch off, and Logic 1 = switch on. Table 13. ADG1439 Input Shift Register Bit Map1 MSB DB7 S4B 1 DB6 S3B DB5 S2B DB4 S1B DB3 S4A DB2 S3A DB1 S2A LSB DB0 S1A Logic 0 = switch off, and Logic 1 = switch on. POWER-ON RESET The ADG1438/ADG1439 contain a power-on reset circuit. On power-up of the device, all switches are off, and the internal shift register is filled with zeros and remains so until a valid write takes place. The part also has a RESET pin. When the RESET pin is low, all switches are off, and the appropriate registers are cleared to 0. DAISY-CHAINING For systems that contain several switches, the SDO pin can be used to daisy-chain several devices together. The SDO pin can also be used for diagnostic purposes and to provide serial readback where the user wants to read back the switch contents. The SDO pin is an open-drain output that should be pulled to the VL supply with an external resistor. The SCLK is continuously applied to the input shift register when SYNC is low. If more than eight clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next switch in the chain, a multiswitch interface is constructed. Each switch in the system requires eight clock pulses; therefore, the total number of clock cycles must equal 8N, where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. Gated clock mode reduces power consumption by reducing the active clock time. Rev. 0 | Page 19 of 20 ADG1438/ADG1439 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 37. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 11 10 6 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 090408-B TOP VIEW 0.50 0.40 0.30 Figure 38. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Model ADG1438BRUZ 1 ADG1438BRUZ-REEL71 ADG1438BCPZ-REEL71 ADG1439BRUZ1 ADG1439BRUZ-REEL71 ADG1439BCPZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08496-0-10/09(0) Rev. 0 | Page 20 of 20 Package Option RU-20 RU-20 CP-20-4 RU-20 RU-20 CP-20-4