a CMOS, Low Voltage Serially Controlled, Octal SPST Switches ADG714/ADG715 FEATURES ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface ADG715 I2C™-Compatible Interface 2.7 V to 5.5 V Single Supply 2.5 V Dual Supply 2.5 On Resistance 0.6 On Resistance Flatness 100 pA Leakage Currents Octal SPST Power-On Reset Fast Switching Times TTL/CMOS-Compatible Small TSSOP Package FUNCTIONAL BLOCK DIAGRAMS ADG715 ADG714 S1 D1 S1 D1 S2 D2 S2 D2 S3 D3 S3 D3 S4 D4 S4 D4 S5 D5 S5 D5 S6 D6 S6 D6 S7 D7 S7 D7 S8 D8 S8 D8 INPUT SHIFT REGISTER INTERFACE LOGIC DOUT RESET APPLICATIONS Data Acquisition Systems Communication Systems Relay Replacement Audio and Video Switching SCLK DIN SYNC RESET GENERAL DESCRIPTION The ADG714/ADG715 are CMOS, octal SPST (single-pole, single-throw) switches controlled via either a 2- or 3-wire serial interface. On resistance is closely matched between switches and very flat over the full signal range. Each switch conducts equally well in both directions and the input signal range extends to the supplies. Data is written to these devices in the form of 8 bits, each bit corresponding to one channel. SDA SCL A0 A1 On power-up of these devices, all switches are in the OFF condition, and the internal registers contain all zeros. Low power consumption and operating supply range of 2.7 V to 5.5 V make this part ideal for many applications. These parts may also be supplied from a dual ± 2.5 V supply. The ADG714 and ADG715 are available in a small 24-lead TSSOP package. PRODUCT HIGHLIGHTS The ADG714 uses a 3-wire serial interface that is compatible with SPI , QSPI, and MICROWIRE and most DSP interface standards. The output of the shift register DOUT enables a number of these parts to be daisy chained. 1. 2- or 3-wire serial interface The ADG715 uses a 2-wire serial interface that is compatible with the I2C interface standard. The ADG715 has four hard wired addresses, selectable from two external address pins (A0 and A1). This allows the 2 LSBs of the 7-bit slave address to be set by the user. A maximum of four of these devices may be connected to the bus. 3. Low on resistance, typically 2.5 Ω 2. Single/dual supply operation. The ADG714 and ADG715 are fully specified and guaranteed with 3 V, 5 V, and ± 2.5 V supply rails. 4. Low leakage 5. Power-on reset 6. Small 24-lead TSSOP package SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. I2C is a trademark of Philips Corporation. REV. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Tel: 781/329-4700 www.analog.com Fax: 781/461-3113 © Analog Devices, Inc., 2013 ADG714/ADG715–SPECIFICATIONS1(V Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) B Version –40C +25C to +85C 2.5 4.5 On Resistance Match Between Channels (ΔRON) On Resistance Flatness (R FLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage I S (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage I D, IS (ON) DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH CIN, Digital Input Capacitance2 DIGITAL OUTPUT ADG714 DOUT 2 Output Low Voltage COUT Digital Output Capacitance 0.6 ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.3 ± 0.3 ± 0.1 IIN, Input Leakage Current 0.005 VHYST, Input Hysteresis CIN, Input Capacitance 0.05 VDD 6 LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage V min V max V min V max μA typ μA max V min pF typ ±1 0.4 0.6 20 95 8 15 tOFF ADG715 85 130 Break-Before-Make Time Delay, t D Charge Injection Off Isolation Channel-to-Channel Crosstalk –3 dB Bandwidth CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 8 ±3 –60 –80 –70 –90 155 11 11 22 V min V max μA typ μA max pF typ 0.7 VDD VDD + 0.3 –0.3 0.3 VDD 140 tOFF ADG714 nA typ nA max nA typ nA max nA typ nA max V max pF typ 32 tON ADG715 Unit 0.4 4 Input Low Voltage, VINL DYNAMIC CHARACTERISTICS 2 tON ADG714 ± 0.3 3 DIGITAL INPUTS (SCL, SDA) 2 Input High Voltage, VINH = 5 V 10%, VSS = 0 V, GND = 0 V unless otherwise noted.) 0 V to VDD V Ω typ 5 Ω max 0.4 Ω typ 0.8 Ω max Ω typ 1.2 Ω max 2.4 0.8 0.005 DD 1 20 VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V VD = VS = 1 V, or 4.5 V VIN = VINL or VINH ISINK = 6 mA VIN = 0 V to VDD V max V max ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ VS = 3 V, RL = 300 Ω, CL = 35 pF μA typ μA max 10 Test Conditions/Comments VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RS = 0 Ω, CL = 1 nF RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF VDD = 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. C 1 SPECIFICATIONS ADG714/ADG715 (VDD = 3 V 10%, VSS = 0 V, GND = 0 V unless otherwise noted.) Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) B Version –40C +25C to +85C 6 11 On Resistance Match Between Channels (ΔRON) On Resistance Flatness (R FLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage I S (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage I D, IS (ON) DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH CIN, Digital Input Capacitance2 DIGITAL OUTPUT ADG714 DOUT 2 Output Low Voltage COUT Digital Output Capacitance ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 IIN, Input Leakage Current 0.005 VHYST, Input Hysteresis CIN, Input Capacitance 0.05 VDD 6 LOGIC OUTPUT (SDA) 2 VOL, Output Low Voltage 0.4 V max pF typ ISINK = 6 mA 0.7 VDD VDD + 0.3 –0.3 0.3 VDD V min V max V min V max μA typ μA max V min pF typ ±1 0.4 0.6 35 130 11 20 tOFF ADG715 115 180 Break-Before-Make Time Delay, t D Charge Injection Off Isolation Channel-to-Channel Crosstalk –3 dB Bandwidth CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 8 ±2 –60 –80 –70 –90 155 11 11 22 1 NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –3– VS = VD = 1 V, or 3 V VIN = 0 V to VDD V max V max ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ VS = 2 V, RL = 300 Ω, CL = 35 pF μA typ μA max 10 20 REV. C VS = 0 V to VDD, IS = 10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V VIN = VINL or VINH ± 0.1 200 tOFF ADG714 VS = 0 V to VDD, IS = 10 mA V min V max μA typ μA max pF typ ± 0.3 65 tON ADG715 VS = 0 V to VDD, IS = 10 mA VS = 1 V/3 V, VD = 3 V/1 V ± 0.3 4 Input Low Voltage, VINL Test Conditions/Comments nA typ nA max nA typ nA max nA typ nA max ± 0.3 3 DIGITAL INPUTS (SCL, SDA) 2 Input High Voltage, VINH DYNAMIC CHARACTERISTICS 2 tON ADG714 0 V to VDD V Ω typ 12 Ω max 0.4 Ω typ 1.2 Ω max 3.5 Ω typ 2.0 0.8 0.005 Unit VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RS = 0 Ω, CL = 1 nF RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF VDD = 3.3 V Digital Inputs = 0 V or 3.3 V ADG714/ADG715–SPECIFICATIONS1 DUAL SUPPLY (V DD = +2.5 V ± 10%, VSS = −2.5 V ± 10%, GND = 0 V unless otherwise noted.) B Version –40C +25C to +85C Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 2.5 4.5 On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) 0.6 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH VSS to VDD V Ω typ 5 Ω max 0.4 Ω typ 0.8 Ω max Ω typ 1 Ω max ± 0.3 ± 0.3 ± 0.3 1.7 0.7 0.005 CIN, Digital Input Capacitance2 Unit nA typ nA max nA typ nA max nA typ nA max Test Conditions/Comments VS = VSS to VDD, IDS = 10 mA VS = VSS to VDD, IDS = 10 mA VS = VSS to VDD, IDS = 10 mA VDD = +2.75 V, VSS = –2.75 V VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V VS = VD = +2.25 V/–1.25 V V min V max μA typ μA max pF typ VIN = VINL or VINH 0.4 V max pF typ ISINK = 6 mA 0.7 VDD VDD + 0.3 –0.3 0.3 VDD V min V max V min V max μA typ μA max V min pF typ ± 0.1 3 2 DIGITAL OUTPUT ADG714 DOUT Output Low Voltage COUT Digital Output Capacitance DIGITAL INPUTS (SCL, SDA)2 Input High Voltage, VINH 4 Input Low Voltage, VINL IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage DYNAMIC CHARACTERISTICS2 tON ADG714 0.005 ±1 0.05 VDD 6 0.4 0.6 20 32 tON ADG715 133 200 tOFF ADG714 8 18 tOFF ADG715 124 190 Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk –3 dB Bandwidth CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 8 ±3 –60 –80 –70 –90 155 11 11 22 1 25 ISS V max V max ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF μA typ μA max μA typ μA max 15 15 25 NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –4– VIN = 0 V to VDD VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 0 V, RS = 0 Ω, CL = 1 nF RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF VDD = +2.75 V, VSS = –2.75 V Digital Inputs = 0 V or VDD REV. C ADG714/ADG715 ADG714 TIMING CHARACTERISTICS1, 2 (V DD = 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.) Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 3 30 33 13 13 0 5 4.5 0 33 20 MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns max SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Rising Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SCLK Rising Edge to DOUT Valid NOTES 1 See Figure 1. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 CL = 20 pF, RL = 1 kΩ. Specifications subject to change without notice. t1 SCLK t8 t2 t3 t7 t4 SYNC t6 t5 DB7 DIN DB0 t9 DB7* DOUT *DATA DB6* DB2* DB1* DB0* FROM PREVIOUS WRITE CYCLE Figure 1. 3-Wire Serial Interface Timing Diagram REV. C –5– ADG714/ADG715 ADG715 TIMING CHARACTERISTICS1 (V DD = 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.) Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCL t1 t2 t3 t4 t5 t6 2 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 kHz max μs min μs min μs min μs min ns min μs max μs min μs min μs min μs min SCL Clock Frequency SCL Cycle Time tHIGH, SCL High Time tLOW, SCL Low Time tHD, STA, Start/Repeated Start Condition Hold Time tSU, DAT, Data Setup Time tHD, DAT, Data Hold Time 300 20 + 0.1Cb3 250 300 0.1Cb3 400 50 ns max ns min ns max ns max ns min pF max ns max t7 t8 t9 t10 t11 t11 Cb tSP4 tSU, STA, Setup Time for Repeated Start tSU, STO, Stop Condition Setup Time tBUF, Bus Free Time Between a STOP Condition and a Start Condition tR, Rise Time of Both SCL and SDA When Receiving tF, Fall Time of SDA When Receiving tF, Fall Time of SDA When Transmitting Capacitive Load for Each Bus Line Pulsewidth of Spike Suppressed NOTES 1 See Figure 2. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 3 Cb is the total capacitance of one bus line in pF. t R and tF measured between 0.3 V DD and 0.7 VDD. 4 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. Specifications subject to change without notice. SDA t9 t3 t4 t11 t10 SCL t4 t6 t2 t5 START CONDITION t7 REPEATED START CONDITION t1 t8 STOP CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram –6– REV. C ADG714/ADG715 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted.) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V Analog Inputs2 . . . . . . . . . . . . . . . . . VSS –0.3 V to VDD +0.3 V or 30 mA, Whichever Occurs First Digital Inputs2 . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C TSSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 128°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 42°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C Infrared Reflow (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 235°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATIONS 24-Lead TSSOP REV. C SCLK 1 24 SYNC SCL 1 24 A0 VDD 2 23 RESET VDD 2 23 RESET DIN 3 22 DOUT SDA 3 22 A1 GND 4 21 VSS GND 4 21 VSS S1 5 20 S8 S1 5 20 S8 D1 6 D1 6 ADG714 ADG715 S2 TOP VIEW 19 D8 (Not to Scale) 7 18 S7 S2 TOP VIEW 19 D8 (Not to Scale) 7 18 S7 D2 8 17 D7 D2 8 17 D7 S3 9 16 S6 S3 9 16 S6 D3 10 15 D6 D3 10 15 D6 S4 11 14 S5 S4 11 14 S5 D4 12 13 D5 D4 12 13 D5 –7– ADG714/ADG715 ADG714 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 SCLK 2 3 VDD DIN 4 5, 7, 9, 11, 14, 16, 18, 20 6, 8, 10, 12, 13, 15, 17, 19 21 22 GND Sx Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices can accommodate serial input rates of up to 30 MHz. Positive Analog Supply Voltage. Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input. Ground Reference Source. May be an input or output. Dx Drain. May be an input or output. VSS DOUT 23 24 RESET SYNC Negative Analog Supply Voltage. For single supply operation this should be tied to GND. Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be pulled to the supply with an external pull-up resistor. Active Low Control Input. Clears the input register and turns all switches to the OFF condition. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the switches. ADG715 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface. 2 3 VDD SDA 4 5, 7, 9, 11, 14, 16, 18, 20 6, 8, 10, 12, 13, 15, 17, 19 21 GND Sx Positive Analog Supply Voltage Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input shift register during the write cycle and used to readback one byte of data during the read cycle. It is a bidirectional open-drain data line which should be pulled to the supply with an external pullup resistor. Ground Reference Source. May be an input or output. Dx Drain. May be an input or output. VSS Negative Analog Supply Voltage. For single supply operation this should be tied to GND. 22 A1 Address Input. Sets the second least significant bit of the 7-bit slave address. 23 RESET Active Low Control Input. Clears the input register and turns all switches to the OFF condition. 24 A0 Address Input. Sets the least significant bit of the 7-bit slave address. –8– REV. C ADG714/ADG715 TERMINOLOGY VDD VSS IDD ISS GND S D RON ΔRON Most positive power supply potential. Most negative power supply in a dual supply application. In single supply applications, this should be tied to ground. Positive Supply Current Negative Supply Current Ground (0 V) Reference Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Ohmic resistance between D and S On resistance match between any two channels, i.e., RON max–RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (OFF) Source leakage current with the switch “OFF.” ID (OFF) Drain leakage current with the switch “OFF.” ID, IS (ON) Channel leakage current with the switch “ON.” VD (VS) Analog voltage on terminals D and S CS (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. CD (OFF) “OFF” Switch Drain Capacitance. Measured with reference to ground. REV. C CD, CS (ON) “ON” Switch Capacitance. Measured with reference to ground. CIN Digital Input Capacitance tON Delay time between loading new data to the shift register and selected switches switching on. tOFF Delay time between loading new data to the shift register and selected switches switching off. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Charge A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by –3 dBs. On Response The frequency response of the “ON” switch. Insertion Loss The loss due to the ON resistance of the switch. Insertion Loss = 20 log10 (VOUT with switch/ VOUT without switch. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL(IINH) Input current of the digital input. IDD Positive Supply Current –9– ADG714/ADG715 –Typical Performance Characteristics 8 8 TA = 25C VSS = GND 7 6 6 VDD = 2.7V ON RESISTANCE – ON RESISTANCE – VDD = 3V VSS = GND 7 5 VDD = 3.3V 4 VDD = 4.5V VDD = 5.5V 3 +85C 4 –40C 3 2 2 1 1 0 +25C 5 0 0 1 2 3 4 VD, VS, DRAIN OR SOURCE VOLTAGE – V 5 0.5 0 1.0 1.5 2.0 TPC 1. On Resistance as a Function of VD (VS) Single Supply TPC 4. On Resistance as a Function of VD (VS) for Different Temperatures; VDD = 3 V 8 8 7 7 6 6 ON RESISTANCE – ON RESISTANCE – TA = 25C 5 4 VDD = +2.25V VSS = –2.25V 3 VDD = +2.5V VSS = –2.5V 5 4 +25C 3 +85C 2 2 VDD = +2.5V VSS = –2.5V 1 –2.7 VDD = +2.75V VSS = –2.75V –2.1 –1.5 –0.9 –0.3 0.3 0.9 1.5 2.1 VD OR VS DRAIN OR SOURCE VOLTAGE – V –40C 1 0 –2.5 2.7 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 VD OR VS DRAIN OR SOURCE VOLTAGE – V TPC 2. On Resistance as a Function of VD (VS); Dual Supply TPC 5. On Resistance as a Function of VD (VS) for Different Temperatures; Dual Supply 0.04 8 VDD = 5V VSS = GND TA = 25C VDD = 5V VSS = GND 7 6 0.02 CURRENT – nA ON RESISTANCE – 3.0 2.5 VD OR VS DRAIN OR SOURCE VOLTAGE – V 5 4 +85C +25C 3 I S , I D (ON) 0 I D (OFF) I S (OFF) –0.02 2 –40C 1 –0.04 0 0 1 2 3 4 VD OR VS DRAIN OR SOURCE VOLTAGE – V 0 5 1 2 3 4 5 VD OR VS – Volts TPC 3. On Resistance as a Function of VD (VS) for Different Temperatures; VDD = 5 V TPC 6. Leakage Currents as a Function of VD (VS) –10– REV. C ADG714/ADG715 0.04 0.1 VDD = 3V VSS = GND TA = 25C 0.02 VDD = 3V VSS = GND VD = 3V/1V VS = 1V/3V 0.05 0 I S (OFF) I D (OFF) I D , I S (ON) CURRENT – nA CURRENT – nA I S , I D (ON) –0.02 0 I D (OFF) I S (OFF) –0.05 –0.04 0 0.5 1.0 1.5 VOLTAGE – V 2.0 –0.1 10 3.0 2.5 TPC 7. Leakage Currents as a Function of VD (VS) 20 30 50 60 40 TEMPERATURE – C 80 70 TPC 10. Leakage Currents as a Function of Temperature 0.04 0 VDD = +2.5V VSS = –2.5V TA = 25C VDD = 5V TA = 25C –20 ATTENUATION – dB 0.02 CURRENT – nA I D (OFF) I S (OFF) 0 I S , I D (ON) –40 –60 –80 –0.02 –100 –0.04 –2 –1 0 VOLTAGE – V 1 –120 30k 2 TPC 8. Leakage Currents as a Function of VD (VS) Dual Supply 10M 100M 0 VDD = +2.75V VSS = –2.75V VD = +2.25V/–1.25V VS = –1.25V/+2.25V VDD = +5V VSS = GND VD = 4.5V/1V VS = 1V/4.5V I S , I D (ON) –2 ATTENUATION – dB CURRENT – nA 1M FREQUENCY – Hz TPC 11. Off Isolation vs. Frequency 0.1 0.05 100k I S (OFF) 0 I D (OFF) –4 –6 –8 –10 –0.05 –12 –0.1 10 20 30 40 50 60 TEMPERATURE – C 70 –14 30k 80 TPC 9. Leakage Currents as Function of Temperature REV. C 100k 1M 10M FREQUENCY – Hz 100M TPC 12. On Response vs. Frequency –11– 300M ADG714/ADG715 GENERAL DESCRIPTION –40 VDD = 5V TA = 25C The ADG714 and ADG715 are serially controlled, octal SPST switches, controlled by either a 2- or 3-wire interface. Each bit of the 8-bit serial word corresponds to one switch of the part. A Logic 1 in the particular bit position turns on the switch, while a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches ON. ATTENUATION – dB –50 –60 –70 When changing the switch conditions, a new 8-bit word is written to the input shift register. Some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. To minimize glitches on the output of these switches, the part cleverly compares the state of switches from the previous write cycle. If the switch is already in the ON condition, and is required to stay ON, there will be minimal glitches on the output of the switch. –80 –90 –100 30k 100k 1M FREQUENCY – Hz 100M 10M TPC 13. Crosstalk vs. Frequency POWER-ON RESET On power-up of the device, all switches will be in the OFF condition and the internal shift register is filled with zeros and will remain so until a valid write takes place. 10 TA = 25C VDD = +3.3V VSS = GND 5 SERIAL INTERFACE 3-Wire Serial Interface QINJ – pC 0 VDD = +5V VSS = GND VDD = +2.5V VSS = –2.5V The ADG714 has a 3-wire serial interface (SYNC, SCLK, and DIN), that is compatible with SPI, QSPI, MICROWIRE interface standards and most DSPs. Figure 1 shows the timing diagram of a typical write sequence. –5 –10 Data is written to the 8-bit shift register via DIN under the control of the SYNC and SCLK signals. Data may be written to the shift register in more or less than eight bits. In each case the shift register retains the last eight bits that were written. –15 –20 –3 –2 –1 0 1 2 VOLTAGE – V 3 4 5 When SYNC goes low, the input shift register is enabled. Data from DIN is clocked into the shift register on the falling edge of SCLK. Each bit of the 8-bit word corresponds to one of the eight switches. Figure 3 shows the contents of the input shift register. Data appears on the DOUT pin on the rising edge of SCLK suitable for daisy chaining, delayed of course by eight bits. When all eight bits have been written into the shift register, the SYNC line is brought high again. The switches are updated with the new configuration and the input shift register is disabled. With SYNC held high, the input shift register is disabled, so further data or noise on the DIN line will have no effect on the shift register. TPC 14. Charge Injection vs. Source/Drain Voltage 45 VSS = GND 40 TO N , V DD = 3V 35 TIME – ns 30 TO N , V DD = 5V 25 20 DB7 (MSB) S8 TOFF , V DD = 3V 15 S7 S5 S4 S3 S2 S1 DATA BITS 10 5 0 10 DB0 (LSB) S6 Figure 3. Input Shift Register Contents TOFF , V DD = 5V 20 30 40 50 60 TEMPERATURE – C 70 SERIAL INTERFACE 2-Wire Serial Interface 80 The ADG715 is controlled via an I2C-compatible serial bus. This device is connected to the bus as a slave device (no clock is generated by the switch). TPC 15. TON /TOFF Times vs. Temperature for ADG714 The ADG715 has a 7-bit slave address. The five MSBs are 10010 and the two LSBs are determined by the state of the A0 and A1 pins. –12– REV. C ADG714/ADG715 The 2-wire serial bus protocol operates as follows: A repeated write function gives the user flexibility to update the matrix switch a number of times after addressing the part only once. During the write cycle, each data byte will update the configuration of the switches. For example, after the matrix switch has acknowledged its address byte, and received one data byte, the switches will update after the data byte; if another data byte is written to the matrix switch while it is still the addressed slave device, this data byte will also cause a switch configuration update. Repeat read of the matrix switch is also allowed. 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte that consists of the 7-bit slave address followed by a R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. However, if the R/W bit is low, the master will write to the slave device. Input Shift Register The input shift register is eight bits wide. Figure 3 illustrates the contents of the input shift register. Data is loaded into the device as an 8-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 2. The 8-bit word consists of eight data bits, each controlling one switch. MSB (Bit 7) is loaded first. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. Write Operation When writing to the ADG715, the user must begin with an address byte and R/W bit, after which the switch will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is followed by the 8-bit word. The write operation for the switch is shown in the Figure 4. 3. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition. In read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse and then high during the tenth clock pulse to establish a STOP condition. READ Operation When reading data back from the ADG715, the user must begin with an address byte and R/W bit, after which the switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that consists of the eight data bits in the input register. The read operation for the part is shown in Figure 5. See Figure 4 for a graphical explanation of the serial interface. SCL SDA 1 0 START COND BY MASTER 0 1 0 A1 A0 R/W S8 S7 S6 S5 ACK BY ADG715 ADDRESS BYTE S4 S3 S2 S1 DATA BYTE ACK BY ADG715 STOP COND BY MASTER NO ACK BY MASTER STOP COND BY MASTER Figure 4. ADG715 Write Sequence SCL SDA START COND BY MASTER 1 0 0 1 ADDRESS BYTE 0 A1 A0 R/W S8 ACK BY ADG715 S7 S6 S5 DATA BYTE Figure 5. ADG715 Readback Sequence REV. C –13– S4 S3 S2 S1 ADG714/ADG715 APPLICATIONS Multiple Devices On One Bus Power Supply Sequencing When using CMOS devices, care must be taken to ensure correct power-supply sequencing. Incorrect power-supply sequencing can result in the device being subjected to stresses beyond those maximum ratings listed in the data sheet. Digital and analog inputs should always be applied after power supplies and ground. In dual supply applications, if digital or analog inputs may be applied to the device prior to the VDD and VSS supplies, the addition of a Schottky diode connected between VSS and GND will ensure that the device powers on correctly. For single supply operation, VSS should be tied to GND as close to the device as possible. Figure 6 shows four ADG715 devices on the same serial bus. Each has a different slave address since the state of their A0 and A1 pins is different. This allows each switch to be written to or read from independently. Daisy-Chaining Multiple ADG714s A number of ADG714 switches may be daisy-chained simply by using the DOUT pin. Figure 7 shows a typical implementation. The SYNC pin of all three parts in the example are tied together. When SYNC is brought low, the input shift registers of all parts are enabled, data is written to the parts via DIN, and clocked through the shift registers. When the transfer is complete, SYNC is brought high and all switches are updated simultaneously. Further shift registers may be added in series. Decoding Multiple ADG714s Using an ADG739 The dual 4-channel ADG739 multiplexer can be used to multiplex a single chip select line to provide chip selects for up to four VDD RP RP SDA MASTER SCL VDD SDA SCL A1 SCL SDA A1 A0 VDD VDD SDA SDA A1 A0 ADG715 SCL A0 ADG715 SCL A1 A0 ADG715 ADG715 Figure 6. Multiple ADG715s On One Bus VDD VDD R SCLK SCLK SYNC DIN SYNC R SCLK ADG714 DIN DOUT VDD ADG714 DIN R SCLK DOUT SYNC ADG714 DIN SYNC DOUT TO OTHER SERIAL DEVICES Figure 7. Multiple ADG714 Devices in a Daisy-Chained Configuration –14– REV. C ADG714/ADG715 devices on the SPI bus. Figure 8 illustrates the ADG739 and multiple ADG714s in such a typical configuration. All devices receive the same serial clock and serial data, but only one device will receive the SYNC signal at any one time. The ADG739 is a serially controlled device also. One bit programmable pin of the microcontroller is used to enable the ADG739 via SYNC2, while another bit programmable pin is used as the chip select for the other serial devices, SYNC1. Driving SYNC2 low enables changes to be made to the addressed serial devices. By bringing SYNC1 low, the selected serial device hanging from the SPI bus will be enabled and data will be clocked into its shift register on the falling edges of SCLK. The convenient design of the matrix switch allows for different combinations of the four serial devices to be addressed at any one time. If more devices need to be addressed via one chip select line, the ADG738 is an 8channel device and would allow further expansion of the chip select scheme. There may be some digital feedthrough from the digital input lines because SCLK and DIN are permanently connected to each device. Using a burst clock will minimize the effects of digital feedthrough on the analog channels. VDD ADG714 R SYNC DIN SCLK VDD ADG714 R SYNC VDD DIN SCLK 1/2 of ADG739 S1A SYNC1 DA VDD S2A R S3A S4A DIN SCLK DIN SYNC FROM CONTROLLER OR DSP SYNC2 DIN SCLK OTHER SPI SYNC DEVICE SCLK VDD R OTHER SPI SYNC DEVICE DIN SCLK Figure 8. Addressing Multiple ADG714s Using an ADG739 REV. C –15– ADG714/ADG715 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 1. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model1 ADG714BRU-REEL ADG714BRU-REEL7 ADG714BRUZ ADG714BRUZ-REEL ADG714BRUZ-REEL7 ADG715BRU ADG715BRU-REEL ADG715BRU-REEL7 ADG715BRUZ ADG715BRUZ-REEL ADG715BRUZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP 24-Lead TSSOP Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 Z = RoHS Compliant Part. REVISION HISTORY 1/13—Rev. B to Rev. C Changes to Dual Supply Table Summary and IDD Test Conditions/Comments ..................................................................... 4 Changes to Ordering Guide ...........................................................16 11/02—Rev. A to Rev. B Edits to Features ................................................................................ 1 Edits to General Description ........................................................... 1 Edits to Product Highlights ............................................................. 1 Edits to Specifications ...................................................................3, 4 Edits to TPCs 2 and 5 .....................................................................10 Edits to TPCs 8 and 9 .....................................................................11 Edits to TPCs 14 ..............................................................................12 Edits to Figure 8...............................................................................15 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00043-0-1/13(C) –16– REV. C