Cologne Chip 4QdQCXUUd 752B 18B3=!13B 8B3=73;2585>R^]ca^[[Ta fXcW BCX]cTaUPRT P]S DRWX_bd__^ac 9P]dPah! Copyright 1994-2001 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by patent or other rights. Cologne Chip products are not designed, intended, or authorized for use in any application intended to support or sustain life, or for any other application in which the failure of the Cologne Chip product could create a situation where personal injury or death may occur. Cologne Chip 863C Revision History Date Jan. 2001 Feb. 2000 Nov. 1999 Aug. 1999 Mar. 1999 Feb. 1999 Aug. 1998 May 1998 Remarks Information added to section: GCI/IOM2 timing. Information added to section: DMA access in processor mode, GCI frame structure. Information added to section: Power down considerations. Section added: Configuring test loops. Information added to section: Processor interface modes, processor mode, FIFO channel operation: receive channels, STATES register bit description, ISA-PC bus or processor access timing, S/T interface activation/deactivation layer 1 for finite state matrix for NT. Changes made on: S/T modules part numbers and manufacturers. Changes made on: CLKDEL register bit description. Changes made on: DMA access in processor mode, Register bit description of GCI/IOM2 bus section: Auxiliary channel handling, B_MODE register bit description. Changes made on: RESET characteristics, FIFO change must no longer be made twice, watchdog/timer, automatically D-channel frame repetition, transparent mode, power down considerations, TRxR register bit description, TRM register bit description, SRAM access, S/T module part numbers and manufacturers, sample circuitry. Cologne Chip Cologne Chip AG Eintrachtstrasse 113 D-50668 Köln Germany Tel.: +49 (0) 221 / 912 96 04 Fax: +49 (0) 221 / 912 96 05 http://www.CologneChip.com http://www.CologneChip.de [email protected] " _V ' :Q^eQbi " ! Cologne Chip 863C Contents 1 General description............................................................................................................................ 6 1.1 Applications ..................................................................................................................................... 7 1.2 Mode description ............................................................................................................................. 8 1.2.1 ISA-PC mode .......................................................................................................................... 8 1.2.2 Processor interface modes....................................................................................................... 8 2 Pin description.................................................................................................................................... 9 2.1 ISA-PC bus and microprocessor interface....................................................................................... 9 2.2 S/T interface transmit signals ........................................................................................................ 11 2.3 S/T interface receive signals.......................................................................................................... 11 2.4 SRAM Interface ............................................................................................................................. 12 2.5 Oscillator........................................................................................................................................ 12 2.6 GCI/IOM2 bus interface ................................................................................................................ 13 2.7 GCI/IOM2 Timeslot enable signals ............................................................................................... 13 2.8 Interrupt outputs............................................................................................................................. 14 2.9 Miscellaneous pins......................................................................................................................... 14 2.10 Power supply ............................................................................................................................. 15 2.11 RESET characteristics............................................................................................................... 15 3 Functional description ..................................................................................................................... 16 3.1 ISA-PC mode ................................................................................................................................. 16 3.2 ISA-PC bus interface ..................................................................................................................... 18 3.3 Processor mode .............................................................................................................................. 19 3.3.1 DMA access in processor mode............................................................................................ 20 3.4 Internal HFC-S+ register description............................................................................................. 21 3.4.1 FIFO control registers ........................................................................................................... 21 3.4.1.1 FIFO select register........................................................................................................... 21 3.4.1.2 FIFO registers ................................................................................................................... 21 3.4.2 Registers of the S/T section .................................................................................................. 23 3.4.3 Registers of the GCI/IOM2 bus section ................................................................................ 24 3.4.4 Interrupt and status registers ................................................................................................. 25 3.5 Timer.............................................................................................................................................. 26 3.6 Watchdog ....................................................................................................................................... 26 3.7 FIFOs ............................................................................................................................................. 27 3.7.1 FIFO channel operation......................................................................................................... 28 3.7.1.1 Send channels (B1, B2 and D transmit)............................................................................ 29 3.7.1.2 Automatically D-channel frame repetition ....................................................................... 29 3.7.1.3 FIFO full condition in send channels................................................................................ 29 3.7.1.4 Receive Channels (B1, B2 and D receive) ....................................................................... 30 3.7.1.5 FIFO full condition in receive channels ........................................................................... 31 3.7.1.6 FIFO reset ......................................................................................................................... 32 3.7.2 Transparent mode of HFC-S+............................................................................................... 32 3.8 External SRAM.............................................................................................................................. 33 3.9 Power down considerations ........................................................................................................... 33 3.10 Configuring test loops ............................................................................................................... 34 4 Register bit description.................................................................................................................... 35 4.1 Register bit description of the FIFO select register ....................................................................... 35 4.2 Register bit description of S/T section .......................................................................................... 35 4.3 Register bit description of GCI/IOM2 bus section ........................................................................ 39 :Q^eQbi " ! # _V ' 863C 4.4 4.5 5 Cologne Chip Register bit description of CONNECT register............................................................................. 42 Register bit description of interrupt, status and control registers.................................................. 43 Electrical characteristics ................................................................................................................. 48 6 Timing characteristics ..................................................................................................................... 51 6.1 ISA-PC bus or processor access .................................................................................................... 51 6.2 SRAM access ................................................................................................................................. 52 6.3 GCI/IOM2 bus clock and data alignment for Mitel STTM bus....................................................... 53 6.4 GCI/IOM2 timing .......................................................................................................................... 54 6.4.1 Master mode.......................................................................................................................... 54 6.4.2 Slave mode ............................................................................................................................ 55 7 S/T interface circuitry...................................................................................................................... 56 7.1 External receiver circuitry ............................................................................................................. 56 7.2 External transmitter circuitry......................................................................................................... 57 7.3 Oscillator circuitry ......................................................................................................................... 60 8 State matrices for NT and TE ......................................................................................................... 61 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 61 8.2 Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 62 9 Binary organisation of the frames .................................................................................................. 63 9.1 S/T frame structure ........................................................................................................................ 63 9.2 GCI frame structure ....................................................................................................................... 64 10 Clock synchronisation...................................................................................................................... 65 10.1 Clock synchronisation in NT-mode........................................................................................... 65 10.2 Clock synchronisation in TE-mode ........................................................................................... 66 11 HFC-S+ package dimensions .......................................................................................................... 67 12 ISDN PC card sample circuitry with HFC-S+ .............................................................................. 68 $ _V ' :Q^eQbi " ! Cologne Chip 863C Figures Figure 1: HFC-S+ block diagram.................................................................................................................. 7 Figure 2: Pin Connection .............................................................................................................................. 9 Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 28 Figure 4: FIFO Data Organisation .............................................................................................................. 30 Figure 5: Function of the CONNECT register bits..................................................................................... 42 Figure 6: GCI/IOM2 bus clock and data alignment.................................................................................... 53 Figure 7: External receiver circuitry........................................................................................................... 56 Figure 8: External transmitter circuitry ...................................................................................................... 57 Figure 9: Oscillator Circuitry...................................................................................................................... 60 Figure 10: Frame structure at reference point S and T ............................................................................... 63 Figure 11: Single channel GCI format........................................................................................................ 64 Figure 12: Clock synchronisation in NT-mode .......................................................................................... 65 Figure 13: Clock synchronisation in TE-mode........................................................................................... 66 Figure 14: HFC-S+ package dimensions .................................................................................................... 67 Tables Table 1: Mode selection................................................................................................................................ 8 Table 2: Selected I/O address after reset .................................................................................................... 16 Table 3: DMA access in processor mode ................................................................................................... 20 Table 4: SRAM and FIFO size ................................................................................................................... 33 Table 5: S/T module part numbers and manufacturer ................................................................................ 59 Table 6: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 61 Table 7: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 62 Timing Diagrams Timing diagram 1: ISA-PC bus or microprocessor access ......................................................................... 51 Timing diagram 2: SRAM access ............................................................................................................... 52 Timing diagram 3: GCI/IOM2 timing......................................................................................................... 54 :Q^eQbi " ! % _V ' 863C Cologne Chip Features One chip ISDN-S-controller with B- and D-channel HDLC support Independent Read and Write HDLC-Channels for 2 ISDN B-channels and one ISDN D-channel B1- and B2-channel transparent mode independently selectable FIFO-size: 4x 7.5 KByte (B-channel) and 2x 512 Byte (D-channel) max. 31 HDLC frames (B-channel) and 15 HDLC frames (D-channel) per channel and direction in FIFO 56 kbit/s restricted mode for U.S. ISDN lines selectable by software full I.430 ITU S/T ISDN support in TE and NT mode for the 3.3V and 5V supply B1+B2 HDLC mode PCM30 interface configurable to interface MITEL STTM bus (MVIPTM), Siemens IOM2TM or GCITM for interface to U-chip or external codecs direct 8 bit ISA-PC bus interface with buffers for ISA-databus 1 General description One of 6 interrupt channels on ISA-PC bus selectable by software ISA-I/O-address selectable by software only 2 I/O addresses used on ISA-PC bus microprocessor interface compatible to Motorala bus and Siemens/Intel bus simple DMA access to PCM30 interface for tone synthetisation Timer with interrupt and watchdog capability in processor mode 3.3V and 5V supply voltage rectangular QFP 100 case The HFC-S+ is an ISDN S/T HDLC basic rate controller for so called „passive“ ISDN PC cards with integrated S/T interface and PCM30 highway interface. It only needs an external SRAM to form a high performance ISDN PC card. Most problems with passive ISDN PC cards as small FIFOs and massive interrupt load for the host CPU are overcome by the HFC-S+. So we call ISDN cards with the HFC-S+ „semi-active“. Additionally the HFC-S+ can be used as a microprocessor peripheral in non-PC applications. The ultra-deep FIFOs of the HFC-S+ are realized with an external SRAM. Also an industrial standard serial interface for telecom peripheral ICs is implemented. Codecs are normally connected to this interface. & _V ' :Q^eQbi " ! Cologne Chip 863C 1.1 Applications ISDN PC card ISDN terminal adapter ISDN PABX ISDN modems Figure 1: HFC-S+ block diagram :Q^eQbi " ! ' _V ' Cologne Chip 863C 1.2 Mode description The HFC-S+ has 4 different bus modes, which can be selected by the lines ALE and IIOSEL0-IIOSEL3. Depending on the selected mode the function of several pins is different (see: Pin description). ALE GND VDD GND pulse IIOSEL0..3 0 all 0 all 0 all 0 Selected mode ISA-PC mode (mode 1) processor mode (mode 2) processor mode (mode 3) processor mode (mode 4) Table 1: Mode selection 1.2.1 ISA-PC mode Mode 1: ALE = GND, IIOSEL3-0 0000 In mode 1 the HFC-S+ is addressed by two successive port addresses on the ISA-PC bus. The port address is selected by the lines SA0 - SA9. The address with SA0='1' is for register selection and the address with SA0='0' is used for data read/write (see also: 3.1). 1.2.2 Processor interface modes The processor modes are selected by IIOSEL3-0 = '0000'. In all processor modes line SA6 must be connected to GND. Mode 2: Motorola bus with control signals /CS, R/W, /DS is selected by setting ALE to VDD. Mode 3: Siemens/Intel bus with seperated address bus and databus and control signals /CS, /WR, /RD is selected by setting ALE to GND. Mode 4: Intel bus with multiplexed address and databus with control signals /CS, /WR, /RD, ALE. ALE latches the address. The address lines SA0-SA7 must be connected to the data lines BD0-BD7 (except SA6 which must be connected to GND). The lines SA0-SA7 (except SA6) are used for direct addressing the internal registers of the HFC-S+ (see also 3.3). ( _V ' :Q^eQbi " ! Cologne Chip 863C 2 Pin description Figure 2: Pin Connection 2.1 ISA-PC bus and microprocessor interface Pin No. u) Pin Name Input Output I u) I u) I u) I u) Mode 1 2 3 4 IIOSEL0 IIOSEL1 IIOSEL2 IIOSEL3 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 5 6 7 8 9 10 11 SA0 SA1 SA2 SA3 SA4 SA5 SA6 I I I I I I I all all all all all all all 12 SA7 I all Function Mode/initial I/O address select bit 0 Mode/initial I/O address select bit 1 Mode/initial I/O address select bit 2 Mode/initial I/O address select bit 3 Register/ISA-PC address bus Address bit 0 Address bit 1 Address bit 2 Address bit 3 Address bit 4 Address bit 5 Address bit 6 (In processer mode SA6 must be connected to GND) Address bit 7 internal pull up :Q^eQbi " ! ) _V ' Cologne Chip 863C Pin No. Pin Name 13 SA8 /DMAAK0 Input Output I I 14 SA9 /DMAAK1 I I Mode 1 2,3,4 1 2,3,4 Function Address bit 8 DMA acknowledge channel 0 Direct access to GCI/IOM2 bus AUX1 channel data register (low active) address bit 9 DMA acknowledge channel 1 direct access on GCI/IOM2 bus AUX2 channel dataregister (low active) * important! If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the read/write enables is inverted. This means a read command on the controller databus writes the AUX-Channel register and a write command reads the register. The address on the address bus (SA0-SA7) is ignored. 15 21 22 23 24 25 26 27 28 31 /AEN /CS IOCHRDY /WAIT /IOR /DS /IOW R/W BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BUSDIR 32 ALE 16 17 18 1) I I O 1) O 1) I I I I I/O I/O I/O I/O I/O I/O I/O I/O O 1 2,3,4 1 2,3,4 1,3,4 2 1,3,4 2 all all all all all all all all 1,2,3,4 I PC bus address enable chipselect low active I/O channel ready low active wait signal for external processor I/O read enable I/O data strobe I/O write enable Read/Write select (WR='0') Databus bit 0 (LSB) Databus bit 1 Databus bit 2 Databus bit 3 Databus bit 4 Databus bit 5 Databus bit 6 Databus bit 7 (MSB) Databus direction signal for external busdriver '0' BD0-BD7 are outputs Address latch enable ALE is also used for mode selection of the HFC-S+. See Mode selection on page 8 for detailed information. open drain, external pull up resistor required ! _V ' :Q^eQbi " ! Cologne Chip 863C 2.2 S/T interface transmit signals Pin No. 34 35 36 37 38 Pin Name TX2_HI /TX1_LO /TX_EN /TX2_LO TX1_HI Input Output O O O O O Function Transmit output 2 GND driver for transmitter 1 Transmit enable GND driver for transmitter 2 Transmit output 1 See also: 7.2 External transmitter circuitry. 2.3 S/T interface receive signals 43 44 45 46 48 R2 LEV_R2 LEV_R1 R1 ADJ_LEV I I I I O Receive data 2 Level detect for R2 Level detect for R1 Receive data 1 Levelgenerator See also: 7.1 External receiver circuitry. :Q^eQbi " ! !! _V ' Cologne Chip 863C 2.4 SRAM Interface Pin No. Pin Name Input Output 53 54 55 56 57 58 59 60 SRD0 SRD1 SRD2 SRD3 SRD4 SRD5 SRD6 SRD7 I/O I/O I/O I/O I/O I/O I/O I/O 63 64 65 66 67 68 69 70 71 72 74 75 76 77 78 SRA0 SRA1 SRA2 SRA3 SRA4 SRA5 SRA6 SRA7 SRA8 SRA9 SRA10 SRA11 SRA12 SRA13 SRA14 O O O O O O O O O O O O O O O 50 79 80 /SRRD /SRCS /SRWR O O O 2.5 Function SRAM data bus SRAM data bit 0 (LSB) SRAM data bit 1 SRAM data bit 2 SRAM data bit 3 SRAM data bit 4 SRAM data bit 5 SRAM data bit 6 SRAM data bit 7 (MSB) SRAM address bus SRAM address bus bit 0 (LSB) SRAM address bus bit 1 SRAM address bus bit 2 SRAM address bus bit 3 SRAM address bus bit 4 SRAM address bus bit 5 SRAM address bus bit 6 SRAM address bus bit 7 SRAM address bus bit 8 SRAM address bus bit 9 SRAM address bus bit 10 SRAM address bus bit 11 SRAM address bus bit 12 SRAM address bus bit 13 SRAM address bus bit 14 (MSB) SRAM control signals Read strobe to external device SRAM chip select SRAM write enable Oscillator 82 OSC_IN I 83 OSC_OUT O !" _V ' Oscillator input or quarz connection 12.288 Mhz or 24.576 MHz Oscillator output or quarz connection :Q^eQbi " ! Cologne Chip 863C 2.6 GCI/IOM2 bus interface Pin No. u) Pin Name 85 C4IO Input Output I/O u) Mode 86 F0IO I/O u) all 87 STIO1 I/O u) all 88 STIO2 I/O u) all all Function 4.096 Mhz clock GCI/IOM2 bus clock master: output GCI/IOM2 bus clock slave: input (reset default) Frame synchronisation, 8kHz pulse for GCI/IOM2 bus frame synchronisation GCI/IOM2 bus master: output GCI/IOM2 bus slave: input (reset default) GCI/IOM2 bus databus I Slotwise programmable as input or output GCI/IOM2 bus databus II Slotwise programmable as input or output internal pull up 2.7 GCI/IOM2 Timeslot enable signals (e. g. for PCM codecs) 91 F1_A O all 92 F1_B O all :Q^eQbi " ! enable signal for external CODEC A Programmable as positive (reset default) or negative pulse. enable signal for external CODEC B Programmable as positive (reset default) or negative pulse. !# _V ' Cologne Chip 863C 2.8 Interrupt outputs Pin No. 94 95 96 97 98 99 1) 2) Pin Name IRQ_A /IRQ_P IRQ_B IRQ_P IRQ_C /WD_RES IRQ_D WD_RES IRQ_E DMARQ0 IRQ_F DMARQ1 Input Output I/O O 1) O O 2) O O 1) O O 2) O O O O Mode 1 2,3,4 1 2,3,4 1 2,3,4 1 2,3,4 1 2,3,4 1 2,3,4 Function PC bus interrupt request A or interrupt input from external device (see: CIRM register bit description) processor interrupt request low active PC bus interrupt request B processor interrupt request high active PC bus interrupt request C Watchdog expired, external reset low active PC bus interrupt request D Watchdog expired, external reset high active PC bus interrupt request E DMA request AUX1 channel register (high active) PC bus interrupt request F DMA request AUX2 channel register (high active) open drain, external pull up resistor required open source, external pull down resistor required 2.9 Miscellaneous pins 49 100 !$ _V ' NC RESET I all Not connected (leave pin open) Reset for HFC-S+ (high active) :Q^eQbi " ! Cologne Chip 863C 2.10 Power supply Pin No. 19, 30, 41, 42, 51, 61, 84, 89 20, 29, 33, 39, 40, 47, 52, 62, 73, 81, 90, 93 Pin Name VDD GND Function VDD (+3V to +5V) GND * important! All power supply pins VDD must be directly connected to each other. Also all pins GND must be directly connected to each other. To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be placed between each pair of VDD/GND pins. 2.11 RESET characteristics The reset signal (hardware reset or software reset) must be active for at least 4 clock cycles. The GCI/IOM2 bus lines STIO1, STIO2 and the interrupt lines are in tristate mode after a reset. The HFC-S+ is in slave mode after reset. C4IO and F0IO are inputs. In the processor modes DMARQ1 and DMARQ2 are inactive ('0'). The S/T state machine is stuck to '0' after reset. This means the HFC-S+ does not react to any signal on the S/T interface before the S/T state machine is initialised. The registers' initial values are described in the Register bit description (section 4 of this data sheet). After RESET the HFC-S+ is in an initialisation cycle and is therefor busy for a maximum of 160 clock cycles. :Q^eQbi " ! !% _V ' Cologne Chip 863C 3 Functional description 3.1 ISA-PC mode ISA-PC mode is selected by ALE = GND and IIOSEL0..3≠0. The HFC-S+ occupies two consecutive addresses in the I/O map of a PC if it is in ISA-PC mode. It decodes only the 10 lower address lines as most slot cards do on the ISA-PC bus. The base I/O address is 2 byte aligned so the lower of both addresses is the one with SA0 = 0 and the higher address is the one with SA0 = 1. After every hardware reset (RESET = 1) the I/O address select circuit inside the HFC-S+ is in hardware mode. In this mode the HFC-S+ can not be accessed until it is initialised to an I/O address. At first one of 15 different I/O addresses must be selected by the 4 inputs IIOSEL0 .. IIOSEL3 as Table 2 shows: IIOSEL 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Selected I/O address processor mode 2E0h 2D0h 210h 2C0h 200h 2F8h 2E8h 2B0h 3E0h 320h 278h 310h 330h 300h 3E8h Table 2: Selected I/O address after reset The hardware selected I/O address might have an address collision with another I/O device in the PC. After a hardware reset (RESET = 1) you must first write an I/O address into the HFC-S+ to set the I/O address for every further access to the device. The procedure is as follows: First you must write the lower 8 bits of the new I/O address you want into the lower address (SA0 = 0) of the hardware selected I/O address. The LSB of the new address is a don't care bit because the HFC-S+ always occupies two I/O addresses. !& _V ' :Q^eQbi " ! Cologne Chip 863C Then the additional 2 bits of the new I/O address have to be written into the higher address (SA0 = 1) of the hardware selected I/O address. The other 6 bits in the byte must have a special pattern to switch over to the software selected address mode. This pattern must be 0101 01aa, whereby aa are the 2 higher address bits. e.g.: wanted I/O address: 3A4h / 3A5h IIOSEL(3:0): 0001 then hardware selected I/O address is: 2E0h = 10 1110 0000 b write the value A4h or A5h into 2E0h write the value 57h into 2E1h = ! ! = ! ! ! h ! !! ! ! !!! R R R R pattern address x = don't care All further accesses to the HFC-S+ can only be done on the addresses 3A4h / 3A5h. Only a hardware reset will switch back the HFC-S+ into hardware selected address mode. * hint: It's useful to solve a possible address conflict by programming the I/O address as early as possible. It is recommendable to set the address with a simple .SYS driver in a DOS environment. :Q^eQbi " ! !' _V ' Cologne Chip 863C 3.2 ISA-PC bus interface The HFC-S+ only uses 2 I/O addresses with SA0 switching between data or control information in ISAPC mode. As normal only 10 bits of the ISA-PC bus address are used for I/O address selection in ISA-PC mode. SA0 /IOR /IOW /AEN Operation X X X 1 no access X 1 1 X no access 0 0 1 0 read data 0 1 0 0 write data 1 0 1 0 read status 1 1 0 0 write control X = don't care * important! ALE must be connected to GND and at least one of the IIOSEL0-3 must be '1' or open! The HFC-S+ has no memory or DMA access to any component on the ISA-PC bus. Because of its power drive characteristic it needs no external driver for the ISA-PC bus data lines. If necessary an external bus driver can be added. In this case the output BUSDIR determines the driver direction. BUSDIR = 1 means that data is driven into the HFC-S+; BUSDIR = 0 means that the HFC-S+ is read and data is driven to the external bus. !( _V ' :Q^eQbi " ! Cologne Chip 863C 3.3 Processor mode Processor mode is selected by IIOSEL0..3=0. In the microprocessor mode the HFC-S+ uses 256 I/O addresses (SA0 - SA7). /IOR /DS X 1 0 0 0 1 0 1 /IOW R/W X 1 1 0 1 0 1 0 /CS ALE Operation Mode 1 X 0 0 0 0 0 0 X X 1 1 0 0 0*) 0*) no access no access read data write data read data write data read data write data all all 2 2 3 3 4 4 X = don't care *) 1-pulse latches I/O address. All registers are directly accessable by their I/O address (see register description). Except in mode 4 ALE is assumed to be stable after a RESET. * important! For write accesses to the HFC-S+ the data lines must be stable and valid before /IOW or /DS get low (see also: Timing diagram 1 on page 51). With Intel compatible processors it may be neccessary to delay the /IOW or /DS signals. :Q^eQbi " ! !) _V ' Cologne Chip 863C 3.3.1 DMA access in processor mode In processor mode a simple DMA access to the auxiliary channels of the GCI/IOM2 interface is possible. This is useful for tone synthetisation or for voice recording. DMAREQ is asserted every 125µs. DMAREQ is reset when /DMAAK is active. * note If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the read/write enables is inverted. This means a read command on the controller databus writes the AUXChannel register and a write command reads the register. The address on the address bus (SA0SA7) is ignored. Mode /DMAAK0 /DMAAK1 /CS ALE /IOR /IOW Function /DS R/W X X X no DMA 2,3,4 1 1 X 2 0 1 X 1 X 1 DMA write AUX1 2 1 0 X 1 X 1 DMA write AUX2 3 0 1 X 0 0 1 DMA write AUX1 3 1 0 X 0 0 1 DMA write AUX2 4 0 1 X 0*) 0 1 DMA write AUX1 4 1 0 X 0*) 0 1 DMA write AUX2 Table 3: DMA access in processor mode *) 1-pulse latches I/O address. * important! If DMA is not used /DMAAK0 and /DMAAK1 must be connected to VDD. " _V ' :Q^eQbi " ! Cologne Chip 863C 3.4 Internal HFC-S+ register description In ISA-PC mode all registers are selected by writing the register address into the Control Internal Pointer (CIP) register. This is done by writing the HFC-S+ on the higher I/O address (SA0 = 1). All consecutive read or write data accesses (SA0 = 0) are done with the selected register until the CIP register is changed. In processor mode all registers can be directly accessed. The registers are selected by SA0 - SA7. 3.4.1 FIFO control registers The FIFO control registers are used to select and control the FIFOs of the HFC-S+. In processor mode the value is the address which directly selects the corresponding register. The FIFO register selection is independent of the B- or D-channel FIFO number. The FIFO is selected by the FIFO select register. 3.4.1.1 FIFO select register CIP / I/O-address Name r/w Function 00010000 FIF_SEL w FIFO selection 10h 3.4.1.2 FIFO registers CIP / I/O-address Name r/w Function 100000xx 100001xx 100010xx 100011xx 101010xx 101011xx 101100xx 101101xx 101110xx 101111xx FIF_Z1L FIF_Z1H FIF_Z2L FIF_Z2H FIF_INC_F1*) FIF_DWR FIF_F1 FIF_F2 FIF_INC_F2*) FIF_DRD r r r r r w r r r r FIFO input counter (Z1) low byte FIFO input counter (Z1) high byte FIFO output counter (Z2) low byte FIFO output counter (Z2) high byte read this register to increment frame counter F1 data write into FIFO and increment Z1 FIFO input HDLC frame counter (F1) FIFO output HDLC frame counter (F2) read this register to increment frame counter F2 data read out of FIFO and increment Z2 *) :Q^eQbi " 80h 84h 88h 8Ch A8h ACh B0h B4h B8h BCh only in HDLC mode; In transparent mode (see also: 3.7.2) the frame counters F1 and F2 must not be incremented. ! "! _V ' 863C Cologne Chip * important! FIFO change, FIFO reset and F1/F2 incrementation Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY period of the HFC-S+. This means an access to FIFO control registers is NOT allowed until BUSY status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2µs). Status, interrupt and control registers can be read and written at any time. "" _V ' :Q^eQbi " ! Cologne Chip 863C 3.4.2 Registers of the S/T section CIP / I/O-address Name r/w Function 00110000 30h STATES r/w State of the TE/NT state machine 00110001 31h SCTRL w S/T control register 00110010 32h SCTRL_E w S/T control register (extended) 00110011 33h SCTRL_R w receive enable for B-channels 00110100 34h SQ_REC SQ_SEND r w receive register for S/Q bits send register for S/Q bits 00110111 37h CLKDEL w setup of the delay time between receive and send direction (TE) receive data sample time (NT) 00111100 3Ch B1_REC*) B1_SEND*) r w B1-channel receive register B1-channel transmit register 00111101 3Dh B2_REC*) B2_SEND*) r w B2-channel receive register B2-channel transmit register 00111110 3Eh D_REC*) D_SEND*) r w D-channel receive register D-channel transmit register 00111111 3Fh E_REC*) r E-channel receive register *) These registers are read/written automatically by the HDLC FIFO controller (HFC) or GCI/IOM2 bus controller and need not be accessed by the user. To read/write data the FIFO registers should be used. :Q^eQbi " ! "# _V ' Cologne Chip 863C 3.4.3 Registers of the GCI/IOM2 bus section GCI/IOM2 bus timeslot selection registers CIP / I/O-address Name r/w Function 00000010 00000011 02h 03h C/I TRxR r/w r C/I command/indication register Monitor Tx ready handshake 00001010 00001011 0Ah 0Bh MON1_D MON2_D r/w r/w first monitor byte second monitor byte GCI/IOM2 bus timeslot selection registers CIP / I/O-address Name r/w Function 00100000 00100001 20h 21h B1_SSL B2_SSL w w B1-channel transmit slot (0..31) B2-channel transmit slot (0..31) 00100010 00100011 22h 23h AUX1_SSL AUX2_SSL w w AUX1-channel transmit slot (0..31) AUX2-channel transmit slot (0..31) 00100100 00100101 24h 25h B1_RSL B2_RSL w w B1-channel receive slot (0..31) B2-channel receive slot (0..31) 00100110 00100111 26h 27h AUX1_RSL AUX2_RSL w w AUX1-channel receive slot (0..31) AUX2-channel receive slot (0..31) GCI/IOM2 bus data registers CIP / I/O-address Name r/w Function 00101000 00101001 28h 29h B1_D*) B2_D*) r/w r/w GCI/IOM2 bus B1-channel data register GCI/IOM2 bus B2-channel data register 00101010 00101011 2Ah 2Bh AUX1_D**) AUX2_D**) r/w r/w AUX1-channel data register AUX2-channel data register *) These registers are read/written automatically by the HDLC FIFO controller (HFC) or by the S/T controller and need not be accessed by the user. **) These registers can also be accessed by DMA "$ _V ' :Q^eQbi " ! Cologne Chip 863C GCI/IOM2 bus configuration registers CIP / I/O-address Name r/w 00101101 2Dh MST_EMOD w extended mode register for GCI/IOM2 bus 00101110 2Eh MST_MODE w mode register for GCI/IOM2 bus 00101111 2Fh CONNECT connect functions for S/T, HFC, GCI/IOM2 w Function 3.4.4 Interrupt and status registers CIP / I/O address Name r/w Function 00010010 12h TRM w transparent mode interrupt mode register 00010011 13h B_MODE w mode of B-channels 00010110 16h CHIP_ID r register for chip identification 00011000 18h CIRM w interrupt selection and softreset register 00011001 19h CTMT w transparent mode and timer control register 00011010 1Ah INT_M1 w interrupt mask register 1 00011011 1Bh INT_M2 w interrupt mask register 2 00011110 1Eh INT_S1 r interrupt status register 1 00011111 1Fh INT_S2 r interrupt status register 2 00011100 1Ch STATUS r common status register :Q^eQbi " ! "% _V ' 863C 3.5 Cologne Chip Timer The HFC-S+ includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer counter is incremented every 125µs. It can be reset by bit 7 of of the CTMT register. Furthermore the timer is reset at every HFC-S+ access when bit 5 of the CTMT register is set. Seven different timer values can be selected. 3.6 Watchdog (only available in processor mode) The watchdog outputs of the HFC-S+ are activated if the timer interrupt bit is active (not reset by reading INT_S1) and the timer elapses a second time. The reset of the timer counter itself and the watchdog value can be programmed in the CTMT register. In automatic reset mode the watchdog/timer is reset by every access to the HFC-S+. "& _V ' :Q^eQbi " ! Cologne Chip 863C 3.7 FIFOs There are 6 FIFOs with 6 HDLC-Controllers in the HFC-S+. The HDLC circuits are located on the S/T device side of the HFC-S+. So always plain data is stored in the FIFO. Zero insertion and deletion is done in HDLC mode: – if the data goes to the S/T or GCI/IOM device in send FIFOs and – when the HDLC data comes from the S/T device or GCI/IOM2 bus in receive operation. There are a send and a receive FIFO for each of the two B-channels and for the D-channel. The FIFOs are realized as ring buffers in the external SRAM. To control them there are some counters. Z1: FIFO input counter Z2: FIFO output counter B-channel 13 Bit 13 Bit D-channel 9 Bit 9 Bit Each counter points to a byte position in the SRAM. On a FIFO input operation Z1 is incremented. On an output operation Z2 is incremented. After every pulse on the F0IO signal two HDLC-bytes are written into the S/T interface (FIFOs No. 0 and 2) and two HDLC-bytes are read from the S/T interface (FIFOs No. 1 and 3). D-channel data is handled in a similar way but only 2 bits are processed. * important! Instead of the S/T interface also GCI/IOM2 bus is selectable for each B-channel (see CONNECT register). If Z1 = Z2 the FIFO is empty. Additionally there are two counters F1 and F2 for every FIFO channel (5Bit for B-channel, 4Bit for Dchannel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too. F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented when a complete frame has been read from the FIFO. If F1 = F2 there is no complete frame in the FIFO. When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all 1s. The access to a FIFO is selected by writing the FIFO number into the FIFO select register (FIF_SEL). :Q^eQbi " ! "' _V ' 863C Cologne Chip * important! FIFO change, FIFO reset and F1/F2 incrementation Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY period of the HFC-S+. This means an access to FIFO control registers is NOT allowed until BUSY status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2µs). Status, interrupt and control registers can be read and written at any time. * important! The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs. If 8k RAM mode is selected counter state 1A00h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs. The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs. The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs. The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs. 3.7.1 FIFO channel operation Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel) "( _V ' :Q^eQbi " ! Cologne Chip 863C 3.7.1.1 Send channels (B1, B2 and D transmit) The send channels send data from the host bus interface to the FIFO and the HFC-S+ converts the data into HDLC code and tranfers it from the FIFO into the S/T or/and the GCI/IOM2 bus interface write registers. The HFC-S+ checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-S+ generates a HDLC-Flag (01111110) and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC flags are sent to the S/T interface and all counters remain unchanged. If the frame counters are unequal F2 is incremented and the HFC-S+ tries to send the next frame to the output device. After the end of a frame (Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If there is another frame in the FIFO (F1≠F2) the F2 counter is incremented. With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3). Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame which is just beeing transmitted to the S/T device side of the HFC-S+. Z1(F2) is the end of frame pointer of the current output frame. In the send channels F1 is only changed from the PC interface side if the software driver wants to say „end of send frame“. Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start address of the next frame. Z1(F2) and Z2(F2) can not be accessed. 3.7.1.2 Automatically D-channel frame repetition The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFC-S+ tries to repeat the frame automatically. * important! The HFC-S+ begins to transmit the bytes from a FIFO at the moment the FIFO is changed or the F1 counter is incremented. Also changing to the FIFO that is already selected starts the transmission. So by selecting the same FIFO again transmission can be started. 3.7.1.3 FIFO full condition in send channels Due to the limited number of registers in the HFC-S+ the driver software must maintain a list of frame start and end addresses to calculate actual FIFO size and check FIFO full condition. Because there are a maximum of 32 frame counter values and the start address of a frame is the incremented value of the end address of the last frame the memory table must have only 32 values of 16 bits (13 bits) instead of 64. Remember that an increment of Z-value 1FFFh is 0200h in the B-channels! :Q^eQbi " ! ") _V ' 863C Cologne Chip There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 31 frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-S+ to manage more frames even if the frames are very small. The second limitation is the size of the FIFO which is 512 byte for the D-channel and 7.5 KByte for the B-channels. 3.7.1.4 Receive Channels (B1, B2 and D receive) The receive channels receive data from the S/T or GCI/IOM2 bus interface read registers. The data is converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus interface. The HFC-S+ checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is converted by the HFC-S+ into plain data. After the ending flag of a frame the HFC-S+ checks the HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC field at the end of the frame. Figure 4: FIFO Data Organisation The ending flag of a HDLC-frame can also be the starting flag of the next frame. After a frame is received completely F1 is incremented by the HFC-S+ automatically and the next frame can be received. # _V ' :Q^eQbi " ! Cologne Chip 863C After reading a frame via the host bus interface F2 must be incremented. If the frame counter F2 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3). Z1(F1) is used for the frame which is just received from the S/T device side of the HFC. Z2(F2) is used for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of frame pointer of the current output frame. To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1. When Z2 reaches Z1 the complete frame has been read. In the receive channels F2 must be incremented from the host interface side after the software detects an end of receive frame (Z1=Z2) and F1F2. Then the current value of Z2 is stored, F2 is incremented and Z2 is copied as start address of the next frame. If Z1 = Z2 and F1 = F2 the FIFO is totally empty. Z1(F1) can not be accessed. * important! Before reading a FIFO a change FIFO operation (see also: FIF_SEL register) must be done even if the desired FIFO is already selected. The change FIFO operation is required to update the internal buffer of the HFC-S+. Otherwise the first byte of the FIFO will be taken from the internal buffer and may be invalid. 3.7.1.5 FIFO full condition in receive channels Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there is no possibility to stop input data if a receive FIFO is full. So there is no FIFO full condition implemented in the HFC-S+. The HFC-S+ assumes that the FIFOs are so deep that the host processor hard- and software is able to avoid any overflow of the receive FIFOs. Overflow conditions are again more than 31 input frames (15 frames for D-channel) or a real overflow of the FIFO because of excessive data. Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. Due to the great size of the FIFOs of the HFC-S+ it is easy to poll the HFC-S+ even in large time intervalls without having to fear a FIFO overflow condition. However to avoid any undetected FIFO overflows the software driver should check the number of frames in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number in the last reading even if there was no reading of a frame in between. After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset bit in the CIRM register. :Q^eQbi " ! #! _V ' 863C Cologne Chip 3.7.1.6 FIFO reset All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET. Then the result is Z1 = Z2 = 1FFFh and F1 = F2 = 1Fh for the B-channels and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel. Please mask bit 4 of D-channel from counter F1, F2. The same initialisation is done if the bit 3 in the CIRM register is set (soft reset). Individual FIFOs can be reset by bit 7 of CIRM register. 3.7.2 Transparent mode of HFC-S+ You can switch off HDLC operation for each B-channel independently. There is one bit for each Bchannel in the CTMT control register. If this bit is set data in the FIFO is sent directly to the S/T or GCI/IOM2 bus interface and data from the S/T or GCI/IOM2 bus interface is sent directly to the FIFO. Be sure to switch into transparent mode only if F1=F2. Being in transparent mode the Fx counters remain unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1=F2 both Z-counters are always accessable and have valid data. Because always one Z-counter is changed by the HFC-S+ and only 8 bits of a counter can be read at a time the counter should be read twice to check for a counter incrementation between low and high byte accesses. If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte written into the FIFO is repeated until there is new data. In receive channels there is no check on flags or correct CRCs and no status byte is added. The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with HDLC-flags. The data is just the same as it comes from the S/T or GCI/IOM2 bus interface or is sent to this. Send and receive transparent data can be handled in two ways. The usual way is tranporting B-channel data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting bit 7 of the FIF_SEL register when the FIFO is selected. #" _V ' :Q^eQbi " ! Cologne Chip 863C 3.8 External SRAM For the FIFO data an 32K x 8 external SRAM is used. A 8K x 8 external SRAM is also possible but not recommended. The required access time is 80 ns or below. 1024 Bytes of the external SRAM are reserved for internal HFC-SP use. External SRAM 8K x 8 32K x 8 B-channel FIFO size per channel and direction 1536 Bytes 7680 Byte D-channel FIFO size per direction 512 Bytes 512 Byte Table 4: SRAM and FIFO size To initialise the HFC-S for 8K x 8 SRAM use: - write 18h to the CIRM register - wait at least 4 clock cycles - write 10h to the CIRM register For all further accesses to the CIRM register bit 4 must be set. * hint! If you connect the HFC-S+ with the SRAM you can simplify PCB layout if you permutate address lines and data lines. If you connect data lines of the SRAM with data lines of the HFC-S+ and SRaddress lines of the HFC-S+ with address lines of the SRAM you can do this in any order. 3.9 Power down considerations For very low power consumption the oscillator of the HFC-S+ can be stopped. Furthermore the external SRAM is disabled (/SR_CS=1). To avoid current generated by floating inputs the data bus of the SRAM and all other inputs must be put to GND or VDD. So it is useful to connect the SRAM data bus to a resistor array of about 1MΩ. If the HFC-S+ is operated in processor mode the unused interrupt lines (and watchdog lines) should not be left open. They should be connected to VDD or GND over a resistor to reduce current. If the oscillator is stopped and the awake option is disabled the supply current is reduced to less than 1mA. :Q^eQbi " ! ## _V ' 863C 3.10 Cologne Chip Configuring test loops For electrical tests of layer 1 it is useful to create a S/T test loop for the B1/B2 channel. The test loop described here transmits the data that has been received on the B1 or B2 channel to the same channel on the S/T interface. To configure this loop the following must be done: - write 0Fh to register CLKDEL (37h) // Adjust the phase offset between receive and // transmit direction (the value depends on the external // circuitry). - write 43h to register SCTRL (31h) // 03h is to enable B1, B2 at the S/T interface for // transmission // 40h is for TX_LO setup (capacitive line mode) - write 00h to register STATES (30h) // Release S/T state machine for activation over the // S/T interface by incoming INFO 2 or INFO 4. - write 03h to register SCTRL_R (33h) // Configure S/T B1 and B2 channel to normal // receive operation. - write 36h to register CONNECT (2Fh) // Configure CONNECT register for B1/B2 channel // test loop. - write 80h to register B1_SSL (20h) // Enable transmit channel for GCI/IOM2 bus, pin // STIO1 is used as output, use time slot #0. - write C0h to register B1_RSL (24h) // Enable receive channel for GCI/IOM2 bus, pin // STIO1 is used as input, use time slot #0. - write 81h to register B2_SSL (21h) // Enable transmit channel for GCI/IOM2 bus, pin // STIO1 is used as output, use transmission slot #1. - write C1h to register B2_RSL (25h) // Enable receive channel for GCI/IOM2 bus, pin // STIO1 is used as input, use time slot #1. - write 01h to register MST_MODE (2Eh) // Configure HFC-S+ as GCI/IOM2 bus master. #$ _V ' :Q^eQbi " ! Cologne Chip 863C 4 Register bit description 4.1 Register bit description of the FIFO select register Name FIF_SEL Addr. 10h Bits 2..0 6..3 7 4.2 r/w Function w select FIFO and operation bit 2 bit 1 bit 0 selected operation 0 0 0 B1 transmit 0 0 1 B1 receive 0 1 0 B2 transmit 0 1 1 B2 receive 1 x 0 D transmit 1 x 1 D receive unused, should be '0' w select data transmission bit order '0' normal read/write data operation '1' reverse bit order read/write data operation Register bit description of S/T section Name STATES (read) Addr. 30h STATES 30h (write) :Q^eQbi " ! Bits 3..0 4 5 r/w r r r 6 7 r r 3..0 w 4 w 6..5 w 7 w Function binary value of actual state (NT: Gx, TE: Fx) Frame-Sync ('1'=synchronized) '1' timer T2 expired (NT mode only, see also 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT on page 61) '1' receiving INFO0 '0' no operation '1' in NT mode allows transition from G2 to G3. This bit is automatically cleared after the transition. binary value of new state (NT: Gx, TE: Fx) (bit 4 must also be set to load the state). '1' loads the prepared state (bit 3..0) and stops the state machine.This bit needs to be set for a minimum period of 5.21Ps and must be cleared by software. (reset default) '0' enables the state machine (bits 3..0 are ignored). After writing an invalid state the state machine goes to deactivated state (G1, F2) '00' no operation '01' no operation '10' start deactivation '11' start activation The bits are automatically cleared after activation/deactivation. '0' no operation '1' in NT mode allows transition from G2 to G3. This bit is automatically cleared after the transition. #% _V ' 863C Cologne Chip * important! The state machine is stuck to '0' after a reset. Writing a '0' to bit 4 of the STATES register restarts the state machine. In this state the HFC-S+ sends no signal on the S/T-line and it is not possible to activate it by incoming INFOx. NT mode: The NT state machine does not change automatically from G2 to G3 if the TE side sends INFO3 frames. This transition must be activated each time by bit 7 of the STATES register. Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data. #& _V ' :Q^eQbi " ! Cologne Chip 863C Name SCTRL Addr. 31h Bits 0 1 2 3 4 5 6 7 SCTRL_E 32h 0 1 2 3 4 6..5 7 :Q^eQbi " ! r/w Function w '0' B1 send data disabled (permanent 1 sent in activated states, reset default) '1' B1 data enabled w '0' B2 send data disabled (permanent 1 sent in activated states, reset default) '1' B2 data enabled w S/T interface mode '0' TE mode (reset default) '1' NT mode w D-channel priority '0' high priority 8/9 (reset default) '1' low priority 10/11 w S/Q bit transmission '0' S/Q bit disable (reset default) '1' S/Q bit and multiframe enable w '0' normal operation (reset default) '1' send 96kHz transmit test signal (alternating zeros) w TX_LO line setup This bit must be configured depending on the used S/T module and circuitry to match the 400Ω pulse mask test. '0' capacitive line mode (reset default) '1' non capacitive line mode w Power down '0' power up, oscillator active (reset default) '1' power down, oscillator stopped This bit is not cleared by a soft reset. w Power down mode bit '0' S/T awake disable (reset default) Power up can only be programmed by register access (SCTRL bit 7). '1' S/T awake enable. Oscillator starts on every non INFO0 S/T signal. w must be '0' w D reset '0' normal operation (reset default) '1' D bits are forced to '1' w D_U enable '0' normal operation (reset default) '1' D channel is always send enabled regardless of E receive bit w force E=0 (NT mode) '0' normal operation (reset default) '1' E-bit send is forced to 0 w must be '0' w '1' swap B1 and B2-channel in the S/T interface #' _V ' Cologne Chip 863C Name SCTRL_R Addr. 33h SQ_REC 34h Bits 0 1 7..2 3..0 4 6..5 7 SQ_SEND CLKDEL 34h 3..0 37h 7..4 3..0 6..4 7 r/w Function w B1-channel receive enable w B2-channel receive enable '0' B-receive bits are forced to '1' '1' normal operation w unused r TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) r '1' a complete S or Q multiframe has been received Reading SQ_REC clears this bit. r not defined r '1' ready to send a new S or Q multiframe Writing to SQ_SEND clears this bit. w TE mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) w not defined w TE: 4 bit delay value to adjust the 2 bit time between receive and transmit direction. The delay of the external S/Tinterface circuit can be compensated. The lower the value the smaller the delay between receive and transmit direction (see also Figure 10) NT: Data sample point. The lower the value the earlier the input data is sampled. The steps are 163ns. w NT mode only early edge input data shaping Low pass characteristic of extended bus configurations can be compensated. The lower the value the earlier input data pulse is sampled. No compensation means a value of 6 (110b). Step size is the same as for bits 3-0. w unused * note! The register is not initialized with a '0' after reset. The register should be initialized as follows before activating the TE/NT state machine: TE mode: 0Dh .. 0Fh NT mode: 6Ch #( _V ' :Q^eQbi " ! Cologne Chip 863C 4.3 Register bit description of GCI/IOM2 bus section Timeslots for transmit direction Name B1_SSL B2_SSL AUX1_SSL AUX2_SSL Addr. 20h 21h 22h 23h Bits 4..0 5 6 r/w w w w 7 w Function select GCI/IOM2 bus transmission slot (0..31) unused select GCI/IOM2 bus data lines '0' STIO1 output '1' STIO2 output transmit channel enable for GCI/IOM2 bus '0' disable (reset default) '1' enable * important! Enabling more than one channel on the same slot causes undefined output data. Timeslots for receive direction Name B1_RSL B2_RSL AUX1_RSL AUX2_RSL Addr. 24h 25h 26h 27h Bits 4..0 5 6 r/w w w w 7 w Function select GCI/IOM2 bus receive slot (0..31) unused select GCI/IOM2 bus data lines '0' STIO2 is input '1' STIO1 is input receive channel enable for GCI/IOM2 bus '0' disable (reset default) '1' enable Data registers Name B1_D B2_D AUX1_D AUX2_D :Q^eQbi " Addr. 28h 29h 2Ah 2Bh ! Bits 0..7 r/w Function r/w read/write data registers for selected timeslot data #) _V ' Cologne Chip 863C * note! Auxiliary channel handling If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for an internal connection between two CODECs. This mirroring is disabled by setting bit 1 in MST_EMOD register In ISA-PC mode: To use the AUX1 channel the address pin SA8 must be '1' at every access to the HFC-S+. To use the AUX2 channel the address pin SA9 must be '1' at every access to the HFC-S+. Name MST_MODE Addr. 2Eh Bits 0 1 2 3 5, 4 7, 6 r/w Function w GCI/IOM2 bus mode '0' slave (reset default) (C4IO and F0IO are inputs) '1' master (C4IO and F0IO are outputs) w polarity of C4- and C2O-clock '0' F0IO is sampled on negative clock transition '1' F0IO is sampled on positive clock transition w polarity of F0-signal '0' F0 positive pulse '1' F0 negative pulse w duration of F0-signal '0' F0 active for one C4-clock (244ns) (reset default) '1' F0 active for two C4-clocks (488ns) w time slot for codec-A signal F1_A '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' signal C2O → pin F1_A (C2O is 2048 kHz clock) w time slot for codec-B signal F1_B '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' AUX2 receive slot The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of the F0IO signal. The polatity of C2O can be changed by bit 1. RESET sets register MST_MODE to all '0's. $ _V ' :Q^eQbi " ! Cologne Chip 863C Name MST_EMOD Addr. 2Dh Bits 0 1 2 5..3 6 7 C/I 02h 3..0 TRxR 03h 7..4 0 1 5..2 6 7 :Q^eQbi " ! r/w Function w slow down C4IO clock adjustment (see Figure 13) '0' C4IO clock is adjusted in the 31th time slot twice for one half clock cycle (reset default) '1' C4IO clock is adjusted in the 31th time slot once for one half clock cycle w enable/disable AUX channel mirroring '0' mirror AUX receive to AUX transmit (reset default) '1' disable AUX channel data mirroring w unused w select D-channel data flow (see also: CONNECT register) destination source bit 3: '0' D-HFC ← D-S/T '1' D-HFC ← D-GCI/IOM2 bit 4: '0' D-S/T ← D-HFC '1' D-S/T ← D-GCI/IOM2 bit 5: '0' D-GCI/IOM2 ← D-HFC '1' D-GCI/IOM2 ← D-S/T w unused w enable GCI/IOM2 write slots '0' disable GCI/IOM2 write slots; slot #2 and slot #3 may be used for normal data '1' enables slot #2 and slot #3 as master, D- and C/I-channel r/w on read: indication on write: command unused r reserved r '1' Monitor transmitter ready Writing on MON2_D starts transmisssion and resets this bit. r reserved r STIO2 in r STIO1 in $! _V ' Cologne Chip 863C 4.4 Register bit description of CONNECT register Name CONNECT Addr. 2Fh Bits 2..0 5..3 7..6 r/w Function w select B1-channel data flow destination bit 0: '0' B1-HFC '1' B1-HFC bit 1: '0' B1-S/T '1' B1-S/T bit 2: '0' B1-GCI/IOM2 '1' B1-GCI/IOM2 w select B2-channel data flow destination bit 3: '0' B2-HFC '1' B2-HFC bit 4: '0' B2-S/T '1' B2-S/T bit 5: '0' B2-GCI/IOM2 '1' B2-GCI/IOM2 w unused ← ← ← ← ← ← source B1-S/T B1-GCI/IOM2 B1-HFC B1-GCI/IOM2 B1-HFC B1-S/T ← ← ← ← ← ← source B2-S/T B2-GCI/IOM2 B2-HFC B2-GCI/IOM2 B2-HFC B2-S/T RESET sets CONNECT register to all '0's. The following figure shows the different options for switching the B-channels with the CONNECT register (similar for D-channel: see MST_EMOD register). Figure 5: Function of the CONNECT register bits $" _V ' :Q^eQbi " ! Cologne Chip 863C 4.5 Register bit description of interrupt, status and control registers Name CIRM Addr. 18h Bits 2..0 3 4 5 6 7 :Q^eQbi " ! r/w Function w select IRQ channel in PC mode '000' IRQ disable '001' IRQ_A '010' IRQ_B '011' IRQ_C '100' IRQ_D '101' IRQ_E '110' IRQ_F '111' IRQ disable w soft reset, similar as hardware reset; the registers CIP, CIRM and CTMT are not changed so selected I/O address is kept in ISA-PC mode. The reset is active until the bit is cleared. '0' deactivate reset (reset default) '1' activate reset w select memory '0' 32K x 8 external RAM (reset default) '1' 8K x 8 external RAM w external interrupt enable '0' ext. interrupt disable, IRQ_A is output (reset default) '1' ext. interrupt enable IRQ_A is input and ored to IRQ output w double clock mode (24.576 MHz external oscillator required) when set, all RAM accesses are double speed w FIFO reset The currently selected FIFO is initialised. This bit is automatically cleared. $# _V ' Cologne Chip 863C Name CTMT Addr. 19h Bits 0 1 4..2 5 6 7 CHIP_ID 16h 3..0 7..4 B_MODE 13h 1..0 2 3 4 5 6 7 $$ _V ' r/w Function w HDLC/transparent mode for B1-channel '0' HDLC mode (reset default) '1' transparent mode w HDLC/transparent mode for B2-channel '0' HDLC mode (reset default) '1' transparent mode w select timer and watchdog (bit 4 = MSB) timer watchdog '000' off off '001' 3.125ms 6.25ms '010' 6.25ms 12.5ms '011' 12.5ms 25ms '100' 25ms 50ms '101' 50ms 100ms '110' 400ms 800ms '111' 800ms 1600ms w timer/watchdog reset mode '0' reset timer/WD by CTMT bit 7 (reset default) '1' automatically reset timer/WD at each access to HFC-S+ w ignored w reset timer/WD '1' reset timer/WD This bit is automatically cleared. r reserved r Chip identification 0001b HFC-S+ w unused w in 64 kbit/s mode: bit is ignored in 56 kbit/s mode: value of the LSB in 7-bit mode w unused w 56 kbit/s mode selection bit for B1-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode w 56 kbit/s mode selection bit for B2-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode w '0' Data not inverted for B1-channel (reset default) '1' Data inverted for B1-channel w '0' Data not inverted for B2-channel (reset default) '1' Data inverted for B2-channel :Q^eQbi " ! Cologne Chip 863C Name INT_M1 Addr. 1Ah Bits 0 1 2 3 4 5 6 7 r/w w w w w w w w w Function interrupt mask for channel B1 in transmit direction interrupt mask for channel B2 in transmit direction interrupt mask for channel D in transmit direction interrupt mask for channel B1 in receive direction interrupt mask for channel B2 in receive direction interrupt mask for channel D in receive direction interrupt mask for state change of TE/NT state machine interrupt mask for timer For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name INT_M2 Addr. 1Bh Bits 0 1 2 3 4 5 7..6 r/w w w w w w w w Function interrupt mask for processing/non processing phase transition interrupt mask for GCI I-change interrupt mask for GCI monitor receive enable for interrupt output ('1' = enable) interrupt output is reversed interrupt from external device is reversed unused For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name TRM Addr. 12h Bits 1..0 4..2 5 6 7 :Q^eQbi " ! r/w Function w interrupt in transparent mode is generated if Z1 in receive FIFOs or Z2 in transmit FIFOs change from: 00: x xxxx x011 1111 → x xxxx x100 0000 01: x xxxx 0111 1111 → x xxxx 1000 0000 10: x xxx0 1111 1111 → x xxx1 0000 0000 11: x 0111 1111 1111 → x 1000 0000 0000 w must be '0' w E → B2 receive channel When set the E receive channel of the S/T interface is connected to the B2 receive channel. w B1+B2 mode '0' normal operation (reset default) '1' B1+B2 are combined to one HDLC or transparent channel. All settings for data shape and connect are derived from B1. w IOM test loop When set MST output data is looped to the MST input. $% _V ' Cologne Chip 863C Name INT_S1 Addr. 1Eh Bits 0 1 2 3 4 5 6 7 INT_S2 1Fh 0 1 2 7 r/w Function r B1-channel interrupt status in transmit direction r B2-channel interrupt status in transmit direction in HDLC mode: '1' a complete frame has been transmitted, the frame counter F2 has been incremented in transparent mode: '1' interrupt as selected in TRM register bits 1..0 r D-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter F2 was incremented r B1-channel interrupt status in receive direction r B2-channel interrupt status in receive direction in HDLC mode: '1' a complete frame has been transmitted, the frame counter F1 has been incremented in transparent mode: '1' interrupt as selected in TRM register bits 1..0 r D-channel interrupt status in receive direction '1' a complete frame was received, the frame counter F1 was incremented r TE/NT state machine interrupt status '1' state of state machine changed r timer interrupt status '1' timer is elapsed r processing/non processing transition interrupt status '1' The HFC-S+ has changed from processing to non processing state. r GCI I-change interrupt '1' a different I-value on GCI was detected r receiver ready (RxR) of monitor channel '1' 2 monitor bytes have been received r unused, '0' * important! Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2 register. New interrupts may occur during read. These interrupts are reported at the next read of INT_S1 or INT_S2. All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2). The mask register settings only influence the interrupt output condition. The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during this read the interrupt line goes active immediately after the read is finished. So processors with level or transition triggered interrupt inputs can be connected. $& _V ' :Q^eQbi " ! Cologne Chip 863C Name STATUS Addr. 1Ch Bits 0 1 2 3 4 5 6 7 r/w Function r BUSY/NOBUSY status '1' the HFC-S+ is BUSY after initialising Reset FIFO, increment F or change FIFO '0' the HFC-S+ is not busy, all accesses are allowed r processing/non processing status '1' the HFC-S+ is in processing phase (every 125µs) '0' the HFC-S+ is not in processing phase r processing/non processing transition interrupt status '1' The HFC-S+ has finished internal processing phase (every 125µs) r unused, '0' r timer status '0' timer not elapsed '1' timer elapsed r TE/NT state machine interrupt state '1' state of state machine has changed r FRAME interrupt has occured (any data channel interrupt) all masked D-channel and B-channel interrupts are "ored" r ANY interrupt all masked interrupts are "ored" Reading the STATUS register clears no bit. :Q^eQbi " ! $' _V ' Cologne Chip 863C 5 Electrical characteristics Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD VI VO Topr Tstg Rating -0.3V to +7.0V -0.3V to VCC + 0.3V -0.3V to VCC + 0.3V -10°C to +85°C -40°C to +125°C Recommended operating conditions Parameter Supply voltage Operating temperature Supply current normal Symbol VDD MIN. 4.75V 3.15V 0°C Topr IDD power down *) Condition VDD=5V VDD=3.3V fCLK=12.288MHz VDD = 5V, running oscillator: VDD = 3.3V, running oscillator: oscillator stopped*): TYP. 5.0V 3.3V MAX. 5.25V 3.45V +70°C 25mA 8mA < 1mA see also: 3.9 Power down considerations Electrical characteristics for 5V power supply VDD = 4.75V to 5.25V, Topr = 0°C to +70°C Parameter Symbol Condition MIN. Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage Output leakage current Pull-up resistor input current VIL VIH VOL VOH | IOZ | | IIL | TTL level TYP. MAX. 0.8V 2.0V 0.4V 4.3V High Z VI = VSS 10µA 50µA CMOS level MIN. TYP. MAX. 1.0V 3.5V 0.4V 4.3V 10µA 50µA Electrical characteristics for 3.3V power supply VDD = 3.15V to 3.45V, Topr = 0°C to +70°C Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage $( _V ' Symbol VIL VIH VOL VOH Condition TTL level MIN. TYP. MAX. 0.8V 2.0V 0.4V 2.4V CMOS level MIN. TYP. MAX. 1.0V 2.3V 0.4V 2.4V :Q^eQbi " ! Cologne Chip 863C I/O Characteristics Input IIOSEL0-3 SA0-9 /AEN /IOR /IOW BD0-7 ALE SRD0-7 C4IO F0IO STIO1-2 IRQ_A RESET :Q^eQbi " ! Interface Level TTL, internal pull-up resistor TTL TTL TTL TTL TTL TTL TTL TTL, internal pull-up resistor TTL, internal pull-up resistor TTL, internal pull-up resistor TTL (as IRQ input) CMOS Schmitt Trigger $) _V ' Cologne Chip 863C Driver Capability Low High Output 0.4V IOCHRDY 6mA BD0-7 18mA BUSDIR 4mA 2mA TX2_HI 4mA 2mA /TX1_LO 12mA /TX_EN 4mA /TX2_LO 12mA TX1_HI 4mA 2mA ADJ_LEV 1mA 0.5mA SRD0-7 4mA 2mA SRA0-14 2mA 1mA /SRRD 4mA 2mA /SRCS 4mA 2mA /SRWE 4mA 2mA C4IO 6mA 3mA F0IO 6mA 3mA STIO1-2 6mA 3mA F1_A-B 6mA 3mA IRQA-F 6mA 3mA % _V ' 0.6V VDD - 0.4V 24mA 8mA 2mA :Q^eQbi " ! Cologne Chip 863C 6 Timing characteristics 6.1 ISA-PC bus or processor access Timing diagram 1: ISA-PC bus or microprocessor access SYMBOL CHARACTERISTICS MIN. MAX. tRDD /IOR Low to Read Data Out Time 3ns 25ns tRDDH /IOR High to Data Buffer Turn Off Time 2ns 15ns tSA Address to /IOR or /IOW Low Setup Time 20ns – tSAH Address Hold Time after /IOR or /IOW High 20ns – tRD Read Time 50ns z tWR Write Time 50ns z tWRDSU Write Data Setup Time to /IOW Low 30ns z tWRDH Write Data Hold Time from /IOW High 10ns – tRDY Delay Time from /IOR or /IOW Low to IOCHRDY Low 3ns 30ns tRDYH Delay Time from /IOR Low or /IOW High to IOCHRDY High 3ns 30ns tBUSRD Delay Time from /IOR Low to BUSDIR Low 3ns 25ns tBUSRDH Delay Time from /IOR High to BUSDIR High 2ns 15ns :Q^eQbi " ! %! _V ' Cologne Chip 863C SYMBOL tCYCLE CHARACTERISTICS Read/Write cycle MIN. MAX. 6 x tCLK – * important! For write accesses to the HFC-S+ the data lines must be stable and valid before /IOW or /DS get low. With Intel compatible processors it may be neccessary to delay the /IOW or /DS signals. 6.2 SRAM access Timing diagram 2: SRAM access SYMBOL CHARACTERISTICS MIN. MAX. 12.288MHz 24.576MHz *) 0 ±10-4 fCLK OSC_IN frequency 'fCLK / fCLK Relative OSC_IN frequency deviation tCLK OSC_IN Cycle Time 1/ fCLK tLOW**) OSC_IN Low Level Width tCLK / 3 tHIGH**) OSC_IN High Level Width tCLK / 3 tSRA Address Stable after OSC_IN ↓ 2ns 15ns tSRAH Address Stable Hold Time after OSC_IN ↓ 1ns – tSRD Data Out Stable after OSC_IN Ç 10ns 30ns %" _V ' :Q^eQbi " ! Cologne Chip 863C SYMBOL CHARACTERISTICS MIN. MAX. tSRDH Data Out Stable Hold Time after OSC_IN Ç 5ns – tSRDSU Data In Setup Time to OSC_IN ↓ 20ns – tSRDHR Data In Hold Time after OSC_IN ↓ 0ns – tSRWR Delay Time OSC_IN Ç to /SRWR Low 5ns 15ns tSRWRH Delay Time OSC_IN Ç to /SRWR High 5ns 15ns tSRWRA Data Hold Time after /SRWR Ç 1ns – tSRWRA Address Hold Time after /SRWR Ç tCLK / 3 – *) **) 6.3 Double clock mode with 24.576MHz OSC_IN should be symmetrical so tLOW = tHIGH GCI/IOM2 bus clock and data alignment for Mitel STTM bus Figure 6: GCI/IOM2 bus clock and data alignment :Q^eQbi " ! %# _V ' Cologne Chip 863C 6.4 GCI/IOM2 timing Timing diagram 3: GCI/IOM2 timing *) F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set F0IO is also awaited one C4IO clock cycle earlier. 6.4.1 Master mode To configure the HFC-S+ as GCI/IOM2 bus master bit 0 of the MST_MODE register must be set. In this case C4IO and F0IO are outputs. SYMBOL CHARACTERISTICS MIN. TYP. *) 308 ns*) tC4P Clock C4IO period (4.096 MHz) 180 ns tC4H Clock C4IO High Width 78 ns *) 122 ns *) 166 ns*) tC4L Clock C4IO Low Width 78 ns *) 122 ns *) 166 ns *) tC2P Clock C2O Period 360 ns 488.28 ns 616 ns tC2H Clock C2O High Width 180 ns 244.14 ns 308 ns tC2L Clock C2O Low Width 180 ns 244.14 ns 308 ns %$ _V ' 244.14 ns MAX. *) :Q^eQbi " ! Cologne Chip 863C SYMBOL tF0iW CHARACTERISTICS MIN. TYP. MAX. Short F0IO 230 ns 244 ns 260 ns Long F0IO 460 ns 488 ns 520 ns 10 ns 25 ns F0IO Width tSToD STIO1/2 Delay fom C4IO ↓ Level 1 Output tF0iCYCLE F0IO Cycle Time 1 half clock adjust 124.955 us 125.000 us 125.045 us 2 half clocks adjust 124.910 us 125.000 us 125.090 us All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 Mhz. *) Time depends on accuracy of OSC_IN frequency. Because of clock adjustment in the 31st time slot these are the worst case timings when C4IO is adjusted. 6.4.2 Slave mode To configure the HFC-S+ as GCI/IOM2 bus slave bit 0 of the MST_MODE register must be cleared (reset default). In this case C4IO and F0IO are inputs. SYMBOL CHARACTERISTICS MIN. TYP. MAX. 244.14 ns*) tC4P Clock C4IO period (4.096 MHz) tC4H Clock C4IO High Width 20 ns tC4L Clock C4IO Low Width 20 ns tC2P Clock C2O Period tC2H Clock C2O High Width 25 ns tC2L Clock C2O Low Width 25 ns tF0iS F0IO Setup Time to C4IO ↓ 20 ns tF0iH F0IO Hold Time after C4IO ↓ 20 ns tF0iW F0IO Width 40 ns tSTiS STIO2 Setup Time 20 ns tSTiH STIO2 Hold Time 20 ns 488.28 ns*) All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 Mhz. *) If the S/T interface is synchronized from C4IO (NT mode) the frequency must be stable to 10 -4. :Q^eQbi " ! %% _V ' Cologne Chip 863C 7 S/T interface circuitry In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the HFC-S+ needs some additional circuitry, which are shown in the following figures. 7.1 External receiver circuitry VDD R1 C3 R2 R7 R3 LEV_R1 R1 R5 R6 10 S/T module 5 RX + D1 R1´ D2 R5´ 11 16 12 14 S/T side VDD GND D3 D4 R6´ LEV_R2 RX - R2´ R2 C3´ R4 ADJ_LEV C1 GND Figure 7: External receiver circuitry Part list VDD R1, R1' R2, R2' R3 R4 R5, R5' R6, R6' R7 5V 1 M: 33 k: 100 k: 3.9 k: 4.7 k: 4.7 k: 1.8 M: 3.3V 680 k: C1 C3, C3' D1, D2 D3, D4 S/T module 47 nF 22 pF 1N4148 or LL4148 1N4148 or LL4148 see Table 5 on page 59 1.2 M: C3, C3' are for reduction of high frequency input noise and should be located as close as possible to the HFC-S+. %& _V ' :Q^eQbi " ! Cologne Chip 863C 7.2 External transmitter circuitry VDD R6 R4 C3 R5 T3 TX_EN TX1_HI TX2_HI R1 R1´ T1 T1´ R7 R2 R2´ T2 TX2_LO T2´ R8 R3 R3´ TX1_LO GND 9 D2 ZD1 D3 S/T module 1 8 3 7 18 GND D4 D5 TX + S/T side TX - Figure 8: External transmitter circuitry Part List VDD R1 R2 R3, R3' *) R4 R5 R6 R7 R8 *) 5V 2.2 k: 1% 3.0 k: 1% 18 : 100 : 5.6 k: 3.3 k: 3.3 k: 2.2 k: 3.3V 560 : 3.9 k: 1% 18 : 0 : 3.3 k: 2.2 k: 1.8 k: 2.2 k: C3 D2, D3 D4, D5 ZD1 T1, T1' T2, T2' T3 S/T module 470 pF 1N4148 or LL4148 1N4148 or LL4148 Z-Diode 2.7 V (e. g. BZV 55C 2V7) BC550C, BC850C or similar BC550C, BC850C or similar BC560C, BC860C or similar see Table 5 on page 59 value is depending on the used S/T module :Q^eQbi " ! %' _V ' 863C Cologne Chip S/T module part number APC 56624-1 manufacturer Advanced Power Components United Kingdom S-Hybrid modules with receiver and transmitter Phone: +44 1634-290-588 Fax: +44 1634-290-591 circuitry included: http://www.apcisdn.com APC 5568-3V APC 5568-5V APC 5568DS-3V APC 5568DS-5V FE 8131-55Z FEE GmbH Singapore Phone: +65 741-5277 Fax: +65 741-3013 Bangkok Phone: +662 718-0726-30 Fax: +662 718-0712 Germany Phone: +49 6106-82980 Fax: +49 6106-829898 transformers: Pulse Engineering, Inc. United States PE-64995 Phone: +1-619-674-8100 PE-64999 Fax: +1-619-674-8262 PE-65795 http://www.pulseeng.com PE-65799 PE-68995 PE-68999 T5006 T5007 S0-modules: T5012 T5034 T5038 transformers: Sun Myung Korea SM TC-9001 Phone: +82-348-943-8525 SM ST-9002 Fax: +82-348-943-8527 SM ST-16311F http://www.sunmyung.com S0-modules: SM TC-16311 SM TC-16311A transformers UMEC GmbH Germany UT21023 Phone: +49 7131-7617-0 S0-modules: Fax: +49 7131-7617-20 UT 21624 Taiwan UT 28624 A Phone: +886-4-359-009-6 Fax: +886-4-359-012-9 United States Phone: +1-310-326-7072 Fax: +1-310-326-7058 http://www.umec.de %( _V ' :Q^eQbi " ! Cologne Chip 863C S/T module part number T 6040... transformers: 3-L4021-X066 3-L4025-X095 3-L5024-X028 3-L4096-X005 3-L5032-X040 S0-modules: 7-L5051-X014 7-M5051-X032 7-L5052-X102 7-M5052-X110 7-M5052-X114 transformers: ST5069 S0-modules: PT5135 ST5201 ST5202 543 76 009 00 manufacturer VAC GmbH Germany Phone: +49 6181/ 38-0 Fax: +49 6181/ 38-2645 http://www.vacuumschmelze.de Valor Electronics, Inc. Asia Phone: +852 2333-0127 Fax: +852 2363-6206 North America Phone: +1 800 31VALOR Fax: +1 619 537-2525 Europe Phone: +44 1727-824-875 Fax: +44 1727-824-898 http://www.valorinc.com Vogt electronic AG Germany Phone: +49 8591/ 17-0 Fax: +49 8591/ 17-240 http://www.vogt-electronic.com Table 5: S/T module part numbers and manufacturer :Q^eQbi " ! %) _V ' Cologne Chip 863C 7.3 Oscillator circuitry Part list: OSC_IN C1 R2 Q1 Q1 12.288 MHz quartz R1 R2 C1, C2 0..50 : 1 M: 47 pF OSC_OUT C2 R1 Figure 9: Oscillator Circuitry The values of C1, C2 and R1, R2 depend on the used quartz. For a load-free check of the oscillator frequency the C4O clock of the GCI/IOM2 bus should be measured (HFC-S+ as master, S/T interface deactivated, 4.096 MHz frequency intented on the C4IO). The input signal on OSC_IN should be as big as possible. & _V ' :Q^eQbi " ! Cologne Chip 863C 8 State matrices for NT and TE 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT State name State number INFO sent Event State machine release (Note 3) Activate request Deactivate request Expiry T2 (Note 2) Receiving INFO 0 Receiving INFO 1 Receiving INFO 3 Reset Deactive Pending activation Active Pending deactivation G0 G1 G2 G3 G4 INFO 0 INFO 0 INFO 2 INFO 4 INFO 0 G2 | | | | G2 (Note 1) G2 (Note 1) | | G2 (Note 1) | Start timer T2 G4 Start timer T2 G4 | G1 G2 G1 G3 (Note 1) G2 (Note 1) / / Table 6: Activation/deactivation layer 1 for finite state matrix for NT / | No state change Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons Impossible by the definition of the physical layer service Note 1: Timer 1 (T1) is not implemented in the HFC-S+ and must be implemented in software. Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32ms (256 x 125µs). This implies that a TE has to recognize INFO 0 and to react on it within this time. Note 3: After reset the state machine is fixed to G0. * hint! Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data. :Q^eQbi " ! &! _V ' Cologne Chip 863C 8.2 Activation/deactivation layer 1 for finite state matrix for TE State name Event State number Info sent State machine release (Note 1) Activate Receiving any signal Request Receiving INFO 0 Expiry T3 (Note 5) Receiving INFO 0 Receiving any signal (Note 2) Receiving INFO 2 (Note 3) Receiving INFO 4 (Note 3) Lost framing (Note 4) Reset Sensing Deactivated Awaiting signal Identifying input Synchronized Activated Lost framing F0 F2 F3 F4 F5 F6 F7 F8 INFO 0 INFO 0 INFO 0 INFO 1 INFO 0 INFO 3 INFO 3 INFO 0 F2 / / / / / / | | F5 F4 | | | | / F3 F3 F3 F3 F3 F3 / / F6 F6 F7 | | F6 F6 F6 F6 F7 F7 F7 F7 F7 / / / / F8 F8 / F3 F5 Table 7: Activation/deactivation layer 1 for finite state matrix for TE | / No change, no action Impossible by the definition of the layer 1 service Impossible situation Notes Note 1: After reset the state machine is fixed to F0. Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined wether it is INFO 2 or INFO 4. Note 3: Bit- and frame-synchronisation achieved. Note 4: Loss of Bit- or frame-synchronisation. Note 5: Timer 3 (T3) is not implemented in the HFC-S+ and must be implemented in software. &" _V ' :Q^eQbi " ! Cologne Chip 863C 9 Binary organisation of the frames 9.1 S/T frame structure The frame structures on the S/T interface are different for each direction of transmission. Both structures are illustrated in Figure 10. Figure 10: Frame structure at reference point S and T F L D E FA M Framing bit D.C. balancing bit D-channel bit D-echo-channel bit Auxiliary framing bit Multiframing bit N B1 B2 A S Bit set to a binary value N = F A (NT to TE) Bit within B-channel 1 Bit within B-channel 2 Bit used for activation S-channel bit * note! Lines demarcate those parts of the frame that are independently d.c.-balanced. The FA bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is enabled (see SCTRL register). The nominal 2-bit offset is as seen from the TE. The offset can be adjusted with the CLKDEL register in TE mode. The corresponding offset at the NT may be greater due to delay in the interface cable and varies by configuration. HDLC-B-channel data start with the LSB, PCM-B-channel data start with the MSB. :Q^eQbi " ! &# _V ' Cologne Chip 863C 9.2 GCI frame structure The binary organistation of a single GCI channel frame is described below. C4IO clock frequency is 4.096MHz. C 4 IO F 0 IO b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b1 b2 b4 b3 b2 b1 D IN D O UT B1 B2 M T im e S lo t 0 T im e S lo t 1 T im e S lo t 2 D C /I T im e S lo t 3 M M R X B1 B1 T im e S lo t 4 T im e S lo t 3 2 G C I F ra m e Figure 11: Single channel GCI format B1 B2 M D C/I MR MX &$ _V ' B-channel 1 data B-channel 2 data Monitor channel data D-channel data Command/indication bits for controlling activation/deactivation and for additional control functions Handshake bit for monitor channel Handshake bit for monitor channel :Q^eQbi " ! Cologne Chip 863C 10 Clock synchronisation 10.1 Clock synchronisation in NT-mode Figure 12: Clock synchronisation in NT-mode :Q^eQbi " ! &% _V ' 863C 10.2 Cologne Chip Clock synchronisation in TE-mode Figure 13: Clock synchronisation in TE-mode The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus twice for one half clock cycle. This can be reduced to one adjustment of a half clock cycle. This is useful if another HFC-S, HFC-SP or HFCS+ is connected as slave in NT mode to the GCI/IOM2 bus. && _V ' :Q^eQbi " ! Cologne Chip 863C 11 HFC-S+ package dimensions Figure 14: HFC-S+ package dimensions :Q^eQbi " ! &' _V ' 863C Cologne Chip 12 ISDN PC card sample circuitry with HFC-S+ &( _V ' :Q^eQbi " ! Cologne Chip 863C :Q^eQbi " ! &) _V ' Cologne Chip 863C Part List Part C1 C2 C3 C7 C8 C9 C10 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 D1 D2 D3 D4 D6 D7 D8 *) ' _V ' Value 47pF *) 47pF *) 47nF optional 1nF 470pF optional 33nF 33nF 33nF 33nF 33nF 33nF 22µF 22µF LL4148 LL4148 LL4148 LL4148 2V7 LL4148 LL4148 Part D9 D10 Q1 Q2 Q3 Q29 Q30 Q34 R1 R2 R3 R4 R5 R5' R6 R6' R7 R7' R8 R8' R9 R10 Value LL4148 LL4148 12.288MHz BC850C BC850C BC850C BC860C BC850C 50:*) 1M:*) 1M: 3.9k: 4.7k: 4.7k: 4.7k: 4.7k: 100k: 100k: 33k: 33k: 1.8M: 3.3k: Part R11 R12 R13 R14 R14' R15 R15' R16 R16' R17 R18 R19 TR1 JP1 CON1 CON2 CON3 U1 U2 Value 100: 5.6k: 100k: 2.2k: 1% 2.2k: 1% 3.0k: 1% 3.0k: 1% 18: 18: 15: 2.2k: 3.3k: S/T module PINHD-2X4 PINHD-2X4 WESTERN ISA HFC-S+ 62256FP values are depending on the used quarz oscillator :Q^eQbi " !