ETC HT27LC4096

HT27LC4096
CMOS 256K´16-Bit OTP EPROM
Features
· Operating voltage: +3.3V
· 256K´16-bits organization
· Programming voltage
· Fast read access time: 90ns
- VPP=12.5V±0.2V
- VCC=6.0V±0.2V
· Fast programming algorithm
· Programming time 75ms typ.
· High-reliability CMOS technology
· Two line controls (OE and CE)
· Latch-up immunity to 100mA from -1.0V to
· Standard product identification code
VCC+1.0V
· Commercial temperature range (0°C to +70°C)
· CMOS and TTL compatible I/O
· 40-pin plastic DIP package
· Low power consumption
44-pin PLCC package
- Active: 15mA max.
- Standby: 1mA typ.
General Description
with respect to spec. This eliminates the need for WAIT
states in high-performance microprocessor systems.
The HT27LC4096 has separate Output Enable (OE)
and Chip Enable (CE) controls which eliminate bus contention issues.
The HT27LC4096 chip family is a low-power, 4096K
(4,194,304) bits, +3.3V electrically one-time programmable (OTP) read-only memories (EPROM). Organized
into 256K words with 16 bits per word, it features a fast
single address location programming, typically at 75ms
per word. Any word can be accessed in less than 90ns
Block Diagram
R o w
A d d re s s
X -D e c o d e r
C e ll A r r a y
C o lu m n
A d d re s s
Y -D e c o d e r
Y - G a tin g
C E & O E &
T E S T
C o n tr o l L o g ic
S A C K T
&
O u tp u t B u ffe r
C E
O E
Rev. 1.20
V C C
1
V S S
V P P
D Q 0 ~ D Q 1 5
November 22, 2002
HT27LC4096
Pin Assignment
3 5
A 1 3
D Q 1 1
7
3 4
A 1 2
D Q 1 0
8
3 3
A 1 1
D Q 9
9
3 2
A 1 0
D Q 8
1 0
3 1
A 9
A 6
2 6
A 5
1 6
2 5
A 4
D Q 2
1 7
2 4
A 3
D Q 1
1 8
2 3
A 2
D Q 0
1 9
2 2
A 1
O E
2 0
2 1
A 0
9
3 7
A 1 1
D Q 9
1 0
3 6
D Q 8
1 1
3 5
A 1 0
A 9
V S S
1 2
N C
1 3
D Q 7
1 4
D Q 6
1 5
D Q 5
1 6
D Q 4
1 7
H T 2 7 L C 4 0 9 6
4 4 P L C C -A
1 8 1 9
2 0 2 1 2 2
2 3 2 4 2 5
2 6
2 7 2 8
3 4
V S S
3 3
3 2
N C
A 8
3 1
A 7
3 0
A 6
2 9
A 5
A 4
2 7
1 5
A 1 2
D Q 1 0
A 3
1 4
D Q 4
D Q 3
A 1 3
3 8
A 2
A 7
4 0
3 9
A 1
2 8
4 2 4 1
8
A 0
1 3
4 4 4 3
D Q 1 1
O E
D Q 6
D Q 5
1
N C
A 8
2
D Q 0
V S S
2 9
3
D Q 1
3 0
1 2
4
7
D Q 2
1 1
5
D Q 1 2
D Q 3
V S S
D Q 7
6
A 1 4
6
A 1 5
A 1 4
D Q 1 2
A 1 6
3 6
A 1 7
A 1 5
5
V C C
A 1 6
3 7
N C
3 8
4
V P P
3
E
A 1 7
5
V C C
3 9
4
4 0
2
3
1
C E
D Q 1 5
D Q 1 4
D Q 1 3
C
D Q 1
D Q 1
D Q 1
V P P
H T 2 7 L C 4 0 9 6
4 0 D IP -A
Pin Description
Pin Name
I/O/P
Description
VPP
P
Program voltage supply
CE
I
Chip enable
DQ0~DQ15
I/O
Data inputs/outputs
VSS
¾
Negative power supply, ground
OE
I
Output enable
A0~A17
I
Address inputs
VCC
¾
Positive power supply
Absolute Maximum Rating
Operation Temperature Commercial ............................................................................................................0°C to 70°C
Storage Temperature.............................................................................................................................-65°C to 125 °C
Applied VCC Voltage with Respect to VSS ................................................................................................. -0.6V to 7.0V
Applied Voltage on Input Pin with Respect to VSS..................................................................................... -0.6V to 7.0V
Applied Voltage on Output Pin with Respect to VSS ......................................................................... -0.6V to VCC+0.5V
Applied Voltage on A9 Pin with Respect to VSS ...................................................................................... -0.6V to 13.5V
Applied VPP Voltage with Respect to VSS ................................................................................................-0.6V to 13.5V
Applied READ Voltage (Functionality is guaranteed between these limits) ................................................+3.0V to 3.6V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
2
November 22, 2002
HT27LC4096
D.C. Characteristics
Symbol
Parameter
Test Conditions
Conditions
VCC
Min.
Typ.
Max.
Unit
Read operation
VOH
Output High Level
3.3V
IOH=-0.4mA
2.4
¾
¾
V
VOL
Output Low Level
3.3V
IOL=2.1mA
¾
¾
0.45
V
VIH
Input High Level
3.3V
¾
2
¾
VCC+0.5
V
VIL
Input Low Level
3.3V
¾
-0.3
¾
0.8
V
ILI
Input Leakage Current
3.3V
VIN=0 to 3.6V
-5
¾
5
mA
ILO
Output Leakage Current
3.3V
VOUT=0 to 3.6V
-10
¾
10
mA
ICC
VCC Active Current
3.3V
CE=VIL, f=5MHz,
IOUT=0mA
¾
¾
15
mA
ISB1
Standby Current (CMOS)
3.3V
CE=VCC±0.3V
¾
1
10
mA
ISB2
Standby Current (TTL)
3.3V
CE=VIH
¾
¾
0.6
mA
IPP
VPP Read/Standby Current
3.3V
CE=OE=VIL,
VPP=VCC
¾
¾
100
mA
2.4
¾
¾
V
Programming operation
VOH
Output High Level
6V
IOH=-0.4mA
VOL
Output Low Level
6V
IOL=2.1mA
¾
¾
0.45
V
¾
0.7VCC
¾
VCC+0.5
V
6V
¾
-0.5
¾
0.8
V
¾
¾
5
mA
VIH
Input High Level
6V
VIL
Input Low Level
ILI
Input Load Current
6V
VIN=VIL, VIH
VH
A9 Product ID Voltage
6V
¾
11.5
¾
12.5
V
ICC
VCC Supply Current
6V
¾
IPP
VPP Supply Current
¾
¾
40
mA
6V
CE=VIL
¾
¾
10
mA
Capacitance
CIN
Input Capacitance
3.3V
VIN=0V
¾
8
12
pF
COUT
Output Capacitance
3.3V
VOUT=0V
¾
8
12
pF
CVPP
VPP Capacitance
3.3V
VPP=0V
¾
18
25
pF
A.C. Characteristics
Symbol
Ta=+25°C±5°C
Test Conditions
Parameter
VCC
Conditions
Min.
Typ.
Max.
Unit
Read operation
tACC
Address to Output Delay
3.3V CE=OE=VIL
¾
¾
90
ns
tCE
Chip Enable to Output Delay
3.3V OE=VIL
¾
¾
90
ns
tOE
Output Enable to Output Delay
3.3V CE=VIL
¾
¾
45
ns
tDF
CE or OE High to Output Float, Whichever
3.3V
Occurred First
¾
¾
¾
40
ns
tOH
Output Hold from Address, CE or OE,
Whichever Occurred First
¾
0
¾
¾
ns
Rev. 1.20
3.3V
3
November 22, 2002
HT27LC4096
Symbol
Test Conditions
Parameter
VCC
Conditions
Min.
Typ.
Max.
Unit
Programming operation
tAS
Address Setup Time
6V
¾
2
¾
¾
ms
tOES
OE Setup Time
6V
¾
2
¾
¾
ms
tDS
Data Setup Time
6V
¾
2
¾
¾
ms
tAH
Address Hold Time
6V
¾
0
¾
¾
ms
tDH
Data Hold Time
6V
¾
2
¾
¾
ms
tDFP
Output Enable to Output Float Delay
6V
¾
0
¾
130
ns
tVPS
VPP Setup Time
6V
¾
2
¾
¾
ms
tPW
CE Program Pulse Width
6V
¾
30
75
105
ms
tVCS
VCC Setup Time
6V
¾
2
¾
¾
ms
tCES
CE Setup Time
6V
¾
2
¾
¾
ms
tOE
Data Valid from OE
6V
¾
¾
¾
150
ns
tPRT
VPP Pulse Rise Time During Programming
6V
¾
2
¾
¾
ms
Test waveforms and measurements
2 .4 V
A C D r iv in g
L e v e ls
0 .4 5 V
2 .0 V
0 .8 V
Output test load
1 .3 V
A C
(1 N 9 1 4 )
M e a s u re m e n t
L e v e l
O u tp u t P in
tR, tF< 20ns (10% to 90%)
C
L
Note: CL=100pF including jig capacitance.
Functional Description
quencing through each address of the HT27LC4096.
This part of the programming algorithm is done at
=6.0V to assure that each EPROM bit is programmed
to a sufficiently high threshold voltage. This ensures
that all bits have sufficient margin. After the final address is completed, the entire EPROM memory is read
at VCC=VPP=3.3±0.3V to verify the entire memory.
Programming of the HT27LC4096
When the HT27LC4096 is delivered, the chip has all
4096K bits in the ²ONE², or HIGH state. ²ZEROs² are
loaded into the HT27LC4096 through programming.
The programming mode is entered when 12.5±0.2V is
applied to the VPP pin, OE is at VIH, and CE is VIL. For
programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
Program inhibit mode
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive algorithm reduces programming time by using 30ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data
is not verified, additional pulses are given until it is verified or until the maximum number of pulses is reached
while sequencing through each address of the
HT27LC4096. This process is repeated while seRev. 1.20
Programming of multiple HT27LC4096 in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE, all like inputs of
the parallel HT27LC4096 may be common. A TTL
low-level program pulse applied to an HT27LC4096 CE
input with Vpp=12.5±0.2V, and OE HIGH will program that
HT27LC4096. A high-level CE input inhibits the
HT27LC4096 from being programmed.
4
November 22, 2002
HT27LC4096
Program verify mode
Standby mode
Verification should be performed on the programmed
bits to determine whether they were correctly programmed. The verification should be performed with OE
at VIL, and CE at VIH, and VPP at its programming voltage.
The HT27LC4096 has CMOS standby mode which reduces the maximum VCC current to 10mA. It is placed in
CMOS standby when CE is at V CC ±0.3V. The
HT27LC4096 also has a TTL-standby mode which reduces the maximum VCC current to 0.6mA. It is placed in
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
Auto product identification
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and the type. This mode is intended for
programming to automatically match the device to be
programmed with its corresponding programming algorithm. This mode is functional in the 25°C±5°C ambient
temperature range that is required when programming
the HT27LC4096.
Two-line output control function
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
· Low memory power dissipation
· Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low-power standby mode and that
the output pins are only active when data is desired from
a particular memory device.
To activate this mode, the programming equipment must
force 12.0±0.5V on the address line A9 of the
HT27LC4096. Two identifier bytes may then be sequenced from the device outputs by toggling address line
A0 from VIL to VIH, when A1=VIH. All other address lines
must be held at VIH during Auto Product Identification
mode.
System considerations
Byte 0 (A0=VIL) represents the manufacturer code, and
byte 1 (A0=VIH), the device code. For HT27LC4096, these
two identifier bytes are given in the Operation mode truth
table. When A1=VIL, the HT27LC4096 will read out the binary code of 7F, continuation code, to signify the unavailability of manufacturer ID codes.
During the switch between active and standby conditions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a
0.1mF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VPP to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM arrays, a 4.7mF bulk electrolytic capacitor should be used
between VCC and VPP for each eight devices. The location of the capacitor should be close to where the
power supply is connected to the array.
Read mode
The HT27LC4096 has two control functions, both of
which must be logically satisfied in order to obtain data
at outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data
is available at the outputs (tOE) after the falling edge of
OE, assuming the CE has been LOW and addresses
have been stable for at least tACC-tOE.
Rev. 1.20
5
November 22, 2002
HT27LC4096
Operation mode truth table
All the operation modes are shown in the table following.
Mode
CE
OE
A0
A1
A9
VPP
Output
Read
VIL
VIL
X
X
X
VCC
Dout
Output Disable
VIL
VIH
X
X
X
VCC
High Z
Standby (TTL)
VIH
X
X
X
X
VCC
High Z
VCC± 0.3V
X
X
X
X
VCC
High Z
VIL
VIH
X
X
X
VPP
DIN
Program Verify
X
VIL
X
X
X
VPP
DOUT
Product Inhibit
VIH
X
X
X
X
VPP
High Z
Manufacturer Code (3)
VIL
VIL
VIL
VIH
VH (1)
VCC
1C
Device Type Code (3)
VIL
VIL
VIH
VIH
VH (1)
VCC
05
Standby (CMOS)
Program
Note:
(1) VH = 12.0V ± 0.5V
(2) X=Either VIH or VIL
(3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F
Product Identification Code
Pins
A0
A1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex
Data
Manufacturer
0
1
0
0
0
1
1
1
0
0
1C
Device Type
1
1
0
0
0
0
0
1
0
1
05
0
0
0
1
1
1
1
1
1
1
7F
1
0
0
1
1
1
1
1
1
1
7F
Code
Continuation
A d d re s s
A d d r e s s V a lid
tC
C E
E
tD
tO
O E
tA
O u tp u t
H IG H
F
E
tO
C C
H
O u tp u t V a lid
Z
Figure 1. A.C. waveforms for read operation
Rev. 1.20
6
November 22, 2002
HT27LC4096
R e a d
( V e r ify )
P ro g ra m
A d d re s s
V
IH
V
V P P
tA
V
IH
D a ta
V C C
A d d r e s s S ta b le
IL
V
tO
S
tD
tD
S
H
6 .0 V
tD
5 .0 V
1 2 .5 V
5 .0 V
V
tV
C S
tV
P S
H
D a ta O u t
V a lid
D a ta In
IL
tP
F P
R T
IH
C E
V
IL
tP
O E
tA
E
V
tO
W
E S
IH
V
IL
Figure 2. Programming waveforms
Rev. 1.20
7
November 22, 2002
HT27LC4096
S T A R T
A d d r e s s = F ir s t L o c a tio n
V
V
C C
P P
= 6 .0 V
= 1 2 .5 V
X = 0
P ro g ra m
In te r a c tiv e
S e c tio n
o n e 7 5 m s P u ls e
In c re m e n t X
X = 2 0 ?
Y e s
N o
F a il
V e r ify
W o rd ?
P a s s
In c re m e n t A d d re s s
L a s t
A d d re s s
N o
F a il
Y e s
V
V e r ify
S e c tio n
C C
= V
P P
= 3 .3 V
V e r ify A ll
W o rd s ?
F a il
D e v ic e F a ile d
P a s s
D e v ic e P a s s e d
N o te : E ith e r 1 0 5 m s o r 3 0 m s p u ls e .
Figure 3. Fast programming flowchart
Rev. 1.20
8
November 22, 2002
HT27LC4096
Package Information
40-pin DIP (600mil) outline dimensions
A
4 0
2 1
1
2 0
B
H
C
D
E
Symbol
Rev. 1.20
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
2045
¾
2065
B
535
¾
555
C
145
¾
155
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
595
¾
615
I
635
¾
670
a
0°
¾
15°
9
November 22, 2002
HT27LC4096
44-pin PLCC outline dimensions
A
B
6
1
4 4
4 0
7
3 9
D
1 7
2 9
1 8
2 8
K
E
a
C
J
H
F
G
I
Symbol
Rev. 1.20
Dimensions in mil
Min.
Nom.
Max.
A
680
¾
700
B
648
¾
658
C
680
¾
700
D
648
¾
658
E
145
¾
155
F
¾
¾
190
G
20
¾
¾
H
¾
50
¾
I
16
¾
22
J
24
¾
32
K
8
¾
12
a
0°
¾
10°
10
November 22, 2002
HT27LC4096
Product Tape and Reel Specifications
Reel dimensions
D
T 2
A
C
B
T 1
PLCC 44
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
32.8+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.20
11
November 22, 2002
HT27LC4096
Carrier tape dimensions
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
PLCC 44
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0±0.3
P
Cavity Pitch
24.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
2.0 Min.
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
18.0±0.1
B0
Cavity Width
18.0±0.1
K1
Cavity Depth
NA
K2
Cavity Depth
4.9±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.20
0.33±0.05
21.3
12
November 22, 2002
HT27LC4096
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
13
November 22, 2002