INTEGRATED CIRCUITS 74F175A Quad D flip-flop Product specification Supersedes data of 1996 Mar 12 IC15 Data Handbook 2000 Jun 30 Philips Semiconductors Product specification Quad D flip-flop 74F175A FEATURES PIN CONFIGURATION • Four edge-triggered D-type flip-flops • Buffered common clock • Buffered asynchronous Master Reset • True and complementary outputs • Industrial temperature range available (–40°C to +85°C) • PNP light loading inputs MR DESCRIPTION 1 16 VCC Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 8 9 CP GND The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. SF00718 The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. TYPE 74F175A All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complementary outputs are required, and the CP and MR are common to all storage elements. TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 160MHz 22mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C PKG. DWG. # 16-pin plastic DIP N74F175AN I74F175AN SOT38-4 16-pin plastic SO N74F175AD I74F175AD SOT109-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS D0 – D3 DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 74F175A 1.0/0.033 20µA/20µA MR Master reset input (active–Low) 74F175A 1.0/0.033 20µA/20µA CP Clock input (active rising edge) 74F175A 1.0/0.033 20µA/20µA Q0–Q3 True outputs 50/33 1.0mA/20mA Q0–Q3 Complementary outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 2000 Jun 30 2 853–0047 24024 Philips Semiconductors Product specification Quad D flip-flop 74F175A LOGIC SYMBOL IEC/IEEE SYMBOL 1 12 13 9 D0 D1 D2 D3 4 4 5 R C1 2 9 1 3 1D 7 CP MR 5 6 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 12 11 15 2 3 7 6 13 10 11 15 14 VCC = Pin 16 GND = Pin 8 14 SF00720 SF00719 LOGIC DIAGRAM D1 D0 D2 5 4 D3 12 13 9 CP D Q D CP RD Q D CP RD Q D CP RD Q CP Q RD 1 MR 3 2 Q0 Q0 VCC = Pin 16 GND = Pin 8 6 Q1 7 Q1 11 Q2 10 Q2 14 Q3 15 Q3 SF00721 FUNCTION TABLE INPUTS OUTPUTS MR CP Dn Qn Qn H = High voltage level h = High state must be present one setup time before the Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time before the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition OPERATING MODE L X X L H Reset (clear) H ↑ h H L Load “1” H ↑ I L H Load “0” ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA 0 to +70 Tambb Operating O erating free air tem temperature erature range °C –40 to +85 °C Tstg Storage temperature range –65 to +150 °C Commercial range 2000 Jun 30 Industrial range 3 Philips Semiconductors Product specification Quad D flip-flop 74F175A RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA 0 +70 °C –40 +85 °C Commercial range Tambb Operating free air temperature range Industrial range DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST LIMITS CONDITIONS1 VOH High-level out output ut voltage VOL Low-level output voltage VIK VCC= MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX Input clamp voltage VCC = MIN, II = IIK TYP2 MIN "10%VCC 2.5 "5%VCC 2.7 UNIT MAX V 3.4 "10%VCC 0.30 0.5 "5%VCC 0.30 0.5 –0.73 –1.2 V V II Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –20 µA –150 mA 31 mA current3 IOS Short-circuit output ICC Supply current (total) VCC = MAX –60 VCC = MAX 22 Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = 25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω VCC = +5V CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX Tamb = *40°C to +85°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fmax Maximum clock frequency Waveform 1 140 160 tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 3.0 4.5 4.0 6.0 6.5 8.5 2.5 4.0 7.5 9.0 2.5 4.0 8.0 10.0 ns tPLH tPHL Propagation delay MR to Qn Waveform 3 4.5 6.5 9.0 4.5 10.0 4.5 11.0 ns tPHL tPHL Propagation delay MR to Qn Waveform 3 4.5 6.0 8.0 4.0 9.0 4.0 10.0 ns 2000 Jun 30 4 125 110 MHz Philips Semiconductors Product specification Quad D flip-flop 74F175A AC SETUP REQUIREMENTS LIMITS Tamb = 25°C SYMBOL PARAMETER ts(H) ts(L) Setup time, High or Low Dn to CP th(H) th(L) TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω VCC = +5V CL = 50pF, RL = 500Ω MIN TYP MAX MIN Tamb = 40°C to +85°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MAX MIN UNIT MAX Waveform 2 3.0 3.0 3.5 3.5 4.0 4.0 ns Hold time, High or Low Dn to CP Waveform 2 0.0 0.0 0.0 0.0 0.0 0.0 ns tw(H) tw(L) CP Pulse width High or Low Waveform 1 3.0 4.0 3.5 5.0 4.0 5.5 ns tw(L) MR Pulse width Low Waveform 3 3.5 3.5 4.0 ns tREC Recovery time MR to CP Waveform 3 4.0 4.5 5.0 ns AC WAVEFORMS For all waveforms, VM = 1.3V. 1/fmax MR CP VM VM VM tw(H) tw(L) tPHL tw(L) VM Qn VM tREC tPLH VM CP VM tPHL tPHL tPLH Qn VM VM Qn VM VM tPLH SF00722 Qn Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency VM SF00723 Waveform 3. Master Reset pulse width, Master Reset to output delay and Master Reset to Clock recovery time Dn CP VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM SF00191 Waveform 2. Data setup time and hold times 2000 Jun 30 5 Philips Semiconductors Product specification Quad D flip-flop 74F175A TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 2000 Jun 30 6 Philips Semiconductors Product specification Quad D flip-flop 74F175A DIP16: plastic dual in-line package; 16 leads (300 mil) 2000 Jun 30 7 SOT38-4 Philips Semiconductors Product specification Quad D flip-flop 74F175A SO16: plastic small outline package; 16 leads; body width 3.9 mm 2000 Jun 30 8 SOT109-1 Philips Semiconductors Product specification Quad D flip-flop 74F175A NOTES 2000 Jun 30 9 Philips Semiconductors Product specification Quad D flip-flop 74F175A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-00 Document order number: yyyy mmm dd 10 9397-750 07531