ETC IBM13T8644NPA-360T

IBM11M4730C4M x 72 E12/10, 5.0V, Au.
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Features
• 144 Pin JEDEC Standard, 8 Byte Small Outline
Dual-In-line Memory Module
• 8Mx64 Synchronous DRAM SO DIMM
• Performance: PC100
-360
3
Units
CAS Latency
fCK
Clock Frequency
100
MHz
tCK
Clock Cycle
10
ns
tAC
Clock Access Time
6
ns
• Inputs and outputs are LVTTL (3.3V) compatible
• 10 Ohm Resistors on DQs
• Single 3.3V ± 0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have four internal banks
• Fully Synchronous to positive Clock Edge
• Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge Commands
• Suspend Mode and Power Down Mode
• 12/9/2 Addressing (Row/Column/Bank)
• 4096 refresh cycles distributed across 64ms
• Serial Presence Detect
• Card size: 2.66" x 1.0" x 0.149"
• Gold contacts
• SDRAMS in TSOP Type II Package
• Data Mask for Byte Read/Write control
Description
IBM13T8644NPA is a 144-pin Synchronous DRAM
Small Outline Dual In-line Memory Module (SO
DIMM) which is organized as a 8Mx64 high-speed
memory array. The SO DIMM uses four 8Mx16
SDRAMs in 400mil TSOP II packages and achieves
high speed data transfer rates of up to 100MHz by
employing a prefetch/pipeline hybrid architecture
that supports the JEDEC 1N rule while allowing very
low burst power. The SO DIMM is intended to comply with all JEDEC and INTEL PC100 rev 1.0 standards set for 144 pin SDRAM SO DIMMs.
All control, address, and data input/output circuits
are synchronized with the positive edge of the externally supplied clock inputs. All inputs are sampled at
the positive edge of the externally supplied clock
(CK0). Internal operating modes are defined by
combinations of the RAS, CAS, WE, S0, DQMB,
and CKE0 signals. A command decoder initiates the
necessary timings for each operation. A 12 bit
address bus accepts address information in a
row/column multiplexing arrangement.
Prior to any access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the SO DIMM by address
inputs A0-A9 during the mode register set cycle.
The SO DIMM uses serial presence detects implemented via a serial EEPROM using the two pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 144-pin SO DIMMs provide a high performance, flexible 8-byte interface in a 2.66" long
space-saving footprint.
Card Outline
(Front)
(Back)
06K3620.H01554
12/99
1
2
59 61
60 62
143
144
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Pin Description
CK0
Clock Input
CKE0
DQ0 - DQ63
Clock Enable
Data Input/Output
DQMB0 - DQMB7
Data Mask
Row Address Strobe
VDD
Power (3.3V)
CAS
Column Address Strobe
VSS
Ground
WE
Write Enable
NC
No Connect
S0
Chip Select
SCL
Serial Presence Detect Clock Input
Address Inputs
SDA
Serial Presence Detect Data
Input/Output
RAS
A0 - A9, A11
A10/AP
Address Input/Autoprecharge
BA0, BA1
Serial Presence Detect Address
Inputs
SA0-2
SDRAM Bank Addresses
Pinout
Pin#
Front
Side
Pin
#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
1
3
VSS
DQ0
2
4
VSS
DQ32
37
39
DQ8
DQ9
38
40
DQ40
DQ41
71
73
NC
DU
72
74
NC
NC
107
109
5
DQ1
6
DQ33
41
DQ10
42
DQ42
75
VSS
76
VSS
111
7
DQ2
8
DQ34
43
DQ11
44
DQ43
77
NC
78
NC
113
9
DQ3
10
DQ35
45
VDD
46
VDD
79
NC
80
NC
115
11
VDD
12
VDD
47
DQ12
48
DQ44
81
VDD
82
VDD
117
13
15
17
19
21
23
25
27
29
31
33
35
DQ4
DQ5
DQ6
DQ7
VSS
14
16
18
20
22
24
26
28
30
32
34
36
DQ36
DQ37
DQ38
DQ39
VSS
49
51
53
55
57
59
DQ13
DQ14
DQ15
VSS
DQ45
DQ46
DQ47
VSS
83
85
87
89
91
93
95
97
99
101
103
105
DQ16
DQ17
DQ18
DQ19
VSS
84
86
88
90
92
94
96
98
100
102
104
106
DQ48
DQ49
DQ50
DQ51
VSS
119
121
123
125
127
129
131
133
135
137
139
141
143
DQMB0
DQMB1
VDD
A0
A1
A2
VSS
DQMB4
DQMB5
VDD
A3
A4
A5
VSS
61
63
65
67
69
50
52
54
56
NC
58
NC
60
VOLTAGE KEY
CK0
62
VDD
64
RAS
66
WE
68
S0
70
NC
NC
CKE0
VDD
CAS
NC
NC
DQ20
DQ21
DQ22
DQ23
VDD
A6
A8
DQ52
DQ53
DQ54
DQ55
VDD
A7
BA0
Front
Side
VSS
A9
A10/A
P
VDD
DQMB
2
DQMB
3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VDD
Pin#
Back
Side
108
110
VSS
BA1
112
A11
114
VDD
DQMB
6
DQMB
7
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
SCL
VDD
All pin assignments are consistent for all 8 Byte versions.
Ordering Information
Part Number
Organization
Clock Cycle
Leads
Dimension
Power
IBM13T8644NPA-360T
8Mx64
10ns
Gold
2.66" x1.0" x 0.149"
3.3V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 16
06K3620.H01554
12/99
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
8Mx64 SDRAM DIMM Block Diagram (x16 SDRAMs)
WE
S0
CS
DQMB0
WE
DQMB4
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQMB1
DQMB5
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D2
UDQM
WE
DQMB6
LDQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
WE
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CS
DQMB2
CS
LDQM
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D1
DQMB7
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
WE
LDQM
D3
UDQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
10 Ohm
* CLOCK WIRING
CLOCK
SDRAMS
INPUT
CK1
CK0
D0 - 3
10 pf
BA0
BA0-BA1: SDRAMS D0 - D3
SERIAL PD
A0-A11: SDRAMS D0 - D3
A0 - A11
VDD
VSS
06K3620.H01554
12/99
D0 - D3
D0 - D3
RAS
RAS: SDRAMs D0 - D3
CAS
CAS: SDRAMs D0 - D3
CKE0
CKE: SDRAMs D0 - D3
SCL
SDA
A0
A1
A2
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
CKE0
Input
Level
Activates the CK0 signal when high and deactivates it when low.
Active High By deactivating the clock, CKE0 low initiates the Power Down mode, Suspend mode, or
the Self Refresh mode.
S0
Input
Pulse
Enables the associated SDRAM command decoder when low and disables the command
Active Low decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS
WE
Input
Pulse
Active Low
BA0, BA1
Input
Level
—
Selects which SDRAM bank is to be active.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
A0 - A9, A11,
A10/AP
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0 defines the bank to be precharged (low=bank A,
high=bank B). If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0 to control which
bank(s) to precharge. If AP is high, both bank A and bank B will be precharged regardless of the state of BA0. If AP is low, then BA0 is used to define which bank to precharge.
DQ0 - DQ63
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output
Active High buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the write operation if
DQM is high.
DQMB0 DQMB7
Input
Pulse
SDA
Input
Output
Level
—
Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
SCL
Input
Pulse
—
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
VDD, VSS
Supply
Power and ground for the module.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 16
06K3620.H01554
12/99
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Serial Presence Detect
Byte #
0
1
2
3
4
5
6-7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 - 61
62
63
64 - 71
72
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=3
SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time (tAC) from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time (tAC) from Clock at CL=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active delay (tRRD)
Minimum RAS to CAS delay (tRCD)
Minimum RAS Pulse width (tRAS)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum for bytes 0 - 62
Manufacturers’ JEDEC ID Code
Module Manufacturing Location
73 - 90
Module Part Number
91 - 92
93 - 94
95 - 98
99 - 125
126
Module Revision Code
Module Manufacturing Date
Module Serial Number
Reserved
Module Supports this Clock Frequency
127
Attributes for Clock Frequency defined in byte 126
128 - 255 Open for Customer Use
1.
2.
3.
4.
5.
6.
SPD Entry Value
128
256
SDRAM
12
8
1
x64
LVTTL
10.0ns
6.0ns
Non-Parity
SR/1x(15.625µs)
x16
N/A
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Unbuffered
Wr-1/Rd Burst, Precharge All,
Auto-Precharge,
VDD ±10%
15.0ns
9.0ns
N/A
N/A
20ns
20ns
20ns
50ns
64MB
2.0
1.0
2.0
1.0
Undefined
1.2A
Checksum Data
IBM
Toronto, Canada
Vimercate, Italy
ASCII ‘13T8644NP”R”-360T’
“R” plus ASCII blank
Year/Week Code
Serial Number
Undefined
100 MHz
CK0,CL3, concurrent
AP
Undefined
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
08
01
4000
01
A0
60
00
80
10
00
01
8F
04
06
01
01
00
Notes
0E
F0
90
00
00
14
14
14
32
10
20
10
20
10
00
12
cc
A400000000000000
91
53
313354383634344E50
rr2D33363054202020
rr20
yyww
ssssssss
00
64
1
2, 3
2, 3
4, 5
6
85
00
cc = Checksum Data byte, 00-FF (Hex)
“R” = Alphanumeric revision code, A-Z, 0-9
rr = ASCII coded revision code byte “R”
yy = Binary coded decimal year code, 00-99 (Decimal) ‘00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) ‘01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
06K3620.H01554
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Absolute Maximum Ratings
Symbol
Parameter
VDD
Power Supply Voltage
VIN
Input Voltage
VOUT
Output Voltage
TOPR
Operating Temperature
TSTG
Storage Temperature
PD
IOUT
Rating
Units Notes
-0.3 to +4.6
SDRAM Devices
-0.3 to +4.6
Serial PD Device
-0.3 to +6.5
SDRAM Devices
-0.3to +4.6
Serial PD Device
-0.3 to +6.5
Power Dissipation
Short Circuit Output Current
V
1
0 to +70
°C
1
-55 to +125
°C
1
1.15
W
1, 2
50
mA
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Power is calculated using IDD1 @ 3.6Volt.
Recommended DC Operating Conditions (TA= 0 to 70°C)
Rating
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
3.0
3.3
3.6
V
1
VIH
Input High Voltage
2.0
—
VDD + 0.3
V
1
VIL
Input Low Voltage
-0.3
—
0.8
V
1
1. All voltages referenced to VSS.
Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V)
Symbol
Max. Capacitance
Units
Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1, RAS, CAS, WE)
24
pF
CI2
Input Capacitance (CKE)
21
pF
CI3
Input Capacitance (S0)
20
pF
CI4
Input Capacitance (CK0)
13
pF
CI5
Input Capacitance (DQMB0 - DQMB7)
10
pF
CI6
Input Capacitance (SCL)
12
pF
CIO1
Input/Output Capacitance (DQ0 - DQ63)
11
pF
CIO2
Input/Output Capacitance (SDA)
15
pF
CI1
Parameter
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 16
06K3620.H01554
12/99
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
DC Output Load Circuit
3.3 V
1200
VOH (DC) = 2.4V, IOH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
870
50pF
Output Characteristics (TA= 0 to +70°C, VDD= 3.3V ±0.3V)
Symbol
II(L)
Parameter
Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD), All Other Pins
Not Under Test = 0V
Min.
Max.
RAS, CAS, WE, CKE0, CK0,
A0-A9, A10/AP, A11, BA0, BA1
-4
+4
S0
-4
+4
DQMB0-7
-1
+1
DQ0 - 63
-1
+1
SCL
-2
+2
DQ0 - 63
-1
+1
SDA
-2
+2
IO(L)
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ VDD)
VOH
Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
2.4
—
VOL
Output Level (LVTTL)
Output “L” Level Voltage (IOUT =
+2.0mA)
—
0.4
Units
Notes
µA
V
1
1. See DC output load circuit.
06K3620.H01554
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Operating, Standby and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
Parameter
Symbol
Test Condition
Current
Units
Notes
IDD1
1 bank operation
320
mA
1,2
IDD2P
CKE ≤ VIL(max), tCK = min, S0, S1 =VIH(min)
4.0
mA
IDD2Ps
CKE ≤ VIL(max), tCK = Infinity, S0, S1 =VIH(min)
4.0
mA
IDD2N
CKE ≥ VIH(min), tCK = min, S0, S1 =VIH (min)
140
mA
IDD2NS
CKE ≥ VIH(min), tCK = Infinity, S0, S1 =VIH (min)
40
mA
IDD3N
CKE ≥ VIH(min), tCK = min, S0, S1 =VIH (min)
160
mA
IDD3P
CKE ≤ VIL(max), tCK = min, S0, S1 =VIH (min)
(Power Down Mode)
40
mA
Burst Operating Current
IDD4
tCK = min, Read/ Write command cycling
360
mA
2,3
Auto (CBR) Refresh Current
IDD5
tCK = min, CBR command cycling
740
mA
4
Self Refresh Current
IDD6
CKE0 ≤ 0.2V
3200
µA
4
Serial PD Device Standby Current
ISB5
VIN = GND or VDD
30
µA
5
Serial PD Device Active Power Supply
Current
ICCA
SCL Clock Frequency = 100KHz
1
mA
6
Operating Current
tRC = tRC(min), tCK = min
Active-Precharge command cycling
without Burst operation
Precharge Standby Current in Power
Down Mode
Precharge Standby Current in NonPower Down Mode
No Operating Current
(Active state: 4 bank)
3
3
1. Input signals are changed up to three times during tRC(min). This assumes the 14 Row Address mode with four-bank operation
using rows A0-A11 and BA0-BA1.
2. The specified values are obtained with the outputs open..
3. Input signals are changed once during three clock cycles.
4. 64ms refresh time (15.6µs, 4K refresh).
5. VDD = 3.3V.
6. As follows:Input pulse levels VDD x 0.1 to VDD x 0.9, Input rise and fall times 10ns, Input and output timing levels VDD x 0.5, Output
load 1 TTL gate and CL=100pf
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 16
06K3620.H01554
12/99
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
An initial pause of 200µs, with DQMB0-7 and CKE0-CKE1 held high, is required after power-up. A Precharge All Banks command must
be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
1. The Transition time is measured between VIH and VIL (or between VIL and VIH).
2. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
3. Load Circuit: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point
4. Load Circuit: AC measurements assume tT=1.2 ns.
AC Characteristics Diagram
tCKH
tT
VIH
Clock
1.4V
tCKL
tSETUP
VIL
Output
tHOLD
Zo = 50Ω
50pF
Input
1.4V
AC Output Load Circuit
tOH
tAC
tLZ
Output
1.4V
Clock and Clock Enable Parameters
Symbol
Parameter
-360
(CL, tRCD, tRP = 3 / 2 / 2)
Min.
Max.
Units
Notes
tCK3
Clock Cycle Time, CAS Latency = 3
10
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
15
1000
ns
1
tAC3
Clock Access Time, CAS Latency = 3
—
6
ns
2
tAC2
Clock Access Time, CAS Latency = 2
—
9
ns
2
tCKH
Clock High Pulse Width
3
—
ns
3
tCKL
Clock Low Pulse Width
3
—
ns
3
tCES
Clock Enable Set-up Time
2
—
ns
tCEH
Clock Enable Hold Time
1
—
ns
tSB
Power down mode Entry Time
0
10
ns
tT
Transition Time (Rise and Fall)
0.5
10
ns
1. For -360 sort, 66Mhz clock: CAS Latency = 2.
2. Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 6, 7 and load circuit B.
3. tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse
width of CLK measured from the negative edge to the positive edge referenced to VIL (max).
06K3620.H01554
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Common Parameters
Symbol
Parameter
-360
(CL, tRCD, tRP = 3 / 2 / 2) Units Notes
Min.
Max.
Command Setup Time
2
—
ns
Command Hold Time
1
—
ns
Address and Bank Select Set-up Time
2
—
ns
Address and Bank Select Hold Time
1
—
ns
tRCD
RAS to CAS Delay
20
—
ns
1
tRC
Bank Cycle Time
70
—
ns
1
tRAS
Active Command Period
50
100000
ns
1
tRP
Precharge Time
20
—
ns
1
tRRD
Bank to Bank Delay Time
20
—
ns
1
tCCD
CAS to CAS Delay Time
1
—
CLK
tCS
tCH
tAS
tAH
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
tRSC
Parameter
Mode Register Set Cycle Time
-360
(CL, tRCD, tRP = 3 / 2 / 2)
Min.
Max.
2
—
Units
Notes
CLK
1
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
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Use is further subject to the provisions at the end of this document.
Page 10 of 16
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IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Read Cycle
Symbol
Parameter
-360
(CL, tRCD, tRP = 3 / 2 / 2)
Min.
Max.
Units
Notes
tOH
Data Out Hold Time
3
—
ns
tLZ
Data Out to Low Impedance Time
0
—
ns
tHZ3
Data Out to High Impedance Time
3
6
ns
1
tHZ2
Data Out to High Impedance Time
3
8
ns
1
tDQZ
DQM Data Out Disable Latency
2
—
CLK
1
Units
Notes
ms
1
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
Symbol
Parameter
-360
(CL, tRCD, tRP = 3 / 2 / 2)
Min.
Max.
64
tREF
Refresh Period
—
tSREX
Self Refresh Exit Time
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-360
(CL, tRCD, tRP = 3 / 2 / 2)
Min.
Max.
Units
tDS
Data In Set-up Time
2
—
ns
tDH
Data In Hold Time
1
—
ns
tDPL
Data Input to Precharge
10
—
ns
tDQW
DQM Write Mask Latency
0
—
CLK
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©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Clock Frequency and Latency
Symbol
Parameter
Units
fCK
Clock Frequency
100
66
MHz
tCK
Clock Cycle Time
10
15
ns
tAA
CAS Latency
3
2
CLK
tRP
Precharge Time
2
2
CLK
tRCD
RAS to CAS Delay
2
2
CLK
tRC
Bank Cycle Time
7
6
CLK
tRAS
Minimum Bank Active Time
5
4
CLK
tDPL
Data In to Precharge
1
1
CLK
tDAL
Data In to Active/Refresh
3
3
CLK
tRRD
Bank to Bank Delay Time
2
2
CLK
tCCD
CAS to CAS Delay Time
1
1
CLK
tWL
Write Latency
0
0
CLK
tDQW
DQM Write Mask Latency
0
0
CLK
tDQZ
DQM Data Disable Latency
2
2
CLK
tCSL
Clock Suspend Latency
1
1
CLK
Max
Unit
Notes
100
kHz
Presence Detect Read and Write Cycle
Symbol
fSCL
Parameter
Min
SCL Clock Frequency
TI
Noise Suppression Time Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out Valid
tBUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
µs
Start Condition Hold Time
4.0
µs
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
tHD:STA
0.3
100
ns
3.5
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
µs
tHD:DAT
Data in Hold Time
0
µs
tSU:DAT
Data in Setup Time
250
tr
SDA and SCL Rise Time
tf
SDA and SCL Fall Time
tSU:STO
ns
1
300
Stop Condition Setup Time
4.7
tDH
Data Out Hold Time
300
tWR
Write Cycle Time
µs
ns
µs
ns
15
ms
1
1. The Write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 16
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IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Functional Description and Timing Diagrams
Refer to the IBM 128Mb Synchronous DRAM data sheet, document 33L8019, for the functional description
and timing diagrams for SDRAM operation.
Refer to the IBM Application Notes: Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
All AC timing information refers to the timings at the SDRAM devices.
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©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 16
IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Layout Drawing
67.60
2.661
2.00 min.
.0787
Front
24.5
.9646
25.4
1.00
6.00
.236
23.2
.9134
2.55
.1004
3.30
.1299
20.00
.7874
(2X) 0
1.800
.0709
4.60
.1811
32.80
1.293
2.50
.0984
1.50+/- 0.10
.0591+/-.0039
0.60+/- .05 Width
.0236
0.25 max.
0.009
4.00
.157
63.60
2.504
0.80 Typ. Pitch
.0315
8M x 64
Side
3.80 max.
9.525
.375 min.
4.00+/- 0.10
.1575+/-.0039
0.1496
_ 0.10
1.00 +
_ .0039
.039 +
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 16
MILLIMETERS
INCHES
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IBM13T8644NPA
8M x 64 PC100 SDRAM SO DIMM
Revision Log
Rev
12/99
06K3620.H01554
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Contents of Modification
Initial Release.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 16

Copyright and Disclaimer
 Copyright International Business Machines Corporation 1999
All Rights Reserved
Printed in the United States of America December 1999
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.
IBM
IBM Logo
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury
or death to persons. The information contained in this document does not affect or change IBM product specifications
or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM
be liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction,
NY 12533-6351
The IBM home page can be found at
http://www.ibm.com
The IBM Microelectronics Division home page
can be found at http://www.chips.ibm.com
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