Discontinued (4/1/00 - last order; 7/31/00 - last ship) . IBM13Q32734BCA 32M x 72 Registered SDRAM Module Features • 200-Pin JEDEC Standard, Registered 8-Byte Dual In-line Memory Module • 32M x 72 Synchronous DRAM DIMM • Performance: -10 Units fCK Clock Frequency CAS Latency = 2* 66 MHz tCK2 Clock Cycle 15 ns tAC2 Clock Access Time 11.3 ns * SDRAM CAS latency = 2; DIMM CAS Latency = 3 • Inputs and outputs are LVTTL (3.3V) compatible • Single 3.3V to 3.6V Power Supply • Single Pulsed RAS interface • Fully Synchronous to positive Clock Edge • Data Mask control • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Programmable Operation: -SDRAM CAS Latency: 2 -Burst Type: Sequential or Interleave -Burst Length: 2 -Operation: Burst Read and Write or Multiple Burst Read with Single Write • Suspend Mode and Power Down Mode • 12/10/2 Addressing (Row/Column/Bank) • 4096 Refresh cycles distributed across 64ms • Parallel Presence Detect • Card size: 6.05" x 1.50" x 0.320" • Gold contacts • SDRAMS in TSOJ Type II, 2-High, Stacked Package Description IBM13Q32734BCA is a registered 200-pin Synchronous DRAM Dual In-line Memory Module (DIMM) which is organized as a 32Mx72 high-speed memory array. The DIMM uses eighteen x4 SDRAMs in 400mil TSOJ II stacked packages. The DIMM achieves high speed data transfer rates of up to 66MHz by employing a prefetch/pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power. The DIMM is intended to comply with all nonoptional JEDEC standards set for the 200-pin registered SDRAM DIMMs. All control and address signals are synchronized with the positive edge of an externally supplied clock. They are latched in an on-DIMM pipeline 04K8918.C75665B 6/99 register and presented to the SDRAMs on the following clock. Prior to any Access operation, the CAS latency, burst type, burst length, and burst operation type must be programmed into the DIMM by address inputs A0-A13 using the Mode Register Set cycle. The DIMM uses parallel presence detects implemented according to the JEDEC standard. All IBM 200-pin DIMMs provide a high performance, flexible 8-byte interface in a 6.05” long high-performance footprint. Related products include both EDO DRAM and SDRAM unbuffered DIMMs in both nonparity x64 and ECC-Optimized x72 configurations in the 168 pin form factor. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Card Outline (Front) (Back) 1 101 16 17 116 117 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 15 78 79 178 179 100 200 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Pin Description CK0 Clock Input (Buffered through PLL) DQM Data Mask (Registered) Clock Enables (Registered) VDD Power (3.3V) RAS Row Address Strobe (Registered) VSS Ground CAS Column Address Strobe (Registered) NC No Connect WE Write Enable (Registered) PD1 - PD8 S0, S1 Chip Selects (Registered) PDE CKE0 A0 - A9, A11 Address Inputs (Registered) A10/AP Presence Detect Enable ID1 - ID3 Address Input/Auto Precharge (Reg) DQ0 - DQ71 A12/BS1, A13/BS0 Data Input/Output Presence Detect (Buffered) IN, OUT ID Bits SDRAM Bank Selects (Registered) Physical Detect (Direct short) Pinout x72 DIMM Pin# Front Side Pin# Back Side Pin# 1 VDD 101 NC 2 NC 102 NC 3 NC 103 4 IN 104 5 6 OUT Front Side Pin# Back Side Pin# 26 VDD 126 DQ53 51 27 DQ51 127 DQ52 52 VSS 28 DQ50 128 VDD 53 NC 29 VSS 129 DQ47 54 105 ID1 NC 106 NC 30 31 DQ49 DQ48 130 131 DQ46 VSS 55 56 Front Side Pin# Back Side VSS 151 RAS 152 VSS NC A13/BS0 VDD Pin# Front Side CK0 76 VDD 77 153 S1 78 154 S0 79 VSS 80 A12/BS1 81 DQ15 181 NC 155 156 Pin# Back Side DQ16 176 VDD VSS 177 NC NC 178 VSS NC 179 VSS VDD 180 NC 7 ID2 107 ID3 32 VDD 132 DQ45 57 A0 157 A10/AP 82 DQ14 182 VDD 8 VSS 108 DQ71 33 DQ43 133 DQ44 58 A1 158 VDD 83 VSS 183 DQ11 9 DQ67 109 DQ70 34 DQ42 134 VDD 59 VSS 159 A2 84 DQ13 184 DQ10 10 DQ66 110 VSS 35 VSS 135 DQ39 60 DQ35 160 A3 85 DQ12 185 VSS 11 VDD 111 DQ69 36 DQ41 136 DQ38 61 DQ34 161 VSS 86 VDD 186 DQ9 12 DQ65 112 DQ68 37 DQ40 137 VSS 62 VDD 162 DQ31 87 DQ7 187 DQ8 VDD 138 DQ37 63 DQ33 163 DQ30 88 DQ6 188 VDD DQ32 164 VDD 89 VSS 189 DQ3 DQ2 13 DQ64 113 VDD 38 14 VSS 114 NC 39 A4 139 DQ36 64 15 DQ63 115 VSS 40 A5 140 VDD 65 VSS 165 DQ29 90 DQ5 190 16 DQ62 116 NC 41 VSS 141 A6 66 DQ27 166 DQ28 91 DQ4 191 VSS 17 NC 117 DQ59 42 A8 142 A7 67 DQ26 167 VSS 92 VDD 192 DQ1 DQ0 18 DQ61 118 DQ58 43 A9 143 VSS 68 VDD 168 DQ23 93 PDE 193 19 DQ60 119 VSS 44 VDD 144 A11 69 DQ25 169 DQ22 94 PD1 194 PD5 20 VDD 120 DQ57 45 CKE1 145 NC 70 DQ24 170 VDD 95 PD2 195 PD6 21 NC 121 DQ56 46 CKE0 146 VDD 71 VSS 171 DQ21 96 PD3 196 PD7 22 NC 122 VDD 47 VSS 147 DQM 72 DQ19 172 DQ20 97 PD4 197 PD8 23 VSS 123 DQ55 48 CAS 148 WE 73 DQ18 173 VSS 98 SCL 198 VDD 24 NC 124 DQ54 49 NC 149 VSS 74 VDD 174 NC 99 NC 199 NC 25 NC 125 VSS 50 VDD 150 NC 75 DQ17 175 NC 100 VSS 200 NC Ordering Information Part Number Organization Clock Cycle Leads Dimension Power IBM13Q32734BCA-10Y 32Mx72 66MHz Gold 6.05" x 1.50" x 0.320" 3.3V 04K8918.C75665B 6/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Input/Output Functional Description Symbol Type Signal Polarity Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CK0 Input Pulse Positive Edge CKE0 Input Level Active High Activates the CK0 signal when high and deactivates the CK0 signal when low. By deactivating the clock, CKE0 low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. S0, S1 Input Pulse Active Low S0, S1 enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. A12/BS1 A13/BS0 Input Level — Select which SDRAM bank is to be active (Bank 0 - Bank3) A0 - A9, A11 A10/AP A12/BS1 A13/BS0 Input Level — During a Bank Activate command cycle, A0-A10/AP and A11 defines the row address (RA0RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8) when sampled at the rising clock edge. In addition to the column address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BS0,BS1 defines the bank to be precharged. If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BS0,BS1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BS. If A10/AP is low, then BS0,BS1 is used to define which bank to precharge. DQ0 DQ71 Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAM DIMMs. Pulse Mask Active High DQM Input VDD, VSS Supply The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of three clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of one and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the module. Presence Detect Pin Value Notes PD1 0 1 PD2 0 1 PD3 1 1 PD4 0 1 PD5 1 1 PD6 0 1 PD7 1 1 PD8 1 1 ID1 1 2 ID2 0 2 ID3 0 2 1. 0 = driven to VOL, 1 = open 2. 0 = ground, 1 = open ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 15 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Block Diagram: Buffered 32Mx72 ECC SDRAM DIMM REGISTER CKE0 DQM RAS CAS WE S0 S1 A0 - A10/AP A11 A12/BS1 A13/BS0 DQ0 DQ1 DQ2 DQ3 I/O 0 I/O 1 I/O 2 I/O 3 D0 DQ40 DQ41 DQ42 DQ43 I/O 0 I/O 1 I/O 2 I/O 3 D10 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 D1 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 D11 DQ8 DQ9 DQ10 DQ11 I/O 0 I/O 1 I/O 2 I/O 3 D2 DQ48 DQ49 DQ50 DQ51 I/O 0 I/O 1 I/O 2 I/O 3 D12 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 D3 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 D13 DQ16 DQ17 DQ18 DQ19 I/O 0 I/O 1 I/O 2 I/O 3 D4 DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 D14 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 D5 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 D15 DQ24 DQ25 DQ26 DQ27 I/O 0 I/O 1 I/O 2 I/O 3 D6 DQ64 DQ65 DQ66 DQ67 I/O 0 I/O 1 I/O 2 I/O 3 D16 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 D7 DQ32 DQ33 DQ34 DQ35 I/O 0 I/O 1 I/O 2 I/O 3 D8 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 D9 CK0 04K8918.C75665B 6/99 DQ68 DQ69 DQ70 DQ71 I/O 0 I/O 1 I/O 2 I/O 3 VSS PD1 - PD8 PDE D17 3.3V Notes: 1. A 10 Ohm resistor is wired in series with all DQn lines near the card edge connector. 2. All clock lines from the PLL Clock Buffer to the SDRAM devices are of equal length. PLL CLOCK BUFFER FEEDBACK 3. S0 tied to CS on DRAMs D0-D17 (lower SDRAMs in stack). 4. S1 tied to CS on DRAMs D0-D17 (upper SDRAMs in stack). 5. CKE0 tied to CKE on DRAMs D0-D17 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Absolute Maximum Ratings Symbol Parameter Rating Units Notes VDD Power Supply Voltage -0.3 to +4.6 V 1 VIN Input Voltage -0.3 to +4.6 V 1 VOUT Output Voltage -0.3 to +4.6 V 1 TOPR Operating Temperature 0 to +70 °C 1 TSTG Storage Temperature -55 to +125 °C 1 Power Dissipation 16 W 1,2 Short Circuit Output Current 50 mA 1 PD IOUT 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum power is calcuated assuming both physical banks on the DIMM are in Auto Refresh mode. Recommended DC Operating Conditions (TA= 0 to 70°C) Rating Symbol Parameter Min. Typ. Max. Units Notes VDD Supply Voltage 3.3 — 3.6 V 1 VIH Input High Voltage 2.0 — VDD + 0.3 V 1 VIL Input Low Voltage -0.3 — 0.8 V 1 1. All voltages referenced to VSS and VSSQ. Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V to 3.6V) Symbol Parameter Max. Units CI1 Input Capacitance (A0 - A9, A10/AP, A11) 15 pF CI2 Input Capacitance (RAS, CAS, WE, DQM, PDE) 25 pF CI3 Input Capacitance (S0, S1, CKE0) 40 pF CI4 Input Capacitance (CK0) 10 pF CI01 Input/Output Capacitance (DQ0 - DQ71) 25 pF C01 Output Capacitance (PD1- PD8) 12 pF ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 15 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Output Characteristics (TA= 0 to +70°C, VDD= 3.3V to 3.6V) Symbol Min. Max. Units II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ 3.6V), All Other Pins Not Under Test = 0V Parameter -20 +20 µA IO(L) Output Leakage Current (DQ) (DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V) -2 +2 µA VOH Output Level (TTL) Output “H” Level Voltage (IOUT = -2.0mA) 2.4 VDD V VOL Output Level (TTL) Output “L” Level Voltage (IOUT = +2.0mA) 0.0 0.4 V IO(L) Output Leakage Current (PD1 - PD8) -10 +10 µA Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V to 3.6V) Parameter Symbol Test Condition Value Units Notes ICC1 1 bank operation tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 2026 mA 1, 3, 4 ICC2P CKE ≤ VIL(max), tCK = min, CS =VIH(min) 532 mA 2 ICC2PS CKE ≤ VIL(max), tCK = Infinity, CS =VIH(min) 61 mA 2 ICC2N CKE ≥ VIH(min), tCK = min, CS =VIH (min) 1396 mA 2, 5 ICC2NS CKE ≥ VIH(min), tCK = Infinity, 241 mA 2, 6 ICC3N CKE ≥ VIH(min), tCK = min, CS =VIH (min) 1576 mA 2, 5 ICC3P CKE ≤ VIL(max), tCK = min, 604 mA 2, 7 Operating Current (Burst Mode) ICC4 tCK = min, Read/ Write command cycling, Multiple banks active, gapless data,BL=4 2656 mA 1, 4, 8 Auto (CBR) Refresh Current ICC5 tCK = min, tRC = tRC(min) CBR command cycling 4456 mA 2 Self Refresh Current ICC6 CKE ≤ 0.2V 61 mA 2, 8 Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) 1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (ICC3N). 2. The specified values are for both DIMM banks operating in the specified mode. 3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 4. The specified values are obtained with the output open. 5. Input signals are changed once during three clock cycles. 6. Input signals are stable. 7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ). 8. Input signals are changed once during tCK(min). 04K8918.C75665B 6/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module AC Characteristics (TA= 0 to +70°C, VDD= 3.3V to 3.6V) 1. An initial pause of 200µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation can begin. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point. 3. The Transition time is measured between VIH and VIL (or between VIL and VIH). 4. AC measurements assume tT=1ns. 5. In addition to meeting the transition rate specification, the clock and CKE0 must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. AC Characteristics Diagram tCH 2.0V 1.4V 0.8V tCL Clock tSETUP tT tHOLD Input 1.4V tAC tOH tLZ Output ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 15 1.4V 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Clock and Clock Enable Parameters Value Symbol Parameter Units Min. Max. tCK2 Clock Cycle Time 15 66MHz ns tAC2 Clock Access Time — 11.3 ns tCH Clock High Pulse Width 6.0 — ns tCL Clock Low Pulse Width 6.0 — ns tCKS Clock Enable Setup Time 2.3 — ns tCKH Clock Enable Hold Time 1.3 — ns tCKSP CKE0 Setup Time (Power down mode) 2.3 — ns Transition Time (Rise and Fall) 1.4 10 ns 1 — ms tT tSTAB PLL Stabilization Time Notes 1, 2 1. CAS latency defined at SDRAMs; DIMM actually has CAS latency of 3. 2. 50pF Load. Common Parameters Value Symbol Parameter Units Min. Max. tS0 Command Setup Time 2.3 — ns tCH Command Hold Time 1.3 — ns tAS Address and Bank Select Setup Time 2.3 — ns tAH Address and Bank Select Hold Time 1.3 — ns RAS to CAS Delay 30 — ns tRC Bank Cycle Time 90 — ns tRAS Active Command Period 60 100000 ns tRP Precharge Time 30 — ns tRRD Bank to Bank Delay Time 20 — ns tCCD CAS to CAS Delay Time 1 — CLK tRCD 04K8918.C75665B 6/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Mode Register Set Cycle Value Symbol tRSC Parameter Mode Register Set Cycle Time Min. Max. 20 — Units Notes ns 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Read Cycle Value Symbol Parameter Units Min. Max. tOH Data Out Hold Time 3.3 — ns tLZ Data Out to Low Impedance Time 0.3 — ns tHZ2 Data Out to High Impedance Time 3.3 10.8 ns tDQZ DQM Data Out Disable Latency 3 — CLK Notes 1 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Refresh Cycle Value Symbol Parameter Min. Max. Units Notes 1 tREF Refresh Period — 64 ms tSREX Self Refresh Exit Time 10 — ns 1. 4096 cycles. Write Cycle Value Symbol Parameter Units Min. Max. tDS Data In Setup Time 3.3 — ns tDH Data In Hold Time 2.3 — ns tDPL2 Data input to Precharge 1 — CLK tDQW DQM Write Mask Latency 1 — CLK ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 15 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Clock Frequency and Latency Symbol Parameter Value Units fCK Clock Frequency 66.667 MHz tCK Clock Cycle Time 15 ns tAA CAS Latency 3 tCK tRCD RAS to CAS Delay 2 tCK tRC Bank Cycle Time 6 tCK tRAS Minimum Bank Active Time 4 tCK tRP Precharge Time 2 tCK tDPL Data In to Precharge 1 tCK tDAL Data In to Active/Refresh 3 tCK tRRD Bank to Bank Delay Time 2 tCK tCCD CAS to CAS Delay Time 1 tCK tWL Write Latency 1 tCK tDQW DQM Write Mask Latency 1 tCK tDQZ DQM Data Disable Latency 3 tCK tCSL Clock Suspend Latency 1 tCK Notes 1 1. SDRAMs have tAA=2, but on-board DIMM register adds one clock cycle Presence Detect Read Cycle Value Symbol tPD tPDOFF Parameter Unit Notes 10 ns 1 10 ns 2 Min Max PDE to Valid Presence Detect Data — PDE Inactive to Presence Detects Inactive 0 1. Measured with the specified current load and 100pF. 2. tPDOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Functional Description and Timing Diagram Refer to IBM 200-pin SDRAM Registered DIMM Functional Description and Timing Diagram (Document 04K8917.C75644C, for SDRAM operation). 04K8918.C75665B 6/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Presence Detect Read Cycle vIH PDE vIL tPDOFF* tPD vOH PD1-PD8 Valid Presence Detect vOL *PD pins must be pulled high at next level of assembly ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 15 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Layout Drawing (200 Pin DIMM) 153.67 6.05 150.67 5.93 6.35 .250 SEE DETAIL A (2) 0 3.1877 .1255 10.0 .3937 (2X) 4.00 .157 38.1 1.5 Front 1.27 pitch .050 1.00 width .039 Side 8.13 Detail A .320 MAX. scale: 4/1 5.029 .198 MIN. R 1.00 .0393 3.0 .118 2.0 .078 _ 0.10 1.27 + _ .004 .050 + Note: All dimensions are typical unless otherwise stated. 04K8918.C75665B 6/99 Millimeters Inches ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 15 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13Q32734BCA 32M x 72 Registered SDRAM Module Revision Log Revision 6/99 6/18/99 Contents Of Modification Initial release. Updated notch dimensions line in layout drawing. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 15 04K8918.C75665B 6/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. 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