NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module 32Mx64 bit Two Bank Unbuffered SDRAM Module based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD Features l 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module l Automatic and controlled Precharge commands l Intended for PC133 applications l Programmable Operation: - Clock Frequency: 133MHz - CAS Latency: 2, 3 - Clock Cycle: 7.5ns - Burst Type: Sequential or Interleave - Clock Assess Time: 5.4ns - Burst Length: 1, 2, 4, 8 l Inputs and outputs are LVTTL (3.3V) compatible - Operation: Burst Read and Write or Multiple Burst Read with l Single 3.3V ± 0.3V Power Supply l Single Pulsed RAS interface l Suspend Mode and Power Down Mode Single Write l SDRAMs have 4 internal banks l 4096 Refresh cycles distributed across 64ms l Module has 2 physical bank l Gold contacts l Fully Synchronous to positive Clock Edge l SDRAMs in TSOP Type II Package l Data Mask for Byte Read/Write control l Serial Presence Detect with Write Protect l Auto Refresh (CBR) and Self Refresh Description NT256S64V8HC0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 32Mx64 high-speed memory arrays and is configured as two 16M x 64 physical bank. The DIMM uses sixteen 16Mx8 SDRAMs in 400mil TSOP II pack-ages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power. All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations of RAS , CAS , WE , S0 - S3 , DQMB, and CKE0 – CKE1 signals. A command decoder initiates the necessary timings for each operation. A 14-bit address bus accepts address information in a row / column multiplexing arrangement. Prior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the customer. Ordering Information Speed Part Number MHz. CL t RCD t RP 143MHz 3 3 3 133MHz 2 2 2 133MHz 3 3 3 100MHz 2 2 2 125MHz 3 3 3 100MHz 2 2 2 Organization Leads Power 32Mx64 Gold 3.3V NT256S64V8HC0G-7K NT256S64V8HC0G-75B NT256S64V8HC0G-8B * CL = CAS Latency Preliminary 10 / 2001 1 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module Pin Description CK0 , CK1 Clock Inputs CK2, CK3 DQ0-DQ63 Data input/output CB0-CB7 Check Bit Data input/output Clock Enable DQMB0-DQMB7 Data Mask RAS Row Address Strobe VDD Power (3.3V) CAS Column Address Strobe VSS Ground WE Write Enable NC No Connect CKE0 – CKE1 S0 , S1 , S2 , S3 Chip Selects SCL Serial Presence Detect Clock Input A0-A9, A11 Address Inputs SDA Serial Presence Detect Data input/output A10 / AP Address Input/Autoprecharge SA0-2 Serial Presence Detect Address Inputs BA0, BA1 SDRAM Bank Address Inputs WP Serial Presence Detect Write Protect Input Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VSS 85 VSS 29 DQMB1 113 DQMB5 57 DQ18 141 DQ50 2 DQ0 86 DQ32 30 S0 114 S1 58 DQ19 142 DQ51 3 DQ1 87 DQ33 31 NC 115 RAS 59 VDD 143 VDD 4 DQ2 88 DQ34 32 VSS 116 VSS 60 DQ20 144 DQ52 5 DQ3 89 DQ35 33 A0 117 A1 61 NC 145 NC 6 VDD 90 VDD 34 A2 118 A3 62 NC 146 NC 7 DQ4 91 DQ36 35 A4 119 A5 63 CKE1* 147 NC 8 DQ5 92 DQ37 36 A6 120 A7 64 VSS 148 VSS 9 DQ6 93 DQ38 37 A8 121 A9 65 DQ21 149 DQ53 10 DQ7 94 DQ39 38 A10/AP 122 BA0 66 DQ22 150 DQ54 11 DQ8 95 DQ40 39 BA1 123 A11 67 DQ23 151 DQ55 12 VSS 96 VSS 40 VDD 124 VDD 68 VSS 152 VSS 13 DQ9 97 DQ41 41 VDD 125 CK1 69 DQ24 153 DQ56 14 DQ10 98 DQ42 42 CK0 126 NC 70 DQ25 154 DQ57 15 DQ11 99 DQ43 43 VSS 127 VSS 71 DQ26 155 DQ58 16 DQ12 100 DQ44 44 NC 128 CKE0 72 DQ27 156 DQ59 17 DQ13 101 DQ45 45 S2 129 S3 73 VDD 157 VDD 18 VDD 102 VDD 46 DQMB2 130 DQMB6 74 DQ28 158 DQ60 19 DQ14 103 DQ46 47 DQMB3 131 DQMB7 75 DQ29 159 DQ61 20 DQ15 104 DQ47 48 NC 132 NC 76 DQ30 160 DQ62 21 CB0 105 CB4 49 VDD 133 VDD 77 DQ31 161 DQ63 22 CB1 106 CB5 50 NC 134 NC 78 VSS 162 VSS 23 VSS 107 VSS 51 NC 135 NC 79 CK2 163 CK3 24 NC 108 NC 52 CB2 136 CB6 80 NC 164 NC 25 NC 109 NC 53 CB3 137 CB7 81 WP 165 SA0 26 VDD 110 VDD 54 VSS 138 VSS 82 SDA 166 SA1 27 WE 111 CAS 55 DQ16 139 DQ48 83 SCL 167 SA2 28 DQMB0 112 DQMB4 56 DQ17 140 DQ49 84 VDD 168 VDD Note: All pin assignments are consistent for all 8-byte unbuffered versions. *CKE1 is terminated with a 10k ohm pullup resistor. Preliminary 10 / 2001 2 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module SDRAM DIMM Block Diagram (2 Bank, 16Mx8 SDRAMs) S0 S1 DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D0 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQMB4 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 CS D12 DQMB5 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D1 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 CS D13 S2 S3 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D2 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 CS D14 DQMB7 D3 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 CS D15 NOTE : Exact DQ wiring may differ from that shown above CK0 CLK : SDRAMs D0 -D1, D4 - D5, 3.3pF Cap CK1 CLK : SDRAMs D8 - D9,D12 - D13, 3.3pF Cap CK2 CLK : SDRAMs D2 - D3,D6 -D7, 3.3pF Cap CKE1 CK3 CLK : SDRAMs D10 - D11, D14 -D15, 3.3pF Cap VDD A0 - A11 BA0 BA1 RAS CAS CKE0 WE VDD 10K CKE : SDRAMs D8- D15 D0 - D15 .33uF A0 - A11 : SDRAMs D0 - D15 A13/BS0 : SDRAMs D0 - D15 A12/BS1 : SDRAMs D0 - D15 RAS : SDRAMs D0- D15 CAS : SDRAMs D0- D15 CKE : SDRAMs D0- D7 WE : SDRAMs D0- D15 0.1 uF VSS D0 - D15 Serial PD SCL WP 47K A0 A1 A2 SA0 SA1 SA2 SDA *All resistor values are 10 ohms except as shown. Preliminary 10 / 2001 3 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module Input/Output Functional Description Symbol Type Signal CK0 , CK2 Input Pulse CKE0 Input Level their associated clock. Active Activates the SDRAM CK0 and CK2 signals when high and deactivates them when low. By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or Active Input Pulse Active Input Pulse Low BA0, BA1 Input Level the Self-Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands Low RAS , CAS , WE The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of Edge High S0 , S2 Function Polarity Positive - are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS , CAS , WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to A0 - A9 A10/AP invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, Input Level - autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. A11 During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63, Input Level CB0 - CB7 - /Output Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. The Data input/output mask places the DQ buffers in a high impedance state when Active DQMB0 -DQMB7 Input Pulse sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and High operates as a byte mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. SA0 – SA2 Input Level - Serial Presence Detect EEPROM address. Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence Input SDA Address inputs. Connected to either VDD or VSS on the system board to configure the Level - /Output Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a pull-up resistor is required on the system board. Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM. SCL Input Pulse - Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on the system board. Active WP Input Level On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied High VDD , VSS Supply Preliminary 10 / 2001 Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited. to ground through a 47K ohm pull-down resistor. Power and ground for the module. 4 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module Absolute Maximum Ratings Symbol Parameter Rating Units Notes V 1 0 to +70 °C 1 VDD Power Supply Voltage VIN Input Voltage -0.3 to VDD +0.3 Output Voltage -0.3 to VDD +0.3 VOUT TA TSTG PD IOUT -0.3 to +4.6 Operating Temperature (ambient) -55 to +125 °C 1 Power Dissipation 6.9 W 1 Short Circuit Output Current 50 mA 1 Storage Temperature 1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (T A =0 to 70 °C) Rating Symbol 1. Parameter Min. Typ. Max. Units Notes VDD Power Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 - VDD + 0.3 V 1,2 VIL Input Low Voltage -0.3 - 0.8 V 1,3 VOH Output High Voltage 2.4 - - V VOL Output Low Voltage - - 0.4 V I IL Input Leakage current -10 - 10 uA All voltages referenced to VSS . 2. VIH (max) = VDD / VDDQ + 1.2V for pulse width ≤ 5ns 3. VIL (min) = VSS / VSSQ - 1.2V for pulse width ≤ 5ns . Capacitance (T A =25 °C , f =1MHz, V DD =3.3 ± 0.3V) Symbol Parameter Max. CI1 Input Capacitance (A0-A9, A10/AP, A11, BA0, BA1, RAS , CAS , WE ) 104 CI2 Input Capacitance (CKE0) 54 CI3 Input Capacitance ( S0 - S2 ) 30 CI4 Input Capacitance (CK0 - CK3) 40 CI5 Input Capacitance (DQMB0 - DQMB7) 17 CI6 Input Capacitance (SA0 - SA2, SCL, WP) 9 CIO1 Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 17 CIO2 Input/Output Capacitance (SDA) 11 Unit pF DC Output Load Circuit 3.3 V 1200 ohms VOH(DC) = 2.4V,IOH= -2mA Output VOL(DC) = 0.4V,IOL= -2mA 50 pF Preliminary 10 / 2001 870 ohms 5 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module Operating, Standby, and Refresh Currents (T A =0 to 70 °C , V DD =3.3 ± 0.3V) Parameter Speed Test condition Symbol Unit Note 1080 mA 1, 3,4 32 32 mA 2 32 32 32 mA 2 800 720 720 mA 2,5 144 144 144 mA 2,6 144 144 144 mA 2,7 960 800 800 mA 2,5 1560 1360 1360 mA 1,4,8 2000 1920 1920 mA 1 - 7K - 75B - 8B 1200 1080 32 1 bank operation , tRC = tRC(mim), tCK = min Operating current ICC1 Active-Precharge Command cycling without burst operation Precharge CKE0 ≤ VIL (max), tCK = min, ICC2P standby current in power-down mode Precharge CKE0 ≤ VIL (max), tCK =oo, ICC2PS ICC2N S0 , S2 = VIH (min) CKE0 ≥ VIH (min), tCK = min S0 , S2 = VIH (min) standby current in non power-down mode S0 , S2 = VIH (min) ICC2NS CKE0 ≥ VIH (min), tCK =oo, S0 , S2 = VIH (min) No Operating current ICC3P CKE0 ≤ VIL (max), tCK =min. S0 , S2 = VIH (min) (Power Down Mode) ( Active state : 4 bank) ICC3N CKE0 ≥ VIH (min), tCK =min S0 , S2 = VIH (min) Operating current ( Burst mode ) tCK =min , Read/ Write command cycling, ICC4 Multiple banks active, gapless data, BL=4 Auto(CBR) refresh current Self refresh current ICC5 tCK =min, CBR command cycling ICC6 CKE0 ≤ 0.2V 32 32 32 mA 2 ISB VIN = GND or VDD 30 30 30 µA 9 SCL Clock Frequency=100 MHz 1 1 1 µA 10 Serial PD Device Standby Current Serial PD Device Active ICCA Power Supply Current 1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I CC3N ). 2. The specified values are for both DIMM banks operating in the specified mode. 3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC . Input signals are changed up to three times during t RC (min). 4. The specified values are obtained with the output open. 5. Input signals are changed once during three clock cycles. 6. Input signals are stable. 7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ). 8. Input signals are changed once during t CK(min) . 9. VDD =3.3V. 10. As follows: • Input pulse levels V DD x 0.1 to V DD x 0.9 • Input rise and fall times 10ns • Input and output timing levels V DD x 0.5 • Output load 1 TTL gate and CL=100pF Preliminary 10 / 2001 6 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module AC Characteristics (TA =0 to 70 °C , VDD =3.3 ± 0.3V) 1. An initial pause of 200us,with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIH and VIL ). 3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit between VIH and VIL (or between VIL and VIH ) in a monotonic manner. 4. AC timing tests have VIL =0.8Vand VIH = 2.0 V with the timing referenced to the 1.40V crossover point. 5. AC measurements assume t T =1.2 ns. AC Output Load Circuits tT tCKL Clock tSETUP tCKH VIH 1.4V VIL tHOLD Output Zo = 50 ohm Input 1.4V tAC 50 pF AC Output Load Circuit tOH tLZ Output Preliminary 10 / 2001 1.4V 7 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module AC Timing Parameters Clock and Clock Enable Parameters - 7K Symbol - 75B - 8B Parameter Unit Min. Max. Min. Max. Min. Max. Note tCK3 Clock Cycle Time, CAS Latency = 3 7 1000 7.5 1000 8 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 7.5 1000 10 1000 10 1000 ns tAC3(B) Clock Access Time, CAS Latency = 3 - 5.4 - 5.4 - 6 ns 1 tAC2(B) Clock Access Time, CAS Latency = 2 - 5.4 - 6 - 6 ns 1 tCKH Clock High Pulse Width 2.5 - 2.5 - 3 - ns 2 tCKL Clock Low Pulse Width 2.5 - 2.5 - 3 - ns 2 tCES Clock Enable Set-up Time 1.5 - 1.5 - 2 - ns tCEH Clock Enable Hold Time 0.8 - 0.8 - 1 - ns tSB Power down mode Entry Time 0 7.5 0 7.5 0 12 ns tT Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 ns 1. Access time is measured at 1.4V. In AC Characteristics section, see notes. 2. t CKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). t CKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max). Common Parameters - 7K Symbol - 75B - 8B Parameter Unit Min. Max. Min. Max. Min. Max. Note tCS Command Setup Time 1.5 - 1.5 - 2 - ns tCH Command Hold Time 0.8 - 0.8 - 1 - ns tAS Address and Bank Select Set-up Time 1.5 - 1.5 - 2 - ns tAH Address and Bank Select Hold Time 0.8 - 0.8 - 1 - ns tRCD RAS to CAS Delay 20 - 20 - 20 - ns 1 tRC Bank Cycle Time 60 - 67.5 - 70 - ns 1 tRFC Auto Refresh to Active/Auto Refresh 60 - 67.5 - 70 - tRAS Active Command Period 45 100K 45 100K 50 100K ns 1 tRP Precharge Time 20 - 20 - 20 - ns 1 tRRD Bank to Bank Delay Time 15 - 15 - 20 - ns 1 tCCD CAS to CAS Delay Time 1 - 1 - 1 - CLK 1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num ber of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle - 7K Symbol tRSC - 75B - 8B Parameter Mode Register Set Cycle Time Min. Max. Min. Max. Min. Max. 2 - 2 - 2 - Unit Note CLK 1 1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num ber of clock cycles = specified value of timing / clock period (count fractions as a whole number). Preliminary 10 / 2001 8 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT256S64V8HC0G 256MB : 32M x 64 Unbuffered SDRAM Module Read Cycle - 7K Symbol tOH - 75B - 8B Parameter Unit Min. Max. Min. Max. Min. Max. - - - - 2.5 - ns 2.7 - 2.7 - 3 - ns 0 - 0 - ns Note Data Out Hold Time tLZ Data Out to Low Impedance Time 0 - tHZ3 Data Out to High Impedance Time 3 5.4 3 5.4 3 6 ns tDQZ DQM Data Out Disable Latency 2 - 2 - 2 - CLK 1 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Refresh Cycle - 7K Symbol - 75B - 8B Parameter tREF Refresh Period tSREX Self Refresh Exit Time Unit Min. Max. Min. Max. Min. Max. - 64 - 64 - 64 ms 10 - 10 - 10 - ns Note Write Cycle - 7K Symbol - 75B - 8B Parameter Unit Min. Max. Min. Max. Min. Max. tDS Data In Set-up Time 1.5 - 1.5 - 2 - ns tDH Data In Hold Time 0.8 - 0.8 - 1 - ns tDPL Data input to Precharge 15 - 15 - 15 - ns 5 - 5 - 5 - CLK 5 - - - - - CLK 0 - 0 - 0 - ns Note Data In to Active Delay tDAL3 CAS Latency = 3 Data In to Active Delay tDAL2 CAS Latency = 2 tDQW DQM Write Mask Latency Preliminary 10 / 2001 9 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com