. IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 16Mx72 Synchronous DRAM DIMM • Performance: DIMM CAS Latency fCK Clock Frequency • • • • • • • -75A Reg. 4 Units 133 MHz tCK Clock Cycle 7.5 ns tAC Clock Access Time 5.65 ns Intended for 133MHz applications Inputs and outputs are LVTTL (3.3V) compatible Single 3.3V ± 0.3V Power Supply Single Pulsed RAS interface SDRAMs have four internal banks Module has one physical bank Fully Synchronous to positive Clock Edge • Programmable Operation: - DIMM CAS Latency:4 (Registered mode) - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8, Full-Page - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Data Mask for Byte Read/Write control • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Suspend Mode and Power Down Mode • 12/10/2 Addressing (Row/Column/Bank) • 4096 refresh cycles distributed across 64ms • Card size: 5.25" x 1.5" x 0.157" • Gold contacts • SDRAMS in TSOP - Type II Package • Serial Presence Detect with Write protect feature Description IBM13M16734JCB is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module (DIMM) organized as a 16Mx72 high-speed memory array. The DIMM uses nine 16Mx8 SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data-transfer rates of 133MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system clock. The DIMM is intended for use in applications operating at 133MHz memory bus speed. All control and address signals are re-driven through registers/buffers to the SDRAM devices. Operating in registered mode (REGE pin tied high), the control/address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock). A phase-lock loop (PLL) on the DIMM is used to redrive the clock signals to the SDRAM devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated on the DIMM.) A single clock enable (CKE0) con- 06K7739.H03380 4/00 trols all devices on the DIMM, enabling the use of SDRAM power-down modes. Prior to any access operation, the device CAS latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A9, I/O addresses BA0 and BA1 using the mode register set cycle. The DIMM CAS latency, when operated in Registered mode, is one clock later than the device CAS latency due to the address and control signals being clocked to the SDRAM devices. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by providing a high level to pin 81 on the DIMM. An on-board pulldown resistor keeps this in the write-enable mode. All IBM 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Card Outline (Front) (Back) 1 85 10 11 94 95 40 124 84 168 41 125 Ordering Information Part Number Organization Clock Cycle (CL, tRCD, tRP) IBM13M16734JCB-75AT 16Mx72 7.5ns (333) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 22 CAS Latency Access Time 3 5.4ns Leads Dimension Power Gold 5.25" x 1.5" x 0.157" 3.3V 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Pin Description CK0 - CK3 CKE0 RAS Clock Inputs Clock Enable Row Address Strobe CAS Column Address Strobe WE Write Enable S0, S2 A0 - A9, A11 A10/AP BA0, BA1 WP DQ0 - DQ63 CB0 - CB7 DQMB0 - DQMB7 VDD VSS Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs SPD Write Protect Data Input/Output Check Bit Data Input/Output Data Mask Power (3.3V) Ground NC SCL SDA SA0-2 REGE No Connect Serial Presence Detect Clock Input Serial Presence Detect Data Input/Output Serial Presence Detect Address Inputs Register Enable Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 VSS 85 VSS 22 CB1 106 CB5 43 VSS 127 VSS 64 VSS 148 VSS 2 DQ0 86 DQ32 23 VSS 107 VSS 44 NC 128 CKE0 65 DQ21 149 DQ53 3 DQ1 87 DQ33 24 NC 108 NC 45 S2 129 NC 66 DQ22 150 DQ54 4 DQ2 88 DQ34 25 NC 109 NC 46 DQMB2 130 DQMB6 67 DQ23 151 DQ55 5 DQ3 89 DQ35 26 VDD 110 VDD 47 DQMB3 131 DQMB7 68 VSS 152 VSS 6 VDD 90 VDD 27 WE 111 CAS 48 NC 132 NC 69 DQ24 153 DQ56 7 DQ4 91 DQ36 28 DQMB0 112 DQMB4 49 VDD 133 VDD 70 DQ25 154 DQ57 8 DQ5 92 DQ37 29 DQMB1 113 DQMB5 50 NC 134 NC 71 DQ26 155 DQ58 9 DQ6 93 DQ38 30 S0 114 NC 51 NC 135 NC 72 DQ27 156 DQ59 10 DQ7 94 DQ39 31 NC 115 RAS 52 CB2 136 CB6 73 VDD 157 VDD 11 DQ8 95 DQ40 32 VSS 116 VSS 53 CB3 137 CB7 74 DQ28 158 DQ60 12 VSS 96 VSS 33 A0 117 A1 54 VSS 138 VSS 75 DQ29 159 DQ61 13 DQ9 97 DQ41 34 A2 118 A3 55 DQ16 139 DQ48 76 DQ30 160 DQ62 14 DQ10 98 DQ42 35 A4 119 A5 56 DQ17 140 DQ49 77 DQ31 161 DQ63 15 DQ11 99 DQ43 36 A6 120 A7 57 DQ18 141 DQ50 78 VSS 162 VSS 16 DQ12 100 DQ44 37 A8 121 A9 58 DQ19 142 DQ51 79 CK2 163 CK3 17 DQ13 101 DQ45 38 A10/AP 122 BA0 59 VDD 143 VDD 80 NC 164 NC 18 VDD 102 VDD 39 BA1 123 A11 60 DQ20 144 DQ52 81 WP 165 SA0 VDD 124 VDD SDA 166 SA1 19 DQ14 103 DQ46 40 61 NC 145 NC 82 20 DQ15 104 DQ47 41 VDD 125 CK1 62 NC NC NC 83 SCL 167 SA2 21 CB0 105 CB4 42 CK0 126 NC 63 NC 147 REGE 84 VDD 168 VDD Note: All pin assignments are consistent with all 8-byte unbuffered versions. 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module x72 ECC SDRAM DIMM Block Diagram (1 Bank, x8 SDRAMs) RS0 RDQMB0 # RDQMB4 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 D0 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CS D5 RDQMB5 RDQMB1 D1 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS D6 RDQMB6 CS D2 CS D7 RDQMB7 RS2 RDQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D3 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS D8 RDQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S0/S2 DQMB0 to DQMB7 BA0-BA1 A0-A11 RAS CAS CKE0 WE 10k VDD REGE PCK DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 R E G I S T E R CS #Unless otherwise noted, resistor values are 22 Ohms. Serial Presence Detect D4 SCL PLL CK0 CK1, CK2, CK3 Terminated RS0/RS2 RDQMB0 - RDQMB7 BA0-BA1: SDRAMs D0-D8 RBA0 - RBA1 A0-A11: SDRAMs D0-D8 RA0-RA11 RRAS RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 RCAS CKE: SDRAMs D0 - D8 RCKE0 RWE WE: SDRAMs D0 - D8 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 22 WP 47K SDA A0 A1 A2 SA0 SA1 SA2 VDD D0 - D8 VSS D0 - D8 Note: DQ wiring may differ from that described in this drawing; however DQ/DQMB relationships are maintained as shown. 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Clock Wiring Clock Net Wiring (CK0): SDRAM CK0 IN 12pF 10 Ohm OUT1 TO OUT3 Phase Lock Loop One of three SDRAM outputs is shown. All PLL clock SDRAM loads are equal-achieved in part through equal-length wiring. OUT4 PCK SDRAM SDRAM PCK Register (1:1) Register (1:1) FDBK OUT10 IN 5.1pF (PLL out to Feedback input) Terminated Clock Nets (CK1, CK2, CK3): 10 0hms CK1, CK2, and CK3 12pF 06K7739.H03380 4/00 Notes: 1. The PLL is programmed via a combination of the feedback path and on-DIMM loading. PLL feedback produces zero phase shift from the delayed CK0 input. 2. Card wiring and capacitance loading variation: ± 100 ps. 3. Timing is based on a driver with a 1 Volt/ns rise time. 4. Feedback Capacitor Value determined by PLL phase characteristics. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Input/Output Functional Description Symbol Type Signal Polarity Function CK0 - CK3 Input Pulse Positive The system clock inputs. All the SDRAM inputs are sampled on the rising edge of their associEdge ated clock. CK0 drives the PLL. CK1, CK2, and CK3 are terminated. CKE0 Input Level Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, the Suspend mode, or the Self Refresh mode. S0, S2 Input Pulse Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0, 1 Input Level — Selects which SDRAM bank of four is activated. Level — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, then BA0 and BA1 are used to define which bank to precharge. DQ0 Input DQ63, Level Output CB0 - CB7 — Data and Check Bit Input/Output pins. A0 - A9, A11, A10/AP DQMB0 DQMB7 Input Input Pulse Active High VDD, VSS Supply The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high impedance state when sampled high. In Read mode, DQMB has a latency of three clock cycles in Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB has a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. Power and ground for the module. REGE Input Active High The Register Enable pin is used to permit the DIMM to operate in Buffered mode (inputs reLevel (Regis- driven asynchronously) or Registered mode (signals re-driven to SDRAMs when clock rises, and ter Mode held valid until next rising clock). Enable) SA0 - 2 Input Level — These signals are tied at the system planar to either VSS or VDD to configure the SPD EEPROM. Input Level Output — This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup. SDA SCL Input Pulse — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus line to VDD to act as a pullup. WP Input Level Active High This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the SPD EEPROM. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Serial Presence Detect (Part 1 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on Assembly 12 0C 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Banks 1 01 6-7 Data Width of Assembly x72 4800 8 Assembly Voltage Interface Levels LVTTL 01 9 SDRAM Device Cycle Time (CL = 3) 7.5ns 75 10 SDRAM Device Access Time from Clock at CL=3 5.4ns 54 11 Assembly Error Detection/Correction Scheme 12 Assembly Refresh Rate/Type 13 SDRAM Device Width 14 Error Checking SDRAM Device Width 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 16 17 18 SDRAM Device Attributes: CAS Latency 19 20 21 SDRAM Module Attributes 22 SDRAM Device Attributes: General 23 ECC 02 SR/1X(15.625µs) 80 x8 08 x8 08 1 Clock 01 SDRAM Device Attributes: Burst Lengths Supported 1, 2, 4, 8, Full Page 8F SDRAM Device Attributes: Number of Device Banks 4 04 2, 3 06 SDRAM Device Attributes: CS Latency 0 01 SDRAM Device Attributes: WE Latency 0 01 Registered/Buffered with PLL IF Write-1/Read Burst, Precharge All, Auto-Precharge 0E Minimum Clock Cycle at CLX-1 (CL = 2) 15.0ns F0 24 Maximum Data Access Time (tAC) from Clock at CLX-1 (CL = 2) 9.0ns 90 25 Minimum Clock Cycle Time at CLX-2 (CL = 1) N/A 00 26 Maximum Data Access Time (tAC) from Clock at CLX-2 (CL = 1) N/A 00 27 Minimum Row Precharge Time (tRP) -260, -360 20.0ns 14 28 Minimum Row Active to Row Active delay (tRRD) 15.0ns 0F 29 Minimum RAS to CAS delay (tRCD) 20.0ns 14 Notes 1, 2 1, 2 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time is 7.5ns (133MHz). 3. cc = Checksum Data byte, 00-FF (Hex). 4. “R” = Alphanumeric revision code, A-Z, 0-9. 5. rr = ASCII coded revision code byte “R”. 6. ww = Binary coded decimal week code, 01-53 (Decimal) ➔ 01-35 (Hex). 7. yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex). 8. ss = Serial number data byte, 00-FF (Hex). 9. These values apply to PC100 applications only. 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Serial Presence Detect (Part 2 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 30 Minimum RAS Pulse width (tRAS) 50.0ns 32 31 Module Bank Density 128MB 20 32 Address and Command Setup Time Before Clock 1.5ns 15 33 Address and Command Hold Time After Clock 0.8ns 8 34 Data Input Setup Time Before Clock 1.5ns 15 35 Data Input Hold Time After Clock 0.8ns 8 Undefined 00 02 02 Checksum Data cc IBM A400000000000000 Toronto, Canada 91 36 - 61 Reserved 62 SPD Revision 63 Checksum for bytes 0 - 62 64 - 71 72 Manufacturer’s JEDEC ID Code Assembly Manufacturing Location 73 - 90 Assembly Part Number 91 - 92 Assembly Revision Code 93 - 94 Assembly Manufacturing Date 95 - 98 Assembly Serial Number 99 - 125 Reserved 126 Module Supports this Clock Frequency 127 Attributes for clock frequency defined in Byte 126 128 - 255 Open for Customer Use Notes 3 Vimercate, Italy 53 ASCII ‘13M16734JC “R” -75AT 31334D31363733344A43 rr2D37354154 4, 5 “R” plus ASCII blank rr20 5 Year/Week Code yyww 6, 7 Serial Number ssssssss 8 Undefined Not Specified 100MHz 64 9 CLK0, CL=3, ConAP 85 9 Undefined 00 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time is 7.5ns (133MHz). 3. cc = Checksum Data byte, 00-FF (Hex). 4. “R” = Alphanumeric revision code, A-Z, 0-9. 5. rr = ASCII coded revision code byte “R”. 6. ww = Binary coded decimal week code, 01-53 (Decimal) ➔ 01-35 (Hex). 7. yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex). 8. ss = Serial number data byte, 00-FF (Hex). 9. These values apply to PC100 applications only. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Absolute Maximum Ratings Symbol VDD VIN VOUT TA TSTG PD Parameter Rating Power Supply Voltage -0.3 to +4.6 Input Voltage Output Voltage SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Register 0 - VDD PLL 0 - VDD Operating Frequency 0 to +70 °C 1 -55 to +125 °C 1 6.55 W 1, 2 50 mA 1 -1.0 to +4.6 -0.3 to +6.5 Power Dissipation F0P 1 SDRAM Devices Storage Temperature Short Circuit Output Current V Serial PD Device Operating Temperature (ambient) IOUT Units Notes Min. 66 Max. 133 MHz 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum power is calculated assuming the physical bank is in Auto Refresh Mode. Recommended DC Operating Conditions Symbol VDD Parameter Supply Voltage (TA= 0 to 70˚C) Rating Min. Typ. 3.0 3.3 Units Notes 3.6 V 1 V 1 V 1 Max. VIH Input High Voltage 2.0 — VDD + 0.3 VIL Input Low Voltage -0.3 — 0.8 1. All voltages referenced to VSS. 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V) Organization Symbol Parameter Units x72 Max CI1 Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1, WE, CAS, RAS, CKE0) CI2 Input Capacitance (S0, S2) CI3 11.5 pF 9 pF Input Capacitance (DQMB0 - DQMB7) 9.5 pF CI4 Input Capacitance (REGE) 10 pF CI5 Input Capacitance (CK0) 28 pF CI6 Input Capacitance (CK1 - CK3) 24 pF CI7 Input Capacitance (SA0 - SA2, SCL, WP) 9 pF CIO1 Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 16 pF CIO2 Input/Output Capacitance (SDA) 11 pF ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Device DC Output Load Circuit 3.3V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF 870Ω Input/Output Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) Symbol x72 Parameter Min. Max. Address and Control Inputs 10 10 DQ0-63, CB0 - 7 -2 +2 DQ0-63, CB0 - 7 -2 +2 SDA -1 +1 II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ 3.6V), All Other Pins Not Under Test = 0V IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V) VOH Output Level Output “H” Level Voltage (IOUT = -2.0mA) 2.4 VDD VOL Output Level Output “L” Level Voltage (IOUT = +2.0mA) 0.0 0.4 Units Notes µA µA V 1 1. See DC output load circuit. 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Operating, Standby, and Refresh Currents (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) Symbol Test Condition Speed -75A Units Notes ICC1 tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 875 mA 1 ICC2P CKE0 ≤ VIL(max), tCK = min, CS =VIH (min) 119 mA 1 ICC2PS CKE0 ≤ VIL (max), tCK = Infinity, S0, S2 =VIH (min) 24 mA ICC2N CKE0 ≥ VIH (min), tCK = min, S0, S2 =VIH (min) 516 mA ICC2NS CKE0 ≥ VIH (min), tCK = Infinity, S0, S2 =VIH (min) 105 mA ICC3N CKE0 ≥ VIH (min), tCK = min, S0, S2 =VIH (min) 626 mA 1 ICC3P CKE0 ≤ VIL (max), tCK = min, S0, S2 =VIH (min) (Power Down Mode) 201 mA 1 Burst Operating Current (Active state: 4bank) ICC4 tCK = min, Read command cycling 1190 mA 1, 2 Auto (CBR) Refresh Current ICC5 tCK = min, CBR command cycling 1821 mA 1 Self Refresh Current ICC6 CKE0 ≤ 0.2V 33 mA Parameter Operating Current 1 bank operation Precharge Standby Current in Power Down Mode Precharge Standby Current in NonPower Down Mode No Operating Current (Active state: 4bank) 1 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed once during tCK(min). tCK(min) = 7.5ns. 2. The specified values are obtained with the DIMM data outputs open. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module AC Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) 1. An initial pause of 200µs, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point. 3. The Transition time is measured between VIH and VIL (or between VIL and VIH). 4. AC measurements assume tT=1.2ns (1 Volt/ns rise). 5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner 6. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. 7. All timings are specified at the input receiver of the signal. This allows times to be specified at the end of the transmission line versus at the DIMM connector which may display significant reflections. AC Characteristics Diagram tCKH Clock 2.0V 1.4V 0.8V tCKL tSETUP tT tHOLD Output Zo = 50Ω Input 50pF 1.4V tAC tOH AC Output Load Circuit tLZ Output 06K7739.H03380 4/00 1.4V ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Clock and Clock Enable Parameters Symbol 1. 2. 3. -75A max. (Device CL tRCD, tRP= 3, 3, 3) Parameter Units Notes Min. Max. tCK4 Clock Cycle Time, DIMM CAS Latency = 4 7.5 1000 ns 1 tAC4 Clock Access Time, DIMM CAS Latency = 4 — 5.65 ns 1, 2 tCKH Clock High Pulse Width 2.5 — ns 3 tCKL Clock Low Pulse Width 2.5 — ns 3 tCES Clock Enable Setup Time 1.65 — ns 1 tCEH Clock Enable Hold Time 0.35 — ns 1 tSB Power Down Mode Entry Time 0 7.5 ns tT Transition Time (Rise and Fall) 0.5 10 ns DIMM CAS latency = device CL [clock cycles] + 1 for the Register mode. Access time is measured at 1.4V. See AC output load circuit. tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max). . Common Parameters -75A Symbol Parameter Min. Units Notes Max. tCS Command Setup Time 1.65 ns 1 tCH Command Hold Time 0.35 ns 1 tAS Address and Bank Select Setup Time 1.65 ns 1 tAH Address and Bank Select Hold Time 0.35 ns 1 tRCD RAS to CAS Delay 20.0 ns 1 tRC Bank Cycle Time 67.5 ns 1 tRAS Active Command Period ns 1 tRP Precharge Time 20.0 ns 1 1 50 100000 tRRD Bank to Bank Delay Time 15 ns tCCD CAS to CAS Delay Time (Same Bank) 1 CLK 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Mode Register Set Cycle -75A Symbol Parameter tRSC Units Min. Max. 2 — Mode Register Set Cycle Time CLK Refresh Cycle -75A Symbol Parameter Min. Max. Units Notes 1, 2 tREF Refresh Period — 64 ms tREFI Average Refresh Interval Time — 15.625 µs tREFC Row Refresh Cycle Time 75 — ns tSREX Self Refresh Exit Time 10 — ns 3 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake up” the device. 3. Self Refresh exit is asynchronous, requiring 10ns to ensure initiation. Self Refresh exit is complete in 10ns + tRC. Read Cycle Symbol Parameter -75A Min. tOH Data Out Hold Time 2.45 tLZ Data Out to Low Impedance Time 0.6 tHZ3 Data Out to High Impedance Time 3.6 tDQZ DQM Data Out Disable Latency Units Max. Notes ns ns 6.6 ns 3 1 CLK 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Write Cycle Symbol Parameter -75A Min. Max. Units tDS Data In Setup Time 1.75 ns tDH Data In Hold Time 1.05 ns tDPL Data input to Precharge 15 ns tDAL3 Data in to Active Delay (CAS Latency = 3) 5 CLK tDQW DQM Write Mask Latency 1 CLK 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Presence Detect Read and Write Cycle Symbol Max. Units SCL Clock Frequency 100 kHz TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 µs Start Condition Hold Time 4.0 µs tLOW Clock Low Period 4.7 µs tHIGH Clock High Period 4.0 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs tHD:DAT Data In Hold Time 0 µs tSU:DAT Data In Setup Time 250 ns fSCL tHD:STA Parameter Min. tr SDA and SCL Rise Time 1 µs tf SDA and SCL Fall Time 300 ns Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns tWR Write Cycle Time tSU:STO 15 ms Notes 1 1. The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Wiring and Topology This section contains the information needed to understand the timing relationships presented in AC Characteristics. Each timing parameter is measured at the first receiving device (SDRAM DQ pin for input data, register input pin for address and control, and PLL CLK input pin for clock). This section will enable the user to understand the pin numbers on the DIMM, the net structures, and the loading associated with these devices. For detailed timing analysis, contact the IBM Marketing Representative for simulation models. Modeling is strongly recommended to determine delay adders of the entire net structure. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Pin Assignments for the 128Mb SDRAM Planar Component (Top View) VDD 1 54 VSS DQ0 VDDQ 2 3 4 5 53 52 51 50 DQ7 VSSQ 6 7 8 9 10 49 48 47 46 45 NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 NC DQ6 VDDQ NC DQ5 VSSQ NC 11 44 DQ4 VSSQ 12 43 VDDQ NC VDD NC WE CAS RAS CS A13/BS0 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 NC VSS NC DQM CLK CKE NC A11 A12/BS1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A1 A2 24 25 26 27 31 30 A6 A5 29 28 A4 VSS A3 VDD 54-pin Plastic TSOP(II) 400 mil 4Mbit x 8 I/O x 4 Bank 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module The table below describes the DQ wiring information for each SDRAM on the DIMM. Note that the DQ wiring is different from that described in the Block Diagram on page 4; the DQs are scrambled within the same device for wiring optimization. Data Wiring Cross Reference DQ SDRAM Designator DQ SDRAM Pin Number DQ0 DQ1 Device position to DIMM Tab Data I/O1 D0 D1 D2 D3 D4 D5 D6 D7 D8 2 7 15 CB1 23 31 32 40 48 56 5 6 14 CB5 22 30 33 41 49 57 DQ2 8 5 13 CB0 21 29 34 42 50 58 DQ3 11 4 12 CB4 20 28 35 43 51 59 DQ4 44 3 11 CB7 19 27 36 44 52 60 DQ5 47 2 10 CB3 18 26 37 45 53 61 DQ6 50 1 9 CB6 17 25 38 46 54 62 DQ7 53 0 8 CB2 16 24 39 47 55 63 1. These numbers can be associated with the corresponding DIMM tab pin by referencing the DIMM connector pinout on page 3 of this specification. Example: DQ14 at the DIMM tab (pin 19) is wired to SDRAM device position D1, pin 5. Data Topology 22Ω ± 5% DIMM Connector TL0 TL1 SDRAM Note: Transmission lines (“TL”) are represented as cylinders and labeled with length designators. These are the only lines which represent physical trace segments. For more detailed topology information please refer to the current PC133 SDRAM Registered DIMM specification. TL0 TL1 Total Unit Min Max Min Max Min Max 0.134 0.312 0.787 1.018 0.838 1.285 in. The table below describes the input wiring for each clock on the DIMM. Clock Input Wiring CK0 CK1 CK2 CK3 PLL CLK Input Pin 24 Termination RC Termination RC Termination RC Clock Topology CK0 DIMM Connector 10Ω TL0 TL1 Phase Lock Loop (PLL) TL0 TL1 Unit 0.127 2.647 in. 10Ω 12pF CK1, CK2, and CK3 12pf ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 22 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module The table below describes the address and control information for each signal on the DIMM. Note that several signals are double loaded at the input of the register. Register Input Wiring Register Pin number Register 1 Signal Register 2 Signal 30 CLK CLK 31 WE BA0 33 CAS A10 34 DQMB0 A11 36 DQMB4 BA1 37 DQMB1 NC 38 DQMB5 CKE0 40 S0 S2 41 RAS DQMB6 42 A0 DQMB2 43 A1 DQMB7 44 A2 DQMB3 45 A3 NC 47 A4 NC 48 A5 NC 49 A6 NC 51 A7 NC 52 A9 NC 54 A8 NC Address/Control Signal Topology DIMM Connector TL0 Register Input TL0 Register Input Unit Min Max 0.293 0.686 in. Note: Each Signal has two register input loads with the exception of DQMBs and Chip Selects (S0 and S2) which have one. For more detailed topology information please refer to the current PC133 SDRAM Registered DIMM specification. Functional Description and Timing Diagrams Refer to the IBM 128Mb Synchronous DRAM data sheet (Document 33L8019.) for the functional description and timing diagrams for buffered-mode operation. Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. 06K7739.H03380 4/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 22 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Layout Drawing 131.35 5.171 127.35 5.014 6.35 .250 1.27 pitch .050 42.18 1.661 66.68 2.63 1.00 width .039 See detail A 17.80 .700 (2) 0 3.18 .1255 Register 2 PLL 3.0 Register 1 D4 38.1 1.50 D3 .157 D1 (2X) 4.00 Front .118 D0 133.35 5.25 Back D8 D7 D6 D2 D5 Side 3.99 .157 max. Detail A SCALE: 4/1 R 1.00 .0393 (Back) 4.24 .167 4.24 .167 2.0 .078 3.0 .118 (Front) 1.27 ± 0.10 .050 ± .004 Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 22 Millimeters Inches 06K7739.H03380 4/00 IBM13M16734JCB 16M x 72 One-Bank Registered / Buffered SDRAM Module Revision Log Rev 4/00 06K7739.H03380 4/00 Contents of Modification Initial release ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 22 Copyright and Disclaimer Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America April 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com 06K7739.H03380 4/00