Discontinued (4/1/00 last order; 7/31/00 - last ship) . IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Features • 144 Pin JEDEC Standard, 8 Byte Small Outline Dual-In-line Memory Module • 8Mx64 Synchronous DRAM SO DIMM • Performance: • • • • • • -10 3 Units CAS Latency fCK Clock Frequency 100 MHz tCK Clock Cycle 10 ns tAC Clock Access Time 7 ns Inputs and outputs are LVTTL (3.3V) compatible Single 3.3V ± 0.3V Power Supply Single Pulsed RAS interface SDRAMs have 4 internal banks Fully Synchronous to positive Clock Edge Data Mask for Byte Read/Write control • Programmable Operation: - CAS Latency: 2, 3 - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only) - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Suspend Mode and Power Down Mode • 12/8/2 Addressing (Row/Column/Bank) • 4096 refresh cycles distributed across 64ms • Serial Presence Detect • Card size: 2.66" x 1.15" x 0.149" • Gold contacts • SDRAMS in TSOP Type II Package Description IBM13T8644MPD is a 144-pin Synchronous DRAM Small Outline Dual In-line Memory Module (SO DIMM) which is organized as a 8Mx64 high-speed memory array. The SO DIMM uses eight 4Mx16 SDRAMs in 400mil TSOP II packages. The SO DIMM achieves high speed data transfer rates of up to 100MHz by employing a prefetch/pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power. The SO DIMM is intended to comply with all JEDEC standards set for 144 pin SDRAM SO DIMMs. RAS, CAS, WE, S0, DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 12 bit address bus accepts address information in a row/column multiplexing arrangement. Prior to any access operation, the CAS latency, burst type, burst length, and burst operation type must be programmed into the SO DIMM by address inputs A0-A9 during the Mode Register Set cycle. All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. The SO DIMM uses serial presence detects implemented via a serial EEPROM using the two pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the customer. All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK1). Internal operating modes are defined by combinations of the All IBM 144-pin SO DIMMs provide a high performance, flexible 8-byte interface in a 2.66" long space-saving footprint. Card Outline (Front) (Back) 1 2 59 61 60 62 143 144 Pin Description CK0, CK1 45L7124.E93903A 5/99 Clock Inputs DQ0 - DQ63 Data Input/Output ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Pin Description CKE0, CKE1 Clock Enable DQMB0 - DQMB7 Data Mask RAS Row Address Strobe VDD Power (3.3V) CAS Column Address Strobe VSS Ground WE Write Enable NC No Connect S0, S1 Chip Selects SCL Serial Presence Detect Clock Input Address Inputs SDA Serial Presence Detect Data Input/Output A0 - A9, A11 A10 /AP Address Input/Autoprecharge BA0 - BA1 Serial Presence Detect Address Inputs SA0-2 SDRAM Bank Address Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 VSS 2 VSS 37 DQ8 38 DQ40 71 S1 72 Pin# Front Side NC 107 VSS 108 VSS A9 110 BA1 Pin# Back Side 3 DQ0 4 DQ32 39 DQ9 40 DQ41 73 DU 74 CK1* 109 5 DQ1 6 DQ33 41 DQ10 42 DQ42 75 VSS 76 VSS 111 A10/AP 112 A11 7 DQ2 8 DQ34 43 DQ11 44 DQ43 77 NC 78 NC 113 VDD 114 VDD 9 DQ3 10 DQ35 45 VDD 46 VDD 79 NC 80 NC 115 DQMB2 116 DQMB6 VDD 117 DQMB3 118 DQMB7 119 VSS 120 VSS 11 VDD VDD 12 47 DQ12 48 DQ44 81 VDD 82 13 DQ4 14 DQ36 49 DQ13 50 DQ45 83 DQ16 84 DQ48 15 DQ5 16 DQ37 51 DQ14 52 DQ46 85 DQ17 86 DQ49 121 DQ24 122 DQ56 17 DQ6 18 DQ38 53 DQ15 54 DQ47 87 DQ18 88 DQ50 123 DQ25 124 DQ57 19 DQ7 20 DQ39 55 VSS 56 VSS 89 DQ19 90 DQ51 125 DQ26 126 DQ58 21 VSS 22 VSS 57 NC 58 NC 91 VSS 92 VSS 127 DQ27 128 DQ59 23 DQMB0 24 DQMB4 59 NC 60 NC 93 DQ20 94 DQ52 129 VDD 130 VDD 25 DQMB1 26 DQMB5 95 DQ21 96 DQ53 131 DQ28 132 DQ60 27 VDD 28 VDD VOLTAGE KEY 61 CK0 62 CKE0 97 DQ22 98 DQ54 133 DQ29 134 DQ61 DQ23 100 DQ55 29 A0 30 A3 63 VDD 64 VDD 99 135 DQ30 136 DQ62 31 A1 32 A4 65 RAS 66 CAS 101 VDD 102 VDD 137 DQ31 138 DQ63 33 A2 34 A5 67 WE 68 CKE1 103 A6 104 A7 139 VSS 140 VSS 35 VSS 36 VSS NC 105 A8 106 BA0 141 SDA 142 SCL 143 VDD 144 VDD 69 S0 70 Ordering Information Part Number Organization Clock Cycle Leads Dimension Power IBM13T8644MPD-10T 8Mx64 10ns Gold 2.66" x 1.15" x 0.149" 3.3V ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Block Diagram S1 WE S0 CS DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE D0 CS WE CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D4 WE CS D2 WE D6 DQMB5 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB4 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 1 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS WE D1 CS WE D5 DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CS WE CS D3 WE D7 DQMB7 DQMB3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 * CLOCK WIRING CLOCK SDRAMs INPUT *CK0 *CK1 BA0-BA1: SDRAMS D0 - D3 BA0 A0-A11: SDRAMs D0 - D7 A0 - A11 VCC VSS 45L7124.E93903A 5/99 D0 - D7 D0 - D7 4 SDRAMs 4 SDRAMs SERIAL PD RAS RAS: SDRAMs D0 - D7 CAS CAS: SDRAMs D0 - D7 CKE0 CKE: SDRAMs D0 - D3 CKE1 CKE: SDRAMs D4 - D7 SCL SDA A0 A1 A2 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Input/Output Functional Description Symbol Type Signal Polarity Function CK0, CK1 Input Pulse Positive Edge The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their associated clock. CKE0, CKE1 Input Level Active High Activates the CK0 and CK1 signals when high and deactivates them when low. By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. S0, S1 Input Pulse Enables the associated SDRAM command decoder when low and disables the command Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low BA0, BA1 Input Level — Selects which SDRAM bank is to be active. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. A0 - A9, A11 A10/AP Input Level — During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA8) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0 defines the bank to be precharged (low=bank A, high=bank B). If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0 to control which bank(s) to precharge. If AP is high, both bank A and bank B will be precharged regardless of the state of BA0. If AP is low, then BA0 is used to define which bank to precharge. DQ0 - DQ63 Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. DQMB0 DQMB7 Input Pulse Active High SDA Input Output Level — Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a pull-up resistor is required on the system board. SCL Input Pulse — Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM. Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on the system board. VDD, VSS Supply Power and ground for the module. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Serial Presence Detect (Part 1 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on Assembly 12 0C 4 Number of Column Addresses on Assembly 8 08 5 Number of DIMM Banks 2 02 6-7 Data Width of Assembly x64 4000 1. 2. 3. 4. 5. 6. 8 Voltage Interface Level of this Assembly LVTTL 01 9 SDRAM Device Cycle Time at CL=3 10.0ns A0 10 SDRAM Device Access Time from Clock at CL=3 7.0ns 70 11 DIMM Configuration Type Non-Parity 00 12 Refresh Rate/Type SR/1x(15.625us) 80 13 Primary SDRAM Device Width x16 10 14 Error Checking SDRAM Device Width N/A 00 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 1 Clock 01 16 SDRAM Device Attributes: Burst Lengths Supported 1,2,4,8, Full Page 8F 17 SDRAM Device Attributes: Number of Device Banks 4 04 18 SDRAM Device Attributes: CAS Latencies Supported 2, 3 06 19 SDRAM Device Attributes: CS Latency 0 01 20 SDRAM Device Attributes: WE Latency 0 01 21 SDRAM Module Attributes Unbuffered 00 22 SDRAM Device Attributes: General Wr-1/Rd Burst, Precharge All, Auto-Precharge, VDD +/- 10% 0E 23 Minimum Clock Cycle at CL=2 15.0ns F0 24 Maximum Data Access Time (tAC) from Clock at CL=2 8.0ns 80 25 Minimum Clock Cycle Time at CL=1 N/A 00 26 Maximum Data Access Time (tAC) from Clock at CL=1 N/A 00 27 Minimum Row Precharge Time (tRP) 30ns 1E 28 Minimum Row Active to Row Active delay (tRRD) 20ns 14 Notes cc = Checksum Data byte, 00-FF (Hex) “R” = Alphanumeric revision code, A-Z, 0-9 rr = ASCII coded revision code byte “R” yy = Binary coded decimal year code, 00-99 (Decimal) ‘00-63 (Hex) ww = Binary coded decimal week code, 01-52 (Decimal) ‘01-34 (Hex) ss = Serial number data byte, 00-FF (Hex) 45L7124.E93903A 5/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Serial Presence Detect (Part 2 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) Notes 29 Minimum RAS to CAS delay (tRCD) 30ns 1E 30 Minimum RAS Pulse width (tRAS) 60ns 3C 31 Module Bank Density 32MB 08 32 Address and Command Setup Time Before Clock 3.0ns 30 33 Address and Command Hold Time After Clock 1.0ns 10 34 Data Input Setup Time Before Clock 3.0ns 30 35 Data Input Hold Time After Clock 1.0ns 10 Undefined 00 02 02 Checksum Data cc Manufacturers’ JEDEC ID Code IBM A400000000000000 Module Manufacturing Location Toronto, Canada 91 Vimercate, Italy 53 ASCII ‘13T8644MP”R”-10T’ 313354383634344D50rr 2D33363054202020 “R” plus ASCII blank rr20 Year/Week Code yyww 4, 5 Serial Number ssssssss 6 Undefined 00 66MHz 66 2, 3 C7 Undefined 00 36 - 61 Reserved 62 SPD Revision 63 Checksum for bytes 0 - 62 64 - 71 1 72 73 - 90 Module Part Number 91 - 92 Module Revision Code 93 - 94 Module Manufacturing Date 95 - 98 Module Serial Number 99 - 125 Reserved 126 Module Supports this Clock Frequency 127 Attributes for Clock Frequency defined in byte 126 128 - 255 Open for Customer Use 1. 2. 3. 4. 5. 6. 2, 3 cc = Checksum Data byte, 00-FF (Hex) “R” = Alphanumeric revision code, A-Z, 0-9 rr = ASCII coded revision code byte “R” yy = Binary coded decimal year code, 00-99 (Decimal) ‘00-63 (Hex) ww = Binary coded decimal week code, 01-52 (Decimal) ‘01-34 (Hex) ss = Serial number data byte, 00-FF (Hex) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Absolute Maximum Ratings Symbol Parameter Rating VDD Power Supply Voltage -0.3 to +4.6 VIN VOUT -0.3 to +4.6 Serial PD Device -0.3 to +6.5 SDRAM Devices -0.3to +4.6 Serial PD Device -0.3 to +6.5 V 1 0 to +70 °C 1 -55 to +125 °C 1 W 1, 2 mA 1 Output Voltage Operating Temperature TSTG Storage Temperature IOUT SDRAM Devices Input Voltage TOPR PD Units Notes 4Mx64 0.8 8Mx64 1.44 Power Dissipation Short Circuit Output Current 50 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Power is calculated using IDD1 @ 3.6Volt. Recommended DC Operating Conditions (TA= 0 to 70°C) Rating Symbol Parameter Min. Typ. Max. Units Notes VDD Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 — VDD + 0.3 V 1 VIL Input Low Voltage -0.3 — 0.8 V 1 1. All voltages referenced to VSS. Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V) Symbol Parameter Max Capacitance Units CI1 Input Capacitance (A0 - A9, A10/AP, BA0, RAS, CAS, WE) 52 pF CI2 Input Capacitance (CKE, CKE1) 32 pF CI3 Input Capacitance (S0, S1) 33 pF CI4 Input Capacitance (CK0, CK1) 38 pF CI5 Input Capacitance (DQMB0 - DQMB7) 12 pF CI6 Input Capacitance (SCL) 12 pF Input/Output Capacitance (DQ0 - DQ63) 18 pF Input/Output Capacitance (SDA) 15 pF C CIO2 45L7124.E93903A 5/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF 870Ω Output Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) 8x64 Symbol II(L) Parameter Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ VDD) VOH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) VOL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) Units Notes Min. Max. RAS, CAS, WE, CKE0, CK0, A0-A9, A10/AP, A11, BA0, BA1 -8 +8 S0 -8 +8 S1 -4 +4 DQMB0-7 -2 +2 SCL -2 +2 DQ0 - 63, SDA -2 +2 2.4 — µA µA V — 1 0.4 1. See DC output load circuit. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Operating, Standby and Refresh Currents Parameter (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) Symbol Test Condition 8Mx64 Units Notes IDD1 1 bank operation 340 mA 1, 3, 4 IDD2P CKE ≤ VIL(max), tCK = min, S0, S1 =VIH(min) 8.0 mA 2 IDD2Ps CKE ≤ VIL(max), tCK = Infinity, S0, S1 =VIH(min) 8.0 mA 2 IDD2N CKE ≥ VIH(min), tCK = min, S0, S1 =VIH (min) 200 mA 2, 5 IDD2NS CKE ≥ VIH(min), tCK = Infinity, S0, S1 =VIH (min) 48 mA 2 IDD3N CKE ≥ VIH(min), tCK = min, S0, S1 =VIH (min) 240 mA 2, 5 IDD3P CKE ≤ VIL(max), tCK = min, S0, S1 =VIH (min) (Power Down Mode) 24 mA 2 Burst Operating Current IDD4 tCK = min, Read/ Write command cycling 480 mA 1, 4, 5 Auto (CBR) Refresh Current IDD5 tCK = min, CBR command cycling 560 mA 1, 6 Self Refresh Current IDD6 CKE0 ≤ 0.2V 3.2 mA 1, 6 Serial PD Device Standby Current ISB5 VIN = GND or VDD 30 µA 7 Serial PD Device Active Power Supply Current ICCA SCL Clock Frequency = 100KHz 1 mA 8 Operating Current tRC = tRC(min), tCK = min Active-Precharge command cycling without Burst operation Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) 1. The specified values are for one SO DIMM bank in the specified mode and the other SO DIMM bank in Active Standby (ICC3N). 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed once during tCK (min). 3. Input signals are changed up to three times during tRC(min). This assumes the 14 Row Address mode with four-bank operation using rows A0-A11 and BA0-BA1. 4. The specified values are obtained with the outputs open. 5. IInput signals are changed once during three clock cycles. 6. 64ms refresh time (15.6µs, 4K refresh). 7. VDD = 3.3V. 8. Input pulse levels VDD x 0.1 to VDD x 0.9, Input rise and fall times 10ns, Input and output timing levels VDD x 0.5, Output load 1 TTL gate and CL=100pf 45L7124.E93903A 5/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) 1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point. 3. The Transition time is measured between VIH and VIL (or between VIL and VIH). 4. AC measurements assume tT=1ns. 5. In addition to meeting the transition rate specification, the clock and CKEn must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. AC Characteristics Diagrams tT 2.0V 1.4V 0.8V Clock tSETUP Vtt=1.4V 50 Output tHOLD Zo = 50Ω 50pF Input 1.4V tAC AC Output Load Circuit tOH tLZ 1.4V Output Clock and Clock Enable Parameters -10 Symbol Parameter Units Min. Max. Notes tCK3 Clock Cycle Time, CAS Latency = 3 10 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 15 1000 ns 1 tAC3 Clock Access Time, CAS Latency = 3 — 7 ns 2 tAC2 Clock Access Time, CAS Latency = 2 — 8 ns 2 tCKH Clock High Pulse Width 3 — ns 3 tCKL Clock Low Pulse Width 3 — ns 3 tCES Clock Enable Set-up Time 3 — ns tCEH Clock Enable Hold Time 1 — ns tSB Power down mode Entry Time 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 ns 1. For 66MHz clock, CAS Latency = 2. 2. Access time is measured at 1.4V. See AC output load circuit above. 3. tCKH is the pulse width of CK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CK measured from the negative edge to the positive edge referenced to VIL (max). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Common Parameters -10 Symbol Parameter Units Min. Max. Notes tCS Command Setup Time 3 — ns tCH Command Hold Time 1 — ns tAS Address and Bank Select Set-up Time 3 — ns tAH Address and Bank Select Hold Time 1 — ns tRCD RAS to CAS Delay 30 — ns 1 tRC Bank Cycle Time 90 — ns 1 tRAS Active Command Period 60 100000 ns 1 tRP Precharge Time 30 — ns 1 tRRD Bank to Bank Delay Time 20 — ns 1 tCCD CAS to CAS Delay Time 1 — CLK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle -10 Symbol tRSC Parameter Mode Register Set Cycle Time Min. Max. 2 — Units Notes CLK 1 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). 45L7124.E93903A 5/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Read Cycle -10 Symbol Parameter Units Min. Max. Notes tOH Data Out Hold Time 3 — ns tLZ Data Out to Low Impedance Time 0 — ns tHZ3 Data Out to High Impedance Time 3 6 ns 1 tHZ2 Data Out to High Impedance Time 3 8 ns 1 tDQZ DQM Data Out Disable Latency 2 — CLK 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levells. Refresh Cycle -10 Symbol Parameter Min. Max. 64 tREF Refresh Period — tSREX Self Refresh Exit Time 10 Units Notes ms 1 ns 1. 4096 auto refresh cycles. Write Cycle -10 Symbol Parameter Units Min. Max. tDS Data In Set-up Time 3 — ns tDH Data In Hold Time 1 — ns tDPL Data Input to Precharge 15 — ns tDAL3 Data In to Active Delay CAS Latency = 3 4 CLK tDAL2 Data In to Active Delay CAS Latency = 2 3 CLK tDQW DQM Write Mask Latency 0 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 17 — CLK 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Clock Frequency and Latency Symbol Parameter -10 Units fCK Clock Frequency 100 66 MHz tCK Clock Cycle Time 10 15 ns tAA CAS Latency 3 2 CLK tRP Precharge Time 3 2 CLK tRCD RAS to CAS Delay 3 2 CLK tRC Bank Cycle Time 9 6 CLK tRAS Minimum Bank Active Time 6 4 CLK tDPL Data In to Precharge 2 1 CLK tDAL Data In to Active/Refresh 4 3 CLK tRRD Bank to Bank Delay Time 2 2 CLK tCCD CAS to CAS Delay Time 1 1 CLK tWL Write Latency 0 0 CLK tDQW DQM Write Mask Latency 0 0 CLK tDQZ DQM Data Disable Latency 2 2 CLK tCSL Clock Suspend Latency 1 1 CLK Max Unit Notes SCL Clock Frequency 100 kHz 100 ns 3.5 µs Presence Detect Read and Write Cycle Symbol fSCL Parameter Min TI Noise Suppression Time Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out Valid 0.3 tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 µs Start Condition Hold Time 4.0 µs tLOW Clock Low Period 4.7 µs tHIGH tHD:STA Clock High Period 4.0 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs tHD:DAT Data in Hold Time 0 µs tSU:DAT Data in Setup Time 250 ns tr SDA and SCL Rise Time 1 µs tf SDA and SCL Fall Time 300 ns Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns tWR Write Cycle Time tSU:STO 15 ms 1 1. The Write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. 45L7124.E93903A 5/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Functional Description and Timing Diagrams Refer to the IBM 64Mb Synchronous DRAM data sheet, document 19L3264.E35855A, for the functional description and timing diagrams for SDRAM operation. Refer to the IBM Application Notes: Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. All AC timing information refers to the timings at the SDRAM devices. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Layout Drawing 67.60 2.661 2.00 MIN .0787 Front 29.21 1.15 24.5 .9646 4.60 .1811 32.80 1.293 2.50 .0984 0.60+/- .05 WIDTH .0236 1.50+/- 0.10 .0591+/-.0039 0.25 MAX 2.55 23.2 .9134 0.009 6.00 .236 3.30 .1299 20.00 .7874 (2X) 0 1.800 .0709 .1004 4.00 .157 63.60 2.504 0.80 TYP PITCH .0315 8M x 64 Side 3.80 MAX 0.1496 6.269 .2468 MIN 4.00+/- 0.10 .1575+/-.0039 _ 0.10 1.00 + _ .0039 .039 + Note: All dimensions are typical unless otherwise stated. 45L7124.E93903A 5/99 MILLIMETERS INCHES ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 17 Discontinued (4/1/00 last order; 7/31/00 - last ship) IBM13T8644MPD Two Bank 8M x 64 SDRAM SO DIMM Revision Log Rev Contents of Modification 2/99 Initial Release 5/99 Updated IDD2NS in Operating, Standby, and Refresh Currents Table ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 17 45L7124.E93903A 5/99 Discontinued (4/1/00 last order; 7/31/00 - last ship) International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant.