IBM11M4730C4M x 72 E12/10, 5.0V, Au. IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 64Mx72 Synchronous DRAM DIMM • Performance: -260 CL=2 -360 CL=3 -360 CL=2 Units Reg. Buff. Reg. Buff Reg. Buff. DIMM CAS Latency 3 2 4 3 3 2 fCK Clock Frequency 100 100 100 100 66 66 MHz fCK Clock Cycle 10 10 10 10 15 15 ns tAC Clock Access 7.2 7.2 7.2 7.2 10.2 10.2 ns • Intended for 66/100MHz and PC100 applications • Inputs and outputs are LVTTL (3.3V) compatible • Single 3.3V ± 0.3V Power Supply • Single Pulsed RAS interface • SDRAMs have four internal banks • Module has one physical bank • Fully Synchronous to positive Clock Edge • Programmable Operation: - DIMM CAS Latency: 3, 4 (Registered mode); 2, 3 (Buffered mode) - Burst Type: Sequential or Interleave - Burst Length:1, 2, 4, 8 - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Data Mask for Byte Read/Write control • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Suspend Mode and Power Down Mode • 13/11/2 Addressing (Row/Column/Bank) • 8192 refresh cycles distributed across 64ms • Card size: 5.25" x 1.70" x 0.157" • Gold contacts • SDRAMs in TSOP - Type II Package • Serial Presence Detect with Write protect Description IBM13M64734BCA is a registered 168-Pin Synchronous DRAM Dual-In-Line Memory Module (DIMM) organized as a 64Mx72 high-speed memory array. The DIMM uses eighteen 64Mx4 SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data-transfer rates of up to 100 MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system clock. The DIMM is intended for use in applications operating from 66MHz to 100 MHz, PC100, memory bus speeds, and/or heavily loaded bus applications. All control and address signals are re-driven through registers/buffers to the SDRAM devices. The DIMM can be operated in either registered mode (REGE pin tied high), where the control/address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (REGE pin tied low), where the input signals pass through the register/buffer to the SDRAM devices on the same clock. XTK simulation models of the DIMM are available to determine which mode to design for. A phase-lock loop (PLL) on the DIMM is used to redrive the clock signals to both the SDRAM devices and the registers to minimize system clock loading. 19L7159.E93855 2/00 (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated on the DIMM.) A single clock enable (CKE0) controls all devices on the DIMM, enabling the use of SDRAM power-down modes. Prior to any access operation, the device CAS latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A9 using the mode register set cycle. The DIMM CAS latency when operated in buffered mode is the same as the device CAS latency as specified in the SPD EEPROM. The DIMM CAS latency when operated in registered mode is one clock later due to the address and control signals being clocked to the SDRAM devices. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by providing a high level to pin 81 on the DIMM. (An on-board pulldown resistor keeps this in the write-enable mode.) All IBM 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Card Outline (Front) (Back) 1 85 10 11 94 95 40 124 84 168 41 125 Pin Description CK0 - CK3 CKE0 RAS Clock Inputs Clock Enable Row Address Strobe CAS DQ0 - DQ63 CB0 - CB7 DQMB0 - DQMB7 VDD Column Address Strobe WE VSS Write Enable S0, S2 A0 - A9, A11, A12 A10/AP BA0, BA1 WP Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs SPD Write Protect Data Input/Output Check Bit Data Input/Output Data Mask Power (3.3V) Ground NC SCL SDA SA0-2 REGE No Connect Serial Presence Detect Clock Input Serial Presence Detect Data Input/Output Serial Presence Detect Address Inputs Register Enable Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 2 3 4 5 VSS 85 86 87 88 89 VSS 22 106 127 128 129 130 131 64 VSS 148 VSS NC NC VDD 43 44 45 46 47 VSS 23 24 25 26 CB5 VSS VSS CKE0 NC DQMB6 DQMB7 65 66 67 68 DQ21 DQ22 DQ23 VSS 149 150 151 152 DQ53 DQ54 DQ55 VSS 90 DQ32 DQ33 DQ34 DQ35 VDD CB1 VSS 27 WE 111 CAS 48 91 92 93 94 DQ36 DQ37 DQ38 DQ39 28 29 30 31 112 113 114 115 DQ40 VSS 32 116 DQMB4 DQMB5 NC RAS VSS 49 50 51 52 95 DQMB0 DQMB1 S0 NC VSS 33 34 35 36 37 38 A0 A2 A4 A6 A8 A10/AP 117 118 119 120 121 122 A1 A3 A5 A7 A9 BA0 54 55 56 57 58 59 6 DQ0 DQ1 DQ2 DQ3 VDD 7 8 9 10 DQ4 DQ5 DQ6 DQ7 11 DQ8 VSS 12 13 14 15 16 17 96 97 98 99 100 101 NC NC VDD 107 108 109 110 53 NC S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS 132 133 134 135 136 137 DQ16 DQ17 DQ18 DQ19 VDD 138 139 140 141 142 143 NC VDD NC NC CB6 CB7 VSS 69 DQ24 153 DQ56 70 71 72 73 DQ25 DQ26 DQ27 VDD 154 155 156 157 DQ57 DQ58 DQ59 VDD 74 DQ28 158 DQ60 DQ48 DQ49 DQ50 DQ51 VDD 75 76 77 78 79 80 DQ29 DQ30 DQ31 VSS 159 160 161 162 163 164 DQ61 DQ62 DQ63 VSS SA0 18 DQ9 DQ10 DQ11 DQ12 DQ13 VDD 102 DQ41 DQ42 DQ43 DQ44 DQ45 VDD 39 BA1 123 A11 60 DQ20 144 DQ52 81 WP 165 19 DQ14 103 DQ46 40 VDD 124 VDD 61 NC 145 NC 82 SDA 166 SA1 20 DQ15 104 DQ47 41 VDD 125 CK1 62 NC 146 NC 83 SCL 167 SA2 21 CB0 105 CB4 42 CK0 126 A12 63 NC 147 REGE 84 VDD 168 VDD CK2 NC CK3 NC Note: All pin assignments are consistent with all 8-byte unbuffered versions. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 20 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Ordering Information Part Number Organization IBM13M64734BCA-260T 64Mx72 IBM13M64734BCA-360T 64Mx72 Device CAS Latency Device Access Time Clock Cycle 3 6ns 10ns 3 6ns 10ns 2 9ns 15ns Leads Dimension Power Gold 5.25" x 0.157" x 1.70" 3.3V Note 1 1. PC100 applications 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module x72 ECC SDRAM DIMM Block Diagram RS0 RDQMB0 # Preliminary (1 Bank, x4 SDRAMs) RDQMB4 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS DQ0 DQ1 DQ2 DQ3 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS DQ4 DQ5 DQ6 DQ7 D0 D1 RDQMB1 DQ32 DQ33 DQ34 DQ35 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ36 DQ37 DQ38 DQ39 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D9 CS D10 RDQMB5 DQ8 DQ9 DQ10 DQ11 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS CB0 CB1 CB2 CB3 CS DQ16 DQ17 DQ18 DQ19 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ40 DQ41 DQ42 DQ43 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ44 DQ45 DQ46 DQ47 DQM I/O 0 I/O 1 I/O 2 I/O 3 CB4 CB5 CB6 CB7 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D2 CS D3 D4 RS2 RDQMB2 CS D11 CS D12 CS D13 RDQMB6 D5 DQ48 DQ49 DQ50 DQ51 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D6 RDQMB3 CS D14 CS D15 RDQMB7 DQ24 DQ25 DQ26 DQ27 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ28 DQ29 DQ30 DQ31 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D7 DQ56 DQ57 DQ58 DQ59 CS D8 DQ60 DQ61 DQ62 DQ63 CS DQM I/O 0 I/O 1 D16 I/O 2 I/O 3 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS R E G I S T E R RS0/RS2 RDQMB0 - RDQMB7 BS0-BS1: SDRAMs D0-D17 RBA0 - RBA1 A0-A12: SDRAMs D0-D17 RA0-RA12 RRAS RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 RCAS CKE: SDRAMs D0 - D17 RCKE0 RWE WE: SDRAMs D0 - D17 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 20 SCL WP 47K D17 #Unless otherwise noted, resistor values are 10 Ohms. S0/S2 DQMB0 to DQMB7 BA0-BA1 A0-A12 RAS CAS CKE0 WE 10k VCC REGE PCK Serial Presence Detect SDA A0 A1 A2 SA0 SA1 SA2 VCC D0 - D17 VSS D0 - D17 Note: DQ wiring may differ from that described in this drawing; however, DQ/DQMB relationships are maintained as shown. PLL CK0 CK1, CK2, CK3 Terminated 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Clock Wiring Clock Net Wiring (CK0): SDRAM 10 Ohms CK0 IN OUT1 to OUT6 12pF SDRAM SDRAM Phase Lock Loop One of six SDRAM outputs is shown. All PLL clock SDRAM loads are equal-achieved in part through equal-length wiring. OUT7 FDBK OUT10 IN PCK Register 1:1 Register 1:1 (PLL out to Feedback input) 12pF Notes: Terminated Clock Nets (CK1, CK2, CK3): 10 Ohms CK1, CK2, and CK3 12pF 19L7159.E93855 2/00 PCK 1. The PLL is programmed via a combination of the feedback path and on-DIMM loading. PLL feedback produces zero phase shift from the delayed CK0 input. 2. Card wiring and capacitance loading variation: ± 100 ps. 3. Timing is based on a driver with a 1 Volt/ns rise time. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Input/Output Functional Description Symbol Type Signal Polarity CK0 - CK3 Input Pulse Positive Edge CKE0 Input Level Active High S0, S2 Input Pulse Enables the associated SDRAM command decoder when low and disables the command Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0, 1 Input Level A0 - A9, A11, A12 10/AP Input DQ0 - DQ63, Input CB0 - CB7 Output DQMB0 DQMB7 Input VDD, VSS Supply Function The system clock inputs. All the SDRAM inputs are sampled on the rising edge of their associated clock. CK0 drives the PLL. CK1, CK2, and CK3 are terminated. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, the Suspend mode, or the Self Refresh mode. — Selects which SDRAM bank of four is activated. Level — During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0CA9, A11) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. Level — Data and Check Bit Input/Output pins Pulse Active High The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high-impedance state when sampled high. In Read mode, DQMB has a latency of two clock cycles in Buffered mode or three clock cycles in Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB has a zero clock latency in Buffered mode and a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by allowing input data to be written if it is low but blocking the write operation if it is high. Power and ground for the module. Active High The Register Enable pin is used to permit the DIMM to operate in “buffered” mode (inputs (Register re-driven asynchronously) or “registered” mode (signals re-driven to SDRAMs when clock rises, and held valid until next rising clock). Mode Enable) REGE Input Level SA0 - 2 Input Level — These signals are tied at the system planar to either VSS or VDD to configure the serial SPD EEPROM. SDA Input Output Level — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup. SCL Input Pulse — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup. WP Input Level Active High This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the SPD EEPROM. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 20 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Serial Presence Detect Byte # (Part 1 of 2) Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 11 0B 5 Number of DIMM Banks 1 01 6-7 Data Width of Assembly x72 4800 LVTTL 01 10ns 10 6.0ns 60 ECC 02 SR/1X(7.813us) 82 8 Assembly Voltage Interface Levels 9 SDRAM Device Cycle Time (CL = 3) 10 SDRAM Device Access Time from Clock at CL=3 11 Assembly Error Detection/Correction Scheme 12 Assembly Refresh Rate/Type 13 SDRAM Device Width x4 04 14 Error Checking SDRAM Device Width x4 04 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 1 Clock 01 16 SDRAM Device Attributes: Burst Lengths Supported 1,2,4,8 0F 17 SDRAM Device Attributes: Number of Device Banks 4 04 18 SDRAM Device Attributes: CAS Latency 2, 3 06 19 SDRAM Device Attributes: CS Latency 0 01 20 SDRAM Device Attributes: WE Latency 0 01 21 SDRAM Module Attributes Registered/Buffered with PLL IF 22 SDRAM Device Attributes: General Write-1/Read Burst, Precharge All, Auto-Precharge 0E 23 Minimum Clock Cycle at CLX-1 (CL = 2) -260 10.0ns A0 -360 15.0ns F0 Maximum Data Access Time (tAC) from Clock at CLX-1 (CL = 2) -260 6.0ns 60 24 -360 9.0ns 90 -260 25 Minimum Clock Cycle Time at CLX-2 (CL = 1) N/A 00 26 Maximum Data Access Time (tAC) from Clock at CLX-2 (CL = 1) N/A 00 27 Minimum Row Precharge Time (tRP) 20.0ns 14 Notes 1, 2 1,2 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time for the -360 is 10ns (100MHz). 3. cc = Checksum Data byte, 00-FF (Hex) 4. “R” = Alphanumeric revision code, A-Z, 0-9 5. rr = ASCII coded revision code byte “R” 6. ww = Binary coded decimal week code, 01-52 (Decimal) ➔ 01-34 (Hex) 7. yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex) 8. ss = Serial number data byte, 00-FF (Hex) 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Serial Presence Detect Byte # Preliminary (Part 2 of 2) Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 20.0ns 14 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 20.0ns 14 30 Minimum RAS Pulse width (tRAS) 50.0ns 32 31 Module Bank Density 512MB 80 32 Address and Command Setup Time Before Clock 2.0ns 20 33 Address and Command Hold Time After Clock 1.0ns 10 34 Data Input Setup Time Before Clock 2.0ns 20 35 Data Input Hold Time After Clock 36 - 61 Reserved 62 SPD Revision 63 Checksum for bytes 0 - 62 64 - 71 72 73 - 90 Manufacturers’ JEDEC ID Code 10 00 PC100 1.2A 12 Checksum Data cc 3 IBM A400000000000000 Toronto, Canada 91 Vimercate, Italy 53 -260 ASCII ‘13M64734BC”R”260T’ 31334D36343733344243rr 2D323630542020 -360 ASCII ‘13M64734BC”R”360T’ 31334D36343733344243rr 2D333630542020 Assembly Manufacturing Location Assembly Part Number 91 - 92 Assembly Revision Code 93 - 94 Assembly Manufacturing Date 95 - 98 Assembly Serial Number 126 Module Supports this Clock Frequency 127 Attributes for clock frequency defined in Byte 126 4, 5 “R” plus ASCII blank rr20 5 Year/Week Code yyww 6, 7 Serial Number ssssssss 8 Undefined Not Specified 100MHz 64 -260 CLK0, CL=2,3, ConAP 87 -360 CLK0, CL=3, ConAP 85 Undefined 00 99 - 125 Reserved 128 255 1.0ns Undefined Notes Open for Customer Use 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time for the -360 is 10ns (100MHz). 3. cc = Checksum Data byte, 00-FF (Hex) 4. “R” = Alphanumeric revision code, A-Z, 0-9 5. rr = ASCII coded revision code byte “R” 6. ww = Binary coded decimal week code, 01-52 (Decimal) ➔ 01-34 (Hex) 7. yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex) 8. ss = Serial number data byte, 00-FF (Hex) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 20 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Absolute Maximum Ratings Symbol VDD VIN VOUT TA TSTG PD Parameter Rating Power Supply Voltage Input Voltage Output Voltage Operating Temperature (ambient) Storage Temperature Units Notes -0.3 to +4.6 SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Register 0 - VDD PLL 0 - VDD V 1 0 to +70 °C 1 -55 to +125 °C 1 SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Power Dissipation 18 W 1, 2 IOUT Short Circuit Output Current 50 mA 1 FMIN Minimum Operating Frequency 66 MHz 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum power is calculated assuming the physical bank is in Burst Operating Mode. 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Recommended DC Operating Conditions Symbol Preliminary (TA= 0 to 70˚C) Rating Parameter Min. Typ. Units Max. Notes VDD Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 — VDD + 0.3 V 1 VIL Input Low Voltage -0.3 — 0.8 V 1 1. All voltages referenced to VSS. Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V Symbol 0.3V) Parameter Max. Units CI1 Input Capacitance (A0 - A9, A10/AP, BA0, BA1, A11, A12) 10.5 pF CI2 Input Capacitance (RAS) 10.0 pF CI3 Input Capacitance (CAS) 10.5 pF CI4 Input Capacitance (S0, S2) 11 pF CI5 Input Capacitance (CKE0) 20.5 pF CI6 Input Capacitance (CK0) 25 pF CI7 Input Capacitance (DQMB0 - DQMB7) 11 pF CI8 Input Capacitance (SA0 - SA2, SCL, WP) 9 pF CI9 Input Capacitance (REGE) 10 pF CI10 Input Capacitance (CK1 - CK3) 14 pF CI11 Input Capacitance (WE) 10 pF CIO1 Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 11 pF CIO2 Input/Output Capacitance (SDA) 11 pF DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 870Ω ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 20 50pF 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Input/Output Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) Symbol x72 Parameter II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ 3.6V), all other pins Not under test = 0V IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V) VOH VOL Min. Max. -10 +10 DQ0-63, CB0 - 7 -2 +2 SDA -1 +1 Output Level Output “H” Level Voltage (IOUT = -2.0mA) 2.4 VDD Output Level Output “L” Level Voltage (IOUT = +2.0mA) 0.0 0.4 Units Notes µA µA V 1 1. See DC output load circuit. 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ±0.3V) Parameter DIMM Operational Parameters ICC1 Clock Cycle Units Notes 1760 mA 1, 2 264 194 mA 1, 2 CKE0 ≤ VIL (max), tCK = Infinity, S0, S2 =VIH (min) 75 75 mA ICC2N CKE0 ≥ VIH (min), tCK = min, S0, S2 =VIH (min) 588 518 mA ICC2NS CKE0 ≥ VIH (min), tCK = Infinity, S0, S2 =VIH (min) 147 147 mA ICC3N CKE0 ≥ VIH (min), tCK = min, S0, S2 =VIH (min) 1038 698 mA 1 ICC3P CKE0 ≤ VIL (max), tCK = min, S0, S2 =VIH (min) (Power Down Mode) 336 266 mA 1 Burst Operating Current (Active state: 4 bank) ICC4 tCK = min, Read/Write command cycling Multiple banks active, Gapless date BL =4 2298 1544 mA 1, 2 Auto (CBR) Refresh Current ICC5 tCK = tCK(min), tRC = tRC (min) CBR command cycling 3298 2534 mA 1 Self Refresh Current ICC6 CKE0 ≤ 0.2V 93 93 mA Operating Current 1 bank operation Symbol -10ns -15ns tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 2298 ICC2P CKE0 ≤ VIL(max), tCK = min, CS =VIH (min) ICC2PS Precharge Standby Current in Power Down Mode Precharge Standby Current in NonPower Down Mode No Operating Current (Active state: 4bank) 1, 2 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed once during tCK(min). 2. The specified values are obtained with the DIMM data outputs open. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 20 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) 1. An initial pause of 200µs, with CKE0 held high, is required after power-up. A Precharge All Banks (logical, not physical) command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point. 3. 4. The Transition time is measured between VIH and VIL (or between VIL and VIH). 5. AC measurements assume tT=1.2ns (1 Volt/ns rise time). 6. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 7. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. AC Output Load Circuits tCKH Clock 2.0V 1.4V 0.8V tCKL tSETUP tT tHOLD Output Zo = 50Ω Input 50pF 1.4V tAC tOH AC Output Load Circuit tLZ Output 19L7159.E93855 2/00 1.4V ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Clock and Clock Enable Parameters Symbol -260 max. (Device CL, tRCD, tRP = 2, 2, 2) -360 max. (Device CL, tRCD, tRP = 3, 2, 2) Min. Max. Min. Max. Registered 10 1000 10 Registered 10 1000 Buffered 10 Parameter Units Notes 1000 ns 1 15 1000 ns 1000 10 1000 ns tCK4 Clock Cycle Time, DIMM CAS Latency = 4 tCK3 Clock Cycle Time, DIMM CAS Latency = 3 tCK2 Clock Cycle Time, DIMM CAS Latency = 2 Buffered 10 1000 15 1000 ns 1 tAC4 Clock Access Time, DIMM CAS Latency = 4 Registered — 7.2 — 7.2 ns 1, 2 tAC3 Clock Access Time, DIMM CAS Latency = 3 tAC2 Clock Access Time, DIMM CAS Latency = 2 tCKH 1 Registered — 7.2 — 10.2 ns Buffered — 7.2 — 7.2 ns Buffered — 7.2 — 10.2 ns 1, 2 Clock High Pulse Width 3 — 3 — ns 3 tCKL Clock Low Pulse Width 3 — 3 — ns 3 tCES Clock Enable Setup Time Registered 2.0 — 2.0 — ns Buffered 7.2 — 7.2 — ns tCEH Clock Enable Hold Time Registered 1.0 — 1.0 — ns Buffered 0.2 — 0.2 — ns tSB Power down mode Entry Time 0 10 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 0.5 10 ns 1. 2. 3. 1, 2 1 1 DIMM CAS latency = device CL [clock cycles] + 1 for Register mode; DIMM CAS latency is one clock less for Buffer mode. Access time is measured at 1.4V. See AC output load circuit. tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 20 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary . Common Parameters -260 Symbol -360 Parameter tCS Command Setup Time tCH Command Hold Time tAS Address and Bank Select Setup Time tAH Address and Bank Select Hold Time Units Min. Max. Min. Max. Registered 2.0 — 2.0 — ns Buffered 7.7 — 7.7 — ns Registered 1.0 — 1.0 — ns Buffered 0.0 — 0.0 — ns Registered 2.0 — 2.0 — ns Buffered 7.7 — 7.7 — ns Registered 1.0 — 1.0 — ns Buffered 0.0 — 0.0 — ns Notes 1, 2 1, 2 1, 2 1, 2 tRCD RAS to CAS Delay 20 — 20 — ns 1 tRC Bank Cycle Time 70 — 70 — ns 1 tRAS Active Command Period 50 100000 50 100000 ns 1 tRP Precharge Time 20 — 20 — ns 1 tRRD Bank to Bank Delay Time 20 — 20 — ns 1 tCCD CAS to CAS Delay Time (Same Bank) 1 — 1 — CLK 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). 2. The set up and hold times refer to the addition of the register. Note that although the Buffered set up times appear much greater, there is no additional clock cycle as there is in Registered mode. Mode Register Set Cycle -260 Symbol tRSC -360 Parameter Mode Register Set Cycle Time Min. Max. Min. Max. 2.0 — 2.0 — Units Notes CLK 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Refresh Cycle -260 Symbol tREF -360 Parameter Units Notes Min. Max. Min. Max. — 64 — 64 Refresh Period ms 1 1. 8192 cycles. Read Cycle -260 Symbol -360 Parameter Units Min. Max. Min. Max. Notes tOH Data Out Hold Time 3.6 — 3.6 — ns tLZ Data Out to Low Impedance Time 0.5 — 0.5 — ns tHZ3 Data Out to High Impedance Time 3.5 6.7 3.5 6.7 ns 1 tHZ2 Data Out to High Impedance Time 3.5 6.7 3.5 6.7 ns 1 Registered 3 — 3 — CLK tDQZ DQM Data Out Disable Latency Buffered 2 — 2 — CLK 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Write Cycle -260 Symbol -360 Parameter Units Min. Max. Min. Max. tDS Data In Setup Time 2.1 — 2.1 — ns tDH Data In Hold Time 1.6 — 1.6 — ns tDPL Registered 10 — 10 — Data input to Precharge Buffered 20 20 tDAL3 Registered 4 4 Data Input to Active, CL = 3 ns Buffered 5 5 Registered 4 4 Buffered 5 5 Registered 1 — 1 — CLK Buffered 0 — 0 — CLK CLK tDAL2 Data Input to Active, CL = 2 tDQW DQM Write Mask Latency ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 20 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Presence Detect Read and Write Cycle Symbol fSCL TI Parameter Min. Max. Units SCL Clock Frequency 100 kHZ Noise Suppression Time Constant at SCL, SDA Inputs 100 ns 3.5 µs tAA SCL Low to SDA Data Out Valid 0.3 tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 µs Start Condition Hold Time 4.0 µs tLOW Clock Low Period 4.7 µs tHIGH tHD:STA Clock High Period 4.0 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs tHD:DAT Data In Hold Time 0 µs tSU:DAT Data In Setup Time 250 ns tr SDA and SCL Rise Time tf SDA and SCL Fall Time 1 300 µs ns Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns tWR Write Cycle Time tSU:STO 15 Notes ms 1 1. The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pullup resistor, and the device does not respond to its slave address. Functional Description and Timing Diagrams Refer to IBM 168 Pin SDRAM Registered DIMM Functional Description and Timing Diagrams (Document 01L5868) for registered-mode operation. Refer to the IBM 256Mb Synchronous DRAM datasheet (Document 29L0000) for the functional description and timing diagrams for buffered-mode operation. Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 20 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Layout Drawing 133.35 5.25 131.35 5.171 127.35 5.014 6.35 .250 3.0 .118 43.33 1.7 (2X) 4.00 .157 Front 42.18 1.661 66.68 2.63 17.80 .700 1.27 pitch .050 (2) 0 3.18 .1255 1.00 width .039 See Detail A Side 4.01 .158 max. Detail A Scale: 4/1 R 1.00 .0393 4.24 .167 4.24 .167 2.0 .078 3.0 .118 (Front) 1.27 ± 0.10 .050 ± .004 Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 20 Millimeters Inches 19L7159.E93855 2/00 IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module Preliminary Revision Log Rev Contents of Modification 6/99 Initial release 2/00 Correct typo in package description 19L7159.E93855 2/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 20 Copyright and Disclaimer Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America February 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com 19L7159.E93855 2/00