ETC IBM13M64734CCA-360Y

.
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Features
• 168-Pin Registered 8-Byte Dual In-Line Memory
Module
• 64Mx72 Synchronous DRAM DIMM
• Performance:
-260
Device Latency
fCK
Clock Frequency
tAC
Clock Access Time
2
-360 -360 Units
2
3
100
66
100
MHz
7.2
10.2
7.2
ns
• Intended for 66/100MHz and PC100 applications
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V power supply
• Single Pulsed RAS interface
• SDRAMs have four internal banks
• Module has two physical banks
• Fully synchronous to positive clock edge
• Programmable operation:
- DIMM CAS Latency: 3, 4 (Registered
mode); 2, 3 (Buffered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge commands
• Suspend mode and Power Down mode
• 12/11/2 Addressing (Row/Column/Bank)
• 4096 refresh cycles distributed across 64ms
• Card size: 5.25" x 1.70" x 0.320"
• Gold contacts
• DRAMs in TSOJ - 2 High Package
• Serial Presence Detect with Write protect
Description
IBM13M64734CCA is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module
(DIMM) organized as a 64Mx72 high-speed memory array and is configured as two 32Mx72 physical
banks. The DIMM uses 18 64Mx4 SDRAMs in 400
mil TSOJ stacked packages. The DIMM achieves
high-speed data-transfer rates of up to 100MHz by
employing a prefetch/pipeline hybrid architecture
that synchronizes the output data to a system clock.
The DIMM is intended for use in applications operating from 66MHz to 100MHz, PC100, memory bus
speeds, and/or heavily loaded bus applications. All
control and address signals are re-driven through
registers/buffers to the SDRAM devices. The DIMM
can be operated in either Registered mode (REGE
pin tied high), where the control/address input signals are latched in the register on one rising clock
edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one
clock), or in Buffered mode (REGE pin tied low),
where the input signals pass through the register/buffer to the SDRAM devices on the same clock.
XTK simulation models of the DIMM are available to
determine which mode to design for.
A phase-lock loop (PLL) on the DIMM is used to redrive the clock signals to both the SDRAM devices
and the registers to minimize system clock loading.
09K3884.F38744
10/99
(CK0 is connected to the PLL, and CK1, CK2, and
CK3 are terminated on the DIMM.) A single clock
enable (CKE0) controls all devices on the DIMM,
enabling the use of SDRAM Power Down modes;
the stacked devices share a common CKE pin.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must
be programmed into the DIMM by address inputs
A0-A9 using the mode register set cycle. The DIMM
CAS latency when operated in Buffered mode is the
same as the device CAS latency as specified in the
SPD EEPROM. The DIMM CAS latency when operated in Registered mode is one clock later due to
the address and control signals being clocked to the
SDRAM devices.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by providing a
high level to pin 81 on the DIMM. An on-board pulldown resistor keeps this in the Write Enable mode.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Card Outline
(Front) 1
(Back) 85
10 11
94 95
40 41
124 125
84
168
Pin Description
CK0 - CK3
Clock Inputs
DQ0 - DQ63
CKE0
Clock Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
VDD
WE
Write Enable
VSS
Ground
S0, S1, S2, S3
Chip Selects
NC
No Connect
Address Inputs
SCL
Serial Presence Detect Clock Input
A10/AP
Address Input/Autoprecharge
SDA
Serial Presence Detect Data
Input/Output
BA0, BA1, (A13, A12)
SDRAM Bank Address Inputs
SA0-2
Serial Presence Detect Address
Inputs
SPD Write Protect
REGE
Register Enable
A0 - A9, A11
WP
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 20
CB0 - CB7
Data Input/Output
DQMB0 - DQMB7
Check Bit Data Input/Output
Data Mask
Power (3.3V)
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Pinout
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB1
VSS
NC
NC
VDD
WE
DQMB0
DQMB1
S0
NC
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CK0
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
CB5
VSS
NC
NC
VDD
CAS
DQMB4
DQMB5
S1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
NC
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
VSS
NC
S2
DQMB2
DQMB3
NC
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
NC
NC
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
VSS
CKE0
S3
DQMB6
DQMB7
NC
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
NC
REGE
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
NC
WP
SDA
SCL
VDD
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
NC
SA0
SA1
SA2
VDD
Note: All pin assignments are consistent with all 8-byte unbuffered versions.
Ordering Information
Part Number
Organization
Clock Cycle
CAS Latency Access Time Leads
IBM13M64734CCA-260Y
64Mx72
10ns
2
6.0ns
IBM13M64734CCA-360Y
64Mx72
10ns
3
6.0ns
Gold
09K3884.F38744
10/99
Dimension
Power
5.25" x 1.70" x 0.320"
3.3V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
x72 ECC SDRAM DIMM Block Diagram
RDQMB0
#
(2-Bank, x4 SDRAMs)
RS0
RS1
RDQMB4
DQ0
DQ1
DQ2
DQ3
DQM CS
I/O 0
I/O 1
D0
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D18
I/O 2
I/O 3
DQ32
DQ33
DQ34
DQ35
DQM CS
I/O 0
I/O 1
D9
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D27
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
DQM CS
I/O 0
I/O 1
D1
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D19
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
DQM CS
I/O 0
I/O 1
D10
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D28
I/O 2
I/O 3
RDQMB5
RDQMB1
DQ8
DQ9
DQ10
DQ11
DQM CS
I/O 0
I/O 1
D2
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D20
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQM CS
I/O 0
I/O 1
D11
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D29
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
DQM CS
I/O 0
I/O 1
D3
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D21
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
DQM CS
I/O 0
I/O 1
D12
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D30
I/O 2
I/O 3
CB0
CB1
CB2
CB3
DQM CS
I/O 0
I/O 1
D4
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D22
I/O 2
I/O 3
CB4
CB5
CB6
CB7
DQM CS
I/O 0
I/O 1
D13
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D31
I/O 2
I/O 3
RS2
RS3
RDQMB2
RDQMB6
DQ16
DQ17
DQ18
DQ19
DQM CS
I/O 0
I/O 1
D5
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D23
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQM CS
I/O 0
I/O 1
D14
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D32
I/O 2
I/O 3
DQ20
DQ21
DQ22
DQ23
DQM CS
I/O 0
I/O 1
D6
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D24
I/O 2
I/O 3
DQ52
DQ53
DQ54
DQ55
DQM CS
I/O 0
I/O 1
D15
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D33
I/O 2
I/O 3
Note: DQ wiring
may differ from that
described in this
drawing; however,
DQ/DQMB relationships are maintained as shown.
RDQMB7
RDQMB3
DQ24
DQ25
DQ26
DQ27
DQM CS
I/O 0
I/O 1
D7
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D25
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQM CS
I/O 0
I/O 1
D16
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D34
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
DQM CS
I/O 0
I/O 1
D8
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D26
I/O 2
I/O 3
DQ60
DQ61
DQ62
DQ63
DQM CS
I/O 0
I/O 1
D17
I/O 2
I/O 3
DQM CS
I/O 0
I/O 1
D35
I/O 2
I/O 3
S0-S3
DQMB0 to DQMB7
BA0, BA1
A0-A11
RAS
CAS
CKE0
WE
10k
VDD
REGE
PCK
*R
E
G
I
S
T
E
R
CK0
CK1, CK2 & CK3
RS0-RS3
RDQMB0 - RDQMB7
RBA0
BA0, RBA1
BA1: SDRAMs D0-D35
RA0-RA11
A0-A11: SDRAMs D0-D35
RRAS
RAS: SDRAMs D0 - D35
RCAS
CAS: SDRAMs D0 - D35
RCKE0
CKE: SDRAMs D0 - D35
RWE
WE: SDRAMs D0 - D35
PLL
Termination
Serial PD
SCL
SDA
WP
47k
A0
A1
A2
SA0
SA1
SA2
VDD
D0 - D35
VSS
D0 - D35
#: Unless otherwise noted, resistor values are 10 OHMS.
Note: Alternate decks in front and back side stack modules selected to improve heat dissipation characteristics.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Clock Wiring
Clock Net Wiring (CK0):
SDRAM STACK
(2 DEVICES)
OUT1
TO
OUT9
IN
CK0
12pF
10 Ohm
Phase
Lock
Loop
One of 9 SDRAM outputs shown.
All PLL clock SDRAM loads equal.
Achieved in part through equal length
wiring.
OUT10
FDBK
OUT11
IN
8pF
10 0hms
(2 SDRAM stack modules,
4 device loads per output)
SDRAM STACK
(2 DEVICES)
REG1 (1:1)
REG2 (1:1)
REG3 (1:1)
(PLL out to Feedback input)
Notes:
Terminated Clock Nets (CK1, CK2, and CK3):
PCK
1. The PLL is programmed via a combination
of the feedback path and on DIMM loading. PLL feedback produces zero phase
shift from the delayed CK0 input.
2. Card wiring and capacitance loading variation: ± 100ps.
3. Timing is based on a driver with a 1 Volt/ns
rise time.
CK1, CK2, and CK3
12pF
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0 - CK3
Input
Pulse
Positive
Edge
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
associated clock. CK0 drives the PLL. CK1, CK2 & CK3 are terminated.
CKE0
Input
Level
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, Suspend mode, or the
Self Refresh mode.
S0 - S3
Input
Pulse
Enables the associated SDRAM command decoder when low and disables the comActive Low mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0 and S2;
Bank 1 is selected by S1 and S3.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
BA0, 1
Input
Level
A0 - A9, A11
A10/AP
Input
DQ0 - DQ63, Input
CB0 - CB7 Output
DQMB0 DQMB7
Input
VDD, VSS
Supply
—
Selects which SDRAM bank of four is activated.
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address
(CA0-CA9, C11) when sampled at the rising clock edge. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or
write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0 or BA1. If AP is low, then BA0 and BA1 are used to define which bank to
precharge.
Level
—
Data and Check Bit Input/Output pins.
Pulse
Active
High
The Data Input/Output masks, associated with one data byte, place the DQ buffers in a
high impedance state when sampled high. In Read mode, DQMB has a latency of two
clock cycles in Buffered mode or three clock cycles in Registered mode, and controls the
output buffers like an output enable. In Write mode, DQMB has a zero clock latency in
Buffered mode and a latency of one clock cycle in Registered mode. In this case, DQMB
operates as a byte mask by allowing input data to be written if it is low but blocks the
write operation if it is high.
Power and ground for the module.
Active
High
The Register Enable pin is used to permit the DIMM to operate in Buffered mode (inputs
(Register re-driven asynchronously) or Registered mode (signals re-driven to SDRAMs when clock
Mode
rises, and held valid until next rising clock).
Enable)
REGE
Input
Level
SA0 - 2
Input
Level
—
These signals are tied at the system planar to either VSS or VDD to configure the SPD
EEPROM.
SDA
Input
Output
Level
—
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus time to VDD to act as a pull up.
SCL
Input
Pulse
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDD to act as a pull up.
WP
Input
Level
Active
High
This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes
of the SPD EEPROM.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM
04
3
Number of Row Addresses on Assembly
12
0C
4
Number of Column Addresses on Assembly
11
0B
5
Number of DIMM Banks
2
02
6-7
Data Width of Assembly
x72
4800
8
Assembly Voltage Interface Levels
LVTTL
01
9
SDRAM Device Cycle Time (CL = 3)
10.0ns
A0
10
SDRAM Device Access Time from Clock at CL=3
6.0ns
60
11
DIMM Configuration Type
ECC
02
12
Assembly Refresh Rate/Type
SR/1X(15.625us)
80
13
SDRAM Device Width
x4
04
14
Error Checking SDRAM Device Width
x4
04
15
SDRAM Device Attr: Min Clk Delay, Random Col Access
16
SDRAM Device Attributes: Burst Lengths Supported
17
SDRAM Device Attributes: Number of Device Banks
18
SDRAM Device Attributes: CAS Latency
19
SDRAM Device Attributes: CS Latency
20
SDRAM Device Attributes: WE Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes: General
23
Minimum Clock Cycle at CLX-1 (CL = 2)
24
Maximum Data Access Time (tAC) from
Clock at CLX-1 (CL = 2)
25
Minimum Clock Cycle Time at CLX-2 (CL = 1)
26
Maximum Data Access Time (tAC) from Clock at CLX-2
(CL = 1)
27
28
1 Clock
01
1,2,4,8, Full Page
8F
4
04
2, 3
06
0
01
0
01
Registered/Buffered with
PLL
IF
Write-1/Read Burst, Precharge All, Auto-Precharge
0E
-260
10.0ns
A0
-360
15.0ns
FO
-260
6.0ns
60
-360
9.0ns
90
N/A
00
N/A
00
Minimum Row Precharge Time (tRP)
20.0ns
14
Minimum Row Active to Row Active delay (tRRD)
20.0ns
14
Notes
1, 2
1, 2
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 10ns (100MHz) for the -260 and -360.
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal) ➔ 01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Serial Presence Detect (Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
29
Minimum RAS to CAS delay (tRCD)
20.0ns
14
30
Minimum RAS Pulse width (tRAS)
50.0ns
32
31
Module Bank Density
256MB
40
32
Address and Command Setup Time Before Clock
2.0ns
20
33
Address and Command Hold Time After Clock
1.0ns
10
34
Data Input Setup Time Before Clock
2.0ns
20
35
Data Input Hold Time After Clock
1.0ns
10
36 - 61
Reserved
62
SPD Revision
63
Checksum for bytes 0 - 62
64 - 71
72
73 - 90
Manufacturers’ JEDEC ID Code
Assembly Manufacturing Location
Assembly Revision Code
93 - 94
Assembly Manufacturing Date
95 - 98
Assembly Serial Number
127
128 - 255 Open for Customer Use
Checksum Data
cc
IBM
A400000000000000
Toronto, Canada
91
3
53
-260
31334D36343733344343rr
2D323630592020
-360
ASCII ‘13M64734CC”R”360Y’
31334D36343733344343rr
2D333630592020
“R” plus ASCII blank
rr20
5
Year/Week Code
yyww
6, 7
Serial Number
ssssssss
8
Undefined
Not Specified
Module Supports this Clock Frequency
Attributes for clock frequency defined in
Byte 126
12
Vimercate, Italy
99 - 125 Reserved
126
00
ASCII ‘13M64734CC”R”260Y’
Assembly Part Number
91 - 92
Undefined
PC100 1.2A
Notes
100MHz
64
-260
CLK0, CL=2,3 ConAP
87
-360
CLK0, CL=3, ConAP
85
Undefined
00
4, 5
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 10ns (100MHz) for the -260 and -360.
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal) ➔ 01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Absolute Maximum Ratings
Symbol
VDD
VIN
VOUT
TA
TSTG
PD
Parameter
Rating
Power Supply Voltage
Units Notes
-0.3 to +4.6
Input Voltage
Output Voltage
SDRAM Devices
-1.0 to +4.6
Serial PD Device
-0.3 to +6.5
Register
0 - VDD
1
0 to +70
°C
1
-55 to +125
°C
1
W
1, 2
1
PLL
0 - VDD
SDRAM Devices
-1.0 to +4.6
Serial PD Device
-0.3 to +6.5
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
V
10ns
24.7
15ns
19.30
IOUT
Short Circuit Output Current
50
mA
FMIN
Minimum Operating Frequency
66
MHz
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Maximum power is calculated assuming physical Bank 0 is in AutoRefresh mode and physical Bank 1 is in AutoRefresh mode.
Recommended DC Operating Conditions (TA= 0 to 70°C)
Symbol
Parameter
Rating
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
3.0
3.3
3.6
V
1
VIH
Input High Voltage
2.0
—
VDD + 0.3
V
1
VIL
Input Low Voltage
-0.3
—
0.8
V
1
1. All voltages referenced to VSS.
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V)
Organization
Symbol
Parameter
Units
x72 Max.
CI1
Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1)
19
pF
CI2
Input Capacitance (RAS)
18
pF
CI3
Input Capacitance (CAS)
18
pF
CI4
Input Capacitance (S0 - S3)
15
pF
CI5
Input Capacitance (CKE0)
38
pF
CI6
Input Capacitance (CK0)
28
pF
CI7
Input Capacitance (DQMB0 - DQMB7)
14
pF
CI8
Input Capacitance (SA0 - SA2, SCL, WP)
9
pF
CI9
Input Capacitance (REGE)
10
pF
CI10
Input Capacitance (CK1, CK2, and CK3)
16
pF
CI11
Input Capacitance (WE)
19
pF
CIO1
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
20
pF
CIO2
Input/Output Capacitance (SDA)
11
pF
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
DC Output Load Circuit
3.3 V
1200W
VOH (DC) = 2.4V, IOH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
870W
Input/Output Characteristics
(TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
x72
Symbol
Parameter
Units
Min.
Max.
Address and Control Inputs
10
10
DQ0-63, CB0 - 7
-4
+4
DQ0-63, CB0 - 7
-4
+4
SDA
-1
+1
II(L)
Input Leakage Current, any input
(0.0V ≤ VIN ≤ 3.6V), All Other Pins
Not Under Test = 0V
IO(L)
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V)
VOH
Output Level
Output “H” Level Voltage (IOUT = -2.0mA)
2.4
VDD
VOL
Output Level
Output “L” Level Voltage (IOUT = +2.0mA)
0.0
0.4
Notes
µA
µA
V
1
1. See DC output load circuit.
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Operating, Standby, and Refresh Currents
(TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
Speed
Parameter
Symbol
Test Condition
Units
Notes
Burst Operating Mode/Active Standby
ICC4/ICC3N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
2529
1707
mA
1, 2, 3
Burst Operating Mode/Precharge
Standby
ICC4/ICC2N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
2439
1635
mA
1, 2, 3
Burst Operating Mode/Auto Refresh
ICC4/ICC5
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
5357
3993
mA
1, 2, 3
Non-burst Operating Mode/Active
Standby
ICC1/ICC3N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
2657
1959
mA
1, 2, 3
Non-burst Operating Mode/Precharge
Standby
ICC1/ICC2N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
1865
1491
mA
1, 2, 3
Non-burst Operating Mode/Auto
Refresh
ICC1/ICC5
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
5177
4083
mA
1, 3
Active Standby/Active Standby
ICC3N/ICC3N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
1847
1275
mA
3
Active Standby/Precharge Standby
ICC3N/ICC2N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
1757
1203
mA
3
Active Standby/Auto Refresh
ICC3N/ICC5
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
4457
3399
mA
1, 3
Precharge Standby/Precharge
Standby
ICC2N/ICC2N
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
1667
1131
mA
3
Precharge Standby/Auto Refresh
ICC2N/ICC5
CKE ≥ VIH (min), tCK = min,
S0 - S3 =VIH (min)
4367
3327
mA
1, 3
Auto Refresh/Auto Refresh
ICC5/ICC5
CKE ≥ VIH (min), tCK = min,
S0 - S3S0 - S3
6849
5361
mA
1, 3
Active Standby Power Down/Active
Standby Power Down
ICC3p/ICC3p
CKE ≤ VIL (max), tCK = min,
S0 - S3 =VIH (min)
767
663
mA
3
Active Standby Power Down/Precharge Standby Power Down
ICC3p/ICC2p
CKE ≤ VIL (max), tCK = min,
S0 - S3 =VIH (min)
605
501
mA
3
Precharge Standby Power Down/Precharge Standby Power Down
ICC2p/ICC2p
CKE ≤ VIL (max), tCK = min,
S0 - S3 =VIH (min)
443
339
mA
3
Precharge Standby Non-power
Down/Precharge Standby Non-power ICC2NS/ICC2NS
Down (NO CLOCK)
CKE ≥ VIH (min), tCK = Infinity,
S0 - S3 =VIH (min)
395
395
mA
3
Precharge Standby Power Down/Precharge Standby Power Down (NO
ICC2PS/ICC2PS
CLOCK)
CKE ≥ VIH (min), tCK = Infinity,
S0 - S3 =VIH (min)
71
71
mA
3
Self Refresh Current/
Self Refresh Current
CKE ≥ VIH (min), tCK = Infinity,
S0 - S3 =VIH (min)
107
107
mA
3
ICC6/ICC6
fCK = 100Mhz fCK = 66Mhz
-260, -360
-260, -360
1. Input signals are changed once during tCK(min). tCK(min) = 10ns for -260, -360;
2. The specified values are obtained with the output open.
3. These parameters and symbols refer to a combination of physical bank 0/physical bank 1.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
AC Characteristics. (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
1. An initial pause of 200µs, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode
Register Set operation.
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between VIH and VIL (or between VIL and VIH).
4. AC measurements assume tT=1.2ns (1 Volt/ns rise time).
5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
6. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.
AC Characteristics Diagrams
tCKH
Clock
2.0V
1.4V
0.8V
tCKL
tSETUP
tT
Output
tHOLD
Zo = 50Ω
50pF
Input
1.4V
tAC
tOH
AC Output Load Circuit
tLZ
Output
09K3884.F38744
10/99
1.4V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Clock and Clock Enable Parameters
Symbol
-260
(Device CL, tRCD, tRP = 2, 2, 2)
Parameter
-360
(Device CL, tRCD, tRP= 3, 2, 2)
Units Notes
Min.
Max.
Min.
Max.
Registered
10
1000
10
1000
ns
Registered
10
1000
15
1000
ns
Buffered
10
1000
10
1000
ns
tCK4
Clock Cycle Time,
DIMM CAS Latency = 4
tCK3
Clock Cycle Time,
DIMM CAS Latency = 3
tCK2
Clock Cycle Time,
DIMM CAS Latency = 2
Buffered
10
1000
15
1000
ns
1
tAC4
Clock Access Time,
DIMM CAS Latency = 4
Registered
—
7.2
—
7.2
ns
1, 2
tAC3
Clock Access Time,
DIMM CAS Latency = 3
Registered
—
7.2
—
10.2
ns
Buffered
—
7.2
—
7.2
ns
tAC2
Clock Access Time,
DIMM CAS Latency = 2
Buffered
—
7.2
—
10.2
ns
1, 2
tCKH
Clock High Pulse Width
3
—
3
—
ns
3
tCKL
Clock Low Pulse Width
3
—
3
—
ns
3
tCES
Registered
2.1
—
2.1
—
ns
Clock Enable Setup Time
Buffered
7.4
—
7.4
—
ns
tCEH
Registered
1.5
—
1.5
—
ns
Clock Enable Hold Time
0
—
0
—
ns
Buffered
tSB
Power Down Mode Entry Time
0
10
0
10
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
ns
1.
2.
3.
1
1
1, 2
1
1
DIMM CAS latency = device CL [clock cycles] + 1 for Register mode; DIMM CAS latency is one clock less for Buffer mode.
Access time is measured at 1.4V. See AC output load circuit.
tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse
width of CLK measured from the negative edge to the positive edge referenced to VIL (max).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
.
Common Parameters
-260
Symbol
Units
Min.
tCS
tCH
tAS
tAH
-360
Parameter
Max.
Min.
Notes
Max.
Registered
2.0
2.0
ns
Buffered
7.4
7.4
ns
Registered
1.1
1.1
ns
Buffered
0.0
0.0
ns
Registered
2.0
2.0
ns
Buffered
7.4
7.4
ns
Registered
1.5
1.0
ns
Buffered
0.0
0.0
ns
1
Command Setup Time
1
Command Hold Time
1
Address and Bank Select Setup Time
1
Address and Bank Select Hold Time
tRCD
RAS to CAS Delay
2.0
2.0
ns
2
tRC
Bank Cycle Time
70
70
ns
2
tRAS
Active Command Period
50
ns
2
tRP
Precharge Time
20
20
ns
2
tRRD
Bank to Bank Delay Time
20
20
ns
2
tCCD
CAS to CAS Delay Time (Same Bank)
1
1
CLK
100000
50
100000
1. The set up and hold times refer to the addition of the register. Note that although the Buffered set up times appear much greater,
there is no additional clock cycle as there is in Registered mode.
2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the
number of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Mode Register Set Cycle
-260
Symbol
tRSC
-360
Parameter
Mode Register Set Cycle Time
Min.
Max.
Min.
Max.
20
—
20
—
Units
Notes
ns
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the
number of clock cycles = specified value of timing/clock period (count fractions as a whole number).
Refresh Cycle
-260
Symbol
tREF
-360
Parameter
Refresh Period
Min.
Max.
Min.
Max.
—
64
—
64
Units
Notes
ms
1
1. 4096 cycles.
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Read Cycle
Symbol
-260
Parameter
Min.
-360
Max.
Min.
Max.
Units
tOH
Data Out Hold Time
3.6
3.6
ns
tLZ
Data Out to Low Impedance Time
0.6
0.6
ns
tHZ3
Data Out to High Impedance Time
3.5
6.7
3.5
6.7
tHZ2
Data Out to High Impedance Time
3.5
6.7
3.5
6.7
tDQZ
DQM Data Out Disable Latency
ns
Notes
1
ns
Registered
3
3
CLK
Buffered
2
2
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
-260
Symbol
-360
Parameter
Units
Min.
Max.
Min.
Max.
tDS
Data In Setup Time
2.1
—
2.1
—
ns
tDH
Data In Hold Time
1.6
—
1.6
—
ns
Registered
10
—
10
—
ns
tDPL
Data input to Precharge
Buffered
20
—
20
—
ns
Registered
4
—
4
—
CLK
Buffered
5
—
5
—
CLK
Registered
4
—
4
—
CLK
Buffered
5
—
5
—
CLK
Registered
1
—
1
—
CLK
Buffered
0
—
0
—
CLK
tDAL3
tDAL2
tDQW
Data input to Active, CL = 3
Data input to Active CL = 2
DQM Write Mask Latency
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Presence Detect Read and Write Cycle
Symbol
fSCL
Max.
Units
SCL Clock Frequency
Parameter
Min.
100
KHz
100
ns
3.5
µs
TI
Noise Suppression Time Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out Valid
0.3
tBUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
µs
Start Condition Hold Time
4.0
µs
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
µs
tHD:DAT
Data in Hold Time
0
µs
tSU:DAT
Data in Setup Time
250
tHD:STA
ns
tr
SDA and SCL Rise Time
1
µs
tf
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
4.7
tDH
Data Out Hold Time
300
tWR
Write Cycle Time
Notes
µs
ns
15
ms
1
1. The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Functional Description and Timing Diagrams
Refer to IBM 168-pin SDRAM Registered DIMM Functional Description and Timing Diagrams (Document
01L5868.E24564) for Registered mode operation.
Refer to the IBM 128Mb Synchronous DRAM Die Revision A datasheet (Document 33L8019) for the functional description and timing diagrams for Buffered mode operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 20
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Layout Drawing
133.35
5.25
131.35
5.171
127.35
5.014
6.35
.250
3.0
.118
43.33
1.7
(2X) 4.00
.157
Front
42.18
1.661
17.78
.700
1.27 pitch
.050
(2) 0
3.1877
.1255
1.00 width
.039
65.68
2.63
See Detail A
Side
8.13
.320 max.
Detail A
Scale: 4/1
Back
R 1.00
.0393
4.24
.167 min.
4.24
.167 min.
2.0
.078
3.0
.118
Front
1.273 0.10
.050 .004
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 18 of 20
Millimeters
Inches
09K3884.F38744
10/99
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
Revision Log
Contents of Modification
Rev
7/99
Initial release.
8/99
Removed Preliminary
10/99
Made minor corrections.
09K3884.F38744
10/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 19 of 20

 International Business Machines Corp.1999
Copyright
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or
visit us on World Wide Web at http://www.chips.ibm.com
IBM Microelectronics manufacturing is ISO 9000 compliant.